JP2012151801A - Error correction device, error correction method and decoding device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an error correction device and an error correction method that can reduce power consumption.SOLUTION: An error correction device 100 includes: an iterative decoding circuit 120 for error-correcting input data by iterative decoding; a block code decoding circuit 150 for error-correcting iteratively decoded data error-corrected by the iterative decoding circuit 120 by block code decoding; a correction count/threshold comparison circuit 230 for comparing a correction count of block code decoding in the block code decoding circuit 150 with a preset correction threshold; and an iteration frequency control circuit 140 for controlling an iterative decoding frequency of the iterative decoding circuit 120. The iteration frequency control circuit 140 controls the iterative decoding frequency on the basis of the error correction result of the block code decoding circuit 150 and the comparison result of the correction count/threshold comparison circuit 230.

Description

  The present invention relates to an error correction device, an error correction method, and a decoding device, and in particular, a code using an iterative decoding method such as an LDPC (Low Density Parity Check) code or a turbo code, an RS (Reed-Solomon) code, or a BCH code. The present invention relates to an error correction apparatus, an error correction method, and a decoding apparatus that can be suitably used for decoding a concatenated code composed of block codes such as.

  In recent years, in wireless communication and digital broadcasting such as mobile phones and wireless LANs, codes that use iterative decoding methods such as LDPC codes and turbo codes with high correction capability for decoding devices that only use block codes, which have been the mainstream in the past, A concatenated code decoding device composed of block codes such as an RS code and a BCH code is used, and power consumption is increased compared to a conventional decoding device using only a block code. For this reason, low power consumption is required not only for mobile devices that require long-time battery driving but also for all devices that are used.

  As a conventional error correction device, a decoding device described in Patent Document 1 is known. The decoding apparatus described in Patent Document 1 is intended to provide a decoding apparatus that prevents unnecessary iterative decoding and insufficient iterative decoding and optimizes error correction performance. The number of iterations is controlled using the correctability information in FIG.

  The decoding apparatus described in Patent Document 1 decodes a signal obtained by superimposing RS (Reed-Solomon) encoding and turbo encoding. That is, the apparatus on the signal transmission side includes an RS encoder and a turbo encoder, and the signal transmitted thereby becomes a block code by RS encoding first, and the block code is turbo. The encoded turbo code is generated.

  FIG. 9 is a block diagram showing a decoding apparatus described in Patent Document 1. In FIG. The decoding apparatus 500 includes an input buffer 510, a turbo decoder 520, an RS decoder 550, an output buffer 570, a control unit 540, and a memory 580.

  The input buffer 510 temporarily stores the received signal, and the stored signal is provided to the turbo decoder 520. The output buffer 570 temporarily stores the signal decoded by the RS decoder 550. The turbo decoder 520 repeatedly performs turbo decoding on the signal input from the input buffer 510.

  The RS decoder 550 performs RS decoding on the signal turbo-decoded by the turbo decoder 520. When error correction is completed as a result of the RS decoding operation of the RS decoder 550, the RS decoder 550 outputs an error correction completion signal.

  The memory 580 stores a setting value that specifies the number of iterations of the decoding operation of the turbo decoder 520, and a maximum value and a minimum value that can be set in this iteration number setting value. The control unit 540 controls the turbo decoder 520 so that the turbo decoder 520 performs the decoding operation until the iteration number setting value stored in the memory 580 is reached. In addition, the control unit 540 resets the iteration number setting value stored in the memory 580 to a new value according to the completion signal output from the RS decoder 550.

  FIG. 10 is a flowchart showing the operation of the decoding apparatus according to Patent Document 1. Next, the decoding method according to Patent Document 1 will be described in more detail. The received signal is input to the input buffer 510 and then input to the turbo decoder 520 (step S510). The turbo decoder 520 performs iterative turbo decoding on the input signal (step S520). At this time, the decoding operation of the turbo decoder 520 is controlled by the control unit 540, and the control unit 540 controls the turbo decoder 520 so that the decoding operation is repeated until the repetition number setting value already set in the memory 580 is reached. Control.

  The signal turbo-decoded up to the iteration number setting value is input to the RS decoder 550, and the RS decoder 550 performs RS decoding on the input signal (step S525). The RS decoder 550 has a function of determining whether or not error correction has been completed. When determining that error correction has been completed (step S530), the RS decoder 550 outputs a completion signal. This completion signal is input to the control unit 540, whereby the control unit 540 is notified whether or not error correction has been completed.

  When the completion signal is input to the control unit 540, the control unit 540 decreases the iteration number setting value set in the memory 580 by one (step S550). At this time, the memory 580 stores a minimum value that can be set for the iteration number setting value, and the control unit 540 compares whether or not the currently set iteration number setting value is smaller than the minimum value. (Step S540), the iteration number setting value is decreased only when it is larger than the minimum value (Step S550).

  If the completion signal is not output even after the RS decoding operation of the RS decoder 550 is completed, the control unit 540 determines that the error correction is not completed. As a result, the control unit 540 increments the iteration count setting value set in the memory 580 by one (step S570). In this case, since error correction has not yet been completed, the repeated turbo decoding operation by the turbo decoder 520 is continued for the current frame of the received signal (step S580). At this time, the maximum value that can be set for the iteration number setting value is stored in the memory 580, and the control unit 540 compares whether or not the currently set iteration number setting value is larger than the maximum value ( In step S560), the iteration number setting value is increased only when it is smaller than the maximum value (step S570).

  The iteration number setting value set in step S550 and step S570 is used as the number of times to repeat turbo decoding during the decoding operation for the next frame of the received signal. When the state of the channel through which the signal is transmitted is good, the data in which the error occurs is reduced, and the data in which the error is generated increases as the channel state is not good. As the number of errors increases, it is necessary to perform turbo decoding with a large number of iterations until a good error correction performance is obtained. When there are few errors, good error correction performance can be obtained even with a small number of iterations of turbo decoding.

  According to Patent Document 1, the memory 580 is set in advance with a setting value for the number of iterations for the turbo decoder 520 to perform iterative turbo decoding, and error correction is sufficiently performed by iterative decoding of the number of iterations of the set value. If it is determined, the current channel state is determined to be good. Therefore, even if the number of turbo decoding iterations for the next frame is reduced, error correction can be sufficiently performed. If error correction cannot be performed by iterative decoding of the set number of iterations, it is determined that the current channel state is defective. Therefore, the number of iterations of turbo decoding for the next frame is increased to increase the error correction capability.

  By the way, even if the number of iterations exceeds the maximum value that can be set, if the input buffer 510 has an extra storage capacity, the problem of time delay due to excessive iterations does not occur. This is because if there is an extra storage capacity in the input buffer 510 (step S575), the delay due to the turbo decoding operation of the turbo decoder 520 is performed during the time that the signal received in the input buffer 510 is additionally stored. This is because even if it occurs, there is no time delay of the decoding operation as a whole. Therefore, if there is an extra storage capacity in the input buffer 510, the iteration count setting value can be increased even if the iteration count setting value exceeds the maximum value (step S578).

Japanese Patent No. 3638930 (FIGS. 2 and 3)

  However, since the number of iterations is controlled only by the block code decoding correction enable / disable information in the technique described in Patent Document 1, when iterative decoding is performed with the minimum number of iterations that can be corrected by block code decoding. However, the number of iterations set for the next data block is reduced. Therefore, in the next data block, if the data after iterative decoding includes an error exceeding the correctable number of block code decoding, correction cannot be performed by block code decoding, and it becomes necessary to perform iterative decoding and block code decoding again. For this reason, unnecessary block code decoding additionally occurs, and there is a problem that the power consumption of the RS decoder 550 increases.

  An error correction apparatus according to the present invention includes an iterative decoding circuit that corrects an error of input data by an iterative decoding method, and a block code decoding circuit that corrects an error of the iteratively decoded data corrected by the iterative decoding circuit by block code decoding. A correction number threshold comparison circuit for comparing the number of block code decoding corrections in the block code decoding circuit with a preset correction threshold; and an iteration number control circuit for controlling the number of iteration decoding of the iterative decoding circuit; The iterative number control circuit controls the number of times of iterative decoding based on an error correction result of the block code decoding circuit and a comparison result of the correction number threshold comparison circuit.

  The error correction method according to the present invention corrects errors by iteratively decoding input block data by a preset number of times using an iterative decoding method, and blocks the iteratively decoded data error-corrected by the iterative decoding. Error correction by code decoding, and based on the error correction result of the block code decoding and the comparison result between the correction number of the block code decoding and a preset correction threshold, the set number of block data to be input next is To decide.

  A decoding apparatus according to the present invention includes an iterative decoding circuit that performs error correction on input data by an iterative decoding method, and a block code decoding circuit that performs error correction on the iteratively decoded data error-corrected by the iterative decoding circuit by block code decoding, and An iterative number control circuit for controlling the iterative decoding number of the iterative decoding circuit, wherein the iterative number control circuit is configured to perform the iterative decoding based on an error correction result in the block code decoding circuit and a correction number of block code decoding. The number of times is controlled.

  In the present invention, in a system that performs block code decoding after iterative decoding, not only the decoding result in block code decoding but also the number of corrections is used when controlling the number of decoding times of iterative decoding. For example, the number of corrections is compared with a preset correction number threshold, and the number of iterations of the next input data is determined based on the comparison result. This makes it possible to control the number of iterative decoding more accurately than in the case where the increase / decrease in the number of iterative decoding is determined only from the result of block code decoding.

  According to the present invention, it is possible to provide an error correction device, an error correction method, and a decoding device that can reduce power consumption.

1 is a block diagram showing an error correction device according to a first exemplary embodiment of the present invention. It is a block diagram which shows the repetition frequency control circuit in the error correction apparatus concerning Embodiment 1 of this invention. It is a flowchart which shows the error correction method concerning Embodiment 1 of this invention. It is a graph which shows the relationship between the number of iteration decoding iterations, and the number of errors after iterative decoding in the error correction apparatus concerning Embodiment 1 of this invention. FIG. 5A is a schematic diagram illustrating a transmission state of a conventional error correction apparatus, and FIG. 5B is a schematic diagram illustrating a transmission state of the error correction apparatus according to the first embodiment of the present invention. It is a block diagram which shows the error correction apparatus concerning Embodiment 2 of this invention. It is a flowchart which shows the error correction method concerning Embodiment 2 of this invention. FIG. 8A is a schematic diagram illustrating a transmission state of the error correction apparatus according to the first embodiment of the present invention, and FIG. 8B illustrates a transmission state of the error correction apparatus according to the second embodiment of the present invention. It is a schematic diagram shown. It is a block diagram which shows the decoding apparatus of patent document 1. FIG. 5 is a flowchart showing a coating method described in Patent Document 1.

  Hereinafter, specific embodiments to which the present invention is applied will be described in detail with reference to the drawings. In the embodiments described below, the present invention relates to a decoding apparatus for a concatenated code composed of an LDPC code, a turbo code, and the like that improve error correction capability by an iterative decoding method, and a block code such as an RS code and a BCH code. (Error correction device).

  The error correction apparatus according to the present embodiment includes a correction number threshold comparison circuit that compares a correction number of block code decoding and a correction threshold, and an iteration that controls the number of iterations of iterative decoding based on a comparison result of the correction number threshold comparison circuit. If the number of corrections is greater than the correction threshold as a result of comparing the correction number of block code decoding and the correction threshold, it is determined that the number of iterations is set to the minimum number, and the number of iterations is retained. When the number of corrections is equal to or less than the correction threshold, it is determined that the number of iterations is not set to the minimum number and there is room for reducing the number of iterations, and the number of iterations is reduced. By using the number of corrections for block code decoding to reduce the number of iterations, it is possible to suppress an excessive reduction in the number of iterations, and no unnecessary block code decoding process is additionally generated, so that power consumption can be reduced.

Embodiment 1 of the present invention.
FIG. 1 is a block diagram showing an error correction apparatus according to Embodiment 1 of the present invention. As shown in FIG. 1, the error correction apparatus 100 includes an iterative decoding circuit 120, a block code decoding circuit 150, a correction number threshold comparison circuit 230, an iteration number control circuit 140, and a threshold setting circuit 240. The iterative decoding circuit 120 is, for example, an LDPC decoder or a turbo decoder, and the block code decoding circuit 150 is, for example, an RS decoder or a BCH decoder. For example, in the case of a turbo decoder and an RS decoder, the decoding device (error correction device) decodes a signal obtained by superimposing RS encoding and turbo encoding. That is, the device on the signal transmission side includes an RS encoder and a turbo encoder, and the signal transmitted thereby becomes a block code by RS encoding first, and the block code is turbo. The encoded turbo code is generated.

  The iterative decoding circuit 120 corrects errors in input block data by an iterative decoding method. The iterative decoding circuit 120 receives the iterative decoding input data 1 from an external device (not shown) such as a demodulator, and the iterative decoding stop continuation signal 12 for instructing whether to stop or continue the iterative decoding from the iteration number control circuit 140. Are input to the block code decoding circuit 150, and the iterative decoding end signal 11 is output to the iteration code control circuit 140, respectively. The iterative decoding end signal 11 is output every time the iterative decoding is completed, and the number of iterative decoding in the iterative decoding circuit 120 can be counted by counting the number of times of completion. The iterative decoding circuit 120 is controlled by the iterative number limiting circuit 140 so as to perform iterative decoding until reaching a preset number of times held by the iterative number limiting circuit 140.

  The iteration number control circuit 140 controls the number of iterations of the iterative decoding circuit 120. The iteration number control circuit 140 includes a correction enable / disable signal 7 indicating an error correction result (whether or not an error has been corrected) of the block code decoding circuit 150, and a comparison result of the correction number threshold comparison circuit 230 (correction in the block code decoding circuit 150). Based on the threshold comparison result signal 6 indicating whether or not the number is equal to or less than the correction threshold, the set number of iterations is determined. Specifically, the iteration count control circuit 140 maintains the set count of the iterative decoding circuit 120 when the correction count threshold comparison circuit 230 determines that the correction count is greater than the correction threshold, and the correction count threshold comparison circuit 230. If the number of corrections is determined to be less than or equal to the correction threshold, the number of times the iterative decoding circuit 120 is set is reduced. If the block code decoding circuit 150 determines that iteratively decoded data cannot be corrected, the iterative number control circuit 140 increases the set number of times of the iterative decoding circuit 120 and the iterative decoding circuit 120 performs iterative decoding again. Let

  The block code decoding circuit 150 corrects an error of the iteratively decoded data 2 that has been error-corrected by the iterative decoding circuit 120. The block code decoding circuit 150 receives the data 2 after iterative decoding from the iterative decoding circuit 120 and sends the data 3 after block code decoding and the correction number threshold comparison circuit 230 to an external device (not shown) such as an MPEG (Moving Picture Experts Group) decoder device. In addition, the correction number 4 in the block code decoding and the correction enable / disable signal 7 indicating whether or not the correction has been made by the block code decoding are output to the iteration number control circuit 140, respectively.

  The correction number threshold comparison circuit 230 is a circuit that compares the block code decoding correction number 4 in the block code decoding circuit 150 with a preset correction threshold value. The correction threshold 5 is input from the setting circuit 240 and the above-described threshold comparison result signal 6 is output to the iteration count control circuit 140. The correction threshold value includes the error correction capability of the block code decoding circuit 150, the iterative decoding correction capability of the iterative decoding circuit, specifically, the number of error corrections performed once in the iterative decoding circuit 120, and the block code decoding circuit 150. The value is determined according to the maximum correction number, and details of the determination method will be described later.

  The threshold setting circuit 240 outputs a preset correction threshold 5 to the correction number threshold comparison circuit 230.

  FIG. 2 is a block diagram showing the iteration number control circuit 140 of the error correction apparatus according to the first exemplary embodiment of the present invention. The iteration count control circuit 140 includes an iterative decoding stop control circuit 200, an iteration count counter circuit 210, and an iteration count setting circuit 220.

  The iteration number counter circuit 210 is a circuit that counts the number of iterations of the iterative decoding circuit 120. The iterative number counter circuit 210 receives the correction enable / disable signal 7 from the block code decoding circuit 150 and the iterative decoding end signal 11 from the iterative decoding circuit 120, respectively. The iterative decoding stop control circuit 200 receives the counted iterative decoding circuit 120. The number of iteration decoding is output as an iteration count counter value 8.

  The iteration count setting circuit 220 is a circuit that determines the iteration count (set count) at which the iterative decoding circuit 120 performs iterative decoding. The iteration count setting circuit 220 receives the threshold comparison result signal 6 from the correction count threshold comparison circuit 230, the correction enable / disable signal 7 from the block code decoding circuit 150, and the iteration count initial value 10 set from the outside of the error correction device. The Then, using the threshold comparison result signal 6 as well as the correction enable / disable signal 7, the iteration number initial value 10 is sequentially updated to the set number for the next iterative decoding input data 1. The number of iterations is output to the decoding stop control circuit 200 as 9 times.

  The iterative decoding stop control circuit 200 receives the iteration number counter value 8 from the iteration number counter circuit 210 and the iteration setting number 9 from the iteration number setting circuit 220, and performs iterative decoding until the iteration number count value reaches the set number. The iterative decoding stop continuation signal 12 for instructing to stop the iterative decoding is output to the iterative decoding circuit 120 when the count value reaches the set number of times.

  Next, the operation of the error correction apparatus according to this embodiment will be described. FIG. 3 is a flowchart showing the error correction method according to the first exemplary embodiment of the present invention. In the error correction apparatus 100, it is assumed that the iteration number initial value 10 set from the outside of the error correction apparatus when the system is reset and the iteration setting number 9 output from the iteration number setting circuit 220 are the same value.

  The iterative decoding circuit 120 receives the iterative decoding input data 1 from an external device such as a demodulation device, and performs iterative decoding for a set number of times (step S10). The iteration count counter circuit 210 counts the iteration count based on the iterative decoding end signal 11 and outputs the iteration count counter value 8 to the iterative decoding stop control circuit 200.

  The iterative decoding stop control circuit 200 determines (number of iterations) ≧ (number of iterations set) (step S20). If (number of iterations) ≧ (number of iterations set), the process proceeds to step S25, where (number of iterations) <( In the case of (iteration set number of times), the iterative decoding stop continuation signal 12 for requesting continuation of iterative decoding is output to the iterative decoding circuit 120, and the process returns to step S10. Thereby, the iterative decoding circuit 120 continues the iterative decoding.

  When the comparison result is (number of iterations) ≧ (number of iterations set), the iterative decoding stop control circuit 200 outputs an iterative decoding stop continuation signal 12 that requests the iterative decoding circuit 120 to stop iterative decoding. Thereby, the iterative decoding circuit 120 stops the iterative decoding, and the block code decoding circuit 150 performs block code decoding using the data 2 after iterative decoding output from the iterative decoding circuit 120 (step S25).

  If correction by the block code decoding circuit 150 is impossible (step S30: No), the process proceeds to step S78, and if correction is possible (step S30: Yes), the process proceeds to step S100.

  When correction by block code decoding is impossible (step S30: No), the block code decoding circuit 150 outputs a correction propriety signal 7 notifying this to the iteration number setting circuit 220 of the iteration number control circuit 140. The iterative number setting circuit 220 increases the iterative setting number by the correction availability signal 7 (step S78). Thereby, the processing from step S10, that is, iterative decoding and block code decoding are repeated again.

  If correction by block code decoding is possible (step S30: Yes), the block code decoding circuit 150 outputs the correction number 4 at that time to the correction number threshold comparison circuit 230. The correction number threshold comparison circuit 230 compares the correction number 4 with the correction threshold value 5 set by the threshold setting circuit 240 (step S100). If (correction number) ≦ (correction threshold value), the process proceeds to step S160. If (the number of corrections)> (correction threshold), the process proceeds to step S150.

  When the comparison result is (number of corrections)> (correction threshold) (step S100: No), the iteration count setting circuit 220 determines that the iteration count is appropriate, maintains the iteration set count, and ends the process. (Step S150). At the end of the process, the iteration count counter circuit 210 resets the iteration count counter value 8.

  When the comparison result is (number of corrections) ≦ (correction threshold) (step S100: Yes), the iteration number setting circuit 220 determines that the number of iterations is excessive, reduces the number of iteration settings by one, and ends the process. (Step S160). At the end of the process, the iteration count counter circuit 210 resets the iteration count counter value 8.

  Next, the mechanism of the first embodiment will be described with reference to FIGS. 4 and 5. FIG. 4 is a graph showing the relationship between the number of iterations of iterative decoding and the number of errors after iterative decoding of the error correction apparatus according to the first exemplary embodiment of the present invention. In FIG. 4, the number of iterations is shown on the I axis, and the number of errors after iterative decoding is shown on the E axis. In this example, S is the maximum number of errors that can be corrected by block code decoding, A is the number of iterations at that time, and R is the number of errors after block code decoding when the number of iterations is A + 1.

  When the correction threshold is R and the number of iterations is A + 1, (number of corrections) = R = (correction threshold R) in step S100 of FIG. Therefore, the process proceeds to step S160, and the number of repetition settings in the next data block is reduced to A. The number of iterations of the next input data block is A. In this case, in step S100 in FIG. 3, (number of corrections) = S> (correction threshold R), and the process proceeds to step 150. Therefore, as shown in step S150, the number of iterations set for the next input data block is maintained at A times. As a result, the minimum number of iterations without error after block code decoding is maintained, the number of iterations is not excessively reduced, and unnecessary block code decoding processing is not additionally generated, thereby suppressing an increase in power consumption. can do.

  FIG. 5 is a schematic diagram illustrating a transmission state of the error correction apparatus according to the first embodiment. In FIG. 5, data blocks are sent in the order of data block DB1, data block DB2,..., And the number of iterations (I1, I2,... For each data block DB1, DB2,. ) And the block code decoding count (B1, B2), respectively. Numerical values in I1, I2, etc. indicate the number of iteration decoding, and numerical values in B1, B2, etc. indicate the number of block code decoding. The data block indicates a decoding processing unit of the iterative decoding circuit 120 and the block code decoding circuit.

  FIG. 5A is a schematic diagram illustrating a transmission state of the error correction apparatus described in Patent Document 1, for example. Here, it is assumed that the number of iterations set in the memory 180 at the start of decoding is set to 20. In this case, in the data block DB1, it is assumed that the turbo decoder 520 performs 20 iterations from the number of iterations I1 to I20 and can be corrected by the block code decoding B1. In this case, the number of repetition settings is reduced to 19. Thereby, in the next data block DB2, the number of iterations is reduced to 19 from I1 to I19. Again, if correction is possible in block code decoding B1, the number of iteration settings is reduced to 18. Thereby, in the next data block DB3, the number of iterations is reduced to 18 times from I1 to I18. Also in DB3, when correction is possible by block code decoding B1, the number of iterations is reduced to 17. Therefore, the number of iterations in the next data block DB4 is reduced to 17 times from I1 to I17 times. Here, in DB4, it is assumed that correction is impossible by block code decoding B1. In this case, it becomes necessary to perform iterative decoding I18 again and to perform block code decoding B2. That is, in this transmission state, although the ideal number of decoding times of the block code decoding circuit is 18, the conventional method sets the number of iterations to 17 times less than 18 times. .

  On the other hand, FIG.5 (b) is a schematic diagram which shows the transmission state of the error correction apparatus concerning Embodiment of this invention. In the present embodiment, a correction threshold is set. Here, the case where the correction threshold is R and the number of iterations A = 18 will be described as in FIG. As in FIG. 5A, a case where the number of iterations set at the start of decoding = 20 will be described.

  In the data block DB1, 20 iterations from I1 to I20 are performed. In this case, since the number of corrections is equal to or less than the set threshold value R in the block code decoding B1, the number of iteration settings is reduced to 19. Thereby, in the next data block DB2, the number of iterations is reduced to 19 (= A + 1) from I1 to I19. In this data block DB2, since the number of iterations is 19 (= A + 1), the number of corrections is R in block coding / decoding B1, and is equal to or less than the set threshold (= R), so the number of iterations set is 18 (= A) Reduce. Therefore, the number of iterations in the next data block DB3 is reduced to 18 times from I1 to I18. Here, in this data block DB3, since the number of iterations is 18 (= A), the number of corrections of block code decoding B1 = S, which is larger than the set threshold = R. Therefore, the number of repetition settings is maintained at 18. As a result, the number of iterations in the next data block DB4 is maintained at 18, and decoding is possible as in the data block DB3. As described above, compared to the case of FIG. 5A, since the number of iterations is not excessively reduced, unnecessary block code decoding processing does not occur, and the increase in power consumption of the block code decoding circuit 150 is suppressed. Is done.

  Next, a correction threshold setting method in the present embodiment will be described. In this embodiment, when the number of error corrections after block code decoding is equal to or less than the correction threshold, the number of iterative decoding is reduced, and when the number of error corrections after block code decoding exceeds the correction threshold, iterative decoding is performed. Maintain the number of times. Here, in this embodiment, the number of times of iterative decoding is reduced to the minimum necessary by setting an optimal value for the correction threshold according to the magnitude of the correction capability of both iterative decoding and block code decoding. Is.

This correction threshold can be obtained by the following equation (1).
(Correction threshold) ≦ (maximum number of block code decoding corrections) − (number of error corrections for one iteration decoding) (1)

  The method for obtaining the correction threshold will be described with reference to Table 1 below. Table 1 shows the number of iterations and iterations when the number of errors corrected in one iteration decoding is 3, the maximum number of corrections in block code decoding is 10, and the number of errors included in the input data of the iteration decoding circuit is 20. The correspondence between the number of errors after decoding and the number of errors after block code decoding is shown.

  When the number of iterative decoding is 0, the number of errors after iterative decoding remains 20, and the number of errors after block code decoding remains 20 because it exceeds the maximum correction number in block code decoding. If the number of iterations is one, the number of errors after iterative decoding is 17. However, since the maximum number of corrections in block code decoding is exceeded, the number of errors after block code decoding remains 17. When the number of iteration decoding is 4, the number of errors after iterative decoding is 8, and the number of errors after block code decoding is 0 because it is less than or equal to the maximum number of corrections in block code decoding. When the number of iterative decoding is 4 or more, the number of errors after block code decoding is zero.

In the case of Table 1, considering that the number of iterative decoding is reduced from 10 times, the minimum number of times of iterative decoding at which the number of errors after block code decoding is 0 is 4. At this time, the number of errors after iterative code decoding is 8, and if the number of one-time iterative decoding is further reduced, the number of errors after iterative code decoding becomes 11, which cannot be corrected by block code decoding.
Therefore, iterative decoding can be reduced within a range that satisfies the following equation (2).
(Number of error corrections for one iteration decoding) ≦ (Maximum number of block code decoding corrections) − (Number of errors after iterative decoding) (2)

The following formula (3) is obtained from the above formula (2).
(Number of errors after iterative decoding) ≦ (maximum number of block code decoding corrections) − (number of error corrections for one iterative decoding) (3)

  If the maximum value of the number of errors after iterative decoding in Equation (3) is used as the correction threshold, the number of iterative decoding can be reduced to the minimum necessary. That is, in the above example, the correction threshold value can be set to 7 (7 or less).

  As described above, in the first embodiment, in the error correction apparatus, the correction number of block code decoding is used to control the number of iterations of iterative decoding. If the correction number is larger than the correction threshold, correction can be performed by block code decoding. It is determined that iterative decoding is performed with the minimum number of iterations, and the number of iterations is maintained. As a result, the number of iterations is not excessively reduced as in the prior art, so that additional block code decoding processing does not occur, and an increase in power consumption can be suppressed.

  Furthermore, if the number of corrections is less than or equal to the correction threshold, it is possible to reduce power consumption by determining that the number of iterations is excessive and performing unnecessary iterative decoding and reducing the number of iterations.

Embodiment 2 of the present invention.
Next, a second embodiment of the present invention will be described. FIG. 6 is a block diagram showing an error correction apparatus according to the second embodiment of the present invention. In the second embodiment shown in FIG. 6, the same components as those in the first embodiment shown in FIG. 1 are denoted by the same reference numerals, and detailed description thereof is omitted. As shown in FIG. 6, the error correction device 110 according to the second embodiment is different from the error correction device 100 according to the first embodiment shown in FIG. Are different.

  The iteration count protection circuit 250 receives the threshold comparison result 6 from the correction count threshold comparison circuit 230, the correction enable / disable signal 7 from the block code decoding circuit 150, and the protection count threshold 13 from the threshold setting circuit 240, respectively. Is output to the iteration number setting circuit 220. The iteration number protection circuit 250 includes a counter that starts counting when the correction number <the correction threshold value. The count value is compared with the protection number threshold value, and the comparison result is used as the iteration number holding reduction signal 14. Output as.

  The iteration count setting circuit 220 receives the iteration count hold reduction signal 14 from the iteration count protection circuit 250, the correction enable / disable signal 7 from the block code decoding circuit 150, and the iteration count initial value 10 set from the outside of the error correction device, respectively. The iteration setting number 9 is output to the iterative decoding stop control circuit 200. The iteration number setting circuit 220 in the present embodiment determines the iteration setting number based on the iteration number holding reduction signal 14 indicating whether or not the count value is less than or equal to the protection number threshold. Specifically, if the count value is less than or equal to the protection count threshold, the number of iterations is not decreased even if the correction count is less than the correction threshold, the correction count is less than the correction threshold, and the count value exceeds the protection count threshold. Only if it reduces the number of iteration settings.

  The threshold setting circuit 240 outputs the correction threshold 5 to the correction count threshold comparison circuit 230 and the protection count threshold 13 to the iteration count protection circuit 250, respectively.

  Next, the operation of the present embodiment will be described. FIG. 7 is a flowchart showing the operation of the error correction apparatus according to this embodiment. Steps S10, S20, and S25 are the same processes as those in the first embodiment shown in FIG.

  The block code decoding circuit 150 determines whether or not the data 2 after iterative decoding output from the iterative decoding circuit 120 can be corrected (step S30). If correction is not possible, the block code decoding circuit 150 proceeds to step S170 and correction is possible. If so, the process proceeds to step S100. The block code decoding circuit 150 outputs a correction availability signal 7 indicating that the correction is impossible when the correction is impossible, and outputs a correction availability signal 7 indicating that the correction is possible when the correction is possible.

  When correction by block code decoding of the block code decoding circuit 150 is impossible (step S30: No), the iteration count protection circuit 250 resets the count value of the number of corrections <the number of corrections (the number of protection times) (step of protection) (step S30). S170). The correction enable / disable signal 7 indicating that correction is impossible is also input to the iteration count setting circuit 220. When the iteration count setting circuit 220 receives the correction enable / disable signal 7 indicating that correction is not possible, the repeat setting count is set as in the first embodiment. Increase (step S78). After that, the process returns to step S10, and iterative decoding (step S10) and block code decoding (step S25) are performed again as in the first embodiment.

  On the other hand, when the correction by the block code decoding of the block code decoding circuit 150 is possible (step S30: Yes), the block code decoding circuit 150 outputs the correction number 4 to the correction number threshold comparison circuit 230. The correction number threshold value comparison circuit 230 compares the correction number 4 with the correction threshold value 5 (step S100). If (correction number) ≦ (correction threshold value), the process proceeds to step S120, and (correction number)> (correction threshold value). In this case, the process proceeds to step S130. The correction number threshold comparison circuit 230 outputs this comparison result as the threshold comparison result 6 to the iteration count protection circuit 250.

  When the comparison result of the correction number threshold comparison circuit 230 is (correction number)> (correction threshold) (step S100: No), that is, when the number of iterations is appropriate, the iteration number protection circuit 250 Is reset (step S130), and the iteration count holding reduction signal 14 for notifying this is output to the iteration count setting circuit 220. In response to this, the iteration number setting circuit 220 maintains the iteration setting number (step S150) and ends the process. At the end of the process, the iteration count counter circuit 210 resets the iteration count counter value 8.

  On the other hand, when the comparison result of the correction number threshold comparison circuit 230 is (correction number) ≦ (correction threshold) (step S100: Yes), the protection count is compared with the protection count threshold 13 (step S120), and (protection). If (number of times) ≧ (threshold number of protection), the process proceeds to step S135. If (number of protections) <(threshold number of protection), the process proceeds to step S140. The iteration count protection circuit 250 outputs this comparison result to the iteration count setting circuit 220 as the iteration count hold reduction signal 14.

  When the comparison result of the iteration count protection circuit 250 is (protection count) ≧ (protection count threshold) (step S120: Yes), the protection count count value is reset (step S135) and the comparison result is stored in the iteration count hold reduction signal 14. To notify the iteration number setting circuit 220. In response to this, the iteration number setting circuit 220 reduces the iteration setting number (step S160) and ends the process. At the end of the process, the iteration count counter circuit 210 resets the iteration count counter value 8.

  When the comparison result of the iteration count protection circuit 250 is (protection count) <(protection count threshold) (step S120: No), the iteration count protection circuit 250 increases the count value of the protection count (step S140). The comparison result is notified to the iteration number setting circuit 220 by the iteration number holding reduction signal 14. In response to this, the iteration number setting circuit 220 maintains the iteration setting number (step S145) and ends the process. At the end of the process, the iteration count counter circuit 210 resets the iteration count counter value 8.

  If the protection frequency threshold 13 set in the threshold setting circuit 240 is set to 0, the operation is the same as that in the first embodiment.

  Next, the mechanism of the second embodiment will be described with reference to FIG. FIG. 8 shows a transmission path state in which there is no error after block code decoding in data blocks DB1 to DB2 after 18 iterations. In data blocks DB3 and DB4, an error after block code decoding is temporarily executed in 17 iterations. In the example in which the data state changes to a transmission state in which data is lost, and after data block DB5 returns to a transmission state in which there are no errors after block code decoding with 18 iterations, each data block (DB1, DB2,...) The number of iterations (I) and the number of block code decoding (B) are shown in a graph.

  FIG. 8A shows the number of iterations (I) and the number of block code decoding (B) in the first embodiment when the protection count threshold is not set, that is, FIG. 8B sets the protection count threshold. In other words, the number of iterations (I) and the number of block code decoding (B) in the second embodiment are shown. Here, a description will be given of a case where the protection count threshold value = 2 is set in the iteration count protection circuit 250 of the error correction apparatus 110 according to the present embodiment.

  As shown in FIG. 8A, in the error correction apparatus according to the first embodiment, the number of corrections after block code decoding in the data block DB3 is equal to or less than the correction threshold. As a result, the number of repetition settings is reduced from 18 times to 17 times. Therefore, in the error correction process of the data block DB4, the number of iterations of the iterative decoding circuit 120 is 17. In the subsequent data block DB5, the number of iterations is maintained at 17. However, in the data block DB5, the transmission state is changed as described above, and if the iterative decoding is not performed 18 times, an error does not disappear after block code decoding. Transmission status. Therefore, in the error correction process of the data block DB5, when the set number of iterations is 17, the correction cannot be made by block code decoding, and it becomes necessary to perform iterative decoding and block code decoding again.

  On the other hand, in the present embodiment, as shown in FIG. 8 (b), the count of the protection count is started when the number of corrections after block code decoding in the data block DB3 is equal to or less than the correction threshold. Here, in this example, since the protection count threshold is set to 2, in the data block DB4, the protection count count value = 1, and the protection count in step S120 meets the condition of the protection count threshold or less. Therefore, the number of iterations is kept 18 (step S145). In the data block DB5, the number of corrections after block code decoding is equal to or less than the correction threshold, the protection count is added, and the protection count value = 2. On the other hand, in the next data block DB5, the number of iterations is 18 times, and the number of corrections after block code decoding is again larger than the correction threshold, so the number of protections is reset (step S130).

  Thus, in the case of this example, by setting the protection frequency threshold to 1 or more, the number of iterations in the data block DB5 is maintained at 18, and the number of iterations and the number of block code decoding are constant. Therefore, fluctuations in power consumption can be prevented.

  As described above, in the second embodiment, in order to reduce the number of iterations, the past decoding result (protection number) stored in the iteration number protection circuit 250 is notified to the iteration number control circuit 140. Supports changes in transmission path conditions. That is, the past transmission state is observed from the past decoding result, and the number of iterations by iterative decoding is not reduced unless the transmission state continues to some extent. As described above, in this embodiment, by determining the number of protection times, unnecessary fluctuations in power consumption can be suppressed when the transmission path state is fluctuating.

  It should be noted that the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the scope of the present invention.

  For example, in the above-described embodiment, the hardware configuration has been described. However, the present invention is not limited to this, and arbitrary processing can be realized by causing a CPU (Central Processing Unit) to execute a computer program. is there. In this case, the computer program can be stored and provided to a computer using various types of non-transitory computer readable media. Non-transitory computer readable media include various types of tangible storage media. Examples of non-transitory computer-readable media include magnetic recording media (for example, flexible disks, magnetic tapes, hard disk drives), magneto-optical recording media (for example, magneto-optical disks), CD-ROMs (Read Only Memory), CD-Rs, CD-s. R / W, semiconductor memory (for example, mask ROM, PROM (ProgrammableROM), EPROM (ErasablePROM), flash ROM, RAM (randomaccessmemory)). The program may also be supplied to the computer by various types of transitory computer readable media. Examples of transitory computer readable media include electrical signals, optical signals, and electromagnetic waves. The temporary computer-readable medium can supply the program to the computer via a wired communication path such as an electric wire and an optical fiber, or a wireless communication path.

1 Iterative decoding input data 2 Data after iterative decoding 3 Data after block code decoding 4 Number of corrections 5 Correction threshold 6 Threshold comparison result 7 Correction enable / disable signal 8 Iteration count counter value 9 Iteration setting count 10 Iteration number initial value 11 Iterative decoding end 12 Iterations Decoding continuation 13 Protection count threshold 14 Repetition count retention reduction 120 Iterative decoding circuit 140 Iteration count control circuit 150 Block code decoding circuit 200 Iteration decoding stop control circuit 210 Iteration count counter circuit 220 Iteration count setting circuit 230 Correction count threshold comparison circuit 240 Threshold Setting circuit 250 Iteration number protection circuit 510 Input buffer 520 Turbo coder 540 Control unit 550 RS decoder 570 Output buffer 580 Memory

Claims (18)

An iterative decoding circuit for error correction of input data by an iterative decoding method;
A block code decoding circuit that performs error correction by block code decoding on the iteratively decoded data error-corrected by the iterative decoding circuit;
A correction number threshold comparison circuit for comparing the number of corrections of block code decoding in the block code decoding circuit with a preset correction threshold;
An iterative number control circuit for controlling the iterative decoding number of the iterative decoding circuit,
The iteration number control circuit controls the number of iterations based on an error correction result of the block code decoding circuit and a comparison result of the correction number threshold comparison circuit.   The error correction apparatus according to claim 1, wherein the correction threshold is a value determined based on an error correction capability of the block code decoding circuit and an iterative decoding correction capability of the iterative decoding circuit. It further includes an iterative number protection circuit for determining whether to increase or decrease the set number of times,
The iterative number protection circuit counts the number of times the number of corrections is less than or equal to the correction threshold,
The error correction apparatus according to claim 1, wherein the iteration number control circuit reduces the set number of times according to a count result of the iteration number protection circuit. The iterative decoding circuit performs iterative decoding a preset number of times, and
The iteration count control circuit maintains the set count when the correction count threshold comparison circuit determines that the correction count is greater than the correction threshold, and the correction count threshold comparison circuit sets the correction count to the correction threshold. The error correction device according to claim 1, wherein the number of times of setting is reduced when it is determined that:   The iterative decoding circuit performs iterative decoding a preset number of times. When the block code decoding circuit determines that correction of the iteratively decoded data is impossible, the iterative number control circuit The error correction device according to claim 1, wherein the set number of times is increased, and the iterative decoding circuit performs iterative decoding again.   The error correction apparatus according to claim 2, wherein the correction threshold is a value set according to an error correction number of one iteration decoding in the iterative decoding circuit and a maximum correction number in the block code decoding circuit. The error correction apparatus according to claim 6, wherein the correction threshold is a value set by the following equation.
Correction threshold ≦ (maximum number of block code decoding corrections) − (number of error corrections for one iteration decoding) The iteration number control circuit includes:
An iterative number setting circuit for setting a setting number for specifying the number of times the iterative decoding circuit performs iterative decoding; and
An iterative number counter circuit for counting the number of iterative decoding times of the iterative decoding circuit;
The error according to any one of claims 1 to 7, further comprising: an iterative decoding stop control circuit that stops decoding of the iterative decoding circuit when a count value of the iterative number counter circuit reaches the set number of times. Correction device. The iterative number protection circuit compares a count value in which the number of corrections is equal to or less than the correction threshold value with a preset protection frequency threshold value,
The error correction apparatus according to claim 3, wherein the iteration number control circuit subtracts the setting circuit when the count value reaches the protection number threshold. A threshold setting circuit;
The error correction apparatus according to claim 9, wherein the correction threshold value comparison circuit and the iteration number protection circuit are set with the correction threshold value and the protection frequency threshold value by the threshold setting circuit, respectively.   The error correction apparatus according to claim 9 or 10, wherein the protection frequency threshold is set according to a degree of fluctuation of a transmission state. Error correction is performed by iteratively decoding the input block data by a preset number of times using an iterative decoding method,
Error-correcting the iteratively decoded data error-corrected by the iterative decoding by block code decoding;
An error correction method for determining the set number of block data to be input next based on an error correction result of the block code decoding and a comparison result between a correction number of the block code decoding and a preset correction threshold.   The error correction method according to claim 12, wherein the correction threshold is a value determined based on an error correction capability in block code decoding and a correction capability in iterative decoding. After error correction by the block code decoding, count the number of times the number of corrections in the block code decoding is equal to or less than a preset correction threshold,
Next, the number of times of setting the block data to be input is considered in consideration of the count result as well as the error correction result of the block code decoding and the comparison result between the correction number of the block code decoding and a preset correction threshold. The error correction method according to claim 12 or 13, wherein the error correction method is determined.   5. The set number of times is maintained when it is determined that the number of corrections is greater than the correction threshold value, and the set number of times is reduced when it is determined that the number of corrections is equal to or less than the correction threshold value. The error correction method described in the paragraph.   The error correction method according to claim 12, wherein when it is determined that correction of the iteratively decoded data by the block code decoding is impossible, the set number of times is increased and iterative decoding is performed again. Compare the count value in which the number of corrections in the block code decoding is equal to or less than a preset correction threshold with a preset protection frequency threshold,
The error correction method according to claim 14, wherein when the count value reaches the protection count threshold, the setting circuit is subtracted. An iterative decoding circuit for error correction of input data by an iterative decoding method;
A block code decoding circuit that performs error correction by block code decoding on the iteratively decoded data error-corrected by the iterative decoding circuit;
An iterative number control circuit for controlling the iterative decoding number of the iterative decoding circuit,
The iterative number control circuit controls the number of times of iterative decoding based on an error correction result in the block code decoding circuit and a correction number of block code decoding.

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