JP2012151220A - Capacitive element, method of manufacturing the same, and semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a capacitive element capable of preventing an increase in conductor loss in a high frequency band and capable of achieving low-loss operation in a wide frequency range, to provide a method of manufacturing the same, and to provide a semiconductor integrated circuit.SOLUTION: A capacitive element 10 of the present invention includes a first electrode 11, a dielectric layer 12 provided on the first electrode 11, and a second electrode 13 provided on the dielectric layer 12. The capacitive element 10 has a sandwich structure in which the dielectric layer 12 is sandwiched between the first electrode 11 and the second electrode 13, and concavity and convexity are provided on the outer surface of the second electrode 13.

Description

  The present invention relates to a capacitive element, a method for manufacturing the same, and a semiconductor integrated circuit, and more specifically, a capacitive element that can suppress an increase in conductor loss in a high frequency band and realize low-loss operation in a wide frequency range. And a method for manufacturing the same and a semiconductor integrated circuit.

  In general, a capacitive element is an indispensable element for many analog circuits, and is widely used regardless of a mounting substrate or an integrated circuit. In addition, it is desired that the capacitive element has a low loss. Capacitance loss is roughly divided into dielectric loss and resistance loss, and various measures for reducing each loss have been studied.

  In order to reduce the dielectric loss, it is conceivable to improve the dielectric material, composition and manufacturing method. For example, in Patent Document 1, a MIM (Metal-Insulator-Metal) capacitor formed between wiring layers is miniaturized, and at the same time, a low temperature coefficient and high reliability are realized. The first problem is that a dielectric material having a high dielectric constant is generally susceptible to structural defects and is less reliable as a capacitor. Second, a material having a high dielectric constant has a large temperature change in the dielectric constant. Therefore, the capacitance changes due to a change in the environmental temperature and the operating state, and the circuit operation varies. 3. The above two problems are mutually contradictory, that is, if the structural defect is reduced and the reliability is improved, the temperature change increases, and if the temperature change is reduced, the reliability is And the like that is in the defeated and will relationship.

  In order to solve such a problem, in Patent Document 1, the dielectric film of the capacitor is composed of a first dielectric film mainly composed of aluminum oxide and a second dielectric composed mainly of crystallized niobium oxide. It is a laminated film with a body film.

  Further, the resistance loss can be reduced by improving the material of the electrode conductor and improving the loss by optimizing the planar shape of the electrode. For example, in Patent Document 2, the MIM capacitor achieves both low loss, downsizing, and high reliability, and the MIM capacitor is effective in the direction perpendicular to the signal propagation direction. Loss is reduced by setting the width and length so that the ratio of the effective width and the effective length in the direction parallel to the signal propagation direction corresponds to the desired value of the resistance component It is a thing. In addition, by reducing the thickness of the lower capacitor electrode, sufficient reliability can be obtained even if the dielectric film is thinned. By reducing the thickness of the dielectric film, sufficient capacity can be obtained even if the area is reduced. In this way, the size is reduced.

JP 2006-173175 A JP 2001-332690 A

  However, in recent years, the frequency characteristics of active elements such as transistors have been continuously improved, and the operating frequency of circuits using them has been increasing. As the signal frequency increases, the resistance increases and the conductor loss tends to increase. Therefore, the conventional technique that has realized low loss in a low frequency band has a problem that the effect of reducing the loss is lost in a high frequency band.

  FIGS. 8A and 8B are configuration diagrams for explaining a conventional capacitive element, FIG. 8A is a perspective view, and FIG. 8B is a substantial conduction range of FIG. 8A. It is sectional drawing of the 2nd electrode which shows this. In the figure, reference numeral 110 denotes a capacitive element, 111 denotes a first electrode, 112 denotes a dielectric layer, 113 denotes a second electrode, 113a denotes an internal region portion of the second electrode 113, and 113b denotes a skin portion of the second electrode 113. . Here, d represents the thickness of the second electrode 113, and δ represents the thickness of the skin portion 113b of the second electrode 113.

  The conventional capacitive element 110 includes a first electrode 111, a dielectric layer 112 provided on the first electrode 111, and a second electrode 113 provided on the dielectric layer 112. . That is, the capacitive element 110 has a sandwich structure in which the dielectric layer 112 is sandwiched between the first electrode 111 and the second electrode 113.

  Further, as shown in FIG. 8B, the second electrode 113 has a thickness d and an internal region portion 113a, and the skin portion 113b of the second electrode 113 has a thickness δ. That is, the second electrode 113 includes a skin portion 113b capable of signal propagation and an internal region portion 113a capable of signal propagation.

  When the propagation direction of the signal is a direction perpendicular to the paper surface, the signal propagates only near the surface of the conductor. Even if the thickness d of the second electrode 113 is increased in order to reduce the resistance of the second electrode 113 of the capacitive element, the signal is not transmitted to the internal region 113a of the second electrode 113 at a high frequency, and compared with the case of a low frequency. Resistance increases and signal loss increases. When the material of the second electrode 113 is gold, the thickness δ of the skin portion is about 0.32 μm when the signal frequency is 60 GHz. Therefore, when the thickness d of the second electrode 113 is 0.64 μm or more, there is a region where a signal of 60 GHz is not conducted, and there is a problem that the loss with respect to the high-frequency signal becomes large as described above.

  The present invention has been made in view of such a problem, and an object of the present invention is to suppress an increase in conductor loss in a high frequency band and realize low-loss operation in a wide frequency range. It is an object of the present invention to provide a capacitor element, a manufacturing method thereof, and a semiconductor integrated circuit.

  The present invention has been made to achieve such an object, and the invention according to claim 1 includes a first electrode, a dielectric layer provided on the first electrode, and the dielectric layer. In the capacitive element including the second electrode provided on the concave and convex portions on the outer surface of the first electrode or the second electrode that is not in contact with the dielectric layer or the inner surface that is in contact with the dielectric layer A capacitor element comprising: (FIG. 1; embodiment)

  The invention described in claim 2 is characterized in that, in the invention described in claim 1, an uneven portion formed by lift-off is provided on the outer surface of the second electrode that is not in contact with the dielectric layer. And (FIG. 2; Example 1)

  The invention according to claim 3 is characterized in that, in the invention according to claim 1, an uneven portion formed by etching is provided on the outer surface of the second electrode that is not in contact with the dielectric layer. And (FIG. 4; Example 2)

  According to a fourth aspect of the present invention, in the first aspect of the present invention, an uneven surface is provided on the outer surface of the first electrode that is not in contact with the dielectric layer. (FIG. 6; Example 3)

  The invention according to claim 5 is the invention according to any one of claims 1 to 4, wherein the first electrode and the second electrode are metal, and the dielectric is an insulator. To do.

  The invention according to claim 6 is the invention according to any one of claims 1 to 5, wherein the height of the uneven portion is 10% or more and 90% of the thickness of the first electrode or the second electrode. It is characterized by the following.

  The invention according to claim 7 is the invention according to any one of claims 1 to 6, wherein the first electrode is provided on a semiconductor substrate.

  According to an eighth aspect of the present invention, there is provided a semiconductor integrated circuit comprising the capacitive element according to any one of the first to seventh aspects.

  According to a ninth aspect of the present invention, there is provided a capacitive element including a first electrode, a dielectric layer provided on the first electrode, and a second electrode provided on the dielectric layer. In the method, the first step of forming a first electrode, the second step of forming a dielectric layer on the first electrode formed by the first step, and the second step. A third step of forming a second electrode on the dielectric, and is in contact with the outer surface of the first electrode or the second electrode that is not in contact with the dielectric layer or with the dielectric layer. It includes a step of forming an uneven portion on the inner surface. (FIG. 1; embodiment)

  The invention described in claim 10 is characterized in that, in the invention described in claim 9, an uneven portion is formed by lift-off on the outer surface of the second electrode that is not in contact with the dielectric layer. (FIG. 3; Example 1)

  According to an eleventh aspect of the present invention, in the ninth aspect of the invention, an uneven portion is formed by etching on the outer surface of the second electrode that is not in contact with the dielectric layer. (FIG. 5; Example 2)

  The invention described in claim 12 is characterized in that, in the invention described in claim 9, an uneven portion is formed on the outer surface of the first electrode that is not in contact with the dielectric layer. (FIG. 7; Example 3)

  The invention according to claim 13 is the invention according to any one of claims 9 to 12, wherein the first electrode and the second electrode are metal, and the dielectric is an insulator. To do.

  The invention according to claim 14 is the invention according to any one of claims 9 to 13, wherein the height of the uneven portion is 10% or more and 90% of the thickness of the first electrode or the second electrode. It is characterized by the following.

  According to a fifteenth aspect of the present invention, in the invention according to the ninth aspect, the step of forming a concavo-convex portion on the surface of the first electrode or the second electrode includes laminating an electrode material over the entire region of the electrode. And a step of laminating an electrode material on a partial region of the electrode.

  The invention according to claim 16 is the invention according to claim 15, wherein a part of the first electrode or the second electrode is composed of a plurality of linear regions.

  The invention according to claim 17 is the invention according to claim 9, wherein the step of forming a concavo-convex portion on the surface of the first electrode or the second electrode comprises applying an electrode material to the entire region of the electrode. The method includes a step of stacking and a step of removing a part of the stacked electrode material.

  The invention according to claim 18 is characterized in that, in the invention according to claim 17, a part of the laminated electrode material comprises a plurality of linear regions.

  The invention according to claim 19 is the invention according to any one of claims 9 to 18, wherein the first electrode is formed on a semiconductor substrate.

  According to the present invention, in a capacitive element including a first electrode, a dielectric layer provided on the first electrode, and a second electrode provided on the dielectric layer, the first electrode or the second electrode Since the concave and convex portions are provided on the outer surface that is not in contact with the dielectric layer or on the inner surface that is in contact with the dielectric layer, the increase in the conductor loss in the high frequency band is suppressed, and the operation with low loss in a wide frequency range is achieved. It is possible to provide a capacitive element that can be realized, a manufacturing method thereof, and a semiconductor integrated circuit.

BRIEF DESCRIPTION OF THE DRAWINGS It is a block diagram for describing embodiment of the capacitive element which concerns on this invention, (a) is a perspective view, (b) is sectional drawing of the 2nd electrode which shows the substantial conduction range of (a). It is a section lineblock diagram for explaining Example 1 of a capacity element concerning the present invention. (A) thru | or (c) are process drawings for demonstrating the manufacturing method of Example 1 of the capacitive element which concerns on this invention. It is a cross-sectional block diagram for demonstrating Example 2 of the capacitive element which concerns on this invention. (A) thru | or (c) are process drawings for demonstrating the manufacturing method of Example 2 of the capacitive element which concerns on this invention. It is a cross-sectional block diagram for demonstrating Example 3 of the capacitive element which concerns on this invention. (A) thru | or (c) are process drawings for demonstrating the manufacturing method of Example 3 of the capacitive element which concerns on this invention. It is a block diagram for demonstrating the conventional capacitive element, (a) is a perspective view, (b) is sectional drawing of the 2nd electrode which shows the substantial conduction range of (a).

Embodiments of the present invention will be described below with reference to the drawings.
FIG. 1 is a configuration diagram for explaining an embodiment of a capacitive element according to the present invention, FIG. 1 (a) is a perspective view, and FIG. 1 (b) shows a substantial conduction range of FIG. 1 (a). It is sectional drawing of a 2nd electrode. In the figure, reference numeral 10 denotes a capacitive element, 11 denotes a first electrode, 12 denotes a dielectric layer, 13 denotes a second electrode, 13a denotes an internal region portion of the second electrode 13, and 13b denotes a convex portion (skin portion) of the second electrode 13. , 13c indicate concave portions of the second electrode 13. Where δ is the thickness of the skin portion 13b of the second electrode 13, a is the width of the convex portion, b is the height of the convex portion (depth of the groove of the concave portion), c is the width of the concave portion, and d is the thickness of the second electrode 13. Show.

  The capacitive element 10 of the present invention includes a first electrode 11, a dielectric layer 12 provided on the first electrode 11, and a second electrode 13 provided on the dielectric layer 12. . That is, the capacitive element 10 has a sandwich structure in which the dielectric layer 12 is sandwiched between the first electrode 11 and the second electrode 13, and is in contact with the outer surface of the second electrode 13, that is, the dielectric layer 12. The uneven surface is provided with an uneven surface.

  Further, as shown in FIG. 1B, the second electrode 13 has a thickness d and an internal region portion 13a, and the skin portion 13b of the second electrode 13 has a thickness δ. That is, the second electrode 13 includes a skin portion 13b capable of signal propagation and an internal region portion 13a capable of signal propagation. Furthermore, the surface (outer surface) of the second electrode 13 is a concavo-convex surface, and has a convex portion width a, a concave portion width c, and a convex portion height (depth of groove in the concave portion) b.

  That is, the capacitive element 10 according to the first embodiment of the present invention is a capacitive element including the first electrode 11, the second electrode 13, and the dielectric layer 12 sandwiched between the first electrode 11 and the second electrode 13. In addition, the surface (outer surface) that is not in contact with the dielectric layer 12 of one of the two electrodes is provided with an uneven portion.

<Definition of irregularities>
The uneven portion on the surface of the second electrode 13 effectively suppresses an increase in conductor loss in a high frequency band and effectively realizes a low loss operation in a wide frequency range. It is preferably 10% or more and 90% or less, and more preferably 30% or more and 90% or less. That is, the thickness b, which is the difference between the top of the convex part and the bottom of the concave part, is preferably 10% or more and 90% or less of the thickness d of the second electrode 13, and more preferably 30% or more and 90% or less. .

<Uneven shape>
Examples of the shape of the convex portion include those having a dot-like top, those having a linear top, and those having a lattice-like top. From the viewpoint of effectively suppressing the increase in conductor loss in a high frequency band and effectively realizing low-loss operation in a wide frequency range, some having a linear top in a direction parallel to the electric conduction direction preferable.

<Locations where irregularities are formed>
In the capacitive element shown in FIG. 1, the outer surface of one second electrode 13 has an uneven portion, but the outer surface of the other first electrode 11 also has an uneven portion, or at least The surface (inner surface) in contact with the dielectric layer of one or both electrodes may have a concavo-convex portion, or a combination thereof. In order to effectively suppress the increase in conductor loss in the high frequency band and effectively realize low-loss operation in a wide frequency range, the inner and outer surfaces of the two electrodes have uneven portions. Form is preferred. From the viewpoint of controlling the electrostatic capacitance as a capacitive element, a form having an uneven portion on the outer surface of the two electrodes is preferable. From the viewpoint of forming by an easy process, a form in which the outer surface of one electrode has irregularities is preferable.

<Configuration of electrode>
The electrode is not particularly limited as long as it has conductivity, but when the capacitor element of the present invention is formed on a semiconductor substrate, it may be a metal from the viewpoint that an existing semiconductor process can be used. Preferable examples include gold, aluminum, copper, and alloys mainly composed of each, but are not limited thereto.

<Configuration of dielectric layer>
Although it does not restrict | limit especially as a dielectric material layer, When forming the capacitive element of this invention on a semiconductor substrate, a thing with a high dielectric constant is preferable from a viewpoint which can use the existing semiconductor process, Specifically, Examples include SiN or SiO _2, but not limited thereto.

<Operational effects of the invention>
FIG. 1B is a cross-sectional view of one second electrode 13 having the concave and convex portions of the capacitive element shown in FIG. 1A. The operation of the capacitive element of the present invention is shown in FIG. 1B. Is described below.

  When an electric signal is transmitted through a conductor, if the frequency of the signal is increased, the signal cannot be transmitted into the conductor due to the skin effect. At this time, the thickness δ of the skin capable of propagating a signal is expressed by the following equation.

  Here, δ is the thickness of the skin capable of propagating the signal, ω is the angular frequency of the signal, μ is the magnetic permeability of the space, and σ is the conductivity of the conductor. The higher the signal frequency, the thinner the skin that can propagate the signal.

  FIG. 1B is a cross-sectional view of one second electrode 13 having the concavo-convex portion of the capacitive element shown in FIG. In the electrode shape of the present invention, when the signal frequency is increased and the skin thickness is thinner than the electrode thickness, the signal propagation region is difficult to decrease, that is, the resistance increases as shown in FIG. By taking a difficult shape, loss can be reduced.

  As shown in FIG. 1B, a signal propagates when the width of the convex portion 13b is a, the height of the convex portion is b, the interval between the convex portions (the width of the concave portion) is c, and the thickness of the entire electrode is d. In order to widen the region to be processed and to narrow the inner region portion 13a where the signal cannot propagate, when the skin thickness corresponding to the main signal frequency is δ, the width a of the convex portion 13b is 2 × δ. It is desirable that the height b of the convex portion 13b is substantially equal to d-2 × δ, and the interval (width of the concave portion) c between the convex portions 13b is as small as possible.

  The capacitive element of the present invention may be in the form of a single element externally arranged on the mounting substrate, or may be in the form of an on-chip capacitor incorporated on the semiconductor substrate. If the capacitive element of the present invention is an on-chip capacitor, it is possible to easily design a capacitive element having a shape and material suitable for the operating frequency of a semiconductor integrated circuit in which the capacitive element is used. In addition, if the capacitive element of the present invention is an on-chip capacitor, it can be produced in the manufacturing process of an existing semiconductor integrated circuit.

<Description of Semiconductor Integrated Circuit>
A semiconductor integrated circuit including the capacitive element of the present invention can suppress an increase in conductor loss in a high frequency band and can realize a low-loss operation in a wide frequency range.

<Capacitance element manufacturing method>
A method for manufacturing the capacitive element according to the above-described embodiment of the present invention will be described.

  In the capacitive element 10 of the present embodiment, a step of forming the first electrode 11, a step of forming the dielectric layer 12 on the first electrode 11, and a second electrode 13 on the dielectric layer 12 are formed. And at least one of the steps of forming the first electrode 11 and the second electrode 13 includes a step of forming an uneven portion of 10% to 90% of the thickness of the electrode on the surface of the electrode. It can be obtained by a device manufacturing method.

  FIG. 2 is a cross-sectional configuration diagram for explaining Example 1 of the capacitive element according to the present invention. In the figure, reference numeral 20 denotes a capacitive element, 21 denotes a first electrode, 22 denotes a dielectric layer, 23 denotes a second electrode, 23a denotes a flat plate portion constituting the second electrode 23, 23b denotes a convex portion constituting the second electrode 23, Reference numeral 23c denotes a recess of the second electrode 23, and reference numeral 24 denotes a semiconductor substrate.

  The capacitive element 20 according to the first embodiment of the present invention includes a first electrode 21 provided on the semiconductor substrate 24, a dielectric layer 22 provided on the first electrode 21, and a dielectric layer 22 on the dielectric layer 22. It is comprised from the 2nd electrode 23 which has the flat part 23a which comprises the provided 2nd electrode 23, and the convex part 23b provided on the flat plate part 23a. That is, the capacitive element 20 has a sandwich structure in which the dielectric layer 22 is sandwiched between the first electrode 21 and the second electrode 23, and an uneven portion is provided on the outer surface of the second electrode 23.

  3A to 3C are process diagrams for explaining the manufacturing method of the first embodiment of the capacitive element according to the present invention.

  The capacitive element according to the first embodiment of the present invention includes a step of forming the first electrode 21 on the semiconductor substrate 24, a step of forming the dielectric layer 22 on the first electrode 21, and the dielectric layer 22 on the dielectric layer 22. Forming the second electrode 23, and the step of forming the second electrode 23 forms an unevenness of 10% to 90% of the thickness of the second electrode 23 on the outer surface of the second electrode 23. It is a manufacturing method of a capacitive element including a process.

<Lift off>
First, the first electrode 21 is formed on the semiconductor substrate 24, the dielectric layer 22 is formed on the first electrode 21, and the flat plate portion 23 a constituting the second electrode 23 is formed on the entire dielectric layer 22. Form (FIG. 3A). Next, after forming the resist 25 on the flat plate portion 23a, the electrode 23b constituting the convex portion of the second electrode is laminated (FIG. 3B). Finally, by removing the resist 25, a capacitive element having the second electrode 23 having a concavo-convex portion on the surface of the flat plate portion 23a is obtained (FIG. 3C). That is, the second electrode 23 has a convex portion 23 b constituting the second electrode 23 and a concave portion 23 c of the second electrode 23.

  At this time, the second electrode 23 having desired irregularities can be formed by setting the thickness of the resist 25 and the thickness of the flat plate portion 23a and the convex portion 23b to a desired size.

  Moreover, the process of forming an uneven | corrugated | grooved part on the surface of the said 1st electrode 21 or the 2nd electrode 23 has the process of laminating | stacking electrode material in the area | region of the whole electrode, and laminating | stacking electrode material in the one part area | region of an electrode, Is included.

  In addition, by forming the resist 25 in a plurality of linear shapes (stripe shapes) extending in a direction parallel to the electric propagation direction, it is possible to effectively suppress an increase in conductor loss in a high frequency band, and to achieve a wide frequency range. Thus, it is possible to effectively realize a low-loss operation.

FIG. 4 is a cross-sectional configuration diagram for explaining Example 2 of the capacitive element according to the present invention.
In the figure, reference numeral 30 denotes a capacitive element, 31 denotes a first electrode, 32 denotes a dielectric layer, 33 denotes a second electrode, 33a denotes a flat plate portion constituting the second electrode 23, 33b denotes a concave portion of the second electrode 33, and 34 denotes a semiconductor. A substrate 35 is a region of the flat plate portion 33a, and 36 is a resist.

  The capacitive element 30 according to the second embodiment of the present invention includes a first electrode 31 provided on the semiconductor substrate 34, a dielectric layer 32 provided on the first electrode 31, and a dielectric layer 32 on the dielectric layer 32. It is comprised from the 2nd electrode 33 which has the flat part 33a which comprises the provided 2nd electrode, and the recessed part 33b provided in the flat plate part 33a. That is, the capacitive element 30 has a sandwich structure in which the dielectric layer 32 is sandwiched between the first electrode 31 and the second electrode 33, and an uneven portion is provided on the outer surface of the second electrode 33.

  5A to 5C are process diagrams for explaining a manufacturing method of the second embodiment of the capacitive element according to the present invention.

  The capacitive element according to the second embodiment of the present invention includes a step of forming the first electrode 31 on the semiconductor substrate 34, a step of forming the dielectric layer 32 on the first electrode 31, and the dielectric layer 32. The step of forming the second electrode 33, and the step of forming the second electrode 33 forms a concavo-convex portion of 10% to 90% of the thickness of the second electrode 33 on the outer surface of the second electrode 33. A method for manufacturing a capacitive element including the step of:

<Etching>
First, the first electrode 31 is formed on the semiconductor substrate 34, the dielectric layer 32 is formed on the first electrode 31, and the flat plate portion 33a constituting the second electrode is formed on the entire dielectric layer 32. (FIG. 5A). Next, after a resist 36 is formed on the flat plate portion 33a, the region 35 where the flat plate portion 33a is exposed is etched using the resist 36 as a mask (FIG. 4B). Finally, by removing the resist 36, a capacitive element having the second electrode 33 having a concavo-convex portion on the surface of the flat plate portion 33a is obtained (FIG. 4C). That is, the second electrode 33 has a concave portion 33 b in the flat plate portion 33 a constituting the second electrode 33.

  At this time, by setting the thickness and etching amount of the flat plate portion 33a to a desired size, the second electrode 33 having a desired uneven portion can be formed.

  Further, the step of forming the concavo-convex portion on the surface of the first electrode 31 or the second electrode 33 includes the step of laminating the electrode material in the entire electrode region and the step of removing a part of the laminated electrode material. It is out.

  Further, by forming the resist 36 in a plurality of linear shapes (stripe shapes) extending in a direction parallel to the electric propagation direction, it is possible to effectively suppress an increase in conductor loss in a high frequency band, and to widen the frequency range. Thus, it is possible to effectively realize a low-loss operation.

  FIG. 6 is a cross-sectional configuration diagram for explaining Example 3 of the capacitive element according to the present invention. In the figure, reference numeral 40 denotes a capacitive element, 41 denotes a first electrode, 41a denotes a flat plate portion constituting the first electrode 41, 41b denotes a convex portion of the first electrode, 42 denotes a dielectric layer, 43 denotes a second electrode, and 44 denotes a semiconductor. A substrate 45 indicates an insulator.

  The capacitive element 40 according to the third embodiment of the present invention includes a first electrode 41 provided on the semiconductor substrate 44, a dielectric layer 42 provided on the first electrode 41, and a dielectric layer 42 on the dielectric layer 42. The second electrode 43 is provided. That is, the capacitive element 40 has a sandwich structure in which the dielectric layer 42 is sandwiched between the first electrode 41 and the second electrode 43, and an uneven portion is formed on the outer surface of the first electrode 41 in contact with the semiconductor substrate 44. Is provided.

  7A to 7C are process diagrams for explaining a manufacturing method of the capacitive element according to the third embodiment of the present invention.

  The capacitive element according to the third embodiment of the present invention includes a step of forming the first electrode 41 on the semiconductor substrate 44, a step of forming the dielectric layer 42 on the first electrode 41, and the dielectric layer 42. The step of forming the second electrode 43, and the step of forming the first electrode 41 forms an uneven portion of 10% to 90% of the thickness of the first electrode 41 on the outer surface of the first electrode 41. A method for manufacturing a capacitive element including the step of:

<Forming on the outer surface of the first electrode (polishing)>
First, the insulator 45 is partially formed on the semiconductor substrate 44, and the first electrode 41a is formed on the insulator 45 and the semiconductor substrate 44 (FIG. 5A). Next, the convex portions 41b on the surface of the first electrode 41 that are not in contact with the semiconductor substrate 44 are made uniform (FIG. 5B). Finally, by laminating the dielectric layer 42 and the second electrode 43, a capacitive element having an uneven portion on the outer surface of the first electrode 41 in contact with the semiconductor substrate 44 is obtained (FIG. 5C).

  At this time, it is possible to form the first electrode 41 having a desired uneven portion by setting the thickness of the first electrode 41 and the etching amount at the time of homogenization to a desired size. Further, when the step of uniforming the surface is not performed, uneven portions are formed on both the inner surface of the first electrode 41 and the second electrode 43 that are in contact with the dielectric layer 42 and the outer surface that is not in contact with the dielectric layer 42. It is possible. From the viewpoint of controlling the capacitance of the capacitive element, it is preferable to have a surface uniformizing step.

  Further, by forming the insulator 45 in a plurality of linear shapes (stripe shapes) extending in a direction parallel to the electric propagation direction, it is possible to effectively suppress an increase in conductor loss in a high frequency band, and to achieve a wide frequency range. It is possible to effectively realize a low-loss operation within the range.

<About other manufacturing methods>
In addition, in order to form an uneven part on the inner surface of the first electrode, the process performed on the second electrode in Examples 1 and 2 shown in FIGS. 3 and 5 is applied to the first electrode. In order to form an uneven portion on the inner surface of the second electrode, the process performed on the first electrode in Example 3 shown in FIG. 7 is applied to the second electrode. It is feasible.

  The present invention relates to a capacitive element capable of suppressing an increase in conductor loss in a high frequency band and realizing low-loss operation in a wide frequency range, a manufacturing method thereof, and a semiconductor integrated circuit. A semiconductor device having the same can be realized.

10, 20, 30, 40 Capacitance elements 11, 21, 31, 41 First electrodes 12, 22, 32, 42 Dielectric layers 13, 23, 33, 43 Second electrode 13a Internal region portion 13b of second electrode Second Electrode convex part (skin part)
13c Recess 23a of second electrode Flat plate portion 23b constituting second electrode Convex portion 23c constituting second electrode Recesses 24, 34, 44 of second electrode Semiconductor substrate 25 Resist 33a Flat plate portion 33b constituting second electrode Two-electrode concave portion 35 Second-electrode flat-plate region 36 Resist 41a Flat-plate portion 41b constituting the first electrode First-electrode convex portion 45 Insulator 110 Capacitor element 111 First electrode 112 Dielectric layer 113 Second electrode 113a Inner region portion 113b of second electrode Skin portion of second electrode

Claims (19)

In a capacitive element including a first electrode, a dielectric layer provided on the first electrode, and a second electrode provided on the dielectric layer,
A capacitor element comprising an uneven portion on an outer surface of the first electrode or the second electrode not in contact with the dielectric layer or an inner surface in contact with the dielectric layer.   2. The capacitive element according to claim 1, further comprising an uneven portion formed by lift-off on an outer surface of the second electrode that is not in contact with the dielectric layer.   2. The capacitive element according to claim 1, further comprising an uneven portion formed by etching on an outer surface of the second electrode that is not in contact with the dielectric layer.   2. The capacitive element according to claim 1, wherein an uneven surface is provided on an outer surface of the first electrode that is not in contact with the dielectric layer.   5. The capacitive element according to claim 1, wherein the first electrode and the second electrode are metal, and the dielectric is an insulator.   6. The capacitive element according to claim 1, wherein a height of the uneven portion is 10% or more and 90% or less of a thickness of the first electrode or the second electrode.   The capacitive element according to claim 1, wherein the first electrode is provided on a semiconductor substrate.   A semiconductor integrated circuit comprising the capacitive element according to claim 1. In a method for manufacturing a capacitive element comprising a first electrode, a dielectric layer provided on the first electrode, and a second electrode provided on the dielectric layer,
A first step of forming a first electrode; a second step of forming a dielectric layer on the first electrode formed by the first step; and the dielectric formed by the second step. A third step of forming a second electrode on the body,
A method of manufacturing a capacitive element, comprising: forming an uneven portion on an outer surface of the first electrode or the second electrode that is not in contact with the dielectric layer or an inner surface of the first electrode or the second electrode that is in contact with the dielectric layer. .   10. The method of manufacturing a capacitive element according to claim 9, wherein an uneven portion by lift-off is formed on an outer surface of the second electrode that is not in contact with the dielectric layer.   10. The method of manufacturing a capacitive element according to claim 9, wherein an uneven portion is formed by etching on an outer surface of the second electrode that is not in contact with the dielectric layer. 11.   The method for manufacturing a capacitive element according to claim 9, wherein an uneven portion is formed on an outer surface of the first electrode that is not in contact with the dielectric layer.   13. The method for manufacturing a capacitive element according to claim 9, wherein the first electrode and the second electrode are metal, and the dielectric is an insulator.   14. The method of manufacturing a capacitive element according to claim 9, wherein a height of the uneven portion is 10% or more and 90% or less of a thickness of the first electrode or the second electrode.   The step of forming a concavo-convex portion on the surface of the first electrode or the second electrode includes a step of laminating an electrode material in a region of the entire electrode, and a step of laminating an electrode material in a partial region of the electrode. The method of manufacturing a capacitive element according to claim 9, comprising:   The method for manufacturing a capacitive element according to claim 15, wherein a part of the first electrode or the second electrode includes a plurality of linear regions.   The step of forming a concavo-convex portion on the surface of the first electrode or the second electrode includes a step of laminating an electrode material in a region of the entire electrode and a step of removing a part of the laminated electrode material. The method of manufacturing a capacitive element according to claim 9.   The method for manufacturing a capacitive element according to claim 17, wherein a part of the laminated electrode material includes a plurality of linear regions.   The method for manufacturing a capacitive element according to claim 9, wherein the first electrode is formed on a semiconductor substrate.

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