JP2012150631A - Design method and design device for semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a circuit design method capable of reducing an unnecessary region and suppressing occurrence of wiring congestion.SOLUTION: Referring to a data flow and defining a register group operating based on the same timing as a terminal point, registers from the terminal point registers to an initial point register group in a preceding stage direction operating based on the same timing are clustered as a collection. When a clustered cluster is further divided into a plurality of clusters (ST207), an initial point register shared by the divided clusters is copied (ST235) so as not to share the initial point register between the divided clusters.

Description

  The present invention relates to the field of semiconductor integrated circuits, and more particularly to a semiconductor integrated circuit design method and design apparatus.

Conventionally, when designing a semiconductor integrated circuit, a hardware description language such as RTL (Register Transfer Level) has been used to describe complicated system operations. However, in recent years, the system scale of semiconductor integrated circuits has become increasingly larger. Therefore, it is required to use a behavior level description language having a higher abstraction instead of the hardware description language, and a method of designing a circuit by behavioral synthesis using the behavior level description language is known.
In this case, circuit information designed in the behavior level description language is converted into circuit information in the RTL description language while performing automatic time scheduling. In converting to the RTL description language, there is a function of generating circuit information in the RTL description language while giving priority to the reduction of the circuit scale so as to reduce the cost. As a result, more intuitive logic design using a behavioral description language is possible, and the cost of the semiconductor chip can be reduced.

However, conventionally, circuit information in RTL description language has only been generated mechanically. Therefore, when the circuit becomes highly complicated, it is sometimes difficult to perform an appropriate floor plan even if the layout is actually performed using the generated gate level netlist.
For example, there is a case where a chip area increases due to generation of a useless area at the time of layout design or generation of wiring congestion. Therefore, even if the circuit increases in complexity, an appropriate floor plan can be made with a gate-level netlist generated by logic synthesis, as well as useless areas and wiring congestion during layout design. There is a growing demand for design methods that never happen.

Japanese Patent Laid-Open No. 2001-14377 discloses a logic synthesis system. In Patent Document 1, the position of a block area is determined in units of functions using RTL floor plan information. Then, the circuits after the logic synthesis result are grouped in cone units. Subsequently, an average value of the group sizes is obtained, and it is checked whether or not the initial group size is within an allowable range. The group is divided or integrated so that the group size is within an allowable range while making the group size uniform.
As a result, the delay information obtained in units of cones can be used as it is, and the size is made uniform, so that useless areas can be reduced. The frequency close to the actual product can reduce the frequency of redoing the floor plan.

Japanese Patent Laid-Open No. 2001-14377

Patent Document 1 appropriately divides and integrates logic synthesis blocks so as to eliminate useless areas generated during layout design.
However, in the method of Patent Document 1, wiring congestion occurs, and a region for securing wiring is required at the time of layout. As a result, there is a problem that reduction in chip area is marginalized.

That is, the logic cone has registers at its start and end points. When the logic cone is divided, the starting point register is shared with the other divided logic cones.
Even if the logic cone is divided and the useless area generated at the time of layout design is eliminated, if the divided logic cones share the start point register, this register and two or more logics are used at the time of actual layout design. It becomes necessary to newly connect the cone.
Also, sharing the start point register means that the divided logic cones must be collected starting from the start point register, so even if the group is divided so that it falls within the allowable group size, after all, They are collected and arranged by the arrangement process at the time of layout design.
Further, since a correction buffer for timing convergence is inserted, the space efficiency due to the uniform size is considerably reduced.

A method for designing a semiconductor integrated circuit according to the present invention includes:
Browse the data flow,
A group of registers that operate at the same timing is used as an end point, and a group from the end point registers to the start point register group in the previous stage that operates at the same timing is clustered as one set.
When the clustered cluster is further divided into a plurality of clusters, the start point register shared by the divided clusters is duplicated so that the start point register is not shared between the divided clusters. To do.

The semiconductor integrated circuit design apparatus of the present invention comprises:
A clustering unit that refers to the data flow, sets a group of registers that operate at the same timing as an end point, and clusters the end point registers from the end point register to the start point register group that operates at the same timing as one set,
A cluster dividing unit that further divides the clustered cluster into a plurality of clusters,
The cluster dividing unit duplicates the start point register so that the divided clusters do not share the start point register.

In the present invention, the start point register shared when the cluster is divided is duplicated so that the start point register is not shared between the clusters.
As described above, since the cluster including the start point register is completely separated, the degree of freedom of circuit arrangement is increased at the time of layout, and the occurrence of wiring congestion can be suppressed.

1 is a functional block diagram for realizing a circuit design device according to a first embodiment. 3 is a flowchart showing a processing procedure of the circuit design method according to the first embodiment. The flowchart which shows the procedure of a cluster size adjustment process. The figure which shows an example of a data flow and a cluster. The detailed flowchart of a circuit scale estimation process. A table in which start point register information and end point register information are extracted for each cluster. The figure which shows an example of a starting point register name list. The figure which shows an example of an end point register name list. The figure which shows an example of a logic cone. The figure which shows an example of estimation of the circuit information between registers. The detailed flowchart of a cluster division | segmentation process. The figure which shows an example of a cluster. The figure which shows an example of a cluster. The figure which shows an example of a cluster. The figure which shows an example of a cluster. The figure which shows an example of a cluster. The figure which shows an example of a cluster. The figure which shows an example of a cluster. The figure which shows an example of a cluster. The figure which shows an example of a cluster. The figure which shows an example of RTL description. The detailed flowchart of a downstream design process. The figure which shows the example which wiring congestion generate | occur | produces in a prior art. The figure for demonstrating the effect of 1st Embodiment. 10 is a flowchart of a circuit scale estimation process in the first modification.

Embodiments of the present invention will be described below with reference to the drawings.
(First embodiment)
FIG. 1 is a hardware configuration diagram for realizing the circuit design device according to the first embodiment.
The circuit design device 100 includes a calculation unit 200, a storage unit 300, an input unit 400, and a display unit 500.
The calculation unit 200 reads the circuit design program stored in the storage unit to realize functions as the upstream design unit 210, the behavioral synthesis unit 220, and the downstream design unit 230. Details will be described later.
In addition to the circuit design program (not shown), the storage unit 300 stores an operator library 301 and a logic cone constraint 302, and stores various data created by the calculation unit 200. is there.
The contents of the logic cone constraint 302 will also be described later together with the operation of the arithmetic unit 200.

FIG. 2 is a flowchart showing a processing procedure of the circuit design method according to the first embodiment.
The circuit design method according to the first embodiment includes an upstream design process ST100, a behavioral synthesis process ST200, and a downstream design process ST300 as main processes.
Hereinafter, each step will be described in detail.

In the upstream design process ST100, first, an operation description is read (ST101).
This behavioral description is created by a circuit designer and represents an algorithm desired to be processed by a circuit to be designed in a behavioral level description language. Then, data flow information is created based on the behavioral description (ST102). Such processing is executed by the data flow conversion unit 211.

Next, the behavioral synthesis step ST200 by the behavioral synthesis unit 220 is executed.
The behavioral synthesis step ST200 includes a cluster size adjustment step ST2001 by the cluster size adjustment unit 230 and an RTL description conversion step ST2002 by the RTL description conversion unit 240.
The cluster size adjustment step ST2001 will be described in detail with reference to FIG.
FIG. 3 is a flowchart showing the procedure of the cluster size adjustment step (ST2001).
In the cluster size adjustment step ST2001, clustering is first executed based on the data flow information (ST201).
Here, in clustering the data flow, register groups having the same time schedule are set as end points, and those from the end point registers to the start point registers in the previous stage having the same time schedule are clustered as one set.

For example, in the data flow shown in FIG. 4, the register E, the register F, and the register G are registers that operate on the same time schedule T2. Therefore, the register E, the register F, and the register G are set as end point register groups, and registers that operate in the same time schedule in the previous stage direction are extracted from the end point register groups.
At this time, it is assumed that the register A, the register B, the register C, and the register D operate with the same time schedule T1. Therefore, these register A, register B, register C, and register D are collected as a starting point register group. An end point register group (register E, register F), a start point register group (register A, register B, register C, register D), and an operator group OP0 between the end point register and the start point register are combined into one. The cluster is CL0.
The above method is applied to all information in the data flow information and clustered.
The result is output as cluster information (ST202).

  The clustering process is executed by the clustering unit 231.

  It should be noted that the extraction of “register groups having the same time schedule” is not limited to registers that all operate with the same clock, but registers that operate with different clocks can operate at the same timing. Can be summarized as operating on the same time schedule.

Next, the circuit scale is estimated by the circuit scale estimation unit 232 (ST203).
FIG. 5 is a detailed flowchart of the circuit size estimation step (ST203).
First, the start point register name and end point register name for each cluster are acquired based on the cluster information (ST221).
FIG. 6 is a table in which start point register information and end point register information are extracted for each cluster.

In FIG. 6, individual cluster information (cluster ID) is taken in the vertical direction.
Further, as the register information in the horizontal direction, for each cluster, start point register information, end point register information, and inter-register circuit information from the start point register to the end point register are represented.
The start point register information includes the number of start point registers (start point register number) and the register name. The end point register information includes the number of end point registers (the number of end point registers) and the register name.
Note that the inter-register circuit information is blank at this stage because it is estimated from now on.

FIG. 7 is a start point register name list, and FIG. 8 is an end point register name list.
The start point register name list (FIG. 7) and the end point register name list (FIG. 8) indicate register instance names.

Next, referring to the operator library 301 (ST222), the circuit scale of each cluster is estimated (ST223). The operator library 301 stores circuit scale information predicted for each operator and for each expression. Therefore, by extracting operators and expressions between the start point register group and the end point register group for each cluster, and converting the operators and expressions into circuits (specific logic circuits) using the operator library 301. The circuit scale can be estimated (ST223).
For example, when the cluster CL is converted into a specific logic circuit, a circuit block as shown in FIG. 9 is obtained.
Hereinafter, this circuit block is referred to as a logic cone L.
The logic cone L is a logic circuit block, and may be a multi-input multi-output or a multi-input single-output.
As circuit scale information, for example, the circuit scale, the number of nets, and the number of pin pairs are estimated and output as inter-register circuit information as shown in FIG. 10 (ST224).
Thereby, the estimation of the circuit scale is completed.

Returning to FIG. 3, the cluster size adjustment step ST2001 is continued.
When the circuit scale estimation (ST203) is completed, the logic cone constraint information 302 is read.

The logic cone constraint information 302 is obtained from development experience so far.
Based on the rules of layout design, in each logical hierarchy, the total number of start point registers of each logic cone, the total number of end point registers, the total number of connection paths from the start point register to the end point register, the total number of connections from the end point register to the start point register The number of passes is defined as a constraint condition.
For example, the total number of start point registers or end point registers should be 100,000 gates or less, the total number of connection paths from the start point register to the end point register, or the total number of connection paths from the end point register to the start point register should be 200 paths or less. An example is setting the logic cone constraint 302 in advance.

  In light of the logic cone constraint 302, the circuit scale determination unit 233 determines the circuit scale (ST205). That is, the circuit scale information of each cluster is checked against the logic cone constraint 302 to determine whether or not the circuit scale satisfies the logic cone constraint (ST205). If there is a cluster exceeding the upper limit of the logic cone constraint (ST206: YES), the cluster is divided (ST207).

Next, the cluster dividing step (ST207) by the cluster dividing unit 234 will be described.
FIG. 11 is a detailed flowchart of the cluster dividing step (ST207).
In dividing a cluster, first, one end point register of the cluster is set as a starting point (ST231).
The data flow is traced in the previous direction starting from this end point register, and up to the start point register in the previous direction is sub-clustered as one set (ST232).
This is performed for all end point registers (ST233).

For example, in the cluster CL0 shown in FIG. 4, the end point register E is set as the start point, and the start point registers A, B, and C in the preceding stage are set as sub-clusters. Then, as shown in FIG. 12, a new cluster CL1 including start point registers A, B, and C, an end point register E, and an operator group OP1 is created.
Similarly, as shown in FIG. 13, the end point register F is set as the starting point, and the starting point registers A, B, C, and D in the preceding direction are sub-clustered as the cluster CL2.
Similarly, as shown in FIG. 14, the end point register G is set as the starting point, and the starting point registers A, B, C, and D in the preceding direction are sub-clustered as a cluster CL3.

Next, it is determined whether the start point register is shared between clusters (ST234).
In the above example, the start point registers A, B, and C are shared by the cluster CL1, the cluster CL2, and the cluster CL3.
Further, the start point register D is shared by the cluster CL2 and the cluster CL3.

Therefore, the register replication is performed so that the start point register is not shared by a plurality of clusters (ST235).
Regarding the registers A, B, and C, registers A1, B1, and C1 are provided for the cluster CL1, registers A2, B2, and C2 are provided for the cluster CL2, and A3, B3, and C3 are provided for the cluster CL3.
As for the register D, a register D2 is provided for the cluster CL2, and a cluster D3 is provided for the cluster CL3.
In this way, the clusters CL1, CL2, and CL3 become completely separated clusters (FIGS. 15, 16, and 17).
As a result, the cluster dividing step is completed.

  The cluster-divided information is updated (ST208), and the loop is repeated until there is no more than the upper limit of the logic constraint by returning to the estimation of the circuit scale (ST203) again.

On the other hand, if there is no cluster exceeding the upper limit of the logic cone constraint in step ST206 (ST206: NO), it is determined whether there is any cluster that is below the lower limit of the logic cone constraint (ST209).
When there are a plurality of items that are below the lower limit of the logic cone constraint (ST209: YES), it is determined whether they can be integrated (ST210).

For example, as shown in FIG. 18, it is assumed that the data flow of the cluster CL4 includes a start point register H4, I4, J4, an end point register M, and an operator group OP4.
Further, as shown in FIG. 19, it is assumed that the data flow of the cluster CL5 includes a start point register H5, I5, J5, K5, an end point register N, and an operator group OP5. Then, it is assumed that the data flow of cluster CL4 and the data flow of cluster CL5 partially overlap.
In this case, the cluster CL4 and the cluster CL5 can be integrated.

When there is a cluster that can be integrated (ST210: YES), the cluster integration unit 235 performs integration processing (ST211).
When the cluster CL4 and the cluster CL5 are integrated, for example, as shown in FIG. 20, a cluster CL6 composed of start point registers H6, I6, J6, K6, end point registers M, N, and an operator group OP6 is formed.
In this way, the separated clusters CL4 and CL5 are integrated into one cluster CL6 shown in FIG.

  The loop is repeated while updating the cluster information (ST208), and when the circuit scale of each cluster falls within the range of the logic cone constraint or there are no clusters that can be integrated, the final cluster information is output (ST212). ), The cluster size adjustment step (ST2001) ends.

Subsequently, using the created cluster information as an input, the RTL description conversion unit 240 performs mapping by reflecting it in the RTL description (ST2002).
For example, when the cluster information of the cluster CL1 (FIG. 15), the cluster CL2 (FIG. 16), and the cluster CL3 (FIG. 17) is output in the RTL description, the RTL description shown in FIG. 21 is obtained.

Subsequently, the downstream design unit 250 performs a downstream design process (ST300).
The downstream design process ST300 is a general layout design according to the RTL description.
FIG. 22 shows a detailed flowchart of the downstream design process ST300.
In the downstream design process (ST300), the logic synthesis unit 251 performs logic synthesis based on the RTL description (ST301) and outputs circuit information (ST302). Then, a floor plan (ST303), timing adjustment (ST304), layout design (ST305), and the like are performed.
Finally, mask data is output (ST400), and the circuit design is completed.

According to such a first embodiment, the following effects are obtained.
(1) Based on the data flow, by dividing or integrating the cluster information therein, each logic cone L is kept within the range of the logic cone constraint.
At this time, by duplicating the start point register shared between the clusters, it is possible to suppress the congestion of wiring when the layout is actually performed. For example, since the start point register is shared in the prior art, as shown in FIG. 23 as an example, the connection between the registers becomes complicated and wiring congestion occurs.
In addition, since the starting point register is shared in the prior art, even if the logic cone is divided, the divided logic cones are collected and arranged at the time of layout.
In this regard, in the first embodiment, the start point register shared when the cluster is divided is duplicated so that the start point register is not shared between the clusters.
As described above, since the cluster including the start point register is completely separated, as shown in FIG. 24 as an example, the arrangement becomes free and the occurrence of wiring congestion can be suppressed.

(2) The output terminal of the start point register needs to secure a wiring property by intentionally securing a space for drawing out the wiring when the number of shared wirings increases. Generally, the wiring property is advantageous when the number of spans indicating the connection cost of the wiring is small. In this respect, according to the first embodiment, by duplicating the shared start point register, the number of wiring spans of the output terminals of each start point register can be reduced to 1, so that the wiring property is advantageous. Become.

(3) By duplicating the start point register, the area of the duplicated register itself can be used as the wiring lead-out space without intentionally securing the wiring lead-out space. Even if the process is not performed, if the start point registers are simply arranged densely, the layout can be performed without causing wiring congestion.

(4) By duplicating the start point register, logic cones divided from the start point register as a starting point are not collected and arranged. Therefore, the delay information obtained in units of logic cones can be used as it is. Further, since it is not necessary to separately insert a delay adjustment circuit or the like, the effect of reducing a useless area can be maximized.

(Modification 1)
In the first embodiment, the case where the circuit scale of each cluster is estimated by referring to the operator library in the circuit scale estimation (ST203) is exemplified.
Here, the actual circuit design may be repeated several times with improvements.
Therefore, it is preferable to store circuit information obtained as a result of logic synthesis (ST401) as circuit data. In the circuit size estimation (ST203), as shown in the flowchart of FIG. 25, the circuit data is searched (ST2211) before referring to the operator library (ST222).
Then, it is determined whether or not circuit data of the corresponding cluster already exists (ST2212).
If there is already circuit data of the corresponding cluster, it is read and used (ST2213).
Thereby, the accuracy of estimation of the circuit scale is remarkably improved.

  Note that the present invention is not limited to the above-described embodiment, and can be changed as appropriate without departing from the spirit of the present invention.

100 ... Circuit design device, 200 ... Calculation unit, 210 ... Upstream design unit, 211 ... Data flow conversion unit, 220 ... Behavior synthesis unit, 230 ... Downstream design unit, 230 ... Cluster size adjustment unit, 231 ... Clustering unit, 232 ... Circuit scale estimation part, 233 ... Circuit scale determination part, 234 ... Cluster division part, 235 ... Cluster integration part, 240 ... RTL description conversion part, 250 ... Downstream design part, 251 ... Logic synthesis part, 300 ... Storage part, 301 ... Operator library, 302 ... Logic cone constraint, 400 ... Input part, 500 ... Display part.

Claims (5)

A method for designing a semiconductor integrated circuit, comprising:
Browse the data flow,
A group of registers that operate at the same timing is used as an end point, and a group from the end point registers to the start point register group in the previous stage that operates at the same timing is clustered as one set.
When the clustered cluster is further divided into a plurality of clusters, the start point register shared by the divided clusters is duplicated so that the start point register is not shared between the divided clusters. A method for designing a semiconductor integrated circuit. In the method for designing a semiconductor integrated circuit according to claim 1,
For each cluster, the operator group between the end point register group and the start point register group is regarded as a logic cone as a logic circuit block, and the circuit scale of each logic cone is estimated.
A method for designing a semiconductor integrated circuit, comprising dividing or integrating the clusters so that a circuit scale of each logic cone is within a predetermined logic cone constraint. In the method for designing a semiconductor integrated circuit according to claim 1 or 2,
The data flow is described using a behavior level description language,
Generating a register transfer level description based on the divided or integrated cluster information;
A method of designing a semiconductor integrated circuit, wherein logic synthesis is performed by reflecting hierarchical information of the register transfer level description. In the method for designing a semiconductor integrated circuit according to claim 3,
The circuit information obtained as a result of logic synthesis is stored as circuit data,
In the estimation of the circuit scale of the logic cone, if circuit information corresponding to the logic cone to be estimated already exists as the circuit data, it is used for the estimation of the circuit scale. Design method. A device for designing a semiconductor integrated circuit,
A clustering unit that refers to the data flow, sets a group of registers that operate at the same timing as an end point, and clusters the end point registers from the end point register to the start point register group that operates at the same timing as one set,
A cluster dividing unit that further divides the clustered cluster into a plurality of clusters,
The cluster dividing unit duplicates a start point register so that the divided clusters do not share the start point register.

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