JP2012146367A - Semiconductor storage device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the current consumption of a semiconductor storage device which is a shared sense amplifier type and employs self-booting by reducing the circuit area.SOLUTION: The semiconductor storage device includes a plurality of sense amplifier arrays 148 and a plurality of driver parts 112-113, 115-116. The sense amplifier arrays 148 each include a pair of bit lines blu, /blu, a sense amplifier part 102, a memory array part 101, and switch parts 114, 117. The sense amplifier part is connected to the pair of bit lines. The memory array part is connected to the pair of bit lines, and provided on both sides outside the sense amplifier part. The switch part is provided between the memory array part and sense amplifier part. The memory array part includes a plurality of memory cells 128, 130 provided at intersections of a plurality of word lines WLU and the pair of bit lines. The switch part propagates cell data based upon a signal generated by a driver part and controlling the switch part when a memory cell is selected.

Description

  The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device using a DRAM macro.

  In recent years, among products equipped with semiconductor memory devices (eg, semiconductor integrated circuit devices), products incorporating large-capacity DRAM macros for high functionality, high quality, small size, and light weight are increasing. In the market, there is a demand for lower power consumption and further reduction in size and weight of products. Also in the DRAM macro field, there is an increasing demand for reduction of power consumption and reduction of the area of large capacity.

  As a technique for reducing power consumption, Japanese Patent Application Laid-Open No. 10-302469 discloses a technique of a semiconductor memory device. This semiconductor memory device has an array circuit using a shared sense amplifier that shares one sense amplifier for amplification of two bit line pairs by switching bit line transfer gates. This array circuit is a method of self-booting the gate of the bit line transfer gate which has received the rise of the bit line when the sense amplifier is active, without directly booting the bit line transfer gate required for data propagation by supplying the boosted potential. Is used. This will be described in detail below.

  FIG. 1 is a block diagram showing a configuration example of a semiconductor memory device disclosed in Japanese Patent Laid-Open No. 10-302469. FIG. 2 is a circuit diagram showing the relationship between the bit line pair and the sense amplifier in FIG. FIG. 3 is a circuit diagram of the bit line transfer gate driving circuit in FIG. FIG. 4 is a timing chart showing the operation of the semiconductor memory device shown in FIGS. The reference numerals in FIGS. 1 to 4 are the same as those described in Japanese Patent Laid-Open No. 10-302469, and are not related to the reference numerals used in the embodiment of the present invention.

  As shown in FIG. 1, each of the memory cell arrays 10 and 20 includes a plurality of word lines WL and a plurality of bit line pairs BL and / BL (/ BL (/ BL means BL bars) intersecting with each other. The same shall apply including Memory cells MC are arranged at each intersection. A sense amplifier SA is arranged between each bit line pair BL, / BL. Between the bit line pair BL, / BL and the sense amplifier SA, bit line transfer gates Q00, Q01, Q02, Q03,... (For the memory cell array 10) for selecting a bit line pair, Q10, Q11, Q12, Q13 ,... (For the memory cell array 20) are provided. The gate electrodes of these bit line transfer gates Q00, Q01,... Are driven by the output BLTl of the bit line transfer gate drive circuit. The gate electrodes of these bit line transfer gates 10, Q11,... Are driven by the output BLTr of the bit line transfer gate drive circuit 44. Hereinafter, a specific example in which the bit line transfer gate drive circuits 42 and 44 in FIG. 2 are replaced with the bit line transfer gate drive circuits 42 and 44 in FIG. 3 will be described.

  As shown in FIG. 2, a plurality of word lines WL1 and a plurality of word lines WL2 are provided in the left and right memory cell arrays 10 and 20, respectively (only one is shown in FIG. 2). Memory cells MC1 and MC2 are provided at intersections between the word lines WL1 and WL2 and the bit line / BL, respectively. The memory cell MC1 is composed of one N-type transistor Q1 and one capacitor C1. The memory cell MC2 is composed of one N-type transistor Q2 and one capacitor C2. Dummy word lines DWL1, DWL2 are arranged between bit line transfer gates Q00, Q01 and bit line transfer gates Q10, Q11. A dummy cell DC1 is provided at the intersection of the dummy word line DWL1 and the bit line BL. A dummy cell DC2 is provided at the intersection of the dummy word line DWL2 and the bit line / BL. In the example of FIG. 2, the dummy cells DC1 and DC2 each have a predetermined coupling capacitance. The dummy cells DC1, DC2 are both shared by the left and right memory cell arrays 10, 20. The sense amplifier array 30 between the left and right memory cell arrays 10 and 20 is provided with a sense amplifier SA composed of a CMOS latch circuit and a bit line precharge circuit BP that precharges the bit line pair to the ground potential Vss. The sense amplifier SA is formed by cross-connecting a CMOS inverter composed of a P-type MOS transistor Q25 and an N-type MOS transistor Q26 and a CMOS inverter composed of a P-type MOS transistor Q27 and an N-type MOS transistor Q28. The common source of the N-type MOS transistors Q26 and Q28 is connected to the ground potential, and the sense amplifier activation signal PSA is applied to the common source of the P-type MOS transistors Q25 and Q27. The bit line precharge circuit BP includes an N-type transistor Q29 for shorting the bit line pair and N-type transistors Q30 and Q31 for grounding for setting the bit line pair to the ground potential Vss. These transistors are controlled and turned on by a bit line reset signal BRS.

  As shown in FIG. 3, the bit line transfer gate drive circuits 42 and 44 use the control signal / act. The control signal / act is a control signal that is high during the precharge period and low during the active period. Memory cell array selection signals A and / A are applied to bit line transfer gate drive circuits 42 and 44, respectively. In this example, the output of the bit line transfer gate drive circuit 42 is composed of N-type transistors N10 and N11, and is driven by an inverter element 62 with level conversion function and a normal inverter element 63. NAND gate 61 receives control signal / act and selection signal A. A clamp circuit 67 is connected to the control signal terminal BLTl of the output of the bit line transfer gate driving circuit 42 to clamp the power supply voltage Vcc to the potential of the three stages of clamping transistor diodes N14, N15, N16 which are raised. Similarly, the output of the bit line transfer gate drive circuit 44 is composed of N-type transistors N12 and N13, and is driven by an inverter element 65 with level conversion function and a normal inverter element 66, respectively. NAND gate 64 receives control signal / act and selection signal / A. A clamp circuit 68 is connected to the control signal terminal BLTr of the output of the bit line transfer gate driving circuit 44 to clamp the power supply voltage Vcc to the potential of the three stages of clamping transistor diodes N14, N15, N16 that are raised.

  As shown in FIG. 4, in the operation of these bit line transfer gate drive circuits 42 and 44, a precharge period, an active period, and a precharge period are performed sequentially. At the end of the active period, the generation of the bit line reset signal BRS causes the transistors Q29 to Q31 of the precharge circuit BP to become conductive, the bit line pair BL, / BL is short-circuited and precharged to the ground potential Vss. . The output bltl of the drive circuit 43 is set to the level of the power supply voltage Vcc (for example, 3V), and the control signal cgl is set to the boosted power supply Vpp (for example, 5V). Similarly, output bltr of drive circuit 445 is set to the level of power supply voltage Vcc, and control signal cgr is set to boosted power supply Vpp. As a result, both drive signals BLTl and BLTr are at the power supply voltage Vcc level. In the precharge period, the control signal / act is High, and both the selection signals A and / A are High. Therefore, the outputs of NAND gates 61 and 64 are both low, and inverter elements 62 and 65 are at the level of boosted voltage Vpp. As a result, the N-type transistors N10 and N12 are turned on, and both control signals BLTl and BLTr are at the power supply voltage Vcc level.

  Next, in the active period, the control signal / act becomes Low, and one of the selection signals A and / A becomes Low. Consider the case where the selection signal / A becomes Low in accordance with the above example. The output of the NAND gate 64 is High, and the output of the inverter element 65 is Low. N-type transistor N12 becomes non-conductive. Since the output of the inverter element 66 becomes High, the N-type transistor N13 conducts and the control signal BLTr falls to Low (ground level). As a result, the corresponding bit line transfer gates Q10 and Q11 become non-conductive, and the bit line pair (memory cell array 20 side) is separated from the sense amplifier SA. On the other hand, the output of the NAND gate 61 is High and the output of the inverter element 62 is Low. N-type transistor N10 is turned off. The output of the inverter element 63 is also Low, and the N-type transistor N11 is also nonconductive. As a result, the signal line of the control signal BLTl is in a floating state. When the signal line of the control signal BLTl is in a floating state, the gate electrodes of the bit line transfer gates Q00 and Q01 are boosted higher than the power supply voltage Vcc by the capacitive couplings C00 and C01 accompanying the rise of the bit lines BL and / BL. Then, rewriting at the power supply voltage Vcc level is performed on the high-side memory cell.

  As a related technique, Japanese Patent Application Laid-Open No. 2002-133869 discloses a semiconductor memory device. This semiconductor memory device operates in response to an external power supply voltage. The semiconductor memory device includes first and second data lines for transmitting storage data whose one of the data levels corresponds to a first voltage, and a memory cell for holding the storage data. The memory cell responds to activation of a storage node for holding the data level and a word line set to a second voltage higher than the first voltage, and the storage node and the first And a data transmission gate for electrically coupling to one of the second data lines. In response to a control signal set to a third voltage higher than the external power supply voltage and lower than the second voltage at the time of activation, each of the first and second data lines is set to the same predetermined voltage. A data line equalizing circuit for setting to. Unlike the above-described self-boot method, this technique generates a boosted potential by a conventional charge pump method.

  Japanese Patent Laid-Open No. 8-125034 discloses a semiconductor memory device. This semiconductor memory device includes a plurality of N and P channel MOS semiconductor elements. The plurality of N and P channel MOS semiconductor elements are formed on an SOI substrate. Each of the plurality of N and P channel MOS semiconductor elements has a source region, a drain region, and a body region located between the source region and the drain region. The body region of at least one N channel MOS semiconductor element among the plurality of N channel MOS semiconductor elements is electrically fixed. The body region of at least one P channel MOS semiconductor element among the plurality of P channel MOS semiconductor elements is in an electrically floating state. In this technology, only the mention of being electrically fixed is made, and there is no description regarding booting of the gate of the transistor connecting the bit line and the sense amplifier.

  Japanese Patent Application Laid-Open No. 9-63266 discloses a semiconductor memory device and a semiconductor circuit device. This semiconductor memory device has a normal operation mode and a special operation mode whose operation speed is slower than that of the normal operation mode. The semiconductor memory device includes first and second sense nodes, a sense amplifier connected to the first and second sense nodes and amplifying a potential difference generated between the first and second sense nodes; A plurality of first bit line pairs disposed on one side of the sense amplifier, a second bit line pair disposed on the other side of the sense amplifier, and a plurality of crossing the first and second bit line pairs. A word line; a row decoder for selectively activating the word line in response to a row address signal; and a first decoder connected between the first and second sense nodes and the first bit line pair. 1 switch means, second switch means connected between the first and second sense nodes and the second bit line pair, and in the normal operation mode, the first and second switch means Connect one of the bit line pairs to the The first and second switch means are controlled to be connected to an amplifier, and in the special operation mode, one of the first and second bit line pairs is connected to the sense amplifier, and the connected The connected bit line pair is disconnected from the sense amplifier after data is read to one bit line pair, and the disconnected bit line pair is again connected after the sense amplifier is activated. And control means for controlling the first and second switch means so as to be connected to a sense amplifier. Unlike the above-described self-boot method, this technique realizes booting by switching the power supply potential and the boosted potential when the transistor is activated.

  Japanese Laid-Open Patent Publication No. 11-288592 discloses a semiconductor integrated circuit. In this semiconductor integrated circuit, a plurality of memory cells provided at intersections of a plurality of data line pairs and a plurality of word lines, and signals from the memory cells read to the plurality of data line pairs, respectively, are supplied with a first potential or a first potential. A plurality of sense amplifiers for amplifying to two potentials; a precharge circuit for precharging the plurality of data line pairs to a third potential; and generating the third potential; Common to a voltage generation circuit for supplying a potential, a plurality of dummy memory cells connected to one of a plurality of data line pairs, each including a storage capacitor and a MOS transistor, and one end of the storage capacitors of the plurality of dummy memory cells A connected plate electrode; and means for driving the plate electrode from the third potential to a fourth potential. The fourth potential is a half of the first potential and the second potential, and the third potential is a potential between the first potential and the fourth potential, or the fourth potential and the A potential between the second potentials. This technique is not a shared sense amplifier system, nor is it a self-boot system.

Japanese Patent Laid-Open No. 10-302469 JP 2002-133869 A JP-A-8-125034 Japanese Patent Laid-Open No. 9-63266 Japanese Patent Laid-Open No. 11-288592

  The technique disclosed in Japanese Patent Laid-Open No. 10-302469 described with reference to FIGS. 1 to 4 has a problem that the current consumption of the boosted voltage Vpp generation circuit that generates the boosted voltage Vpp increases. The reason will be described below. In this technique, for example, when data written in the memory cell MC1 (or MC2) is read, a bit line transfer gate that is passed through in order to propagate a difference potential generated in the bit line pair BL, / BL to the sense amplifier SA. The voltage value of the drive signal BLTl (or BLTr), which is the gate contact of Q00, Q01 (or Q10, Q11), is made higher than the power supply voltage Vcc by self-boot accompanying the activation of the sense amplifier SA, and the memory cell MC1 (or MC2) Is set to the Vcc level.

  Here, the drive signals BLTl and BLTr are routed along the bit line columns of the memory cell arrays 10 and 20, and are long wires and have a large capacitive load. Therefore, it is necessary to precharge the gate drive signals BLTl and BLTr of the bit line transfer gates Q00, Q01, Q10, and Q11 to the Vcc potential. In addition, in order to precharge the gate nodes BLTl and BLTr of the bit line transfer gates Q00, Q01, Q10 and Q11 to the Vcc potential, the bit line transfer gate drive for driving the gates of the bit line transfer gates Q00, Q01, Q10 and Q11 is performed. As a power source for inverter elements 62 and 65 connected to the gates of N-type transistors N10 and N12 which are bit line transfer gate active elements of circuits 42 and 44, a boosted voltage Vpp potential (5 V with respect to Vcc3V in the known example) is supplied. is necessary. Therefore, the load on the boosted voltage Vpp generation circuit that generates the boosted voltage Vpp potential increases.

  Hereinafter, means for solving the problem will be described using the numbers and symbols used in the embodiments for carrying out the invention. These numbers and symbols are added with parentheses in order to clarify the correspondence between the description of the claims and the mode for carrying out the invention. However, these numbers and symbols should not be used for interpreting the technical scope of the invention described in the claims.

  The semiconductor memory device of the present invention includes a plurality of sense amplifier arrays (148 (150)) and a plurality of driver units (112-113, 115-116, 121-122) extending in the first direction and arranged in the second direction. 124-125). Each of the plurality of sense amplifier arrays (148 (150)) includes a bit line pair (blu-blc-bll, / blu / blc- / bll), a sense amplifier unit (102 (149)), and a precharge unit. (109-111, 118-120), a memory array unit (101, 104), and a switch unit (114, 117, 123, 126). A bit line pair (such as blu and / blu) extends in the first direction. The sense amplifier unit (102, etc.) is connected to a bit line pair (blu, / blu, etc.). The precharge unit (109-111 etc.) is connected to a bit line pair (blu, / blu etc.) and is provided on both sides of the sense amplifier unit (102 etc.). A memory array unit (such as 101) is connected to a bit line pair (such as blu and / blu) and is provided on the opposite side of the sense amplifier unit (such as 102) of each precharge unit (such as 109-111). . The switch unit (such as 114) is provided on a bit line pair (such as blu and / blu) between the precharge unit (such as 109-111) and the sense amplifier unit (such as 102). The memory array unit (101, etc.) includes a plurality of memory cells (corresponding to intersections between a plurality of word lines (WLU, WLL) extending in the second direction and bit line pairs (blu, / blue, etc.)). 128, 130, 132, 134). A precharge unit (such as 109-111) precharges a bit line pair (such as blu and / blu) to a predetermined potential during the precharge period. The switch unit (eg, 114) is configured to select a memory based on a signal for controlling the switch unit (eg, 114) generated by any one of the plurality of driver units (eg, 112-113) when the memory cell (eg, 128) is selected. Propagate cell data.

  In the present invention, a plurality of driver units (such as 112-113) are provided instead of one for a plurality of sense amplifier arrays (such as 148). Accordingly, it is sufficient to operate only the driver unit (112-113) that bears the sense amplifier array (148, etc.) selected and activated, and the switch unit (114, etc.) to be charged by one driver unit (112-113, etc.). ) Can be reduced. Therefore, in a sense amplifier array (such as 148) that has been selected and activated, a switch portion (by a rising width of the bit line (blc) that accompanies the activation of the sense amplifier portion (such as 102) required for writing and reading cell data ( 114) and the like, and without receiving the boosted potential (Vpp) used for the word line (WLU), which has been necessary in the prior art, [driving potential necessary for memory cell data propagation] = [A boosted potential higher than the power supply potential (VCC)] can be secured. Therefore, it is possible to reduce the load and current consumption of the circuit that generates the boosted potential (Vpp) used for the word line (WLU).

  According to the present invention, in a semiconductor memory device using self-boot in the shared sense amplifier method, the circuit area can be reduced and the current consumption can be reduced.

FIG. 1 is a block diagram showing a configuration example of a semiconductor memory device disclosed in Japanese Patent Laid-Open No. 10-302469. FIG. 2 is a circuit diagram showing the relationship between the bit line pair and the sense amplifier in FIG. FIG. 3 is a circuit diagram of the bit line transfer gate driving circuit in FIG. FIG. 4 is a timing chart showing the operation of the semiconductor memory device shown in FIGS. FIG. 5 is a block diagram showing a configuration of the semiconductor memory device according to the first embodiment of the present invention. FIG. 6 is a timing chart showing the operation of the semiconductor memory device according to the first embodiment of the present invention. FIG. 7 is a block diagram showing a configuration of a semiconductor memory device according to the second embodiment of the present invention. FIG. 8 is a timing chart showing the operation of the semiconductor memory device according to the second embodiment of the present invention.

  Hereinafter, embodiments of a semiconductor memory device of the present invention will be described with reference to the accompanying drawings.

(First embodiment)
The configuration of the semiconductor memory device according to the first embodiment of the present invention will be described with reference to the accompanying drawings. FIG. 5 is a block diagram showing a configuration of the semiconductor memory device according to the first embodiment of the present invention. The semiconductor memory device 1 includes a plurality of sense amplifier arrays 148, a plurality of bit line transfer gate selection circuits 105, and a plurality of bit line transfer gate non-selection circuits 106.

  The sense amplifier array 148 includes a sense amplifier unit 102, cell array units 101 and 104 that share and share the sense amplifier unit 102 when cell data is amplified, a read / write element unit 103, and a bit line pair equalize element. N-type transistors 109, 110, 111 and N-type transistors 118, 119, 120, N-type transistors 114, 117 and N-type transistors 123, 126 as bit line transfer gate elements, N-type transistors 114, 117, and N-type Low VTN transistors 112 and 115 which are driver elements for supplying a potential to the gate nodes of the transistors 123 and 126 and are activated with a threshold voltage smaller than that of a normal N-type transistor (114, 117, 123, 126, etc.) Normal N-type transistor 114, 117, 123, 126, etc.) and low VTN transistors 121 and 124 that are activated with a threshold voltage lower than that, N-type transistors 113 and 116, N-type transistors 122 and 125, and a reference when amplifying with a sense amplifier Dummy cells 146 and 147 for potential generation are provided. The low VTN transistors 112 and 115 and the low VTN transistors 121 and 124 are driven by the power supply voltage VCC.

  The cell array unit 101 includes a plurality of word lines WLU0 to WLUn (n is arbitrary), bit line pairs blu and / bl, N-type transistors 127 and 129 which are cell data propagation switches, and memory cells 128 and 130. The cell array unit 104 includes a plurality of word lines WLL0 to WLLn (n is arbitrary), a pair of bit lines bll and / bll, N-type transistors 131 and 133 which are cell data propagation switches, and memory cells 132 and 134. Which of the cell array units 101 and 104 is selected and activated is determined by the array selection signals TGLP and TGUP, and the sense amplifier unit 102 is shared and shared when cell data is amplified.

  Word lines WLU0 and WLU1 are connected to the gates of N-type transistors 127 and 129, which are cell data propagation switches, respectively. The sources of the N-type transistors 127 and 129 are connected to the memory cells 128 and 130, respectively. The drains of the N-type transistors 127 and 129 are connected to the bit line pair blu and / blu, respectively. Further, the word lines WLU0 and WLU1 are connected to the plurality of cell array units 101 in units of the sense amplifier array 148. Word lines WLL0 and WLL1 are connected to the gates of N-type transistors 131 and 133 which are cell data propagation switches, respectively. The sources of the N-type transistors 131 and 133 are connected to the memory cells 132 and 134, respectively. The drains of the N-type transistors 131 and 133 are connected to the bit line pair bll and / bll, respectively. Further, the word lines WLL0 and WLL1 are connected to the plurality of cell array units 104 in units of the sense amplifier array 148.

  Non-high breakdown voltage N-type transistors 114 and 117 which are bit line transfer gate elements of bit lines blu and / bl, and non-high breakdown voltage N-type transistors 123 and 126 which are bit line transfer gate elements of bit lines bll and / bll Means a sense amplifier unit 102 shared by shared sense amplifier units, a write / read element unit 103, and dummy cells 146 and 147.

  The bit line pair blu and / bl in the cell array unit 101 and the bit line pair bll and / bll in the cell array unit 104 are respectively N-type transistors 114 and 117 and N-type transistors 123 which are bit line transfer gate elements and are not high withstand voltages. , 126 are connected to the bit line pair blc, / blc, which is the amplification node of the sense amplifier unit 102.

  The sense amplifier unit 102 is formed by cross-connecting a CMOS inverter composed of a P-type MOS transistor 13 and an N-type MOS transistor 14 and a CMOS inverter composed of a P-type MOS transistor 15 and an N-type MOS transistor 16. The common source of the N-type MOS transistors 14 and 16 is connected to the ground potential, and the common source of the P-type MOS transistors 13 and 15 is connected to the source of the P-type MOS transistor 17. The drain of the P-type MOS transistor 17 is connected to VCC, and the gate is connected to the output of the inverter element 11 that inverts the sense amplifier activation signal SAP that drives the sense amplifier unit 102.

  The write / read element unit 103 includes a write / read bus, a column switch, an address decoder, and the like.

  The dummy cell 146 is a capacitance formed between the bit line / blc that is an amplification node of the sense amplifier unit 102 and the dummy word line DWL0 that drives the dummy cell 146. The dummy cell 147 is a capacitance formed between the bit line blc that is an amplification node of the sense amplifier unit 102 and the dummy word line DWL1 that drives the dummy cell 147.

  The gate nodes gu and / gu of the N-type transistors 114 and 117 that are not high withstand voltage, which are bit line transfer gate elements, are each a driver in which two N-type transistors are connected vertically (the gate length is low VT with VCC as a source). The low VTN type transistor 112 and the N type transistor 113 having GND as a source, the low VVT type having a low VT having VCC as a source, and the low VTN type transistor 115 having a large gate length and the N type transistor 116 having GND as a source are respectively included. .) Connected as output. The gates of the low VTN transistors 112 and 115 are connected to the bit line transfer gate selection signal TGU. The gates of the N-type transistors 113 and 116 are connected to the bit line transfer gate non-selection signal STBU.

  The gate nodes gl and / gl of the N-type transistors 123 and 126 which are not high withstand voltage which are bit line transfer gate elements are drivers each having two N-type transistors connected vertically (the gate length is low VT with VCC as a source). The low VTN type transistor 121 and the N type transistor 122 having the GND as the source, the low VTN type gate 124 having the low gate VT and the N type transistor 125 having the GND as the source, respectively. Connected) as an output. The gates of the low VTN transistors 121 and 124 are connected to the bit line transfer gate selection signal TGL. The gates of the N-type transistors 122 and 125 are connected to the bit line transfer gate non-selection signal STBL.

  The bit line transfer gate selection signal TGU and the bit line transfer gate non-selection signal STBU are wired on the sense amplifier row along the sense amplifier row, and a plurality of bit line transfer gate selection signals TGU are connected to the sense amplifier array 148. The bit line transfer gate selection signal TGL and the bit line transfer gate non-selection signal STBL are wired on the sense amplifier array along the sense amplifier array, and a plurality of bit line transfer gate selection signals TGL are connected to the sense amplifier array 148.

  An N-type transistor 109 having a source and drain connected to the bit line pair and a gate connected to the equalize signal PDLU is arranged as a balance element for equalizing the bit line pair. N-type transistors 110 and 111 having a drain connected to the bit lines blu and / blu, a source connected to GND, and a gate connected to the equalize signal PDLU are arranged as the GND precharge elements for bit line equalization. Similarly to the word lines, the equalize signals PDLU are wired along the sense amplifier row, and a plurality of equalize signals PDLU are connected to the sense amplifier array 148. An N-type transistor 118 having a source and drain connected to the bit line pair and a gate connected to the equalize signal PDLL is arranged as a balance element for equalizing the bit line pair. N-type transistors 119 and 120 having a drain connected to the bit lines bll, / bll, a source connected to GND, and a gate connected to the equalize signal PDLL are arranged as a GND precharge element for bit line equalization. Similarly to the word lines, the equalize signals PDLL are wired along the sense amplifier row, and a plurality of equalize signals PDLL are connected to the sense amplifier array 148.

  Two bit line transfer gate selection circuits (105, 107) are arranged so as to sandwich the sense amplifier section 102 therebetween. Bit line transfer gate selection circuit 105 has an array selection signal TGUP and an array activation signal / act as inputs. An output of the NAND gate 135, which is input with the inverted signal obtained by inverting the array activation signal / act by the inverter element 134, the array selection signal TGUP, and the delay signal of the array selection signal TGUP via the delay element 136, The signal is input to the inverter element 137 and the output is output as the bit line transfer gate selection signal TGU. Inverter element 137 is driven by power supply voltage VCC.

  Bit line transfer gate selection circuit 107 has an array selection signal TGLP and an array activation signal / act as inputs. The output of the NAND gate 139, which receives the inverted signal obtained by inverting the array activation signal / act by the inverter element 138, the array selection signal TGLP, and the delay signal of the array selection signal TGLP via the delay element 140, The signal is input to the inverter element 141, and the output is output as the bit line transfer gate selection signal TGL. Inverter element 141 is driven by power supply voltage VCC.

  Two bit line transfer gate non-selection circuits (106, 108) are arranged so as to sandwich the sense amplifier section 102 therebetween. Bit line transfer gate non-selection circuit 106 has an array selection signal TGLP and an array activation signal / act as inputs. The output of the NOR gate 142 having the array activation signal / act and the array selection signal TGLP as inputs is input to the inverter element 143, and the output is output as the bit line transfer gate non-selection signal STBU.

  Bit line transfer gate non-selection circuit 108 has an array selection signal TGUP and an array activation signal / act as inputs. The output of the NOR gate 144 having the array activation signal / act and the array selection signal TGUP as inputs is input to the inverter element 145, and the output is output as the bit line transfer gate non-selection signal STBL.

  In the example of FIG. 5, a driver element for supplying a potential to the gate nodes of the N-type transistors 114 and 117 and the N-type transistors 123 and 126, which is a normal N-type transistor (114, 117, 123, 126, etc.) A set of low VTN transistors 112 and 115 that are activated with a smaller threshold voltage and low VTN transistors 121 and 124 that are activated with a smaller threshold voltage than a normal N-type transistor (114, 117, 123, 126, etc.). Are provided for each bit line pair. However, the present invention is not limited to this example, and the set of these low VTN transistors may be provided for every two or more bit line pairs (however, at least two sets). In that case, the installation area of these low VTN transistors can be reduced.

Next, the operation of the semiconductor memory device according to the first embodiment of the present invention will be described.
FIG. 6 is a timing chart showing the operation of the semiconductor memory device according to the first embodiment of the present invention. In this figure, changes in WLU, DWL, PDLU, and PDLL (indicated by PDLU / L), / act, TGU, TGL, SAP, and blu, / bl in timing periods t1 to t6 are shown on the upper side of the graph (ground potential GND˜ (Power supply potential VCC) to boosted potential Vpp), and changes in gu, / gu, blc, and / blc are shown on the lower side of the graph (ground potential GND to power supply potential VCC). The array selection signals TGUP and TGLP and the bit line transfer gate non-selection signals STBU and STBL are not shown. Hereinafter, the example of this figure shows an example in which the memory cell 128 of the upper cell array unit 101 in FIG. 5 is selected. At this time, the array selection signal TGLP is at the low level (GND), TGUP is at the high level (VCC), and the N-type transistors 123 and 126 are turned off. Therefore, the sense amplifier unit shared and shared by the cell array units 101 and 104 102 is activated to amplify the data in the memory cells of the cell array unit 101. Although description is omitted, when the memory cell 132 of the lower cell array unit 104 in FIG. 5 is selected, only the state of the array selection signals TGLP and TGUP is reversed, and thereafter the same operation is performed.

(1) Standby timing period t1
The bit line pair blu and / blu are balanced and precharged (GND) by the high level (VCC) of the bit line pair equalize signals PDLU and PDLL. During this time, the bit line transfer gate selection signals TGU and TGL, which are the outputs of the bit line transfer gate selection circuits 105 and 107, become the low level (GND) according to the high level (VCC) of the array activation signal / act. Further, since the array activation signal / act is at the high level (VCC) regardless of the decoding state of the array selection signals TGUP and TGLP, the bit line transfer gate non-selection signals STBU and STBL (not shown in FIG. 6) Is at a high level (VCC), and the self-boot nodes gu, / gu, gl, / gl are initialized to the GND level.

(2) Timing period t2 of standby release, array selection, and start of precharge to self-boot node
Decoding of the array selection signals TGUP and TGLP and the array activation signal / act are Low (GND), the bit line transfer gate selection signal TGU on the selected array side (cell array unit 101 side) is High (VCC), and the non-selected array side The bit line transfer gate selection signal TGL on the (cell array unit 104 side) remains Low (GND). As a result, the shared / shared sense amplifier unit 102 is activated to amplify the data in the memory cells of the cell array unit 101. Low VTN type transistors 112 and 115 which are bit line transfer gate active elements that output gate input signals (gu, / gu) of non-high-voltage N type transistors 114 and 117 which are bit line transfer gates on the selected array side, Precharge is started to self-boot nodes gu and / gu. At the same time, the bit line equalize signal PDLU on the selected array side becomes Low level (GND), and the balance and precharge of the bit line pair blu and / bl are released.

(3) Timing period t3 of word activation and self-boot node precharge
The gate nodes gu and / gu of the N-type transistors 114 and 117 that are not high withstand voltage, which are self-boot nodes, have a small load capacitance, and the gate node potentials of both N-type transistors 114 and 117 that do not have high withstand voltage are VCC-Vtn112 ( Vtn112: threshold value of the low VTN transistor 112,
Vtn112≈Vtn115 (: The threshold value of the low VTN transistor 115 is the same as that of the low VTN transistor 112, so the threshold value is almost the same including the process variation))
Set to In parallel with the activation (Vpp) of the word line WLU0, the data of the cell 128 propagates to the bit line blu, and then passes through the N-type transistor 114 which is a bit line transfer gate and does not have a high withstand voltage. Propagates to the bit line blc. At the same time, due to the activation (Vpp) of the dummy word line DWL0, the charge corresponding to the capacity of the dummy cell 146 propagates to the bit line / blc in the sense amplifier, slightly raises the potential from the GND level, and subsequently serves as a bit line transfer gate. It propagates to the bit line / bl via the N-type transistor 117 which is not high withstand voltage.

(4) Sense amplifier active, self boot start timing period t4
Amplification by the sense amplifier unit 102 is started by the activation (VCC) of the sense amplifier activation signal SAP, and the potential in the sense amplifier bit line blc rises. This raises the potential of the bit line blu via the N-type transistor 114 which is a bit line transfer gate and does not have a high breakdown voltage. As the potential of the bit line blu rises, the self-boot gate node gu of the N-type transistor 114 which is a bit line transfer gate and does not have a high breakdown voltage rises to VCC or higher due to self-boot. When the potential that has risen above VCC reaches VCC + Vtn112 (Vtn112: the threshold value of the low VTN transistor 112), the write voltage (bit line blue potential) to the memory cell 128 becomes VCC, and sufficient charge is required for reading. Can be secured. The self-boot gate node gu holds the booted potential because there is no potential drop of blu during the active period of the sense amplifier unit 102. The potential of the self-boot gate node / gu settles to VCC-Vtn115 (Vtn115: threshold of the low VTN transistor 115) via the low VTN transistor 115 without being affected by the activity of the sense amplifier unit 102.

(5) Timing period t5 of internal initialization start and self-boot end
After securing the rewrite charge of the memory cell 128, the word line WLU0 and the dummy word line DWL0 are deactivated (GND). In response to the subsequent inactivation (GND) of the sense amplifier activation signal SAP, the gate node gu of the N-type transistor 114 which is not a high withstand voltage and is a bit line transfer gate goes to the GND level. In response to the high level (VCC) of the array activation signal / act, the bit line transfer gate selection signal TGU becomes the low level (GND). The bit line transfer gate non-selection signal STBU becomes High level (VCC), and the gate node / gu of the N-type transistor 117 that is not a high breakdown voltage and is the bit line transfer gate of the bit line / bllu also settles at the GND level. The bit line pair blu, / bl receives the high level (VCC) of the bit line pair equalizer PDLU, and is balanced and precharged to the GND level.

(6) Timing period t6 when initialization is performed
Thereafter, the inside repeatedly operates from t1 to t5.

  In the case of a semiconductor memory device using a shared sense amplifier that is configured by a plurality of word lines and a plurality of bit line pairs intersecting the word lines and shares both the P-type transistor and the N-type transistor of the sense amplifier, the bit from the sense amplifier When data High is propagated to the line, it is indispensable to supply a boosted potential to the gate of the bit line transfer gate in order to avoid a potential drop corresponding to VT (threshold) of the transfer gate. In the example of FIGS. 1 to 4 (FIGS. 1 to 4), as shown in FIG. 3, the nodes BLTl and BLTr for driving the bit line transfer gate, which is essential for booting at the time of bit line data propagation, are long wires and have a large capacitive load. Therefore, the boosted voltage Vpp is used for the driving inverters 62 and 65 in order to charge a sufficient charge before booting, the boosted potential Vpp is applied to the gates of the N-type transistors N10 and N12 which are the previous stage drivers, and the output is The configuration was VCC.

  However, in the present embodiment, as shown in FIG. 5, by dividing the nodes indispensable for booting in units of sense amplifier arrays (each sense amplifier array 148), self-boot nodes gu (, / gu, gl, / Gl) and a driver for supplying a potential to the gate capacitance of the N-type transistor 114 (117, 123, 126) as a bit line transfer gate and the self-boot nodes gu (, / gu, gl, / gl). Diffusion layer of low VTN transistor 112 and N transistor 113 (low VTN transistor 115 and N transistor 116, low VTN transistor 121 and N transistor 122, low VTN transistor 124 and N transistor 125) Minimizing the load on nodes that require self-boot by using only capacity Over preparative run before the potential ensured by sufficiently reliably so that according efficiently boot.

  In addition, by using a low VT transistor for the VCC supply side element indicated by the low VTN transistor 112 (115, 121, 124) of FIG. 5, self-boot nodes gu (, / gu, gl, / gl ) Is applied to the gate of the driver that supplies the potential to the gate of the normal peripheral circuit instead of the boosted potential Vpp generated by the VCC level booster circuit, and the output potential is set to “VCC−VTN (low VT transistor ( The threshold value of the low VTN transistor 112 (, 121, 115, 124))) ”. This is because VTN is small and (VCC-VTN) can be boosted to exceed VCC. Since the VTN of the low VT transistor is smaller than that of a normal N-type transistor, the difference between the output potential VCC−VTN and VCC is much smaller than the potential width that rises due to self-boot associated with the SAP activity. It is sufficiently possible to output VCC + VTN to the self-boot node gu, the output capable of propagating the VCC level as the maximum potential from the high-side bit line blc in 149 to the high-side bit line blu in the memory cell 101. Therefore, the boosted potential Vpp generation circuit excluding the word line driver can be deleted, and the power supply of the boosted potential Vpp can be saved. Specifically, the boosted power supply generation circuit including voltage comparison, the pumping circuit, the oscillator, etc. There is an effect of reducing current consumption by reducing the scale. In this embodiment, the gate node potential of the bit line transfer gate immediately before booting is lower by the threshold value of the low VT than in the example of Patent Document 1, but the capacitive load at the node is the example of Patent Document 1. The boot potential is not deficient because it is extremely small compared to the long wiring portion.

(Second Embodiment)
The configuration of the semiconductor memory device according to the first embodiment of the present invention will be described with reference to the accompanying drawings. FIG. 7 is a block diagram showing a configuration of a semiconductor memory device according to the second embodiment of the present invention. In this semiconductor memory device 1a, the bit line pair shown in the semiconductor memory device 1 (FIG. 5) of the first embodiment is changed from the GND precharge method to the HfVcc (≈VCC × 0.5) precharge method. A circuit is used. The semiconductor memory device 1a (FIG. 7) is not changed in the characteristic part of the present invention as compared with the semiconductor memory device 1 (FIG. 5). However, since the HfVcc precharge method is used, the following three circuit configurations are used. It is different in point.

(A) The first difference is
In the GND precharge method, a dummy word circuit (including DWL0 and DWL1) for generating a reference level for comparison, which is required to determine whether the bit line of the cell of interest is High, becomes unnecessary.
(B) The second difference is
In the GND precharge method, there is a sufficient potential difference between the equalization level (GND) of the bit line and when PDLU and PDLL are active, so-called VGS (gate-source voltage, substantial VCC), and the bit line pair can be equalized without any problem. In the HfVcc method, since the equalization level of the bit line becomes HfVcc (≈VCC × 0.5), so-called VGS becomes half of the GND precharge method, so that the potential when PDLU and PDLL are active It is necessary to boost the pressure. Although the potential at the time of activation of PDLU and PDLL is not required up to the boosted potential Vpp potential, the potential is boosted from VCC to the level exceeding the VT of N-type transistors 109, 110, 111, 118, 119, and 120 shown in FIG. Vpp2 is required. However, a high breakdown voltage transistor is not used and is within a range that can be handled by optimization of potential supply.
(C) In the sense amplifier unit 102 of the semiconductor memory device 1 (FIG. 5), the swing width is in the vicinity of VCC from GND. However, in the sense amplifier unit 149 of the present system (semiconductor memory device 1a (FIG. 7)), the swing width is changed from HfVcc to the vicinity of VCC, so the self-boot boosting width decreases. However, this is also the boot required for potential propagation by optimizing the channel width W of the N-type transistors 114, 117, 123, 126 and the channel length L of the low VTN transistors 112, 115, 121, 121 shown in FIG. A sufficient level can be secured.

  The semiconductor memory device 1a of the present embodiment has a circuit configuration as shown in FIG. Compared with the semiconductor memory device 1, there is basically no change except that the sense amplifier activation signal SAN is added to the sense amplifier unit 149 and the dummy word system element is deleted.

  The sense amplifier unit 149 is formed by cross-connecting a CMOS inverter composed of a P-type MOS transistor 13 and an N-type MOS transistor 14 and a CMOS inverter composed of a P-type MOS transistor 15 and an N-type MOS transistor 16. The common source of the N-type MOS transistors 14 and 16 is connected to the source of the N-type MOS transistor 18. The drain of the N-type MOS transistor 18 is connected to the ground potential, and the signal obtained by inverting the sense amplifier activation signal SAN for driving the sense amplifier unit 149 by the inverter element 12 is connected to the gate. The source of the P-type MOS transistor 17 is connected to the common source of the P-type MOS transistors 13 and 15. The drain of the P-type MOS transistor 17 is connected to VCC, and the gate is connected to a signal obtained by inverting the sense amplifier activation signal SAP for driving the sense amplifier unit 149 by the inverter element 11.

  The control and the accompanying operation are the same as those in the first embodiment except for the precharge potential and the boot width. Note that the sense amplifier array 148 in the first embodiment corresponds to the sense amplifier array 150 in the present embodiment.

Next, the operation of the semiconductor memory device according to the second embodiment of the present invention will be described.
FIG. 8 is a timing chart showing the operation of the semiconductor memory device according to the second embodiment of the present invention. In this figure, changes in WLU, PDLU and PDLL (indicated by PDLU / L), / act, TGU, TGL, SAP and SAN, and blu and / bl in timing periods t1 to t6 are shown on the upper side of the graph (ground potential GND˜ (HfVcc) to (power supply potential VCC) to (boosted potential Vpp2) to boosted potential Vpp), and changes in gu, / gu, blc, / blc are shown on the lower side of the graph (ground potential GND to (HfVcc) to power supply potential VCC. ). The array selection signals TGUP and TGLP and the bit line transfer gate non-selection signals STBU and STBL are not shown. Hereinafter, the example of this figure shows an example in which the memory cell 128 of the upper cell array unit 101 in FIG. 7 is selected. At this time, the array selection signal TGLP is at the low level (GND), TGUP is at the high level (VCC), and the N-type transistors 123 and 126 are turned off, so that the sense amplifier unit shared and shared by the cell array units 101 and 104 102 is activated to amplify the data in the memory cells of the cell array unit 101. Although description is omitted, when the memory cell 132 of the lower cell array unit 104 in FIG. 7 is selected, only the state of the array selection signals TGLP and TGUP is reversed, and thereafter the same operation is performed.

(1) Standby timing period t1
The bit line pair equalizing signals PDLU and PDLL for supplying a boosted potential Vpp2 (VCC + (potential higher than the threshold value of the N-type transistors 109 to 111 and 118 to 120)) sufficient to balance the bit lines are at a high level (Vpp2). The bit line pair blu, / blu is balanced and precharged to the HfVcc potential. Since other than that is the same as (1) in 1st Embodiment, description is abbreviate | omitted.

(2) Timing period t2 of standby release, array selection, and start of precharge to self-boot node
Since there is no difference from (2) in the first embodiment except for the precharge potential (HfVcc) of the bit line pair, the description is omitted.

(3) Timing period t3 of word activation and self-boot node precharge
In the example of FIGS. 1 to 4 (FIGS. 1 to 4), the control signals BLTl and BLTr that are connected to a plurality of sense amplifier arrays 30 and become long wirings are not high withstand voltages, which are nodes of self-boot in this embodiment. The gate nodes gu and / gu of the N-type transistors 114 and 117 have a small load capacity and are not high withstand voltage.
VCC-Vtn112 (Vtn112: threshold value of the low VTN transistor 112,
Vtn112≈Vtn115 (: The threshold value of the low VTN transistor 115 is the same as that of the low VTN transistor 112, so the threshold value is almost the same including the process variation))
Set to In parallel with the activation (Vpp) of the word line WLU0, the data of the cell 128 propagates to the bit line blu, and then passes through the N-type transistor 114 which is a bit line transfer gate and does not have a high withstand voltage. Propagates to the bit line blc. At the same time, the bit line / blc in the sense amplifier maintains the HfVcc potential together with the bit line / bl via the N-type transistor 117 which is a bit line transfer gate and is not high withstand voltage.

(4) Sense amplifier active, self boot start timing period t4
Sense amplifier activation signals SAP and SAN (VCC and GND) activate amplification by the sense amplifier unit 149, the sense amplifier bit line blc potential rises, and the sense amplifier bit line / blc potential begins to fall. This raises the potential of the bit line blu smaller by HfVcc than that of the first embodiment via the N-type transistor 114 which is a bit line transfer gate and does not have a high breakdown voltage. As the potential of the bit line blu rises, the self-boot gate node gu of the N-type transistor 114 which is a bit line transfer gate and does not have a high breakdown voltage rises to VCC or higher due to self-boot. When the potential that has risen above VCC reaches VCC + Vtn112 (Vtn112: the threshold value of the low VTN transistor 112), the write voltage (bit line blue potential) to the memory cell 128 becomes VCC, and sufficient charge is required for reading. Can be secured. The self-boot gate node gu holds the booted potential because there is no potential drop of blu during the active period of the sense amplifier unit 149. The potential of the self-boot node / gu finally settles to VCC-Vtn 115 (Vtn 115: threshold of the low VTN transistor 115) via the N-type transistor 115.

(5) Timing period t5 of internal initialization start and self-boot end
After securing the rewrite charge of the memory cell 128, the word line WLU0 becomes inactive (GND). In response to the subsequent inactivation (GND and VCC) of the sense amplifier activation signals SAP and SAN, the gate node gu of the N-type transistor 114, which is a bit line transfer gate and is not high withstand voltage, goes to the GND level. The array activation signal / act receives a high level (VCC), and the bit line transfer gate selection signal TGU becomes a low level (GND). The bit line transfer gate non-selection signal STBU becomes High level (VCC), and the gate node / gu of the N-type transistor 117 that is not a high breakdown voltage and is the bit line transfer gate of the bit line / bllu also settles at the GND level. The bit line pair blu / bl receives a high level (Vpp2) of the bit line pair equalizer PDLU, and is balanced and precharged to the HfVcc potential.

(6) Timing period t6 when initialization is performed
Thereafter, the inside repeatedly operates from t1 to t5.

  As shown in the present embodiment, the technique shown in the first embodiment in the bit line precharge method can be applied to the ½ (Half) VCC method, and is the same as in the first embodiment. The effect of can also be obtained. Therefore, the present invention has a wide application range.

The present invention has at least the following effects.
(I) The first effect is reduction of current consumption. The reason is that the present invention can obtain a self-boot without supplying the boosted potential Vpp potential to the bit line transfer gate selection circuit, so that the load of the boosted potential Vpp generation circuit can be reduced.
(II) As a second effect, there is a reduction in circuit area. This is because the boosted potential Vpp generation circuit and related circuits are reduced in size, and a high breakdown voltage transistor in the array is not required.

  The present invention is not limited to the embodiments described above, and it is obvious that the embodiments can be appropriately modified or changed within the scope of the technical idea of the present invention.

DESCRIPTION OF SYMBOLS 1 Semiconductor memory device 101, 104 Cell array part 102, 149 Sense amplifier part 103 Write / read system element part 105, 107 Bit line transfer gate selection circuit 106, 108 Bit line transfer gate non-selection circuit Q29, 109, 118 N-type transistor Q30 Q31, 110, 111, 119, 120 N-type transistor N10, N12 N-type transistors 112, 115, 121, 124 Low VTN type transistors N11, N13, 113, 116, 122, 125 N-type transistors 114, 117, 123, 126 N-type transistors 62, 63, 65, 66 Inverter elements Q25, Q27, 13, 15 P-type MOS transistors Q26, Q28, 14, 16 N-type MOS transistor 17 P-type MOS transistor 18 N MOS transistors 11, 12 Inverter elements DC1, DC2, 146, 147 Dummy cells Q1, Q2, 127, 129, 131, 133, N-type transistors C1, C2 Capacities 128, 130, 132, 134 Memory cells 61, 64, 135, 139 NAND gate 137, 141 Inverter element 143, 145 Inverter element 136, 140 Delay element 142, 144 NOR gate 10, 20 Memory cell array 30, 148, 150 Sense amplifier array MC1, MC2 Memory cells BL, / BL, blu, / blu, bll, / bll Bit line pairs WL1, WL2, WLU0-WLUn, WLL0-WLLn Word lines DWL1, DWL2, DWL0 Dummy word line SA Sense amplifier BP Precharge circuit Q00-Q11 Bit line traffic Scan fur gate 42 bit line transfer gate drive circuit C00~C11 coupling capacitance N14, N15, N16 clamping transistor diode Vpp boosted voltage Vpp2 boosted voltage

Claims (7)

A plurality of sense amplifier arrays extending in the first direction and arranged in the second direction;
A plurality of driver units connected to the plurality of sense amplifier arrays,
Each of the plurality of sense amplifier arrays includes:
A pair of bit lines extending in the first direction;
A sense amplifier connected to the bit line pair;
A precharge unit connected to the bit line pair and provided on both sides of the sense amplifier unit;
A memory array unit connected to the bit line pair and provided on the opposite side of the sense amplifier unit of each precharge unit;
A switch unit provided on the bit line pair between the precharge unit and the sense amplifier unit,
The memory array unit includes a plurality of memory cells provided corresponding to intersections of a plurality of word lines extending in the second direction and the bit line pair,
The precharge unit precharges the bit line pair to a predetermined potential during a precharge period,
The switch unit propagates memory cell data based on a signal for controlling the switch unit generated by any one of the plurality of driver units when the memory cell is selected. The semiconductor memory device according to claim 1,
The driver unit includes two N-type transistors connected in series,
Of the two N-type transistors, the source of one N-type transistor is connected to the power supply potential, and the source of the other N-type transistor is connected to the GND potential.
The threshold voltage of the one N-type transistor is lower than the threshold voltage of the other N-type transistor. The semiconductor memory device according to claim 1,
The driver unit drives the switch unit only when the bit line pair is active. Semiconductor memory device. The semiconductor memory device according to claim 2,
A selector for driving the one N-type transistor;
A non-selection unit for driving the other N-type transistor,
The element of the selection unit is driven by the power supply potential. The semiconductor memory device according to claim 1,
The semiconductor memory device, wherein the precharge unit has a precharge potential of a GND potential. The semiconductor memory device according to claim 1,
In the semiconductor memory device, the precharge unit has a precharge potential that is ½ of a power supply potential. The semiconductor memory device according to claim 1,
The driver section is provided for each of the bit line pairs.

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