JP2012143048A - Disconnection detection circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a disconnection detection circuit that can reliably detect a disconnection of a load even when using an LC filter circuit on an output side for synchronous rectification operation.SOLUTION: In a configuration having an LC filter circuit 8 inserted between a common connection point A of N channel MOSFETs 3, 4 and a load 6, a synchronous rectification control circuit 13 periodically stops a synchronous rectification operation for a constant time, and in the stop duration the N channel MOSFET 3 provides a fixed duty pulse drive. As the synchronous rectification control circuit 13 operates as above, a load disconnection check circuit 14 determines a disconnection according to whether or not a pulsed voltage signal appears at a source of the N channel MOSFET 3, that is, the point A.

Description

  The present invention relates to a disconnection detection circuit that detects disconnection of a load in a configuration including a series circuit of a driving switching element that energizes a load and a switching element for synchronous rectification between a power source and a ground.

  For example, in Patent Document 1, an energization path 3 composed of a series circuit with a resistor R2 and a transistor 5 sufficiently larger than the load resistance R1 is formed in parallel with the switching element 2 for supplying power, and the energization path 3 A configuration is disclosed in which a microcomputer 12 detects a voltage change at a connection point A between the load 1 and the load 1. Then, by turning on the transistor 5 when the switching element 2 is off, the state where the load 1 is disconnected is detected by the divided potential A between the power supply and the ground.

JP 2002-199577 A (see FIG. 1)

  By the way, in the drive system as described above, radiation noise is generated by changing the energization voltage waveform to the load into a rectangular wave shape. Therefore, an LC filter circuit may be connected for the purpose of suppressing the generation of noise. In addition, when the L load such as a motor is driven on the high side as described above, the switching element is connected to the low side in order to prevent loss due to the return current flowing during the OFF period of the switching element. A synchronous rectification method for turning on the switching element may be employed.

  When the disconnection detection method of Patent Document 1 is adopted for the configuration to which these are applied, the synchronous rectification operation is continued when resonance is generated by the LC filter circuit even if the load 1 is disconnected, and the voltage dividing point if the low-side switching element is turned on. The potential decreases. Therefore, disconnection cannot be detected. Although it is conceivable to insert a resistance element for current detection in series with the load to monitor the energization state of the load current, there is a problem that the drive efficiency of the load is lowered.

  The present invention has been made in view of the above circumstances, and an object thereof is to provide a disconnection detection circuit capable of reliably detecting disconnection of a load even in a configuration in which an LC filter circuit is arranged on the output side to perform a synchronous rectification operation. There is.

  According to the disconnection detection circuit of claim 1, in the configuration in which the LC filter circuit is inserted between the common connection point of the series circuit of the driving switching element and the synchronous rectification switching element and the load, the control circuit is fixed The synchronous rectification operation is stopped for a fixed time for each period, and pulse driving is performed with a fixed duty by the driving switching element during the stop period. Then, the disconnection detection unit determines the disconnection based on whether or not a pulse voltage signal is output to the output terminal of the drive switching element when the control circuit operates. Therefore, even when the LC filter circuit is arranged on the output side and the synchronous rectification operation is performed by the synchronous rectification switching element, it is possible to reliably detect the disconnection of the load by eliminating those influences.

  According to the disconnection detection circuit of claim 2, the disconnection detection unit determines disconnection when a pulse voltage signal is not continuously detected a predetermined number of times in the disconnection determination performed every predetermined period. It is possible to more reliably detect the occurrence of.

  According to the disconnection detection circuit of the third aspect, the first abnormality detection unit detects an abnormality by comparing the drive control signal given to the drive switching element with the voltage signal outputted to the output terminal of the element. The second abnormality detection unit performs abnormality detection based on a change in the voltage between the output terminals of the element during the period when the driving switching element is on. That is, if no disconnection occurs, a voltage signal corresponding to the drive control signal should be output to the output terminal of the drive switching element, and the output during the period when the drive switching element is on Although the voltage between terminals is reduced, it should not be lower than the on-voltage generated when the load is driven in a normal state. When either of the first and second abnormality detection units detects an abnormality, the disconnection determination operation is performed by the control circuit and the disconnection detection unit, so that the occurrence of the disconnection can be more reliably detected. In addition, since the disconnection determination operation is performed only when one of the first and second abnormality detection units detects an abnormality, the energization current to the load is not affected by the disconnection determination operation.

  According to the disconnection detection circuit of the fourth aspect, the first abnormality detection unit changes the drive control signal and changes the voltage signal output to the output terminal of the drive switching element for each period of pulse driving the load. Is detected, and abnormality detection is performed when the mismatch condition continues for a certain period of time. As described above, since the voltage signal corresponding to the drive control signal should be output to the output terminal of the drive switching element if no disconnection occurs, the first abnormality detection unit changes both signals. The occurrence of disconnection can be detected by monitoring the coincidence.

  According to the disconnection detection circuit of the fifth aspect, the second abnormality detection unit monitors the voltage between the output terminals of the driving switching element during the period when the load is pulse-driven, and the low level of the voltage between the output terminals is predetermined. When the state below the threshold value is repeated for a certain period of time, abnormality detection is performed. In other words, if disconnection occurs during the period when the load is pulse-driven and synchronous rectification is performed, the current that flows through the drive switching element is no longer supplied to the load, and only the charge / discharge current for the capacitor of the LC filter circuit. When the synchronous rectification operation is performed, the voltage between the output terminals of the driving switching element changes in a pulse shape due to the charging current, so that the state where the low level of the voltage between the output terminals falls below a predetermined threshold is repeated for a certain period of time. become. Therefore, even when the synchronous rectification operation is continued, it is possible to check the occurrence of disconnection.

  According to the disconnection detection circuit of the sixth aspect, the second abnormality detection unit monitors the voltage between the output terminals of the driving switching element during the period when the load is fully turned on, and the voltage between the output terminals of the driving switching element. When the low level state continues for a certain period of time, abnormality detection is performed. That is, during the period in which the load is fully turned on, a large amount of current flows through the driving switching element, so that the voltage between the output terminals is relatively large. When a disconnection occurs from this state, the current flowing through the driving switching element decreases, and the voltage between the output terminals decreases. Therefore, by detecting this state, it is possible to check the occurrence of disconnection even in the full-on drive state.

The figure which is 1st Example and shows schematically the structure of a disconnection detection circuit Timing chart showing operation of load disconnection check circuit FIG. 1 equivalent view showing the second embodiment The figure which shows the detailed structure of a 2nd abnormality detection part (the 1) Timing chart showing circuit operation The figure which shows the detailed structure of a 1st abnormality detection part. Figure equivalent to FIG. The figure which shows the detailed structure of a 2nd abnormality detection part (the 2) Figure equivalent to FIG. Flow chart showing overall processing including each circuit operation FIG. 3 equivalent view showing the third embodiment

(First embodiment)
The first embodiment will be described below with reference to FIGS. FIG. 1 schematically shows a configuration of a disconnection detection circuit. A series circuit of two N-channel MOSFETs 3 and 4 is connected between the positive terminal + B of the power source (battery) 1 and the ground line 2a, and the N-channel MOSFET 3 (driving switching) that is a common connection point between them. The source (output terminal) of the element is connected to the ground via a series circuit of a coil 5 (drive coil) and a load 6. The coil 5 forms an LC filter circuit 8 together with a capacitor 7 connected between the common connection point of the coil 5 and the load 6 and the positive terminal + B. The load 6 is, for example, a motor for driving a fuel pump in a vehicle.

  The ground line 2a is connected to the ground via a coil 9, and the coil 9 is connected to capacitors 10 and 11 connected between both ends thereof and the positive terminal + B, and a π-type filter circuit (LC filter circuit). 12 is constituted. The synchronous rectification control circuit 13 is provided with a PWM signal having a carrier frequency of about 93 kHz, for example, via a load disconnection check circuit (disconnection detection unit) 14 to be described later from a host controller (not shown). 13 drives the N-channel MOSFET 3 through the gate drive circuit 15 in accordance with the PWM signal. The gate drive circuit 15 is supplied with a high voltage via a diode 16 from a booster circuit (not shown), and the cathode of the diode 16 is connected to a common connection point (point A) of the N-channel MOSFETs 3 and 4 via a capacitor 17. It is connected.

  The synchronous rectification control circuit 13 performs a synchronous rectification operation by turning on the N-channel MOSFET 4 (regenerative MOS, synchronous rectification switching element) during the OFF period of the N-channel MOSFET 3 (driving MOS) via the AND gate 18. . The negative logic input terminal of the AND gate 18 is connected to the point A for protection against a power fault. In other words, the AND gate 18 reliably turns off the N-channel MOSFET 4 during the period when the potential at the point A is at a high level. The potential at the common connection point of the coil 5 and the load 6 is input to the control device as a signal for performing feedback control.

  The load disconnection check circuit 14 includes a multiplexer 19, a pulse presence / absence determination unit 20, and a pulse non-detection counter 21. When the check mode enable signal becomes active, the multiplexer 19 converts the PWM signal given to the synchronous rectification control circuit 13 according to feedback control from the control device into a constant duty PWM signal for checking disconnection of the load 6. Switch to output. The check mode enable signal is also given directly to the synchronous rectification control circuit 13. When the check mode enable signal becomes active, the synchronous rectification control circuit 13 stops the synchronous rectification operation by the N-channel MOSFET 4. The pulse presence / absence determining unit 20 determines whether or not a pulsed voltage is output at the point A according to the PWM signal during a period in which the pulse detection timing signal is active.

  The pulse non-detection counter 21 performs a counting operation during a period when the pulse detection timing signal is active, and detects a load disconnection and outputs a diagnosis signal to the control device when the pulse detection timing signal becomes a full count without being cleared. The pulse presence / absence determination unit 20 outputs a signal for clearing the count operation of the pulse non-detection counter 21 when the output of the pulse voltage is detected during the period when the pulse detection timing signal is active.

  Next, the operation of this embodiment will be described with reference to FIG. FIG. 2 is a timing chart showing the operation of the load disconnection check circuit 14. The check mode enable signal shown in FIG. 2 (a) and the pulse detection timing signal shown in FIG. 2 (d) are output in the same cycle, but the latter high level period is located at the end of the former high level period. The falling timings of the two coincide. Further, hatched portions in the figure are periods during which PWM signals are output in accordance with feedback control.

  As shown in FIGS. 2B and 2C, when the check mode enable signal becomes active, a PWM signal having a constant duty is given to the synchronous rectification control circuit 13, and the synchronous rectification operation by the N-channel MOSFET 4 is performed. Is stopped. At this time, if the disconnection of the load 6 has not occurred, the signal output to the point A is a pulse voltage corresponding to the PWM signal as shown in FIG. Therefore, the pulse non-detection counter 21 is cleared via the pulse presence / absence determination unit 20 during the period when the pulse detection timing signal is active. That is, the input unit of the pulse presence / absence determination unit 20 may be configured as an AND gate with one of the negative logic inputs, for example, like the AND gate 18.

  On the other hand, when the disconnection of the load 6 occurs, when the check mode enable signal becomes active, no pulse voltage is output to the point A. Therefore, the pulse non-detection counter is in the period when the pulse detection timing signal is active. Since 21 is not cleared and becomes a full count, a diagnosis signal is output to the control device.

  As described above, according to the present embodiment, in the configuration in which the LC filter circuit 8 is inserted between the common connection point of the N-channel MOSFETs 3 and 4 and the load 6, the synchronous rectification control circuit 13 is constant every fixed period. The synchronous rectification operation is stopped for a time, and pulse driving is performed with a fixed duty by the N-channel MOSFET 3 during the stop period. Then, when the synchronous rectification control circuit 13 operates as described above, the load disconnection check circuit 14 determines disconnection depending on whether or not a pulse voltage signal is output to the source; point A of the N-channel MOSFET 3. . Therefore, even when the LC filter circuit 8 and the π-type filter circuit 12 are arranged on the output side and the synchronous rectification operation is performed by the N-channel MOSFET 4, it is possible to reliably detect the disconnection of the load 6 by eliminating those influences. . In this case, the load disconnection check circuit 14 determines the disconnection of the load 6 when the pulse voltage signal is not continuously detected a predetermined number of times at the point A in the disconnection determination performed at regular intervals. It is possible to detect the occurrence more reliably.

(Second embodiment)
3 to 10 show a second embodiment. The same parts as those in the first embodiment are denoted by the same reference numerals, and the description thereof is omitted. Hereinafter, different parts will be described. As shown in FIG. 3, in the second embodiment, a synchronous rectification control circuit 22 is arranged instead of the synchronous rectification control circuit 13, and further, a first abnormality detection unit 23, a second abnormality detection unit 24, and an OR gate 25. And have been added. The first abnormality detection unit 23 performs abnormality detection by comparing the PWM signal output from the synchronous rectification control circuit 22 to the gate drive circuit 15 and the voltage signal output at the point A, and the second abnormality detection unit 24 The change in the gate-source voltage of the N-channel MOSFET 3 is monitored to detect an abnormality.

  The abnormality detection signals output from the first and second abnormality detection units 23 and 24 are output to the load disconnection check circuit (disconnection detection unit) 26 inside the synchronous rectification control circuit 22 via the OR gate 25. The function of the load disconnection check circuit 26 is basically the same as that of the load disconnection check circuit 14 of the first embodiment.

  4 and 8 show a detailed configuration of the second abnormality detection unit 24, and FIG. 6 shows a detailed configuration of the first abnormality detection unit 23. Although these are shown in an independent state in each figure, they are actually connected in parallel. First, the second abnormality detection unit 24A shown in FIG. 4 corresponding to the case where the load 6 is fully turned on will be described. In FIG. 4, circuit elements that are not necessary for explanation are omitted. An open switch inserted between the point A and the load 6 indicates a disconnection of the load 6.

  A current drop detection unit 27 is connected between the drain and source of the N-channel MOSFET 3, and the current drop detection unit 27 outputs a high level detection signal when detecting a voltage drop between the drain and source. The output terminal of the current drop detection unit 27 is connected to the clear terminal CLR of the 3-bit counter 29 via the inverter gate 28. For example, the 3-bit counter 29 performs an up-count operation with a clock signal having a period of 8 ms, and outputs a high-level full count signal to the abnormality detection circuit 30 when the count value reaches “7”. The abnormality detection circuit 30 is configured by, for example, a D flip-flop, and a clock signal (determination period signal) having a period of, for example, 0.2 s is supplied to the clock terminal CK.

  FIG. 5 is a timing chart showing the operation of the circuit shown in FIG. The corresponding signals in both figures are marked with a circle number. In the case of full-on driving, the driving signal (driving control signal) GH supplied to the gate of the N-channel MOSFET 3 is maintained at a high level, and the load 6 is energized continuously. At this time, since the drain-source voltage of the N-channel MOSFET 3 is obtained by multiplying the ON resistance of the N-channel MOSFET 3 by the drain current, the current drop detection unit 27 outputs a low level signal, and the 3-bit counter 29 It continues to be cleared. For example, even if the current drop detection unit 27 temporarily outputs a high level signal due to the influence of noise or idling when the load 6 is a pump motor, the high level period is less than 56 ms. The 3-bit counter 29 does not reach full count.

  When the load 6 is disconnected, no drain current flows, so the drain-source voltage of the N-channel MOSFET 3 decreases. Then, since the clearing of the 3-bit counter 29 is released, when 56 ms elapses, the count is full and a high level signal is output to the abnormality detection circuit 30. Since the abnormality detection circuit 30 performs abnormality determination with a clock cycle of 0.2 s, an abnormality detection signal is output when the clock is input.

  Next, the first abnormality detection unit 23 shown in FIG. 6 will be described. The non-inverting input terminal of the comparator 31 is connected to the point A, and a reference voltage for comparison is given to the inverting input terminal (not shown, but the output signal of the comparator 31 is actually synchronized with a clock signal of 4 MHz. ). The drive signal GH given to the gate of the N-channel MOSFET 3 and the output signal terminal of the comparator 31 are connected to the input terminal of the pulse presence / absence coincidence determination unit 32, respectively. The pulse presence / absence coincidence determination unit 32 is supplied with a 10.25 μs clock signal synchronized with the carrier wave period of the PWM signal.

  The pulse presence / absence coincidence determination unit 32 compares the output signal of the comparator 31 with the PWM signal applied to the gate of the N-channel MOSFET 3. The output signal of the pulse presence / absence coincidence determination unit 32 is given to the clear terminal CLR of the 3-bit counter 34 via the OR gate 33. Similar to the counter 29, the 3-bit counter 34 performs an up-count operation with a clock signal having a cycle of 8 ms, and outputs a low-level full count signal to the abnormality detection circuit 35 when the count value reaches “7”. A clock signal with a period of 0.2 s is applied to the clock terminal CK of the abnormality detection circuit 35. The clock signal is also given to the input terminal of the OR gate 33. In FIG. 6, a NOR gate is connected to the gate of the N-channel MOSFET 4 in place of the AND gate 18. This is because the illustration is simplified for explaining the operation principle.

  FIG. 7A is a timing chart showing the operation of the first abnormality detector 23, and FIG. 7B shows a part of FIG. The pulse presence / absence coincidence determination unit 32 uses each cycle of the PWM signal as a determination interval and detects both the rising edge of the drive signal GH applied to the gate of the N-channel MOSFET 3 and the rising edge of the output signal of the comparator 31. Detects coincidence of pulses and outputs a low level signal. However, when the 3-bit counter 34 reaches full count, a low level signal is not output even if a pulse coincidence is detected (in this case, the 3-bit counter 34 is cleared by a clock pulse having a period of 0.2 s). . For example, a logical product signal of both signals obtained by capturing each rising edge with a flip-flop and the full count signal is applied to the data terminal D of the flip-flop of the next stage and triggered by a clock signal of 10.25 μs. The edge detection flip-flop may be cleared by giving a slight delay to the clock signal.

  Actually, as shown in FIG. 7B, a dead time is added between the drive signals GH and GL supplied to the gates of the N-channel MOSFETs 3 and 4. The output signal (detection signal) of the comparator 31 is slightly delayed in response to the drive signal GH, but by detecting the rising edge of both signals, the coincidence of both pulses can be reliably detected within the carrier wave period. it can.

  The 3-bit counter 34 is cleared at a period of 0.2 s and the output signal becomes high level. However, since there is a propagation delay due to the OR gate 33, the abnormality detection circuit 35 is triggered first. Therefore, if no disconnection occurs, the abnormality detection circuit 35 outputs a low level. If the charge / discharge current to the capacitor 7 of the LC filter circuit 8 is small after the disconnection occurs and the current supply to the load 6 is cut, the potential drop at the point A when the N-channel MOSFET 3 is turned off Since the output signal of the comparator 31 becomes high level, a pulse corresponding to the rising edge of the drive signal GH is not output, and the 3-bit counter 34 is cleared. When a period in which only one of the rising edges is not detected occurs at a timing of 56 ms or less, the high level signal is latched at the trigger timing of the abnormality detection circuit 35, and abnormality detection is performed.

  The time of 56 ms is determined in consideration of the following points. Even when the disconnection of the load 6 occurs, the control device continues the feedback control for the temporary increase of the output potential, so that the N-channel MOSFET 3 is once turned off continuously. The N-channel MOSFET 4 is also continuously turned off by the action of the AND gate 18 when the voltage at the point A is increased. Since the A point has a finite impedance with respect to the ground by various connected circuits, the potential at the A point has a certain time constant even when the PWM control is stopped. Go down. As a result, PWM control is resumed. Therefore, in the above-described temporary N-channel MOSFET 3 continuous off period, the pulse presence / absence coincidence determination unit 32 makes a coincidence determination. Therefore, the determination time 56 ms by the 3-bit counter 34 is until the PWM control is resumed. Set to be longer than

  Next, the circuit shown in FIG. 8 will be described. This is a configuration (second abnormality detection unit 24B) that detects a decrease in energization current of the N-channel MOSFET 3 during PWM control in the second abnormality detection unit 24, and includes a current decrease detection unit 36, a pulse presence / absence determination unit 37, A 3-bit counter 38 and an abnormality detection circuit 39 are included. The current drop detection unit 36 outputs a high level signal when the low level of the drain-source voltage of the N-channel MOSFET 3 falls below a predetermined threshold. That is, as in the case of FIG. 4, when the disconnection of the load 6 occurs, the low level of the drain-source voltage becomes lower than before the disconnection occurs.

  Similar to the pulse presence / absence coincidence determination unit 32, the pulse presence / absence determination unit 37 sets each cycle of the PWM signal as a determination section, and when the current drop detection unit 36 outputs a high level signal during that period, the low level signal is converted into 3 bits. Output to the clear terminal CLR of the counter 38. However, when the 3-bit counter 38 reaches full count, a low level signal is not output even if a pulse signal is detected. Other configurations around the 3-bit counter 38 and the abnormality detection circuit 39 are the same as those shown in FIGS. In FIG. 8, a NOT gate is connected to the gate of the N-channel MOSFET 4 instead of the AND gate 18. This is because the illustration is simplified in order to explain the operation principle as in FIG.

  FIG. 9A is a timing chart showing the circuit operation of FIG. 8, and FIG. 8B is an enlarged view of a part of FIG. If the N-channel MOSFET 3 is PWM-controlled without disconnection, the low level of the drain-source voltage when the N-channel MOSFET 3 is turned on exceeds the threshold value. A level signal is output. Therefore, since the pulse presence / absence determination unit 37 outputs a high level signal, the 3-bit counter 38 is continuously cleared.

Then, if the synchronous rectification operation by the N-channel MOSFET 4 continues when the load 6 is disconnected, the following occurs.
(1) When the N-channel MOSFET 3 is turned on, the coil 5 and the capacitor 7 are energized.
(2) When the N-channel MOSFET 3 is turned off, the potential at the point A is lowered by the electromagnetic energy accumulated in the coil 5, and the N-channel MOSFET 4 is turned on.
(3) Then, the direction of the current flowing through the coil 5 is reversed.
(4) When the N-channel MOSFET 4 is turned off, the potential at the point A rises due to the electromagnetic energy accumulated in the coil 5 and exceeds the power supply voltage, so that the current drop detection unit 36 detects the potential drop between the drain and source. A high level signal is output (see FIG. 9B).
(5) When the direction of the current flowing through the coil 5 is reversed again so as to flow toward the capacitor 7, the potential at the point A decreases, and the output signal of the current decrease detection unit 36 becomes low level.
In the above (4), the pulse presence / absence determination unit 37 receives the high level signal and cancels the clearing of the 3-bit counter 38, so that the 3-bit counter 38 performs a counting operation. If this state continues for 56 ms, the 3-bit counter 38 outputs a high level signal, so that the high level signal is latched at the trigger timing of the abnormality detection circuit 39 and abnormality detection is performed.

  The second abnormality detection unit 24 outputs a logical sum signal of the output signal of the abnormality detection circuit 30 shown in FIG. 4 and the output signal of the abnormality detection circuit 35 shown in FIG. It is like that.

  When the signal of the PWM cycle counter is constantly generated regardless of the driving state of the N-channel MOSFET 3, the pulse presence / absence determining unit 37 detects an abnormality by detecting the high level of the input within the PWM cycle interval. Therefore, an abnormality can be detected in the same manner as the abnormality detection circuit 30 shown in FIG. 4 even when the input high level continues, such as a load disconnection that occurs when the N-channel MOSFET 3 is fully turned on. In this case, it is good also as a structure only of the 2nd abnormality detection part 24B shown in FIG.

  FIG. 10 is a flowchart showing the cooperation of circuit operations by the synchronous rectification control circuit 22, the first abnormality detection unit 23, the second abnormality detection unit 24, and the load disconnection check circuit 26, and (a) shows a schematic flow. (B) shows more detailed operation contents. In FIG. 10A, S1 to S3 correspond to abnormality detection operations in the second abnormality detection unit 24A, the first abnormality detection unit 23, and the second abnormality detection unit 24B, respectively. When an abnormality is detected by any of these, the operation proceeds to a disconnection check operation by the load disconnection check circuit 26.

  Then, as shown in FIG. 2, the multiplexer 19 is switched to the PWM signal side having a constant duty for a short period with a period of 0.2 s (step S4; PWM check mode), and the pulse detection timing signal becomes active. If a pulse voltage (VMS) is output at point A (step S5; present), the abnormal state has been resolved and the state is "returned". On the other hand, if no pulse voltage is output during the period, load disconnection diagnosis output is performed (step S6). Subsequent steps S7 to S9 are processes for canceling the load disconnection diagnosis output. If the pulse voltage is output by repeatedly executing the PWM check mode at a cycle of 0.1 s until the pulse voltage is output at point A. Cancel the diagnostic output.

  In FIG. 10B, first, as an initial process, a counter for the number of consecutive undetected times is set to zero, and the diagnosis output is canceled (DI = L, step S11). Then, it is determined whether to shift to the load disconnection check mode (step S12). “Migration determination” here corresponds to the processing of steps S1 to S3 in FIG. 10A, and steps S13 to S25 correspond to the processing of steps S4 to S9 (processing of the first embodiment).

  That is, in step S13, the multiplexer 19 is switched to the constant duty side, the synchronous rectification operation by the N-channel MOSFET 4 is stopped, and in step S14, it is determined whether or not the pulse voltage is output at point A during the period in which the pulse detection timing signal is active. . If the detection frequency of the pulse voltage is equal to or greater than the predetermined number m1, the counter for the number of consecutive non-detections is set to zero (step S15), and the multiplexer 19 is returned to the f / b control duty side (step S16). Then, when the timer for counting the period of 0.2 s in step S4 is reset (step S17), the process returns to step S12.

  On the other hand, if the detection frequency of the pulse voltage is less than the predetermined number m1 in step S14, the counter for the number of consecutive undetections is counted up (step S18). If the number of consecutive undetected times is less than two, the process proceeds to step S16, and if the number of consecutive undetected times is two, load disconnection diagnosis output is performed (step S20). The steps so far correspond to steps S4 to S6, and the subsequent steps correspond to steps S7 to S9.

When the diagnosis output is performed, the process proceeds to step S21 and the same processing as S16 is performed, and a timer for counting the period of 0.1 s in step S7 is set (step S22). Subsequently, the same processes as S13 and S14 are performed in steps S23 and S24, and if the detection frequency of the pulse voltage is less than the predetermined number m1 in step S24, the process returns to step S21. If the detection frequency of the pulse voltage is equal to or greater than the predetermined number m1, the counter for the number of consecutive undetections is set to zero and the diagnosis output is canceled (step S25), and the process returns to step S16.
In addition, the above detection can be similarly detected not only when the load 6 is disconnected, but also when the common connection point between the coil 5 and the load 6 is a power fault, for example.

  As described above, according to the second embodiment, the first abnormality detection unit 23 compares the drive signal GH supplied to the gate of the N-channel MOSFET 3 with the voltage signal output to the source of the N-channel MOSFET 3 to detect an abnormality. The second abnormality detector 24 detects an abnormality based on a change in the drain-source voltage during the period when the N-channel MOSFET 3 is on. When either of the first and second abnormality detectors 23 and 24 detects an abnormality, the disconnection determination operation is performed by the synchronous rectification control circuit 22 and the load disconnection check circuit 26, so that the occurrence of the disconnection is more reliably detected. Can be detected.

  In this case, the first abnormality detection unit 23 monitors whether or not the change in the drive signal GH and the change in the voltage signal at the point A coincide with each other in every cycle in which the load 6 is pulse-driven. Since abnormality detection is performed when it continues only for a certain period of time or less, the occurrence of disconnection can be detected by monitoring the discrepancy between changes in both signals. Further, the second abnormality detection unit 24B monitors the drain-source voltage of the N-channel MOSFET 3 during the period in which the load 6 is pulse-driven, and the state where the low level of the voltage falls below a predetermined threshold is repeated for a certain time. Anomaly detection is performed. Therefore, even when the synchronous rectification operation is continued, it is possible to check the occurrence of disconnection.

  Furthermore, the second abnormality detection unit 24 monitors the drain-source voltage of the N-channel MOSFET 3 during a period in which the load 6 is fully turned on, and performs abnormality detection when the state in which the voltage indicates a low level continues for a certain period of time. Therefore, by detecting this state, it is possible to check the occurrence of disconnection even in the full-on drive state.

(Third embodiment)
FIG. 11 shows the third embodiment, and the differences from the second embodiment will be described. The third embodiment shows a configuration corresponding to the case where the load 6 is driven on the low side. In this case, the N-channel MOSFET 4 is a driving MOS, and a P-channel MOSFET 40 is arranged instead of the N-channel MOSFET 3, and this is a regenerative MOS. A NAND gate 41 is connected between the synchronous rectification control circuit 22L and the gate of the P-channel MOSFET 40, and another input terminal of the NAND gate 41 is connected to the point A.
In such a configuration, the detection processing by the first and second abnormality detection units 23L and 24L and the load disconnection check operation circuit 26L is appropriately performed corresponding to the low-side drive, and similarly to the first and second embodiments. Disconnection of the load 6 can be detected.

  When the determination time using the 3-bit counter in the first abnormality detection unit 23L is set to 56 ms as in the second embodiment, for example, it is determined in consideration of the following points corresponding to the low side drive. That is, even when the load 6 is disconnected, the control device continues the feedback control with respect to the temporary decrease of the output potential, so that the N-channel MOSFET 4 is continuously turned off. Further, the P-channel MOSFET 40 is continuously turned off by the action of the NAND gate 40 when the voltage at the point A decreases.

Since the point A has a finite impedance to the power supply through the connected circuit, the potential at the point A rises with a certain time constant even when the PWM control is stopped. Therefore, the PWM control is resumed. Accordingly, since the pulse presence / absence coincidence determination unit 23L makes a coincidence determination during the temporary off-period of the N-channel MOSFET 4 described above, the determination time 56ms by the 3-bit counter is the time until the PWM control is resumed. Set to be longer than
As described above, according to the third embodiment, the same effects as those of the first and second embodiments can be obtained when the load 6 is driven on the low side.

The present invention is not limited to the embodiments described above or shown in the drawings, and the following modifications or expansions are possible.
A P-channel MOSFET may be used instead of the N-channel MOSFET 3 of the first and second embodiments. Further, the switching element is not limited to a MOSFET, but may be a bipolar transistor, an IGBT, or the like.
The processing of the first embodiment may be executed by software using a microcomputer.
The π-type filter circuit 12 may be deleted.
Only one of the second abnormality detectors 24A and 24B may be used.
The PWM carrier frequency is not limited to 93 kHz. Further, the predetermined time for performing the abnormality detection is not limited to 56 ms, and these may be appropriately changed according to individual designs.

  In the drawing, 1 is a power source, 3 is an N-channel MOSFET (switching element for driving), 4 is an N-channel MOSFET (switching element for synchronous rectification), 6 is a load, 8 is an LC filter circuit, 13 is a synchronous rectification control circuit, 14 Is a load disconnection check circuit (disconnection detection unit), 22 is a synchronous rectification control circuit, 23 is a first abnormality detection unit, 24 is a second abnormality detection unit, 26 is a load disconnection check circuit (disconnection detection unit), and 40 is a P channel. A MOSFET (synchronous rectification switching element) is shown.

Claims (6)

A driving switching element connected between a power source and a ground, for energizing a load, and a series circuit of synchronous rectification switching elements for performing synchronous rectification during a period when the driving switching element is off;
An LC filter circuit inserted between the output terminal of the driving switching element, which is a common connection point of the series circuit, and the load;
A control circuit that stops the synchronous rectification operation for a fixed time every fixed period and performs pulse driving with a fixed duty by the driving switching element during the stop period;
A disconnection detection circuit comprising: a disconnection detection unit configured to determine whether or not a pulse voltage signal is output to an output terminal of the driving switching element when the control circuit operates. .   2. The disconnection detection circuit according to claim 1, wherein the disconnection detection unit performs disconnection determination when a pulsed voltage signal is not continuously detected a predetermined number of times in the disconnection determination performed at each predetermined period. 3. . A first abnormality detection unit that performs abnormality detection by comparing a drive control signal applied to the drive switching element and a voltage signal output to an output terminal of the drive switching element;
A second abnormality detection unit that performs abnormality detection based on a change in the voltage between the output terminals of the driving switching element during a period in which the driving switching element is on;
3. The disconnection detection circuit according to claim 1, wherein when any one of the first and second abnormality detection units detects an abnormality, a disconnection determination operation is performed by the control circuit and the disconnection detection unit.   The first abnormality detection unit determines whether or not the change in the drive control signal and the change in the voltage signal output to the output terminal of the drive switching element coincide with each other for each period of pulse driving the load. 4. The disconnection detection circuit according to claim 3, wherein monitoring is performed and abnormality detection is performed when the inconsistency state continues for a predetermined time.   The second abnormality detector monitors a voltage between the output terminals of the driving switching element during a period in which the load is pulse-driven, and a low level of the output terminal voltage of the driving switching element has a predetermined threshold value. 5. The disconnection detection circuit according to claim 3, wherein abnormality detection is performed when the lowering state is repeated for a predetermined time.   The second abnormality detection unit monitors the voltage between the output terminals of the driving switching element during a period in which the load is fully turned on, and the state where the voltage between the output terminals of the driving switching element is at a low level is constant for a certain period of time. 6. The disconnection detection circuit according to claim 3, wherein abnormality detection is performed when the connection is continued.

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