JP2012137944A - Memory access device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To read data with high speed even when a data size of a read request does not match an access unit of a memory.SOLUTION: A memory command output control unit 90 reads data by an access unit from a memory device 30 based on a read request of a CPU 10, and a read preliminary data holding unit 60 holds the data of the last access unit among the read data. When the next read request is made by the CPU 10, a data selection control unit 70 reads only data of the access units which are not held in the read preliminary data holding unit 60 among the data which is an object of the read request, from the memory device 30 through the memory command output control unit 90, and returns the data read from the memory 30 and the data held by the read preliminary data holding unit 60 to the CPU 10. High-speed data readout is thus possible because it is not necessary to redundantly read the same access units from the memory device 30.

Description

  The present invention relates to a technique for speeding up reading of data from a memory.

Compared with a memory control device without an ECC control function, a conventional memory control device with an ECC (Error Correcting Code) control function requires extra ECC inspection and correction processing when reading data from the memory. It is disadvantageous in performance.
For this reason, the conventional memory control device with an ECC control function reads in advance a certain amount of data at an address beyond the necessity of a read request and holds it in a buffer in the memory control device, If a read request is made later for the memory address where the data is stored in the buffer, the memory is not read again, and the contents in the buffer that has been read and held in advance are not read. Speeding up is performed by transmitting data to the read request source (for example, Patent Document 1).

JP 2002-149501 A

  The conventional memory control device adopts a horizontal ECC method, and prepares ECC bits or ECC memory elements in the width direction of data (for example, in FIG. 4, 4 columns are ECC bits or data). This is effective when the size required for one memory access is the same as the size of the data requested by the read request source, or one of them is an integer multiple of the other. In this case, there is a problem that the cost of the memory element is high.

In recent embedded devices and the like, the memory capacity itself does not need to be so large, and there is no cost for using a memory element having a wide data width for ECC or preparing a memory element for ECC separately. Therefore, it is required to improve the reliability of products.
For this reason, it has become necessary to adopt a vertical ECC method in which ECC is added in the depth direction of data. However, since the arrangement of data on the memory is shifted in the depth direction, the conventional memory control device stores data in advance. In order to read extra data and keep it in the buffer, an extra read access will occur if the address requested to be read is an intermediate address for the memory access unit on the memory. There is a problem.

For example, the memory is arranged with the data as shown in FIG. 3 adopting the vertical ECC method, but the read request source recognizes the memory address with the data arrangement without the ECC as shown in FIG. Suppose.
In this case, if an attempt is made to read 16 bytes from the address 10 on the arrangement of the read request source data without ECC (FIG. 2) (1 BANK in memory access unit), the memory access unit in FIG. ) Requires BANK1 and BANK2 reads.
Therefore, in order to read 1 BANK from address 20, which is the next BANK on the read request source data arrangement (FIG. 2), the BANK2 and BANK3 reads are required in the memory data arrangement (FIG. 3). .
Thus, in order to read addresses 10 and 20 on the data arrangement (FIG. 2) of the read request source, BANK2 (FIG. 3) must be read twice.
Even in the conventional technique of pre-reading the buffer up to the previous address in advance, when reading to BANK where half of the data is left, ECC check and correction are performed within the range where all the data and ECC bytes are prepared, and the buffer is stored. It is necessary to read and discard the half-length part to enter.
When the BANK memory read for half-end becomes necessary, it is necessary to read the same BANK from the memory again, which is not efficient.

  The main object of the present invention is to solve the above-described problems, and to realize a method capable of reading data at high speed even when the data size of the read request does not match the access unit of the memory device. With a purpose.

A memory access device according to the present invention includes:
It is connected to a memory device that stores data by dividing the address space by an access unit of a specific size,
When there is a read request for data in the memory device from a processor device using the memory device, data is read from the memory device according to an access unit so that the data requested by the read request is included, and the memory device A memory access unit for outputting data read from the processor device;
And a data storage unit for selecting and storing data of the last access unit among the data read by the memory access unit.

  According to the present invention, the data in the last access unit among the data read from the memory device is held in the data storage unit. Therefore, in the next read request, other than the access unit held in the data storage unit Since it is only necessary to read the access unit from the memory device, even if the data size of the read request and the access unit of the memory device do not match, there is no need to read the same access unit from the memory device again. Data can be read.

1 is a diagram illustrating a configuration example of a memory control system according to Embodiment 1. FIG. The figure which illustrates the relationship between the data recognized by the read request origin, and an address. The figure which illustrates the relationship between the data and the address in a memory device. The figure which shows the structure which prepared the bit for ECC in the width direction of data. FIG. 4 is a diagram illustrating a configuration example of a memory control system according to a second embodiment.

Embodiment 1 FIG.
In this embodiment, a method for realizing high-speed data reading when the memory device access unit is odd with respect to the data size of the read request will be described.
FIG. 1 shows a configuration example of the memory control system of the present invention according to the present embodiment.

In FIG. 1, reference numeral 10 denotes a CPU (Central Processing Unit) which is a processor device.
Reference numeral 11 denotes a CPU command bus.
Reference numeral 12 denotes a CPU data bus.

Reference numeral 30 denotes a memory device (hereinafter also simply referred to as a memory 30).
As shown in FIG. 4, the memory device 30 stores data by dividing an address space into access units of a specific size (16 bytes in the case of FIG. 4).

Reference numeral 20 denotes a memory read / write control unit with an ECC control function.
The memory read / write control unit 20 with an ECC control function adds an ECC to the data received through the CPU data bus 12 for a write request including address information received from the CPU 10 to the memory 30 through the CPU command bus 11.
Also, the address received via the CPU command bus 11 is converted into an address on the memory 30, a write request including address information is issued to the memory 30 via the memory command bus 100, and the write target data is sent via the memory data bus 500. Send.
Further, for a read request including address information received from the CPU 10 to the memory 30 through the CPU command bus 11, the address received through the CPU command bus 11 is converted into an address on the memory 30, and the memory command bus 100 is sent to the memory 30. The read request including the address information is issued through the memory 30 and the read data received from the memory 30 is received through the memory data bus 500.
The connection method between the CPU 10 and the memory read / write control unit 20 with the ECC control function may be a one-to-one connection as in the present configuration, or a bridge to the I / O bus or other functional means may be connected. It may be a general purpose bus.

Reference numeral 70 denotes a data selection control unit.
When there is a read request for data in the memory device 30 from the CPU 10, the data selection control unit 70 reads the data from the memory device 30 according to the access unit so that the data requested by the read request is included, and the memory device The data read from 30 is output to the CPU 10 via the memory read / write control unit 20 with ECC control function.
More specifically, the data selection control unit 70 inputs a memory command issued from the memory read / write control unit 20 with ECC control function 20 to the memory 30 via the memory command bus 100, and the memory command is stored in the memory 30. The address stored in the memory 30 of the read spare data holding unit 60 is input from the read spare data address holding unit 50, and the two are compared and compared. If the results match, the data in the read spare data holding unit 60 input from the read spare data bus 300 is selected and output to the memory data bus 500. If the comparison results do not match, the data is read from the memory 30. The data input via the memory data interface bus 200 is selected and the memory data bus 500 is selected. To output.
When a memory command issued from the memory read / write control unit 20 with ECC control function 20 to the memory 30 is input via the memory command bus 100 and the memory command is a write request to the memory 30, the ECC Write data input from the memory read / write control unit with control function 20 via the memory data bus 500 is output to the memory 30 as it is.
The data selection control unit 70 and the memory command output control unit 90 constitute a memory access unit.

Reference numeral 90 denotes a memory command output control unit.
The memory command output control unit 90 matches the address of the memory read command issued by the memory read / write control unit with ECC control function 20 via the memory command bus 100 with the address stored in the read spare data address holding unit 50. In this case, the information is received from the data selection control unit 70 via the read spare data address hit control bus 900, and the read access is not output to the memory 30.
In addition, when the address of the memory read command issued by the memory read / write control unit 20 with the ECC control function 20 via the memory command bus 100 does not match the address stored in the read spare data address holding unit 50, Memory read access to the memory 30 is performed.
The memory command output control unit 90 and the data selection control unit 70 constitute a memory access unit.

Reference numeral 60 denotes a read spare data holding unit.
The read spare data holding unit 60 selects and stores the last access unit (BANK) data among the data read by the data selection control unit 70 and the memory command output control unit 90.
The read spare data holding unit 60 is an example of a data storage unit.

Reference numeral 50 denotes a read spare data address holding unit.
The read spare data address holding unit 50 stores the address range of the last access unit in which data is stored in the read spare data holding unit 60.
The read spare data address holding unit 50 is an example of an address storage unit.

Also, 100 is a memory command bus, 200 is a memory data interface bus, and 300 is a read spare data bus.
500 is a memory data bus, 600 is a memory device command bus, 700 is a memory command data synchronization signal, and 900 is a read spare data address hit control bus.

  In FIG. 1, the range surrounded by the alternate long and short dash line corresponds to the memory access device of the present application.

Next, the operation will be described.
First, a read operation from the CPU 10 to the memory 30 will be described.

The CPU 10 issues a read request to the memory 30 to the memory read / write control unit 20 with an ECC control function via the CPU command bus 11.
When the memory read / write control unit 20 with the ECC control function receives a read request from the CPU 10 to the memory 30, the memory read / write control unit 20 issues a read request to the memory 30 via the memory command bus 100 to the memory command output control unit 90. To do.

At the time of reading, the data selection control unit 70 compares the address stored in the read spare data address holding unit 50 with the address output by the memory read / write control unit 20 with ECC control function 20 to the memory command bus 100, and they match. In this case, the data selection control unit 70 is notified to the memory command output control unit 90 via the read spare data address hit control bus 900, and the memory command output control unit 90 does not issue a read access to the memory 30.
In this case, the data selection control unit 70 outputs the data input from the read spare data holding unit 60 via the read spare data bus 300 to the memory data bus 500.

On the other hand, if the addresses do not match, that is, the address stored in the read spare data address holding unit 50 by the data selection control unit 70 and the memory read / write control unit 20 with ECC control function are output to the memory command bus 100. As a result of comparing the addresses, if the two addresses do not match, the memory command output control unit 90 performs read access to the memory 30.
The read data is input to the data selection control unit 70 via the memory data interface bus 200.
The data selection control unit 70 outputs the data received from the memory data interface bus 200 to the memory read / write control unit 20 with ECC control function via the memory data bus 500.
The memory read / write control unit with ECC control function 20 performs ECC inspection and correction processing on the data input from the memory data bus 500 and then transmits the data to the CPU 10 via the CPU data bus 12.
Further, the data selection control unit 70 reads the data to be received from the memory data interface bus 200 when the next received data is the last BANK in the unit (1BANK) for accessing the memory. The read preliminary data holding unit 60 and the read preliminary data address holding unit 50 are notified via 900.
When the next received BANK data is the last BANK being read, the read spare data holding unit 60 stores the data, and the read spare data address holding unit 50 stores the address.

For example, the data arranged on the memory in FIG. 3 is recognized by the CPU 10 as shown in FIG. 2 excluding the ECC bytes.
Here, if the CPU 10 tries to read from address 0 to address f, which is a memory access unit, it actually requires up to address 13 on the memory 30 including the ECC byte. The read / write control unit 20 requests the memory 30 to read BANK0 and BANK1 in FIG.
Here, if the BANK1 data is not held in the read spare data holding unit 60, the next time the CPU 10 attempts to read from the address 10 in FIG. 2 to the address 1f which is one memory access unit, the memory in FIG. On BANK 30, BANK1 and BANK2 need to be read, and BANK1 must be read once more, which is not efficient.
However, in the present embodiment, the last BANK of the memory access is stored in the read spare data holding unit 60.
Therefore, in the above example, when the BANK0 and BANK1 data of FIG. 3 is read from the memory 30, the BANK1 data which is the last BANK data is stored in the read spare data holding unit 60.
Therefore, when there is a read request from address 10 to address 1f in FIG. 2 (read request for BANK1 and BANK2 in FIG. 3), BANK1 reads data from the read spare data holding unit 60, and only BANK2 is stored in the memory. By making a read access to 30, the data requested by the CPU 10 can be returned.

As in Patent Document 1, for example, in the memory read / write control unit 20 with ECC control function, even when data previously read up to the previous address is held in the buffer, from address 0 to address 1f in FIG. Is read and held, BANK0, BANK1, and BANK2 in FIG. 3 are issued to the memory 30, and if an attempt is made to read addresses 2f from the previous address 20, BANK2 is read again. Is required and is not efficient.
In addition, when trying to read up to a well-defined address (for example, address 4f) in advance in the memory of FIG. 3, the capacity of the buffer has to be increased, and no further read is issued. When it becomes useless.
Further, when the CPU 10 is connected to the general-purpose bus, if there is a means for requesting memory read other than the CPU 10, the CPU 10 will occupy the memory for a long time, and the system performance may be sacrificed. .

  As described above, in the present embodiment, even in the case where a memory access with respect to the memory access unit (BANK) occurs due to a shift in the address in the memory configuration employing the vertical ECC, the BANK data corresponding to the half end is retained. Therefore, it is not necessary to perform redundant memory access for the half-length BANK data, and useless memory access can be eliminated.

  Next, a write operation from the CPU 10 to the memory 30 will be described.

The CPU 10 issues a write request to the memory 30 via the CPU command bus 11 and issues data to be written to the memory read / write control unit 20 with an ECC control function via the CPU data bus 12.
When the memory read / write control unit 20 with the ECC control function receives a write request to the memory 30 from the CPU 10, it issues a write request to the memory 30 via the memory command bus 100 to the memory command output control unit 90. To do.

Data to be written is added with ECC by the memory read / write control unit 20 with ECC control function and transmitted via the memory data bus 500, but the data selection control unit 70 receives data input from the memory data bus 500 at the time of writing. Is output to the memory data interface bus 200.
At the time of writing, the data selection control unit 70 compares the address stored in the read spare data address holding unit 50 with the address output by the memory read / write control unit 20 with ECC control function 20 to the memory command bus 100, and they match. In this case, the read spare data holding unit 60 receives the read spare data address hit control bus 900 to read and store the data of the memory data interface bus, and the read spare data address holding unit 50 receives the address input from the memory command bus 100. Is stored.

On the other hand, if the addresses do not match, that is, as a result of comparing the address stored in the read spare data address holding unit 50 and the address output to the memory command bus 100 by the memory read / write control unit 20 with ECC control function, If the addresses do not match, the read spare data holding unit 60 and the read spare data address holding unit 50 do not update the stored data and address.
In response to a write request from the memory read / write control unit 20 with ECC control function received from the memory command bus 100, the memory command output control unit 90 sends a memory write command to the memory 30 via the memory device command bus 600. Issue.
Data to be written is transferred from the data selection control unit to the memory 30 via the memory data interface bus 200, and synchronization with a memory command is performed by a memory command data synchronization signal 700.
For example, the memory command output control unit 90 notifies the data selection control unit 70 of the timing at which the memory command is issued by the memory command data synchronization signal 700, and the memory command output control unit 90 measures the output timing of the data from the information and outputs it. It is possible to do so.
Here, the timing differs depending on the type of the memory 30 to be connected.

As described above, in the present embodiment,
A system having a CPU and an ECC control function and means for controlling read and write access to a memory,
When the CPU reads data with ECC from the memory, a read spare data holding unit that holds data for the unit of memory access accessed last;
A read spare data address holding unit that holds an address on a memory of data stored in the read spare data holding unit;
Means for selecting data of the read spare data holding unit when the comparison result matches the function of comparing the read spare data address holding unit and the address of the memory access request;
A data selection control unit having a unit that selects data read from the memory when the comparison result does not match the function of comparing the read spare data address holding unit and the address of the memory access request;
Described a memory control system including a memory command output control unit having a function of not issuing a memory access request when a result of comparison between a read spare data address holding unit and a function of comparing a memory access request address matches .

Embodiment 2. FIG.
In the first embodiment described above, only the last accessed BANK is held when the CPU reads from the memory. Next, when there is a multitask or a plurality of read request sources. FIG. 4 shows an embodiment in which BANK accessed last for a plurality of addresses is held. FIG.
FIG. 5 shows an example of a memory control system in such a case.

Although the basic configuration is the same as that of the first embodiment, a read spare data holding unit 51 and a read spare data address holding unit 61 are added to hold a plurality of BANK data. The read spare data address holding unit and the address input from the memory command bus 100 are compared.
Further, since there are a plurality of read spare data holding units and read spare data address holding units, a read spare data selecting unit 1100 for selecting which read spare data holding unit stores the last read BANK, and its address. A read spare data address selection unit 1000 is provided to select which read spare data address holding unit stores.

  Next, the operation will be described.

The basic operation is the same as in the first embodiment, but the read spare data address selection unit 1000 selects which read spare data address holding unit stores the address of the data read from the memory.
For example, if the read is for the next address after the address stored in the read spare data address holding unit 51, the read preliminary data address holding unit 51 stores the read address.
Alternatively, it is stored in a read spare data address holding unit that has been used recently.
Alternatively, a plurality of read spare data address holding units are stored in order.
For these storage methods, a method convenient for the system may be selected.

The data selection control unit 70 compares a plurality of read spare data addresses with an address input from the memory command bus 100, and determines whether there is a matching address.
If there is a matching address, the memory command output control unit 90 is notified via the read spare data address hit control bus 900 so that the read access to the memory 30 is not issued.
Then, the data selection control unit 70 outputs the data in the read preliminary data holding unit corresponding to the matched read preliminary data address holding unit to the memory read / write control unit 20 with ECC control function via the memory data bus 500.
The data selection control unit 70 reads the target data from the memory device 30 and returns it to the CPU 10 for the data not held in the read spare data holding unit, as in the first embodiment.
At this time, the last BANK data among the data read from the memory device 30 is held in one of the read spare data holding units.

As described above, since the last BANK data to the memory for a plurality of addresses is held, it is possible to cope with access to a plurality of address systems generated by multitasking or the like.
Further, when there are a plurality of access request sources for not only the CPU 10 but also the memory, access to a plurality of address systems can be handled.

  As described above, in the present embodiment, the memory control system including a plurality of read spare data holding units and read spare data address holding units has been described.

  10 CPU, 11 CPU command bus, 12 CPU data bus, 20 memory read / write control unit with ECC control function, 30 memory device, 50 read spare data address holding unit, 51 read spare data address holding unit, 60 read spare data holding 61, spare read data holding unit, 70 data selection control unit, 90 memory command output control unit, 100 memory command bus, 200 memory data interface bus, 300 read spare data bus, 500 memory data bus, 600 memory device command bus, 700 memory command data synchronization signal, 900 read spare data address hit control bus, 1000 read spare data address selector, 1100 read spare data selector.

Claims (6)

It is connected to a memory device that stores data by dividing the address space by an access unit of a specific size,
When there is a read request for data in the memory device from a processor device using the memory device, data is read from the memory device according to an access unit so that the data requested by the read request is included, and the memory device A memory access unit for outputting data read from the processor device;
A memory access device comprising: a data storage unit for selecting and storing data in the last access unit among the data read by the memory access unit. The memory access unit
When there is a read request, if a part of the data requested by the read request is stored in the data storage unit, the data stored in the data storage unit is read and requested by the read request. The data is read from the memory device according to the access unit so that a portion excluding the data stored in the data storage unit is included in the stored data, and the data read from the data storage unit and the memory device is read from the processor The memory access device according to claim 1, wherein the memory access device outputs to the device. The memory access device further includes:
An address storage unit that stores an address range of the last access unit in which data is stored in the data storage unit;
The memory access unit
The address range stored in the address storage unit is referred to, and it is determined whether or not a part of the data requested by the read request is stored in the data storage unit. 3. The memory access device according to 2. The memory access device is:
4. The memory access device according to claim 3, further comprising a plurality of sets of data storage units and address storage units. The memory access unit
When there is a read request, refer to address ranges stored in a plurality of address storage units to identify and specify a data storage unit in which a part of the data requested in the read request is stored The data stored in the data storage unit is read out, and the memory device includes a portion excluding the data stored in the data storage unit in the data requested by the read request according to the access unit. 5. The memory access device according to claim 4, wherein data is read, and data read from the data storage unit and the memory device is output to the processor device. The memory access device is:
6. The memory access device according to claim 1, wherein the memory access device is connected to a memory device in which ECC bits are arranged by a vertical ECC (Error Correcting Code) method.

Images