JP2012134696A - Δς a/d converter - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve a PSRR (Power Supply Rejection Ratio) of a ΔΣ A/D converter.SOLUTION: A switched capacitor type D/A converter 4 converts a digital output signal Dinto an analog feedback voltage V. The D/A converter 4 has m switch circuits 10 each of which is provided for each bit of the digital output signal D. Each switch circuit 10 includes a first switch group (M1 and M4) that is controlled to be turned on when a corresponding bit (Vdata) is 1 and controlled to be turned off when the bit is 0, and a second switch group (M2 and M3) that is controlled to be turned on when the corresponding bit (Vdata) is 0 and controlled to be turned off when the bit is 1. Each switch (M1-M4) of the first switch group and the second switch group is constituted by a P-channel MOSFET (Metal Oxide Semiconductor Field Effect Transistor). A ground voltage is applied to each lower power supply terminal of a first inverter 12 and a second inverter 14.

Description

  The present invention relates to a ΔΣ type A / D converter using a switched capacitor.

  As an A / D converter that converts an analog signal into a digital signal, a ΔΣ type A / D converter is known. The ΔΣ A / D converter includes a feedback D / A converter, an integrator, and a quantizer (see, for example, Patent Document 1).

  As shown in FIG. 7 of Patent Document 1, let us consider a case where the D / A converter and the integrator are configured as a switched capacitor type. As disclosed in Patent Document 3, in a general switched capacitor type D / A converter, an N-channel MOSFET (Metal Oxide Semiconductor Field Effect Transistor) or a transfer gate using the N-channel MOSFET is used as a switch.

JP 2007-049232 A JP 2003-283337 A JP 2001-111427 A

  The present inventor has studied a switched capacitor type D / A converter including an N-channel MOSFET as a switch, and has come to recognize the following problems.

FIG. 1 is a circuit diagram showing a part of the configuration of a switched capacitor type D / A converter.
The switches of the switched capacitor type D / A converter can be classified into a first switch group M11 that is turned on when each bit of the digital signal is 1, and a second switch group M12 that is turned on when it is 0. The first switch group M11 and the second switch group M12 are supplied with gate signals G1 and G2 via the inverters 502 and 504, respectively.

  The N-channel MOSFET is turned on when a high level voltage is applied to its gate and turned off when a low level voltage is applied. The gate signals G1 and G2 output from the inverters 502 and 504 have a high level voltage as the power supply voltage Vdd and a low level voltage as the ground voltage Vgnd. Therefore, the on-resistance of each switch depends on the power supply voltage Vdd. That is, when noise is superimposed on the power supply voltage Vdd, the on-resistance of the switch fluctuates, and there is a problem that the power supply rejection ratio (PSRR) of the D / A converter deteriorates.

  In particular, when the output voltage of a DC / DC converter such as a charge pump circuit or a switching regulator is used as the power supply voltage Vdd, the PSRR deteriorates significantly. When such a D / A converter is used for audio signal processing, there is a problem that sound quality is deteriorated.

  The above consideration should not be taken as a common general knowledge scope in the field of the present invention. Furthermore, the above-mentioned consideration itself is the first time the present applicant has conceived.

  The present invention has been made in view of the above-mentioned problems, and one of the exemplary purposes of an aspect thereof is to provide a ΔΣ A / D converter with improved PSRR.

  One embodiment of the present invention relates to a ΔΣ A / D converter that receives an analog input voltage and converts the analog input voltage into a digital output signal of m bits (m is a natural number). The ΔΣ A / D converter includes a D / A converter and an integrator. The D / A converter converts an m-bit digital output signal into an analog feedback voltage. The integrator adds a voltage obtained by multiplying each of the analog input voltage and the analog feedback voltage by a predetermined coefficient, and integrates the addition result. The D / A converter includes m switch circuits each provided for each bit of the digital output signal, a first inverter, and a second inverter. Each switch circuit includes a first switch group that is turned on when the corresponding bit is 1 and turned off when the corresponding bit is 0, and a second switch group that is turned on when the corresponding bit is 0 and turned off when the corresponding bit is 1. . The first inverter outputs a gate signal to each switch of the first switch group. The second inverter outputs a gate signal to each switch of the second switch group. Each switch of the first switch group and the second switch group is composed of a P-channel MOSFET (Metal Oxide Semiconductor Field Effect Transistor), and a ground voltage is applied to the lower power supply terminal of each of the first inverter and the second inverter. The

  According to this aspect, since the ground voltage is applied to the gate of the P-channel MOSFET to be turned on, the on-resistance of the switch is not easily affected by fluctuations in the power supply voltage, and PSRR can be improved. .

The back gate of the P-channel MOSFET may be fixed at a potential lower than the voltage input to the upper power supply terminals of the first inverter and the second inverter.
The on-resistance of the P-channel MOSFET is higher than the on-resistance of the N-channel MOSFET. Therefore, by fixing the back gate of the P-channel MOSFET to a voltage lower than the power supply voltage, the on-resistance can be lowered and the disadvantage of the P-channel MOSFET can be compensated.

The output voltage of the DC / DC converter may be supplied to the upper power supply terminals of the first and second inverters.
When switching noise is superimposed on the output voltage of the DC / DC converter, when a P-channel MOSFET is used as a switch, an effect that PSRR is not affected by the switching noise can be obtained.

  Another aspect of the present invention also relates to a ΔΣ A / D converter. In addition to the D / A converter and the integrator, the ΔΣ A / D converter includes a band gap reference circuit that generates a reference voltage, and a linear regulator that outputs a voltage corresponding to the reference voltage. The D / A converter includes m switch circuits each provided for each bit of the digital output signal, a first inverter, and a second inverter. Each of the m switch circuits is a first switch group that is turned on when the corresponding bit is 1 and turned off when the corresponding bit is 0, and a second switch group that is turned on when the corresponding bit is 0 and turned off when the corresponding bit is 1. including. The first inverter outputs a gate signal to each switch of the first switch group. The second inverter outputs a gate signal to each switch of the second switch group. Each switch of the first switch group and the second switch group is composed of an N-channel MOSFET (Metal Oxide Semiconductor Field Effect Transistor), and the output voltage of the linear regulator is supplied to the upper power supply terminals of the first inverter and the second inverter. Is done.

  Since the linear regulator generates a voltage according to the reference voltage from the band gap reference circuit, its output voltage has a high PSRR, and the high level voltage of the gate signal output from the first and second inverters is also high. Will have PSRR. Therefore, even if an N-channel MOSFET is used as a switch, fluctuations in on-resistance can be suppressed, deterioration of PSRR of the A / D converter can be suppressed, or PSRR can be improved.

  Yet another embodiment of the present invention is also a ΔΣ A / D converter. This ΔΣ A / D converter includes a D / A converter, an integrator, a band gap reference circuit that generates a reference voltage, and a linear regulator that outputs a voltage corresponding to the reference voltage. The D / A converter includes m switch circuits each provided for each bit of the digital output signal, a first inverter, and a second inverter. Each of the m switch circuits is a first transfer gate group that is turned on when the corresponding bit is 1 and turned off when it is 0, and a second transfer gate that is turned on when the corresponding bit is 0 and turned off when it is 1. Includes gates. The first inverter outputs a gate signal to the N-channel MOSFET of the first transfer gate group and the P-channel MOSFET of the second transfer gate group. The second inverter outputs a gate signal to the P-channel MOSFET of the first transfer gate group and the N-channel MOSFET of the second transfer gate group. The ground voltage is applied to the lower power supply terminals of the first inverter and the second inverter, and the output voltage of the linear regulator is applied to the upper power supply terminals of the first inverter and the second inverter.

  According to this aspect, fluctuations in the ON resistance of the P channel MOSFET and the ON resistance of the N channel MOSFET can be suppressed, deterioration of the PSRR of the A / D converter can be suppressed, or PSRR can be improved.

  The analog input voltage may be an audio signal. According to the A / D converter of any one of the above aspects, high-quality audio signal processing can be realized.

  Note that any combination of the above-described components, or a conversion of the expression of the present invention between methods, apparatuses, and the like is also effective as an aspect of the present invention.

  According to an aspect of the present invention, PSRR can be improved.

It is a circuit diagram which shows a part of structure of a switched capacitor type D / A converter. 1 is a block diagram illustrating a configuration of a ΔΣ A / D converter according to a first embodiment. FIG. It is a circuit diagram which shows a part of structure of a delta-sigma type A / D converter. It is a circuit diagram which shows the structure of the power supply part of the delta-sigma type A / D converter which concerns on 2nd Embodiment. It is a circuit diagram which shows the structure of a part of ΔΣ A / D converter according to a third embodiment. FIG. 3 is a circuit diagram showing a configuration of an output stage of the ΔΣ A / D converter of FIG. 2.

  The present invention will be described below based on preferred embodiments with reference to the drawings. The same or equivalent components, members, and processes shown in the drawings are denoted by the same reference numerals, and repeated descriptions are omitted as appropriate. The embodiments do not limit the invention but are exemplifications, and all features and combinations thereof described in the embodiments are not necessarily essential to the invention.

In this specification, “the state in which the member A is connected to the member B” means that the member A and the member B are electrically connected in addition to the case where the member A and the member B are physically directly connected. It includes the case of being indirectly connected through another member that does not affect the connection state.
Similarly, “the state in which the member C is provided between the member A and the member B” refers to the case where the member A and the member C or the member B and the member C are directly connected, as well as an electrical condition. It includes the case of being indirectly connected through another member that does not affect the connection state.

(First embodiment)
FIG. 2 is a block diagram showing a configuration of the ΔΣ A / D converter 2 according to the first embodiment. The ΔΣ A / D converter 2 includes a D / A converter 4, a primary integrator 6, and a quantizer 8. The ΔΣ A / D converter 2 receives the analog input voltage _VIN and converts it to an m-bit (m is a natural number) digital output signal D _OUT . The analog input voltage _VIN is, for example, an audio signal.

The quantizer 8 is provided in the output stage (final stage) of the ΔΣ A / D converter 2 and converts the analog voltage from the integrator 6 in the previous stage into an m-bit digital output signal D _OUT . The D / A converter 4 converts the m-bit digital output signal D _OUT into an analog feedback voltage V _FB . The integrator 6 adds voltages obtained by multiplying the analog input voltage _VIN and the analog feedback voltage V _FB by predetermined coefficients b ₁ and c ₁ , and integrates the addition result. The configuration of the integrator 6 is not particularly limited, but a primary integrator 6a is provided at least in the first stage.

For example, the integrator 6 has the following configuration in addition to the primary integrator 6a. The multiplier 50 multiplies the coefficient _{a 1} in the output of the primary integrator 6a. The adder 52 adds the output of the multiplier 60 and the output of the primary integrator 6a. The integrator 54 integrates the output of the adder 52 is multiplied by a coefficient _{c 2.} The integrator 56, the output of the integrator 54 integrates, multiplied by coefficients _{c 3.} The multiplier 60 multiplies the output of the integrator 56 by a coefficient −g ₁ . The multiplier 62 multiplies the coefficient _{a 3} on the output of the integrator 56. The adder 64 adds the analog input voltage V _IN and the outputs of the multipliers 50, 58 and 62, and outputs the result to the subsequent-stage quantizer 8.

The above is the overall configuration of the ΔΣ A / D converter 2.
Subsequently, specific configurations of the D / A converter 4 and the primary integrator 6a will be described. FIG. 3 is a circuit diagram showing a part of the configuration of the ΔΣ A / D converter 2. Although FIG. 3 shows a case where the analog input voltage _VIN is given in a differential format, the present invention is not limited to this and may be a single-ended format.

The D / A converter 4 receives an m-bit (m is a natural number) digital output signal _DOUT and outputs a differential analog signal corresponding to the value. Each bit of the digital output signal D _OUT [m−1: 0] is denoted as Vdata ₁ to Vdata _m .

D / A converter 4, respectively the m switching circuits ₁₀ 1 to 10 _m provided for each bit Vdata ₁ ~Vdata _m of the input data, m pieces provided for each bit Vdata ₁ ~Vdata _m Input capacitor pairs (CiH / CiL) ₁ to (CiH / CiL) _m and switches SW1 to SW4.

An upper reference voltage V _H , an intermediate reference voltage V _M , and a lower reference voltage V _L are applied to terminals P _H and P _L of the D / A converter 4, respectively.

Since the switch circuit ₁₀ 1 to 10 _m is to be constructed in the same manner, by focusing on the switch circuit 10 of the _first bit it will be explained the configuration. The switch circuit 10 includes a first input terminal IN _H , a second input terminal IN _L , a first output terminal OUTp, and a second output terminal OUTn.

The switch circuit 10 _i, when data Vdata _i is 1 (high level), the first output terminal OUTp a first input terminal IN _H connected, connecting the second output terminal OUTn and the second input terminal IN _L.

The switch circuit 10 _i, when data Vdata _i is 1 (high level), the first output terminal OUTp a first input terminal IN _H connected, connecting the second output terminal OUTn and the second input terminal IN _L. The switch circuit 10 _i Conversely, when the data Vdata _i is 0 (low level), the first output terminal OUTp and the second input terminal IN _L connected, connecting the second output terminal OUTn and the first input terminal IN _H To do.

The switch circuit 10 _i is turned on when the corresponding bit Vdata _i of the input data is 1, the first switch group M1, M4 to turn off when 0, turned on when the corresponding bit Vdata _i is 0, 1, A second switch group M2, M4 that is sometimes turned off is included.

In the present embodiment, switches M1 to M4 are configured by P-channel MOSFETs. The second inverter 14 inverts Vdata _i and supplies it as a gate signal to the second switch groups M2 and M3. The first inverter 12 inverts the output signal of the second inverter 14 and supplies it as a gate signal to the first switch group M1, M4.

  As shown in the lower right of FIG. 2, the ground voltage (0 V) is applied to the lower power supply terminal of each of the first inverter 12 and the second inverter 14. The power supply voltage Vdd is applied to the upper power supply terminal of each of the first inverter 12 and the second inverter 14. The power supply voltage Vdd is generated by the DC / DC converter 40.

The back gate of the P-channel MOSFET is fixed at a potential V _H lower than the voltage Vdd input to the upper power supply terminals of the first inverter 12 and the second inverter 14.

The first terminals of the input capacitors CiH _{1 to} CiH _m are connected in common. The second terminal of the input capacitor CiH _i is connected to the first input terminal IN _H of the switch circuit 10 _i. The first terminals of the input capacitors CiL _{1 to} CiL _m are connected in common. The second terminal of the input capacitor CiL _i is connected to the second input terminal IN _L of the switch circuit 10 _i .

  The D / A converter 4 alternately repeats the first state φ1 and the second state φ2 in synchronization with the clock signal. The on / off state of each switch in FIG. 2 corresponds to the first state φ1, and the switch that is off in FIG. 3 is on in the second state φ2.

The first switch SW1, an input capacitor _CiH 1 _{~CiH m} first terminal P1, which is common to connect the upper reference voltage _{V H} is provided between the terminals _{P H} is applied. The third switch SW3, an input capacitor _CiH 1 ～CiH first terminal P1, which is common to connect _m, is provided between the terminals _{P L} to the lower reference voltage _{V L} is applied.

The second switch SW2, the input capacitor _CiL 1 _{~CiL m} first terminal P2 which is commonly connected to an upper reference voltage _{V H} is provided between the terminals _{P H} is applied. The fourth switch SW4, the input capacitor _CiL 1 _{~CiL m} first terminal P2 which is common to connect, is provided between the terminals _{P L} to the lower reference voltage _{V L} is applied.

Power supply circuit 42 generates an upper reference voltage _{V H.} The power supply circuit 42 includes a band gap reference circuit 30, a linear regulator 46, and a capacitor C10. The band gap reference circuit 30 generates a reference voltage V _REF stabilized to about 1.2V. A capacitor C _BGR is connected to the output terminal of the band gap reference circuit 30. The reference voltage V _BGR is received and the upper reference voltage V _H corresponding to the reference voltage V _BGR is generated. Capacitor C10 is provided to stabilize the upper reference voltage V _H.

The primary integrator 6 a includes switches SW <b _> 11 _{P / N to} SW <b _> 14 _{P / N} , capacitors C <b _> 1 _{P / N} and C <b _> 2 _{P / N} , and a differential amplifier 7.

The capacitor C1 _P is provided between the non-inverting input terminal and the inverting output terminal of the differential amplifier 7. Between the noninverting input terminal of the input terminal Pi _P and the differential amplifier 7, the switch SW11 _P, the capacitor C2 _P, switch SW14 _P is sequentially provided in series. Switch SW12 _P is provided between the connection point of the switch SW11 _P and the capacitor C2 _P and the ground terminal. Switch SW13 _P has a connection point of the capacitor C2 _P and the switch SW14 _P, is provided between the ground terminal.
The same applies to the capacitors C1 _N and C2 _N and the switches SW11 _{N to} SW14 _N.

Output OUTn of the D / A converter 4 is connected points and connection of the capacitor C2 _P and the switch SW14 _P. Output terminal OUTp of the D / A converter 4 is connected points and connection of the capacitor C2 _N and the switch SW14 _N.

  The above is the specific configuration of the D / A converter 4 and the integrator 6 of the ΔΣ A / D converter 2. Next, the operation will be described. The switch groups M1 to M4 which are P-channel MOSFETs are turned on when the gate signals from the inverters 12 and 14 are at a low level, that is, the ground voltage is 0V. The ground voltage 0 V is not affected by the power supply voltage Vdd, or even if it is affected, the influence is very small. That is, the ON resistances of the switch groups M1 to M4 hardly change even if the power supply voltage Vdd changes.

Therefore, according to the D / A converter 4 of FIG. 3, the PSRR characteristics can be improved as compared with the case where N-channel MOSFETs are used for the switches M1 to M4. Specifically, when an N-channel MOSFET is used, PSRR is about 60 dB, but by using a P-channel MOSFET, it can be improved to about 80 dB. This is a very noticeable effect.
From the above, the ΔΣ A / D converter 2 can be suitably used for audio signal processing that requires particularly high PSRR.

Also, since the on-resistance of the P-channel MOSFET is larger than that of the N-channel MOSFET of the same size, it is necessary to increase the area of the P-channel MOSFET when trying to obtain the same on-resistance as when using the N-channel MOSFET. .
In general, the power supply voltage Vdd is applied to the back gate of the P-channel MOSFET. However, in the D / A converter 4 of FIG. 3, a voltage lower than the power supply voltage Vdd is applied to the back gate of the switches M1 to M4. Specifically, the upper reference voltage V _H is applied. As a result, the on-resistance of the P-channel MOSFET can be reduced, the size of the P-channel MOSFET need not be increased so much, and an increase in circuit area can be suppressed.

  As described above, the on-resistances of the transistors M1 to M4 are not affected by the power supply voltage Vdd. Therefore, the output voltage of the DC / DC converter 40 having a large fluctuation amount (ripple) can be used as the power supply voltage Vdd. Since the conversion efficiency of the DC / DC converter is superior to that of the linear regulator, the power consumption of the entire system can be reduced by using the D / A converter 4.

(Second Embodiment)
In the second embodiment, a technique for improving the PSRR of the ΔΣ A / D converter by an approach different from that of the first embodiment will be described.

  FIG. 4 is a circuit diagram showing the configuration of the power supply section of the ΔΣ A / D converter 2a according to the second embodiment. In the second embodiment, the switches M1 to M4 constituting the switch circuit 10 of the D / A converter are constituted by N-channel MOSFETs.

  The power supply unit of the ΔΣ A / D converter 2 a includes a DC / DC converter 40, a band gap reference circuit 30, a starting circuit 32, a first linear regulator 34, and a second linear regulator 36.

  The DC / DC converter 40 receives an input voltage of about 3V and converts it into a power supply voltage Vdd of about 1.8V. The input voltage may be a battery voltage, for example.

The band gap reference circuit 30 generates a reference voltage V _{BGR of} about 1.2V. The activation circuit 32 is provided to activate the band gap reference circuit 30. The band gap reference circuit 30 and the starting circuit 32 may be configured using a known technique. A capacitor C _BGR is connected to the output terminal of the band gap reference circuit 30. Note that the power supply voltage Vdd may be supplied to the power supply terminal of the error amplifier EA of the band gap reference circuit 30 or the second power supply voltage Vdd ′ generated by the first linear regulator 34 in the subsequent stage may be supplied. Good.

The first linear regulator 34 includes a voltage follower that receives the reference voltage V _BGR and generates a second power supply voltage Vdd ′ of about 1.2V. The second power supply voltage Vdd ′ is supplied to the upper power supply terminals of the first inverter 12 and the second inverter 14. The first linear regulator 34 also divides the second power supply voltage Vdd ′ to generate a common voltage Vcom.

The second linear regulator 36 receives the common voltage Vcom, and generates an upper reference voltage V _H , an intermediate reference voltage V _M , and a lower reference voltage V _L. A smoothing capacitor C10 is externally attached to a terminal of the second linear regulator 36 where the upper reference voltage _VH is generated. The upper reference voltage V _H is supplied to the upper power supply terminals of the first inverter 12 and the second inverter 14.

The above is the configuration of the ΔΣ A / D converter 2a. Since the upper reference voltage V _H is generated by the first linear regulator 34 and the second linear regulator 36 based on the reference voltage V _BGR , the upper reference voltage V _H is not affected by fluctuations in the power supply voltage Vdd and has a stable voltage level. Therefore, the on-resistances of the transistors M1 to M4, which are N-channel MOSFETs, are not easily affected by fluctuations in the power supply voltage Vdd.

  According to the ΔΣ A / D converter 2a of FIG. 4, PSRR can be improved while using N-channel MOSFETs for the switches M1 to M4.

  In the first embodiment, the second power supply voltage Vdd ′ generated by the first linear regulator 34 of FIG. 4 may be supplied to the upper power supply terminals of the first inverter 12 and the second inverter 14.

(Third embodiment)
The third embodiment can be understood as a combination of the first and second embodiments. FIG. 5 is a circuit diagram showing a partial configuration of the ΔΣ A / D converter 2b according to the third embodiment. The power supply unit of the ΔΣ A / D converter 2 is omitted because it may be configured similarly to the power supply unit of FIG.

  In the ΔΣ A / D converter 2b, the switch constituting the switch circuit 10b is configured by a transfer gate TG. The transfer gate TG includes a P-channel MOSFET and an N-channel MOSFET. The second power supply voltage Vdd 'is supplied to the upper power supply terminals of the first inverter 12 and the second inverter 14, and the ground voltage 0V is supplied to their lower power supply terminals.

  According to the third embodiment, a high PSRR can be obtained while reducing the on-resistance of the switches constituting the switch circuit 10.

FIG. 6 is a circuit diagram showing the configuration of the output stage of the ΔΣ A / D converter 2 of FIG. In FIG. 6, an adder 64, a quantizer 8, and multipliers 50, 58, and 62 are shown. The output stage of FIG. 6 shows the configuration of the i-th bit of the digital output signal _DOUT , and the same configuration is provided for each bit of the digital output signal _DOUT . In the case of the single bit ΔΣ A / D converter 2, the circuit block 9 is unnecessary.

The output stage includes a latch comparator CMP, capacitors C30 _{1 to} C30 ₈ , and first and second quantization capacitors C20 ₁ and C20 ₂ for each bit of the digital output signal D _OUT .

The capacitance values of the first and second quantization capacitors C20 ₁ and C20 ₂ are weighted for each bit of the digital output signal _DOUT . The capacitors C30 _{1 to} C30 ₈ have capacitance values corresponding to the coefficients a _{1 to} a ₃ of the multipliers 50, 58, and 62, respectively.

The first capacitor C30 _1, the third capacitor C30 _3, fifth capacitor C30 _5, seventh capacitor C30 ₇ and the first quantization capacitor C20 ₁ Each end is connected to the non-inverting input terminal of the latch comparator CMP.
The second capacitor C30 _2, the fourth capacitor C30 _4, sixth capacitor C30 _6, 8 capacitors C30 ₈ and the second quantization capacitor C20 ₂ each end is connected to the inverting input terminal of the latch comparator CMP.

The first capacitor C30 ₁ at the other end, a positive signal (P) or the lower reference voltage V _L of the analog input voltage V _IN of the differential is selectively applied via a switch. Negative signal (N) or the lower reference voltage V _L of the analog input voltage V _IN of the differential is selectively applied through a switch to the second terminal of the capacitor C30 _2.

The third capacitor C30 ₃ at the other end, a positive signal (P) or the lower reference voltage V _L of the differential output signal of the integrator 6a is selectively applied via a switch.
The other end of the fourth capacitor C30 _4, negative signal (N) or the lower reference voltage V _L of the differential output signal of the integrator 6a is selectively applied via a switch.

The other end of the fifth capacitor C30 _5, positive signals (P) or the lower reference voltage V _L of the differential output signal of the integrator 54 is selectively applied through a switch.
The other end of the sixth capacitor C30 _6, negative signal (N) or the lower reference voltage V _L of the differential output signal of the integrator 54 is selectively applied through a switch.

The other end of the seventh capacitor C30 _7, the positive signal (P) or the lower reference voltage V _L of the differential output signal of the integrator 56 is selectively applied through a switch.
The other end of the eighth capacitor C30 _8, negative signal (N) or the lower reference voltage V _L of the differential output signal of the integrator 56 is selectively applied through a switch.

The other end of the first quantization capacitor C20 _1, via a switch matrix _{SW20 to d,} the upper reference voltage _{V H,} the lower reference voltage _{V L} is selectively applied. The second end of quantized capacitor C20 _2, through the switch matrix SW20, upper reference voltage _{V H,} the lower reference voltage _{V L} is selectively applied.

  The present invention has been described based on the embodiments. This embodiment is an exemplification, and it will be understood by those skilled in the art that various modifications can be made to combinations of the respective constituent elements and processing processes, and such modifications are within the scope of the present invention. is there. Hereinafter, such modifications will be described.

The topology of the capacitor and the switch shown in FIG. 2 is an example, and the present invention can be applied to ΔΣ A / D converters of various topologies that are known or can be used in the future.
In the embodiment, the case where the D / A converter and the integrator are of the differential type has been described, but the present invention can also be applied to a single-ended type.

  Although the present invention has been described using specific terms based on the embodiments, the embodiments only illustrate the principles and applications of the present invention, and the embodiments are defined in the claims. Many variations and modifications of the arrangement are permitted without departing from the spirit of the present invention.

2 ... ΔΣ A / D converter, 4 ... D / A converter, 6 ... integrator, 6a ... primary integrator, 7 ... differential amplifier, 8 ... quantizer, 10 ... switch circuit, 12 ... first inverter , 14 ... second inverter, 30 ... band gap reference circuit, 32 ... start-up circuit, 34 ... first linear regulator, 36 ... second linear regulator, 40 ... DC / DC converter, 42 ... power supply circuit.

Claims (7)

A ΔΣ A / D converter that receives an analog input voltage and converts it into an m-bit (m is a natural number) digital output signal,
A switched capacitor type D / A converter for converting the m-bit digital output signal into an analog feedback voltage;
A switched capacitor type integrator that adds a voltage obtained by multiplying each of the analog input voltage and the analog feedback voltage by a predetermined coefficient, and integrates the addition result;
With
The D / A converter
A first switch group which is provided for each bit of the digital output signal, each turned on when the corresponding bit is 1, and turned off when the corresponding bit is 0; and turned on when the corresponding bit is 0; M switch circuits including a second switch group that is turned off when 1.
A first inverter that outputs a gate signal to each switch of the first switch group;
A second inverter that outputs a gate signal to each switch of the second switch group;
With
Each switch of the first switch group and the second switch group is composed of a P-channel MOSFET (Metal Oxide Semiconductor Field Effect Transistor),
A ΔΣ A / D converter, wherein a ground voltage is applied to a lower power supply terminal of each of the first inverter and the second inverter.   2. The ΔΣ-type A / C according to claim 1, wherein a back gate of the P-channel MOSFET is fixed to a potential lower than a voltage input to an upper power supply terminal of the first inverter and the second inverter. D converter.   3. The ΔΣ A / D converter according to claim 1, wherein an output voltage of the DC / DC converter is supplied to upper power supply terminals of the first and second inverters. A ΔΣ A / D converter that receives an analog input voltage and converts it into an m-bit (m is a natural number) digital output signal,
A switched capacitor type D / A converter for converting the m-bit digital output signal into an analog feedback voltage;
A switched capacitor type integrator that adds a voltage obtained by multiplying each of the analog input voltage and the analog feedback voltage by a predetermined coefficient, and integrates the addition result;
A bandgap reference circuit for generating a reference voltage;
A linear regulator that outputs a voltage according to the reference voltage;
With
The D / A converter
A first switch group which is provided for each bit of the digital output signal, each turned on when the corresponding bit is 1, and turned off when the corresponding bit is 0; and turned on when the corresponding bit is 0; M switch circuits including a second switch group that is turned off when 1.
A first inverter that outputs a gate signal to each switch of the first switch group;
A second inverter that outputs a gate signal to each switch of the second switch group;
With
Each switch of the first switch group and the second switch group is composed of an N-channel MOSFET (Metal Oxide Semiconductor Field Effect Transistor),
The ΔΣ A / D converter, wherein an output voltage of the linear regulator is supplied to upper power supply terminals of the first inverter and the second inverter. A ΔΣ A / D converter that receives an analog input voltage and converts it into an m-bit (m is a natural number) digital output signal,
A switched capacitor type D / A converter for converting the m-bit digital output signal into an analog feedback voltage;
A switched capacitor type integrator that adds a voltage obtained by multiplying each of the analog input voltage and the analog feedback voltage by a predetermined coefficient, and integrates the addition result;
A bandgap reference circuit for generating a reference voltage;
A linear regulator that outputs a voltage according to the reference voltage;
With
The D / A converter
A first transfer gate group is provided for each bit of the digital output signal, and is turned on when the corresponding bit is 1 and turned off when it is 0, and turned on when the corresponding bit is 0. M switch circuits including a second transfer gate group that is turned off when 1.
A first inverter that outputs a gate signal to the N-channel MOSFET of the first transfer gate group and the P-channel MOSFET of the second transfer gate group;
A second inverter that outputs a gate signal to the P-channel MOSFET of the first transfer gate group and the N-channel MOSFET of the second transfer gate group;
With
A ground voltage is applied to a lower power supply terminal of the first inverter and the second inverter,
The ΔΣ A / D converter, wherein an output voltage of the linear regulator is applied to upper power supply terminals of the first inverter and the second inverter. An output stage for generating the m-bit digital output signal;
The output stage, for each bit of the digital output signal,
A latch comparator;
A first capacitor having one end connected to the non-inverting input terminal of the latch comparator and the other end to which a positive signal of the differential analog input voltage or a lower reference voltage is applied via a switch;
A second capacitor having one end connected to the inverting input terminal of the latch comparator and the other end to which a differential negative signal of the analog input voltage or a lower reference voltage is applied via a switch;
A third capacitor having one end connected to the non-inverting input terminal of the latch comparator and the other end to which a positive signal of the differential output signal of the integrator or a lower reference voltage is applied via a switch;
A fourth capacitor having one end connected to the inverting input terminal of the latch comparator and the other end to which a negative signal of the differential output signal of the integrator or a lower reference voltage is applied via a switch;
A first quantization capacitor having one end connected to the non-inverting input terminal of the latch comparator, the other end applied with an upper reference voltage or a lower reference voltage via a switch, and a capacitance value weighted for each bit When,
A second quantization in which one end is connected to the inverting input terminal of the latch comparator, the upper reference voltage or the lower reference voltage is applied to the other end via a switch, and the capacitance value is weighted for each bit. A capacitor;
The ΔΣ A / D converter according to claim 1, comprising:   The ΔΣ A / D converter according to claim 1, wherein the analog input voltage is an audio signal.

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