JP2012133835A - Nonvolatile semiconductor memory device and method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a nonvolatile semiconductor memory device which is capable of effectively increasing a dispersion of data, and preventing unnecessary data randomization processing.SOLUTION: A nonvolatile semiconductor memory device is provided, which includes: a determination circuit which calculates an index indicating a dispersion degree of data to be written in a memory cell array, and determines whether the index is equal to or greater than a predetermined value; a randomization circuit which outputs the data to the memory cell array as it is if the determination circuit determines that the index is equal to or greater than the predetermined value, and randomizes the data to output to the memory cell array if the index is less than the predetermined value.

Description

  The present invention relates to a nonvolatile semiconductor memory device and method, and more particularly, to a nonvolatile semiconductor memory device and method having a data randomization processing function.

  In a nonvolatile semiconductor device such as a flash memory, data is programmed into and erased from a memory cell by controlling the amount of electrons in a floating gate included in the memory cell. For example, when data “1” is programmed in the memory cell, electrons are injected into the floating gate, and the apparent gate threshold value of the transistor having the floating gate is increased. When erasing data “1” in the memory cell (that is, when writing data “0”), electrons are extracted from the floating gate and the gate threshold value of the transistor is returned to the initial state.

  In general, since the above-described injection and extraction of electrons to and from the floating gate of the memory cell are performed through the gate oxide film of the transistor that constitutes the memory cell, the gate oxide film deteriorates as the number of data writing increases. It progresses and the electric characteristics of the memory cell tend to change gradually. Such a phenomenon becomes prominent when a specific data program is repeated in a specific memory cell.

  Further, a phenomenon (program disturb) in which data held in an unselected memory cell is destroyed in a data write mode is known. For example, in the case of a flash memory, when the same data is continuously programmed in a plurality of memory cells connected to the same word line, the gates of unselected memory cells connected to the word line have a long time. As a result, the data held in the non-selected memory cell may be destroyed.

  Further, in a flash memory employing a common source line method in which a source line is shared by a plurality of memory strings, for example, data “0” is programmed in all memory cells in a certain string, When data “1” is programmed in all the memory cells, the currents flowing through the respective strings are different. As a result, the potential of the source line is likely to fluctuate during verification or reading, and data in the memory cell may be erroneously detected.

  Each of the above-described phenomena becomes prominent when the same data is continuously programmed, that is, when there is a deviation of “0” and “1” in the data to be written and the variation is small. Therefore, conventionally, when data is written by so-called data randomization processing, the data is inverted according to a random number to increase the variation of “0” and “1” in the data actually written to the memory cell array.

JP 2009-163774 A

  However, according to the above-described prior art, even if the deviation of “0” and “1” in the data to be written is small and the variation is sufficiently large, the data randomization process is performed regardless of this. For this reason, not only data randomization processing may be performed wastefully, but also randomization cancellation processing for returning data to an array before randomization processing is required at the time of reading. Further, the data variation after the data randomization process is not necessarily larger than the original data variation before the data randomization process, and conversely, the data variation may be reduced.

  The present invention has been made in view of the above circumstances, and provides a nonvolatile semiconductor memory device and method capable of effectively increasing the variation in data and preventing unnecessary data randomization processing. With the goal.

In order to solve the above problems, a nonvolatile semiconductor memory device according to the present invention includes a memory cell array, and is configured to write data into the memory cell array specified by an address signal, An index representing the degree of variation in data to be written to the memory cell array is calculated, a determination circuit for determining whether the index is equal to or greater than a predetermined value, and a result of determination by the determination circuit, the index is equal to or greater than the predetermined value The data is output to the memory cell array as it is, and when the index is lower than the predetermined value, the data is randomized and output to the memory cell array.
The structure of the non-volatile semiconductor memory device provided with.

  According to the above configuration, when the index is equal to or greater than a predetermined value, the data is output as it is as data to be written into the memory cell array, so that useless data randomization processing can be prevented. In addition, when the index is less than the predetermined value, the data is randomized, so that it is possible to effectively improve data variation.

  In the nonvolatile semiconductor memory device according to the present invention, in the above configuration, when the data to be written to the memory cell array is data composed of N bits (N is an arbitrary natural number), the index is the N It is the number of “1” included in the difference number sequence obtained by calculating the exclusive OR of two adjacent bits included in the bit data, and the predetermined value is (N−1) / 2. The configuration of the nonvolatile semiconductor memory device is characterized.

  In the nonvolatile semiconductor memory device according to the present invention, in the configuration described above, the determination circuit calculates an exclusive OR of two adjacent bits included in data to be written to the memory cell array to calculate the difference number sequence. , A count circuit for counting the number of “1” included in the difference number sequence output from the exclusive OR circuit, a count value of the count circuit, and the count circuit It has a configuration of a non-volatile semiconductor memory device comprising a comparison circuit for comparing with a predetermined value.

  Furthermore, the nonvolatile semiconductor memory device according to the present invention has the configuration described above, wherein the randomizing circuit generates a random number signal based on the address signal, and the random number according to a determination result of the determination circuit. A non-volatile semiconductor memory device comprising: a gate circuit that inverts the data by a random number signal generated by a signal generation circuit or outputs the data as it is.

  Furthermore, the method according to the present invention is a method of writing data to the memory cell array specified by an address signal in a nonvolatile semiconductor memory device having a memory cell array, and the degree of variation of data to be written to the memory cell array Calculating an index representing the value, and determining whether the index is equal to or greater than a predetermined value; and as a result of the determination, if the index is equal to or greater than the predetermined value, the data is output to the memory cell array as it is; Randomizing the data and outputting the data to the memory cell array when the index is less than the predetermined value.

  According to the present invention, it is possible to prevent useless data randomization processing and to effectively increase the variation in data compared to the original data.

1 is a block diagram showing a configuration of a nonvolatile semiconductor memory device according to an embodiment of the present invention (configuration related to data writing). It is a block diagram which shows the structural example of the randomization circuit (300) with which the non-volatile semiconductor memory device by embodiment of this invention is provided. It is a block diagram which shows the structural example of the random number signal generation circuit (310) with which the randomization circuit (300) by embodiment of this invention is provided. It is a block diagram which shows the structural example of the determination circuit (400) with which the non-volatile memory device by embodiment of this invention is provided. FIG. 5 is a diagram illustrating an example of an arrangement of data stored in a memory cell array (600) included in a nonvolatile semiconductor memory device according to an embodiment of the present invention. 1 is a block diagram showing a configuration of a nonvolatile semiconductor memory device according to an embodiment of the present invention (configuration related to data reading). It is a block diagram which shows the structural example of the randomization cancellation | release circuit (700) with which the non-volatile semiconductor memory device by embodiment of this invention is provided. It is a figure for demonstrating operation | movement (data variation determination method) of the determination circuit (400) with which the non-volatile semiconductor memory device by embodiment of this invention is provided. It is a figure for demonstrating operation | movement (determination reference | standard of the dispersion | variation in data) of the determination circuit (400) with which the non-volatile semiconductor memory device by embodiment of this invention is provided.

  Hereinafter, a nonvolatile semiconductor memory device according to an embodiment of the present invention will be described in detail with reference to the drawings.

1. Configuration FIG. 1 schematically shows the overall configuration of the nonvolatile semiconductor memory device according to the present embodiment.
Note that FIG. 1 shows only the configuration related to data writing, and the configuration related to data reading and other general circuits (for example, address-related circuits, control-related circuits, etc.) are omitted. Has been.

  As shown in FIG. 1, the nonvolatile semiconductor memory device according to the present embodiment includes a data terminal 100, a temporary data storage area 200 (for example, SRAM), a randomization circuit 300, a determination circuit 400, a page as a configuration related to data writing. A buffer 500 and a memory cell array 600 are provided.

  Here, the data terminal 100 is an external terminal for receiving data D to be written to the memory cell array 100 from the outside. The temporary data storage area 200 is for temporarily storing data D input from the outside via the data terminal 100. The randomizing circuit 300 is for performing a randomizing process on the data DA output from the temporary data storage area 200.

  The determination circuit 400 is a characteristic part of the nonvolatile semiconductor memory circuit according to the present embodiment, and is for determining the variation of the data D input through the data terminal 100. The presence / absence of the randomizing process in the above-described randomizing circuit 300 is controlled according to the determination result of the determination circuit 400.

  In the present embodiment, when the determination circuit 400 determines that the variation in the data D is small, the determination circuit 400 outputs a logical value “0” as the determination signal Sbypass representing the determination result. In this case, the randomizing circuit 300 performs a randomizing process on the data DA. If the determination circuit 400 determines that the variation in the data D is large, the determination circuit 400 outputs a logical value “1” as the determination signal Sbypass. In this case, the randomizing circuit 300 does not perform the randomizing process, and the randomizing process is bypassed.

  The page buffer 500 is for temporarily storing the data DB output from the randomizing circuit 300.

  The memory cell array 600 is composed of a group of memory cells having floating gates. In general, each memory cell is arranged in a matrix so as to be located at intersections of a plurality of word lines and a plurality of bit lines. ing. A row decoder and a column decoder (not shown) select a word line and a bit line based on an external address signal, thereby specifying a memory cell to which data is to be written.

FIG. 2 shows a configuration example of the randomization circuit 300.
As shown in the figure, the randomization circuit 300 includes a random number signal generation circuit 310, an inverter 320, an AND gate circuit 330, and an exclusive OR gate circuit 340. Here, the random number signal generation circuit 310 is for generating a random number signal SP used in randomization processing from an external address signal AD when data is written.

  Further, the determination signal Sbypass is given from the determination circuit 400 of FIG. The output part of the inverter 320 is connected to one input part of the AND gate circuit 330 and the output part of the random number signal generation circuit 310 is connected to the other input part. The output part of the AND gate circuit 330 is connected to one input part of the exclusive OR gate circuit 340, and the data DA output from the temporary data storage area 200 is supplied to the other input part.

  According to the randomization circuit 300, the randomization process for the data DA is controlled according to the determination signal Sbypass. That is, when the logical value of the determination signal Sbypass is “0”, the random number signal SP output from the random number signal generation circuit 310 is given to the exclusive OR gate circuit 340 via the AND gate circuit 330, The OR gate circuit 340 performs a randomization process on the data DA based on the random number signal SP, and outputs a randomized data DB. At this time, the exclusive OR gate circuit 340 selectively inverts each bit of the data DA by the random number signal SP generated by the random number signal generation circuit 310.

  On the other hand, when the logical value of the determination signal Sbypass is “1”, the output of the AND gate circuit 330 is fixed to the logical value “0”. In this case, the exclusive OR gate circuit 340 outputs the data DA as it is as the data DB. That is, in this case, the randomization process is bypassed. In this case, the random number signal generation circuit 310 is deactivated based on the determination signal Sbypass, and the circuit operation for the randomization process is not performed.

FIG. 3 shows a configuration example of the random number signal generation circuit 310.
As shown in the figure, the random number signal generation circuit 310 includes a shift register composed of n flip-flops 311-1, 311-2, ... 311-n (n is a natural number) connected in cascade, and an exclusive OR. The gate circuit 312 is configured. Here, one input section of the exclusive OR gate circuit 312 is connected to the input section of the final flip-flop 311-n, and the other input section is connected to the output section of the flip-flop 311-n. The output part of this exclusive OR gate circuit 312 is connected to the input part of the first stage flip-flop 311-1. The flip-flop 311-1 and 311-2, the ... 311-n, as their initial values (seed value of the random number), the value _A 0 of each bit of the address signal _AD, A 1, is ... _{A n} set Is done.

  According to the random number signal generation circuit 310, each value of the n flip-flops 311-1, 311-2,... 311-n is sequentially shifted in synchronization with a predetermined clock signal (not shown), and the final stage signal is output. A signal appearing at the input and output of the flip-flop 311-n is operated by the exclusive OR gate circuit 312, and the result of the operation is returned to the flip-flop 311-1 at the first stage, thereby synchronizing with the clock signal, A random number signal SP is output from the flip-flop circuit 311-n at the final stage.

FIG. 4 shows a configuration example of the determination circuit 400.
As shown in the figure, the determination circuit 400 includes an exclusive OR circuit 410, a count circuit 420, and a comparison circuit 430. Here, the data D input from the outside is given to the input part of the exclusive OR circuit 410 through the data terminal 100 of FIG. The exclusive OR circuit 410 generates data D ′ corresponding to the difference number sequence of the data D by calculating the exclusive OR of two adjacent bits among the bits of the data D.

  The output section of the exclusive OR circuit 410 is connected to the input section of the count circuit 420, and the data D ′ is supplied from the exclusive OR gate circuit 410 to the count circuit 420. The count circuit 420 is for counting the number of bits having a logical value “1” (the weight of the difference number sequence D ′) among the bits included in the data D ′.

  An output part of the count circuit 420 is connected to an input part of the comparison circuit 430, and the count value CNT is given to the comparison circuit 430 from the count circuit 420. The comparison circuit 430 compares the count value CNT with a predetermined value and outputs the comparison result as a determination signal Sbypass. In this example, if the count value CNT is greater than or equal to a predetermined value, a logical value “1” is output as the determination signal Sbypass, and if the count value CNT falls below the predetermined value, a logical value “0” is output as the determination signal Sbypass. .

FIG. 5 shows an arrangement of data stored in the memory cell array 600.
As shown in the figure, the memory cell array 600 includes a data area 610 for storing values B ₀ , B ₁ ,... B _N of each bit of the data DB output from the randomizing circuit 300, and a determination circuit 400. a data area 620 for storing data B _R of 1 bit representing the logical value of the decision signal Sbypass is output as one set, the data is stored.

In the present embodiment, for each data DB of one N bits written in the write operation (N is an arbitrary natural number), the data B _R of 1 bit on the basis of the determination signal Sbypass output from the determination circuit 400 is set The Here, the logical value data B _R "0" represents that data DB that forms the data B _R and pairs were randomized processed, data B _R of a logical value "1", the data B _R and pairs This means that the data DB that constitutes is not randomized. The data B _R, when reading data DB written in the memory cell array 600, is used to determine whether to require randomizing release processing.

Next, a configuration related to data reading will be described with reference to FIGS.
FIG. 6 schematically shows the overall configuration of the nonvolatile semiconductor memory device according to the present embodiment related to data reading. In the figure, elements common to the components shown in FIG. 1 described above are denoted by the same reference numerals and description thereof is omitted.

  In the present embodiment, for convenience of explanation, FIG. 1 shows a configuration related to data writing, and FIG. 6 shows a configuration related to data reading. The nonvolatile semiconductor memory device according to the present embodiment is shown in FIG. 1 and the configuration of FIG. 6 are integrally provided.

As shown in FIG. 6, the nonvolatile semiconductor memory device according to the present embodiment includes a randomization cancellation circuit 700 between the page buffer 500 and the temporary data storage area 200 as a configuration related to data reading, and this randomization cancellation. The above-described data DB and data _BR are input to the circuit 700 from the memory cell array 600 via the page buffer 500. Randomized release circuit 700, when reading the data DB from the memory cell array 600, to determine the necessity of randomizing release process based on the data B _R constituting the data DB and set, the logical value of the data B _R is "0" In other words, when the data DB is randomized at the time of writing, the randomization cancellation processing is performed on the data DB.

FIG. 7 shows a configuration example of the randomization cancellation circuit 700.
As shown in the figure, the randomization cancellation circuit 700 includes a random number signal generation circuit 710, an inverter 720, an AND gate circuit 730, and an exclusive OR gate circuit 740. Here, the random number signal generation circuit 710 is for generating a random number signal SR to be used in randomization cancellation processing from an external address signal AD when reading data, and basically the random number signal generation circuit 710 The algorithm for generating the random number signal SR is the same as that of the random number signal generating circuit 310. Therefore, the random number SR used for randomization cancellation is the same as the random number SP generated at the time of data writing.

Further, the input of inverter 720, the data _{B R} is given from the memory cell array 600 via the page buffer 500 of FIG. The output part of the inverter 720 is connected to one input part of the AND gate circuit 730, and the output part of the random number signal generation circuit 710 is connected to the other input part. One input portion of the exclusive OR gate circuit 740 is connected to the output portion of the AND gate circuit 730, and the other input portion is supplied with data DB from the memory cell array 600 via the page buffer 500 of FIG. It is done.

According to the randomized release circuit 700, randomizing release processing for the data DB according to the data B _R is controlled. That is, when the logical value of the data B _R is "0", the random number signal SR output from the random number signal generating circuit 710 is supplied to the exclusive OR gate circuit 740 through the AND gate circuit 730, the exclusive The logical OR gate circuit 740 performs a randomization cancellation process on the data DB based on the random number signal SR, and outputs the randomized data DA.

At this time, the logical value of the inverted bit at the time of data writing is returned to the original logical value before the randomizing process. In contrast, when the logical value of the data B _R is "1", the output of the AND gate circuit 730 is fixed to the logic value "0". In this case, the exclusive OR gate circuit 740 outputs the data DB from the memory cell array 600 as it is to the temporary data storage area 200 as data DA. That is, the randomization cancellation process is bypassed.

2. Operation Next, with reference to FIGS. 8 and 9 in addition to FIGS. 1 to 7 described above, focusing on the randomization process, the data write operation (data write method) of the nonvolatile semiconductor memory device according to the present embodiment will be described. A data read operation (data read method) will be described.

<Data writing operation>
As illustrated in FIG. 8, a 10-bit (N = 10) bit string “0001101111” is assumed as data D of N bits (N is an arbitrary natural number) to be written. The data D is input to the temporary data storage area 200 via the data terminal 100, and is supplied from the temporary data storage area 200 to the randomization circuit 300 as data DA.

  Data D is also given to the determination circuit 400. The determination circuit 400 determines whether the distribution variation (hereinafter simply referred to as “data variation”) between the “0” bit and the “1” bit in the bit string of the data D to be written is large or small. That is, the exclusive OR circuit 410 shown in FIG. 4 constituting the determination circuit 400 calculates the exclusive OR of two adjacent bits in the bit string of the data D, thereby obtaining the data composed of the difference sequence of the data D. D ′ is generated.

  The count circuit 420 counts the number of bits of the logical value “1” included in the data D ′ and outputs a count value CNT. The comparison circuit 430 compares the count value CNT with a predetermined value and outputs a logical value corresponding to the magnitude relationship as the determination signal Sbypass. At this time, when the count value CNT is equal to or larger than the predetermined value, the logical value of the determination signal Sbypass is set to “1” indicating that the variation of the data D is large, and conversely, when the count value CNT is lower than the predetermined value. The logic value of the determination signal Sbypass is “0” indicating that the variation of the data D is small.

Here, the principle of determination of data variation will be described.
The determination of the variation of the data D is based on the number of boundaries between “0” bits and “1” bits in the bit string of the data D. In the example of FIG. 8, the above boundary is indicated by a broken line. In the bit string “0001101111” of the data D illustrated in FIG. 8, between the third bit and the fourth bit counted from the left side, between the fifth bit and the sixth bit, and the sixth bit. The above boundary exists between the 7th bit and the 7th bit. In this example, the number of boundaries is “3”.

  In each section delimited by the boundary, one bit of “0” or “1” is continuous, and bits having the same logical value exist in one section. Accordingly, the larger the number of the above-mentioned boundaries in the data D of a certain size, the shorter the section in which the same logical value bits continue, and the deviation in the distribution of the “0” bits and the “1” bits becomes smaller. The variation of data becomes large. Conversely, the smaller the number of the above-mentioned boundaries in the data D of a certain size, the longer the section in which bits of the same logical value continue, and the distribution of the distribution of “0” bits and “1” bits becomes more uneven. Large and data variation is small. Therefore, data variation can be evaluated from the number of the boundaries. For these reasons, the number of boundaries described above can be used as an index representing the degree of data variation.

  In the example shown in FIG. 8, the boundary is “1” in the bit string “001011000” of the data D ′ obtained as the difference number sequence when the bit string “0001101111” of the data D to be written is viewed as a number sequence. It corresponds to. This data D ′ is generated by the exclusive OR circuit 410 of FIG. That is, the exclusive OR circuit 410 generates the bit string “001011000” of the data D ′ by calculating the exclusive OR of two adjacent bits in the bit string “0001101111” of the data D in FIG. .

  Here, the bit “1” in the bit string of the data D ′ is obtained when one of two adjacent bits in the data D has a logical value “0” and the other has a logical value “1”. Obtained by calculating the exclusive OR of the logical values of the two bits (the absolute value of the difference). In the example of FIG. 8, the exclusive logical OR of the two bit logical values adjacent to each other across the boundary is calculated. Obtained when computing the absolute value of the difference. Therefore, in FIG. 8, the bit “1” in the bit string of the data D ′ corresponds to the boundary in the bit string of the data D, and the number of the boundary is determined by the count circuit 420 in FIG. It is obtained by counting the number of “1” bits.

  As described above, the count value CNT representing the number of boundaries is compared with a predetermined value by the comparison circuit 430, and the comparison circuit 430 outputs a determination signal Sbypass having a logical value corresponding to the magnitude relationship. Here, it is preferable to adopt (N−1) / 2 as the predetermined value. N represents the number of bits of data D to be written.

Here, with reference to FIG. 9, the technical significance of adopting (N−1) / 2 as the predetermined value will be described.
In general, except for special cases such as data initialized to a specific value, the arrangement of logical values in the bit string of data to be written takes various patterns, and the weight of the difference number sequence (logical value) of the data. The number of “1”) follows a binomial distribution.

That is, when N-bit data D is considered, the number of terms in the difference number sequence (the number of bits of data D ′) is “N−1”, and the weight of the difference number sequence (“1” included in data D ′) "Number of bits" follows a binomial distribution with an average value of (N-1) / 2, as shown in FIG. Accordingly, the distribution of the number of boundaries corresponding to the weights of the difference number sequence follows a binomial distribution with an average value of (N-1) / 2. The same applies to the data after randomization processing.
In FIG. 9A, the area surrounded by the curve representing the binomial distribution and the horizontal axis is 1, that is, the total probability for each weight is 100%.

  Now, considering an arbitrary weight x of the above-mentioned difference number sequence, in FIG. 9A, the probability that the weight is greater than or equal to x is represented by the area S of the hatched area in FIG. 9A. Here, x is a variable representing an arbitrary value from 0 to N-1. In the present invention, the randomization process is performed when the variation of the data D is small (when the weight is less than the predetermined value), and when the data D is large (when the weight is greater than or equal to the predetermined value), Write. From this, the probability Pi that the weight of the difference sequence of the data DB that is finally written in the memory cell array is greater than or equal to x is the probability P1 when the weight of the difference sequence of the original data D is greater than or equal to x. When the weight of the difference sequence of the original data D is less than x, the randomization process is performed, so that the sum (P1 + P2) with the probability P2 when the weight of the difference sequence of the data is greater than or equal to x.

  Since the probability P1 is represented by S and the probability P2 is represented by (1-S) S, the probability Pi is represented by the following equation (1), and as shown in FIG. 0) and is expressed by a quadratic function curve having coordinates (1, 1) as a vertex.

Pi = P1 + P2 = S + (1-S) S = −S ² + 2S = − (S−1) ² +1 (1)

  On the other hand, the probability Pj when the weight of the difference sequence obtained by simply performing the randomization process on the data D by the conventional technique is greater than or equal to x is expressed by the following equation (2), and FIG. ), It is represented by a straight line passing through coordinates (0, 0) and having an inclination of 1.

  P2 = S (2)

  Here, from the equations (1) and (2), the difference ΔP between the probability Pi according to the present invention and the probability Pj according to the prior art is expressed by the following equation (3).

ΔP = Pi−Pj
= (-S ² + 2S) -S = -S ² + S =-(S-1 / 2) ² +1/4 (3)

  From equation (3), it can be seen that ΔP is maximized when S = ½. This corresponds to the case where the variable x is (N−1) / 2 in FIG. Therefore, in determining whether the variation of the data D before writing is large or small, (N−1) / 2 is set as the predetermined value in the comparison circuit 430, and it is obtained as an index representing the degree of variation of the data D. By comparing the count value CNT representing the number of the boundaries with (N−1) / 2, it is possible to determine to most effectively improve the variation of the data D. However, as described above, the predetermined value is not limited to (N−1) / 2, and even when the value is set to a value other than this, data variation can be improved.

  As a result of the determination as described above, the determination signal Sbypass output from the determination circuit 400 is applied to the randomization circuit 300 of FIGS.

Here, the description returns to FIG. 1 and FIG.
If the logical value of the determination signal Sbypass input from the determination circuit 400 is “1”, the randomization circuit 300 supplies the data DA input from the temporary data storage area 200 as it is to the page buffer 500 as the data DB. In this case, the randomization process is not performed and bypassed. If the logical value of the determination signal Sbypass is “0”, randomization processing is performed on the data DA input from the temporary data storage area 200 using the random number signal SP output from the random number signal generation circuit 310. Then, the randomized data DB is given to the page buffer.

The data DB output from the randomizing circuit 300 is written into the memory cell in the memory cell array 600 specified by the address signal via the page buffer 500.
The data write operation has been described above.

<Data read operation>
Next, a data read operation will be described with reference to FIGS.
As described above, when reading the data DB written in the memory cell array 600, the same address signal AD as that at the time of writing is designated from the outside, and the data DB is transferred from the memory cell array 600 via the page buffer 500 based on this address signal AD. To the randomization cancellation circuit 700. In this case, the data constituting the data DB and the set B _R also read together from the memory cell array 600.

Randomized release circuit 700, if the logical value of the data B _R is "1", giving the data DB input from the page buffer 500 as it is to the temporary data storage area 200 as the data DA. In this case, the randomization cancellation processing is not performed and bypassed. Further, if the logical value of the data B _R is "0", for the data DB input from the page buffer 500, performing the randomizing cancellation processing using the random number signal SR output from the random number signal generating circuit 710, The randomized data DA is given to the temporary data storage area 200.

The temporary data storage area 200 outputs the data DA input from the randomization cancellation circuit 700 as data D to the outside through the data terminal 100.
The data read operation has been described above.

  As described above, in the present embodiment, the presence / absence of the randomization process is controlled according to the variation of the data D to be written. Thereby, it is possible to effectively improve the variation of the data DB actually written in the memory cell array 600.

In the following, the extent to which data variation can be improved will be described.
Here, the above-mentioned predetermined value when determining the data variation is set to the average value (= (N−1) / 2), and “0” and “1” in the bit string of the data DB actually written in the memory cell. The probability of the occurrence of an event A in which the number of boundaries between “and“ is greater than the average value is calculated.

Event A occurs when:
(I) The number of boundaries between “0” and “1” in the bit string of the data D to be written is equal to or greater than the above average value.
(Ii) The number of boundaries between “0” and “1” in the bit string of the data D to be written is less than the average value, and “0” and “1” in the bit string in the data DB after randomization processing When the number of boundaries between is greater than the above average.

In the case of (i), the probability is 1/2.
In the case of (ii), the probability of the data D to be written is less than the average value (= 1/2), and “0” and “1” in the bit string of the data DB after randomization processing. And the probability that the number of the above-mentioned boundaries between the two is greater than or equal to the average value (= 1/2). Since these are independent events, they are simply multiplied to give 1/2 × 1/2 = 1/4.
Since the above (i) and (ii) are contradictory events, the probability that the event A will occur is the sum of the probability of (i) and the probability of (ii), and 1/2 + 1/4 = 3/4.

  On the other hand, according to the conventional randomization method, the probability that the number of boundaries between “0” and “1” in the data actually written in the memory cell is equal to or greater than the average value is irrelevant to the data before the randomization processing. 1/2.

  Therefore, according to the present embodiment, data whose variation is equal to or greater than the average value can be written in the memory cell array with a probability 1.5 times that of the conventional randomization method. Therefore, it is possible to effectively improve the variation in data, and it is possible to obtain a higher effect than problems in the conventional randomization method for problems such as program disturb.

Further, according to the present embodiment, when the variation of the original data is sufficient (when the boundary value is equal to or greater than the average value), randomization processing is not performed, thereby preventing unnecessary circuit operation. It is possible to reduce power consumption.
Furthermore, according to the present embodiment, as a result of effectively improving the variation in data, the number of times of writing to each memory cell is made uniform as the number of times of writing data increases. Therefore, stress is not concentrated on a specific memory cell, and reliability can be improved.

  Although the embodiments of the present invention have been described above, the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the scope of the present invention.

  DESCRIPTION OF SYMBOLS 100 ... Data terminal, 200 ... Temporary data storage area, 300 ... Randomize circuit, 400 ... Judgment circuit, 410 ... Exclusive OR circuit, 420 ... Count circuit, 430 ... Comparison circuit, 500 ... Page buffer, 600 ... Memory cell array, 700: Randomize cancel circuit.

Claims (5)

A nonvolatile semiconductor memory device comprising a memory cell array and configured to write data to the memory cell array specified by an address signal,
A determination circuit that calculates an index representing a degree of variation of data to be written to the memory cell array and determines whether the index is equal to or greater than a predetermined value;
As a result of determination by the determination circuit, when the index is equal to or greater than the predetermined value, the data is output to the memory cell array as it is, and when the index is lower than the predetermined value, the data is randomized and stored in the memory cell array. A randomizing circuit to output,
A non-volatile semiconductor memory device.   When the data to be written into the memory cell array is data consisting of N bits (N is an arbitrary natural number), the index is an exclusive OR of two adjacent bits included in the N-bit data. The nonvolatile semiconductor memory device according to claim 1, wherein the number is “1” included in the difference number sequence obtained by the calculation, and the predetermined value is (N−1) / 2. The determination circuit includes:
An exclusive OR circuit for calculating the exclusive OR of two adjacent bits included in the data to be written in the memory cell array and outputting the difference number sequence;
A count circuit for counting the number of “1” included in the difference number sequence output from the exclusive OR circuit;
A comparison circuit for comparing the count value of the count circuit with the predetermined value;
The nonvolatile semiconductor memory device according to claim 2, further comprising: The randomization circuit is:
A random number signal generating circuit for generating a random number signal based on the address signal;
In accordance with a determination result of the determination circuit, a gate circuit that inverts the data by a random number signal generated by the random number signal generation circuit or outputs the data as it is,
4. The nonvolatile semiconductor memory device according to claim 1, further comprising: In a nonvolatile semiconductor memory device including a memory cell array, a method of writing data to the memory cell array specified by an address signal,
Calculating an index indicating the degree of variation of data to be written to the memory cell array, and determining whether the index is a predetermined value or more;
As a result of the determination, when the index is equal to or greater than the predetermined value, the data is output to the memory cell array as it is, and when the index is lower than the predetermined value, the data is randomized and output to the memory cell array. When,
Including methods.

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