JP2012133513A - Storage device, control method and control program for storage device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent delay in transmission of data responding to data transmitted from a host device.SOLUTION: In response to request data transmitted from a host device, a storage device executes processing requested by the request data. The storage device comprises: a storage; a processor for executing first processing including storage control and second processing for, in response to the request data transmitted from the host device, transmitting response data responding to the request data to the host device; and a substitute processing unit for executing the second processing of predetermined request data so as to substitute for the processor.

Description

  The present invention relates to a storage apparatus, a storage apparatus control method, and a control program.

  The drive device is not used by itself, but is used connected to the host. Examples of the drive device include an optical disk recording / reproducing device and a hard disk device. Examples of the host include a PC (Personal Computer), a recorder, and a player.

  Transmission of data read from the disk from the drive device to the host or reception of data to be written on the disk from the host in the drive device is performed via the I / F. One of such I / F standards is SATA (Serial Advanced Technology Attachment). In this standard, data transfer is controlled by three layers. FIG. 5 shows three layers defined in the SATA standard. As the three layers, a transport layer, a link layer, and a physical layer are defined.

The transport layer performs generation of FIS (Frame Information Structure) and order (protocol) control.
The link layer performs transmission path arbitration, flow control, and conversion of FIS and control codes into bit strings (8 / 10b conversion).
The physical layer serially converts and transfers the bit string. That is, actual communication is performed in the physical layer.

The operation of such a drive device will be described.
The operation of the drive device is controlled by the type of FIS managed in the transport layer. Whether the FIS is being transmitted or received is managed by a control code called a primitive in the link layer.

  Specifically, an example of FIS transmission / reception between the drive device and the host will be described. Here, a case where the FIS is transmitted from the host to the drive device will be described.

  Before the FIS transfer is performed, SYNC Primitive is transmitted and received between the host and the drive device. SYNC Primitive is a primitive that indicates that the bus is idle. When transmitting the FIS, the host transmits X_RDY Primitive, which is a FIS transmission request, to the drive device. When the X_RDY Primitive is received from the host, the drive device transmits R_RDY Primitive that notifies FIS reception permission to the host. As a result, the drive apparatus is in a reception-permitted state, and the host starts transmission of the FIS to the drive apparatus.

  When the drive apparatus normally receives the FIS from the host, the drive apparatus transmits R_IP Primitive to the host. As a result, the FIS transmission ends, and therefore the host transmits a WTRM Primitive that notifies the FIS transmission end to the drive device. When the drive apparatus receives WTRM Primitive from the host, the drive apparatus transmits R_OK Primitive to notify the reception completion to the host. Thereafter, transmission and reception of SYNC Primitive is again started between the host and the drive device. Then, the host and the drive device wait for transmission / reception of the next FIS.

  As described above, the case where the FIS is transmitted from the host to the drive device has been described. However, when the transmission direction of the FIS changes, each of the primitives described above is transmitted in the reverse direction.

  Normally, the drive device receives requested data and information indicating the contents of the Task File Register (hereinafter referred to as “Task File Register information”) in response to a request from the host, such as reset and ATA / ATAPI command issuance. Send to. Such a request from the host is made based on a specification defined in the SATA standard. In this specification, the host is defined as waiting for a response from the drive device and issuing a new request to the drive device.

  However, some hosts issue the next request without waiting for a response from the drive device when they violate the SATA standard or use Port Multiplier. That is, some hosts issue the next request without waiting for sufficient time. If the drive device cannot respond to such a host within the time until the host issues the next request, the drive device receives the next request from the host at an unexpected timing. As a result, there is a problem in that the data handled by the host and the drive device is flawed and the host or the drive device cannot operate normally.

  A case where such a problem occurs will be specifically described with reference to FIG. FIG. 6A is a diagram illustrating a flow of data transmission / reception at a normal time, and FIG. 6B is a diagram illustrating a flow of data transmission / reception when a problem occurs. Although not described in detail, the FIS in the description of FIG. 6 is transmitted by the transmission procedure described above.

First, normal data transmission / reception in FIG. 6A will be described.
When the COMRESET is transmitted from the host, the drive apparatus transmits a Register FIS including Task File Register information. COMRESET from the host corresponds to the above-described reset from the host. Next, when the host issues an ATA / ATAPI command to the drive device, the host transmits an FIS indicating the ATA / ATAPI command to the drive device. When the drive apparatus receives the FIS from the host, the drive apparatus transmits an FIS responding to the ATA / ATAPI command indicated by the FIS to the host.

Next, data transmission / reception when the problem of FIG. 6B occurs will be described.
When the COMRESET is transmitted from the host, the drive device tries to transmit the FIS including the Task File Register information. However, as described above, some hosts issue the next request without waiting for a response from the drive device. In the case of such a host, if the transmission of the FIS from the drive device is delayed, the next FIS may be transmitted from the host before the FIS is transmitted from the drive device. After that, when the FIS is transmitted from the drive device, the FIS responding to the reset from the host is transmitted instead of the FIS responding to the ATA / ATAPI command indicated by the FIS transmitted next by the host. As a result, the host or drive device cannot operate normally.

  Here, as a factor that delays transmission of FIS from the drive device, there is an operation delay of software that controls transmission and reception of FIS in the drive device. Generally, a drive device has a CPU (Central Processing Unit). The CPU executes a plurality of software such as software for controlling transmission / reception of FIS to / from the host and software for controlling the disk. Therefore, there is a problem in that the FIS transmission may be delayed when the CPU continues to be occupied by software other than the software that controls the transmission / reception of the FIS to / from the host.

  That is, there is a problem that in a storage apparatus having a storage such as a hard disk or an optical disk, transmission of data in response to data transmitted from the host apparatus may be delayed.

  A storage device according to a first aspect of the present invention is a storage device that executes processing requested by request data in accordance with request data transmitted from a host device, and controls the storage and the storage. A processor that executes a first process including: a second process for transmitting response data to the host apparatus in response to the request data transmitted from the host apparatus; and the host apparatus Among the request data transmitted from the above, a predetermined processing data is provided with an alternative processing unit that executes the second processing instead of the processor.

  A storage apparatus control method according to a second aspect of the present invention is a storage apparatus control method for executing processing requested by request data in response to request data transmitted from a host apparatus. Performing a first process including storage control and a second process of transmitting response data to the host device in response to the request data transmitted from the host device, and In the execution of the process, when transmission of predetermined request data from the host device is detected, and the predetermined request data is detected, an alternative processing unit substitutes the processor for the predetermined request data. The process is executed.

  The control program according to the third aspect of the present invention includes a first process including storage control in a storage apparatus that executes a process requested by the request data in accordance with the request data transmitted from the host apparatus. A second processor provided together with a first processor for executing a second process of transmitting response data responding to the request data to the host device in response to the request data transmitted from the host device; A control program to be executed, the process for detecting transmission of predetermined request data from the host device, and replacing the first processor for the predetermined request data when the predetermined request data is detected And causing the second processor to execute a process for executing the second process.

  According to each aspect of the present invention described above, it is possible to execute processing for transmitting response data to respond to request data to the host device without being affected by processing executed by the processor for predetermined request data. it can.

  According to each aspect of the present invention described above, it is possible to provide a storage apparatus, a storage apparatus control method, and a control program that can prevent a delay in data transmission in response to data transmitted from a host apparatus.

1 is a configuration diagram of a storage system according to an embodiment of the present invention. FIG. It is a flowchart which shows the process in the starting sequence of the drive device concerning embodiment of this invention. It is a flowchart which shows the process of the OOB sequence determination circuit concerning embodiment of this invention. It is a flowchart which shows the process of the starting sequencer management circuit concerning embodiment of this invention. It is a figure for demonstrating each layer prescribed | regulated in the SATA specification concerning embodiment of this invention. It is a figure for demonstrating the subject concerning embodiment of this invention.

  The configuration of the storage system 1 according to the embodiment of the present invention will be described with reference to FIG. FIG. 1 is a configuration diagram of a storage system 1 according to an embodiment of the present invention.

  The storage system 1 has a drive device 2 and a host 3. The drive device 2 includes an LSI (Large Scale Integration) 10, a memory 11, a driver 12, and a mechanical unit 13. The LSI 10 includes a CPU 20 and a DSP (Digital Signal Processor) 21. The DSP 21 includes an OOB sequence determination circuit 30, a primitive / FIS transmission / reception control circuit 31, and an activation sequencer management circuit 32. The drive device 2 and the host 3 are connected to each other by an SATA standard interface.

  The drive device 2 is a storage device having a storage. The storage is, for example, an optical disc, a hard disk, or a memory. That is, the drive device 2 is, for example, an optical disk drive, an HDD (Hard Disk Drive), or an SSD (Solid State Drive). In the present embodiment, the case where the drive device 2 is an optical disk drive is illustrated.

  The drive device 2 executes the process requested by the request data in accordance with the request data transmitted from the host 3. The request data is, for example, an OOB signal, Align, FIS, or the like. The OOB signal is, for example, COMRESET, COMMIT, COMWAKE or the like. The FIS requesting arbitrary processing is, for example, an FIS indicating an ATA / ATAPI command. For example, in response to a request from the host 3, the drive device 2 executes processing stipulated by the SATA standard such as resetting the drive device 2 and reading / writing from / to the storage.

The host 3 is a device that transmits request data for requesting arbitrary processing to the drive device 2 and acquires an execution result of the drive device 2.
The LSI 10 has a task file register (not shown) used for control in the SATA standard, a processing function for a signal acquired from a disk, and a memory control function.
The memory 11 stores a program executed by the CPU 20, data calculated by the CPU 20, and data acquired from the disk.

The driver 12 controls the mechanical unit 13 based on the control information output from the CPU 20. The driver 12 controls the mechanical unit 13 by outputting control information indicating the control contents of the mechanical unit 13 to the mechanical unit 13. The driver 12 controls the position of the lens with respect to the optical disc (not shown), for example.
The mechanical unit 13 reads / writes data from / to the optical disc based on the control information output from the CPU 20 and the driver 12.

  The CPU 20 executes processing for transmitting / receiving data to / from the host 3 and processing for controlling the optical disc. The CPU 20 executes these processes by executing a program for causing the CPU 20 to execute a process for transmitting / receiving data to / from the host 3 and a program for causing the CPU 20 to execute a process for controlling the optical disk. For example, when receiving an FIS indicating an ATA / ATAPI command from the host 3, the CPU 20 generates an FIS responding to the ATA / ATAPI command indicated by the FIS and transmits the FIS to the host 3. Specifically, the CPU 20 outputs control information for requesting transmission of the generated FIS to the primitive / FIS transmission / reception control circuit 31 together with the generated FIS, so that the host / host control unit 31 sends the control information to the host. FIS is sent to 3.

  Further, the CPU 20 controls the mechanical unit 13. The CPU 20 outputs control information indicating the control contents of the mechanical unit 13 to the mechanical unit 13. The CPU 20 adjusts, for example, the intensity of light that the mechanical unit 13 irradiates the optical disc and the tilt of the lens.

The DSP 21 executes processing in the startup sequence of the drive device 2 and data transmission / reception processing. The DSP 21 corresponds to an alternative processing unit.
The OOB (Out Of Band) sequence determination circuit 30 monitors the progress of the OOB sequence. The OOB sequence determination circuit 30 generates an OOB signal and Align according to the progress of the OOB sequence, and transmits the OOB signal and Align to the host 3. The OOB sequence determination circuit 30 outputs the generated OOB signal or Align, together with the generated OOB signal or Align, to the primitive / FIS transmission / reception control circuit 31 by outputting the OOB signal / primitive information requesting transmission of the generated OOB signal or Align. The OOB signal or Align is transmitted from the transmission / reception control circuit 31 to the host 3.

  The primitive / FIS transmission / reception control circuit 31 transmits / receives data such as an OOB signal, primitive, and FIS to the host 3. The primitive / FIS transmission / reception control circuit 31 transmits the FIS to the host 3 based on the control information output from the CPU 20. The primitive / FIS transmission / reception control circuit 31 transmits an OOB signal or Align to the host 3 based on the OOB signal / primitive information output from the OOB sequence determination circuit 30. The primitive / FIS transmission / reception control circuit 31 transmits the FIS to the host 3 based on the FIS information output from the activation sequencer management circuit 32.

  The activation sequencer management circuit 32 monitors the progress of the activation sequence of the drive device 2. The activation sequencer management circuit 32 executes transition of the operation mode of the drive device 2, generation of FIS, and transmission of the generated FIS to the host 3 according to the progress degree of the OOB sequence. The activation sequencer management circuit 32 outputs the generated FIS and FIS information requesting transmission of the generated FIS to the primitive / FIS transmission / reception control circuit 31, so that the host 3 Send FIS to

  Subsequently, processing of the storage system 1 according to the embodiment of the present invention will be described with reference to FIGS. FIG. 2 is a flowchart showing processing in the startup sequence of the drive device 2 according to the embodiment of the present invention. FIG. 3 is a flowchart showing a process of the OOB (Out Of Band) sequence determination circuit 30 according to the embodiment of the present invention. FIG. 4 is a flowchart showing processing of the activation sequencer management circuit 32 according to the embodiment of the present invention.

  First, when the drive device 2 and the host 3 are connected to each other and activated, an OOB sequence is started in order to establish SATA communication (S1). The OOB sequence determination circuit 30 determines what value the OOB sequence management number has (S101). Here, a case where the initial value of the OOB sequence management number is “0” will be described. The OOB sequence management number is stored in, for example, a storage device included in the OOB sequence determination circuit 30. The storage device is, for example, a memory or a register. The OOB sequence management number is initialized to an initial value by the OOB sequence determination circuit 30 when the drive device 2 is activated, for example.

  When the OOB sequence management number is “0”, the OOB sequence determination circuit 30 determines whether or not the OOB sequence is started. Specifically, it is determined whether or not a COMRESET is transmitted from the host 3 (S102).

  When the COMRESET has not been transmitted from the host 3 (S102: NO), the OOB sequence determination circuit 30 continues to determine whether the COMRESET has been transmitted from the host (S102).

  When COMRESET is transmitted from the host 3 (S102: YES), the OOB sequence determination circuit 30 transmits COMINIT to the host 3 (S103). Specifically, the OOB sequence determination circuit 30 outputs an OOB signal / primitive information requesting transmission of COMINIT to the primitive / FIS transmission / reception control circuit 31. The primitive / FIS transmission / reception control circuit 31 transmits COMINIT to the host 3 in accordance with the OOB signal / primitive information from the OOB sequence determination circuit 30. The OOB sequence determination circuit 30 updates the OOB sequence management number to “1” (S104). The OOB sequence determination circuit 30 outputs the updated OOB sequence management number to the activation sequencer management circuit 32.

  On the other hand, the activation sequencer management circuit 32 determines what value the activation sequence management number is (S201). Here, a case where the initial value of the activation sequence management number is “0” will be described. The activation sequence management number is stored in, for example, a storage device included in the activation sequence management number. The activation sequence management number is initialized to an initial value by the activation sequencer management circuit 32, for example, when the drive device 2 is activated or when communication with the host is interrupted after communication with the host is established.

  When the activation sequence management number is “0”, the activation sequencer management circuit 32 determines whether or not the OOB sequence is started (S202). Specifically, it is determined whether or not the OOB sequence management number is “1”.

When the OOB sequence management number is not “1” (S202: NO), the activation sequencer management circuit 32 continues to determine whether or not the OOB sequence has been started (S202).
When the OOB sequence management number becomes “1” (S202: YES), the activation sequencer management circuit 32 updates the activation sequence management number to “1” (S203). Here, when the OOB sequence management number updated to “1” is output from the OOB sequence determination circuit 30, the activation sequencer management circuit 32 determines that the OOB sequence management number is “1”.

  After execution of step S104, the OOB sequence determination circuit 30 determines the OOB sequence management number again (S101). When the OOB sequence management number is “1”, the OOB sequence determination circuit 30 determines whether COMWAKE is transmitted from the host 3 (S105).

  When COMWAKE has not been transmitted from the host 3 (S105: NO), the OOB sequence determination circuit 30 continues to determine whether COMWAKE has been transmitted from the host 3 (S105).

  When COMWAKE is transmitted from the host 3 (S105: YES), the OOB sequence determination circuit 30 transmits COMWAKE to the host 3 (S106). Specifically, the OOB sequence determination circuit 30 outputs an OOB signal / primitive information requesting transmission of COMWAKE to the primitive / FIS transmission / reception control circuit 31. The primitive / FIS transmission / reception control circuit 31 transmits COMWAKE to the host 3 in accordance with the OOB signal / primitive information from the OOB sequence determination circuit 30.

  Further, the OOB sequence determination circuit 30 transmits Align to the host 3 (S107). Specifically, the OOB sequence determination circuit 30 outputs an OOB signal / primitive information requesting transmission of Align to the primitive / FIS transmission / reception control circuit 31. The primitive / FIS transmission / reception control circuit 31 transmits Align to the host 3 in accordance with the OOB signal / primitive information from the OOB sequence determination circuit 30. The OOB sequence determination circuit 30 updates the OOB sequence management number to “2” (S108). The OOB sequence determination circuit 30 outputs the updated OOB sequence management number to the activation sequencer management circuit 32.

  The OOB sequence determination circuit 30 again determines the OOB sequence management number (S101). When the OOB sequence management number is “2”, the OOB sequence determination circuit 30 determines whether or not Align is transmitted from the host 3 (S109).

  When the Align is not transmitted from the host 3 (S109: NO), the OOB sequence determination circuit 30 continues to determine whether the Align is transmitted from the host 3 (S109).

  When the Align is transmitted from the host 3 (S109: YES), the OOB sequence is completed. In that case, the OOB sequence determination circuit 30 starts transmission of the SYNC Primitive to the host 3 (S2, S110). Specifically, the OOB sequence determination circuit 30 outputs an OOB signal and primitive information requesting the start of transmission of SYNC Primitive to the primitive and FIS transmission / reception control circuit 31. The primitive / FIS transmission / reception control circuit 31 starts transmission of the SYNC Primitive to the host 3 according to the OOB signal / primitive information from the OOB sequence determination circuit 30. The OOB sequence determination circuit 30 updates the OOB sequence management number to “3” (S111). The OOB sequence determination circuit 30 outputs the updated OOB sequence management number to the activation sequencer management circuit 32.

  On the other hand, the activation sequencer management circuit 32 determines the activation sequence management number again after executing step S203 (S201). When the activation sequence management number is “1”, the activation sequencer management circuit 32 determines whether or not the OOB sequence is completed (S204). Specifically, the activation sequencer management circuit 32 determines whether or not the OOB sequence management number is “3”.

If the OOB sequence management number is not “3”, the activation sequencer management circuit 32 continues to determine whether or not the OOB sequence has ended (S204).
When the OOB sequence management number becomes “3”, the activation sequencer management circuit 32 sets the operation mode of the drive device 2 to a mode in which X_RDY Primitive is ignored (S3, S205). Specifically, even if the X_RDY Primitive is transmitted from the host 3 in order to reject all requests from the host 3 until the necessary response from the drive apparatus 2 is completed after the OOB sequence is completed, the drive apparatus 2 Transition to a mode in which R_RDY Primitive is not transmitted. Here, when the OOB sequence management number updated to “3” is output from the OOB sequence determination circuit 30, the activation sequencer management circuit 32 determines that the OOB sequence management number is “3”.

  Here, the activation sequencer management circuit 32 transmits an FIS including Task File Register information (hereinafter also referred to as “Register FIS”) to the host 3 (S4, S206). Specifically, the activation sequencer management circuit 32 outputs FIS information requesting transmission of the Register FIS to the primitive / FIS transmission / reception control circuit 31. The primitive / FIS transmission / reception control circuit 31 transmits a Register FIS to the host 3 in accordance with the FIS information from the OOB sequence determination circuit 30. The activation sequencer management circuit 32 updates the activation sequence management number to “2” (S207).

  The activation sequencer management circuit 32 again determines the activation sequence management number (S201). When the activation sequence management number is “2”, the activation sequencer management circuit 32 determines whether or not the transmission of the Register FIS has been completed normally (S5, S208). Specifically, the activation sequencer management circuit 32 determines whether or not the primitive / FIS transmission / reception control circuit 31 has received R_OK Primitive transmitted from the host 3 when reception of the Register FIS is completed.

  If R_OK Primitive has not been received (S208: NO), the activation sequencer management circuit 32 continues to determine whether or not the transmission of the Register FIS has been completed normally (S208).

  When R_OK Primitive is received (S208: YES), the activation sequencer management circuit 32 sets the operation mode of the drive device 2 to a mode that permits a response of X_RDY Primitive (S6, S209). Specifically, in order to permit a request from the host 3, when the X_RDY Primitive is transmitted from the host 3, the mode shifts to a mode in which the R_RDY Primitive is transmitted from the drive device 2.

  The activation sequencer management circuit 32 updates both the OOB sequence management number and the activation sequence management number to “0” (S210, S211). For example, the activation sequencer management circuit 32 outputs initialization request information requesting initialization of the OOB sequence management number to the OOB sequence determination circuit 30, and the OOB sequence determination circuit 30 initializes the OOB sequence management number. Execute according to request information.

  In this way, the next SATA communication establishment is prepared. The case where the process is executed again from step S1 and communication is established is, for example, when the drive device 2 and the host 3 are reconnected, or when the host 3 detects an illegal operation of the drive device 2 and performs COMRESET. For example, the drive device 2 may be reset. For example, when there is no response from the drive device 2 for a predetermined time, the host 3 resets the drive device 2.

  Then, activation sequencer management circuit 32 outputs to CPU 20 end notification information notifying that the SATA communication establishment process and the transmission of Task File Register information have ended. The CPU 20 starts executing processing for transmitting / receiving data to / from the host 3 in accordance with the end notification information output from the startup sequencer management circuit 32. Further, when the activation sequence of the drive device 2 is executed again after the notification of the end notification information, the CPU 20 transmits instruction information for instructing execution of the processing in the above-described activation sequence to the DSP 21. The DSP 21 executes the above-described activation sequence according to the instruction information output from the CPU 20.

  As described above, in the present embodiment, when the end of the OOB sequence is notified from the physical layer to the link layer, control is performed to transmit Task File Register information to the host 3 in the link layer. Therefore, the initial recognition response can be stably executed with respect to the host 3 regardless of the specifications of the software in the drive device 2.

  As described above, in the present embodiment, the process of transmitting the response data in response to the request data to the host 3 in accordance with the request data transmitted from the host 3 is performed for the predetermined request data. It has a DSP 21 that executes instead. According to this, it is possible to execute the process of transmitting response data to the host 3 in response to the request data without being affected by the process executed by the processor 20 for the predetermined request data. Therefore, the request data that the host 3 does not wait for a response from the drive device 2 for a sufficient time is set as predetermined request data, thereby preventing a delay in transmission of response data in response to the request data transmitted from the host 3. can do.

  In the present embodiment, when request data transmitted next to predetermined request data is received from the host 3, if response data responding to the predetermined request data is not transmitted, it is transmitted next. The reception of request data is suppressed. According to this, it is possible to prevent the transmission of the next request data from the host 3 from being completed before transmitting the response data in response to the previously transmitted request data. Therefore, wrinkles can be prevented from occurring in data handled by the host 3 and the drive device 2.

  In the present embodiment, management information indicating the progress degree of the startup sequence is updated in response to reception of request data in the startup sequence from the host 3. If request data corresponding to the degree of progress indicated by the management information is not transmitted from the host 3, the management information is not updated and response data is not transmitted. According to this, even if the host 3 does not transmit the request data in a normal order due to a failure or failure, it is possible to prevent malfunction in the drive device 2. At this time, by not transmitting response data, it is possible to attempt recovery by causing the host 3 that has detected a timeout to reset again and executing the startup sequence again.

  Note that the present invention is not limited to the above-described embodiment, and can be changed as appropriate without departing from the spirit of the present invention.

  In the present embodiment, an explanation has been given of an example in which, when an Align indicating the end of an OOB sequence from the host 3 is detected, an FIS is transmitted instead of the CPU 20 for an FIS responding to the Align, The predetermined request data to be replaced is not limited to Align. For the FIS that responds to the FIS indicating any ATA / ATAPI command, the FIS may be transmitted instead of the CPU 20. For example, when FIS indicating the ATA / ATAPI command is continuously transmitted from the host 3, the host 3 does not wait for a sufficient time before transmitting the FIS in response to the previous FIS. When the FIS is transmitted, the data handled by the host and the drive device can be prevented from being wrinkled.

  In this embodiment, the progress of the OOB sequence and the startup sequence is managed by the OOB sequence management number and the startup sequence management number. However, the present invention is not limited to this as long as the information indicates the progress. For example, management may be performed using information such as character strings and bit patterns other than numbers.

  In the present embodiment, the case where the CPU 20 is replaced and the process of transmitting data in response to the data transmitted from the host 3 is realized by a circuit is exemplified, but means for replacing the CPU 20 is not limited thereto. For example, a processor such as a DSP or a CPU may be realized by executing a program that executes processing in the OOB sequence determination circuit 30 and the startup sequencer management circuit 32. In this case, the OOB sequence management number and the activation sequence management number may be stored in the memory 11.

  The program can be stored using various types of non-transitory computer readable media and supplied to the storage device. Non-transitory computer readable media include various types of tangible storage media. Examples of non-transitory computer-readable media include magnetic recording media (for example, flexible disks, magnetic tapes, hard disk drives), magneto-optical recording media (for example, magneto-optical disks), CD-ROMs (Read Only Memory), CD-Rs, CD-R / W, semiconductor memory (for example, mask ROM, PROM (Programmable ROM), EPROM (Erasable PROM), flash ROM, RAM (Random Access Memory)) are included. In addition, the program may be supplied to the storage device by various types of temporary computer readable media. Examples of transitory computer readable media include electrical signals, optical signals, and electromagnetic waves. The temporary computer readable medium can supply the program to the storage device via a wired communication path such as an electric wire and an optical fiber, or a wireless communication path.

  Further, the processor executes the program that realizes the function of the above-described embodiment, so that not only the function of the above-described embodiment is realized, but also the OS ( The case where the functions of the above-described embodiment are realized in cooperation with the Operating System) or application software is also included in the embodiment of the present invention. Furthermore, when all or part of the processing of this program is performed by a function expansion board inserted into the storage device or a function expansion unit connected to the storage device, the functions of the above-described embodiment are realized. It is included in the embodiment of the present invention.

1 Storage system 2 Drive device 3 Host 10 LSI
11 Memory 12 Driver 13 Mechanical unit 20 CPU
21 DSP
30 OOB sequence determination circuit 31 Primitive / FIS transmission / reception control circuit 32 Start sequencer management circuit

Claims (10)

In accordance with request data transmitted from a host device, a storage device that executes processing requested by the request data,
Storage,
A processor that executes a first process including control of the storage and a second process of transmitting response data in response to the request data to the host apparatus in response to the request data transmitted from the host apparatus; ,
Of the request data transmitted from the host device, for predetermined request data, an alternative processing unit that executes the second processing instead of the processor;
A storage device with   When the storage apparatus receives the next request data transmitted next to the predetermined request data from the host apparatus and does not transmit response data in response to the predetermined request data, the storage apparatus The storage apparatus according to claim 1, further comprising a management unit that suppresses reception of data. The storage device sends and receives data to and from the host device according to the SATA (Serial Advanced Technology Attachment) standard,
The request data is data that requires a FIS response to the host device,
The storage apparatus according to claim 1, wherein the response data is an FIS (Frame Information Structure) responding to the request data. The storage device sends and receives data to and from the host device according to the SATA standard,
The predetermined request data is an Align defined by the SATA standard,
The storage apparatus according to claim 1, wherein the response data is a FIS that responds to the Align. The storage device sends and receives data to and from the host device according to the SATA standard,
The predetermined request data is an Align defined by the SATA standard,
The response data is a FIS responding to the Align,
The storage apparatus according to claim 2, wherein the next request data is an FIS indicating an ATA / ATAPI command. The storage device
A storage unit for storing management information indicating a degree of progress of the startup sequence of the storage device;
The management unit updates management information stored in the storage unit in response to reception of request data in the activation sequence from the host device,
The storage apparatus according to claim 4 or 5, wherein the substitution processing unit transmits the response data when the management information stored in the storage unit indicates that the Alignn has been received. The storage device
A storage unit for storing management information indicating a degree of progress of the startup sequence of the storage device;
The management unit updates management information stored in the storage unit in response to reception of request data in the activation sequence from the host device,
When the data transmission / reception unit indicates completion of reception of the Align indicated by the management information stored in the storage unit, the data transmission / reception unit starts suppression of reception of the next request data, and the management information indicates completion of transmission of the response data. The storage apparatus according to claim 5, wherein the storage apparatus cancels suppression of reception of the next request data.   The storage device according to any one of claims 1 to 7, wherein the storage is a hard disk, an optical disk, or a memory. In accordance with request data transmitted from a host device, a storage device control method for executing processing requested by the request data,
A processor executes a first process including storage control and a second process of transmitting response data in response to the request data to the host apparatus in response to the request data transmitted from the host apparatus. ,
In the execution of the process,
Detecting transmission of predetermined request data from the host device;
A method for controlling a storage apparatus, wherein, when the predetermined request data is detected, an alternative processing unit executes the second processing for the predetermined request data by replacing the processor. In response to the request data transmitted from the host device, the storage device that executes the processing requested by the request data is provided with a first process including storage control, and according to the request data transmitted from the host device. A control program to be executed by a second processor provided together with a first processor for executing response processing for responding to the request data and transmitting the response data to the host device;
Processing for detecting transmission of predetermined request data from the host device;
A process of executing the second process instead of the first processor for the predetermined request data when the predetermined request data is detected;
A control program for causing the second processor to execute

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