JP2012133280A - Manufacturing method of board pattern, and exposure device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a manufacturing method of board pattern and an exposure device that improve the accuracy of a board pattern at a joining part in step and repeat exposure and improve the uniformity of the board patterns on a wafer substrate.SOLUTION: A method for manufacturing a board pattern 81 having a great number of dot patterns 101 cyclically arranged at a predetermined pitch in a plurality of directions by means of repeated exposures of a wafer substrate 41 using a mask pattern 61 on a reticle 21, comprises a multiple exposure step in which an exposure area A (and/or B) on the wafer substrate that has been already exposed with the mask pattern 61 is duplicatedly exposed with the mask pattern 61. In the multiple exposure step, the mask pattern 61 is shifted by an integral multiple of the pitch of the dot patterns, with respect to the exposure area A on the wafer substrate 41, while two or more exposures including already-finished exposure are conducted with the amount of light reduced according to the number of duplications of exposure.

Description

  The present invention relates to a substrate pattern manufacturing method capable of accurately and uniformly forming a substrate pattern having periodicity, and an exposure apparatus for carrying out this method.

  In recent years, devices having various periodic microstructures have been manufactured using semiconductor manufacturing techniques. For example, on a sapphire substrate used for a light emitting diode (LED), a diffraction grating-like substrate pattern (PSS: Patterned Sapphire) having periodicity for returning light emitted in all directions by an active layer formed on the upper surface to the upper side. Substrate) is provided.

  The PSS has a configuration in which, for example, a substantially cylindrical protrusion having a height of about 2 μm and a diameter of about 2 μm is periodically formed at intervals of about 3 μm on a sapphire substrate using a photolithography technique. As for the arrangement of each protrusion, a vertex of a polygon, for example, three adjacent protrusions are respectively arranged at the vertices of an equilateral triangle. In addition, each of the above dimensions is required to have a precision within a range where each protrusion can function as a diffraction grating as a whole. In order to satisfy this accuracy requirement, a PSS may be formed using a projection type exposure apparatus (stepper) for semiconductor manufacturing.

  A general stepper for manufacturing a semiconductor has a depth of focus (DOF) of about 2 μm when its numerical aperture (NA: Numerical Aperture) is a relatively high value such as 0.5. It was a shallow thing. On the other hand, the sapphire substrate for forming the PSS has warpage in the Z direction (perpendicular to the stage surface) on the stage, and step and repeat of the stepper in consideration of this warpage. The exposure area for one shot in the exposure had to be determined. For example, in the case of a sapphire substrate having a diameter of 50 mm (2 inch wafer substrate), warpage of about 20 μm occurs in the Z direction on the stage. In order to cope with this warp with a DOF of about 2 μm, for example, the exposure area of one shot is narrowed down to a square having a side of about 7 mm.

  On the other hand, an exposure method is known in which a substrate on a stage is scanned (scanned) in order to form a substrate pattern having periodicity. In general, an exposure apparatus used for this scanning exposure has a configuration in which a reticle on which a mask pattern having periodicity is drawn and an aperture opening in a rectangular shape are arranged between a substrate arranged on a stage and a light source of the exposure apparatus. It has become. In scanning exposure using such an exposure apparatus, for example, the substrate on the stage is scanned (scanned) in the X direction at a constant speed, and exposure light that has passed through the rectangular aperture of the aperture is irradiated onto the substrate. Further, for example, an exposure method is known in which every time scanning in the X direction is completed, the X direction scanning in the direction opposite to the upper stage is repeated while shifting the substrate step by step in the Y direction (see Patent Document 1). ).

JP 2010-14811 A

<Problems related to substrate pattern accuracy and uniformity>
However, when the above-described conventional step-and-repeat exposure is applied as it is and a substrate pattern having periodicity such as PSS is formed, due to the positioning error of the substrate stage, the connecting portion of the substrate pattern (wafer) There is a problem that a formation defect occurs in the vicinity of a portion where the exposure areas on the substrate are adjacent to each other (see FIG. 12A).

  That is, in step-and-repeat exposure, a connection portion is generated between the substrate patterns exposed in the preceding and following shots, and due to the positioning error of the substrate stage, the connection portion between the substrate patterns is, for example, about 0.1. In some cases, a connecting error of about 0.2 μm may occur. For this reason, if the conventional step-and-repeat exposure is applied as it is, the dimensional accuracy such as the pitch of the substrate pattern in the joint portion is extremely lowered, and a high-precision PSS that can fully perform the function of the diffraction grating can be obtained. It could not be formed efficiently.

  In addition, when the conventional step-and-repeat exposure is applied as it is and a substrate pattern having periodicity such as PSS is formed, the formation failure occurs near the joint portion of the substrate pattern due to the reticle pattern structure of the reticle. There was a problem that would occur.

  For example, when a PSS composed of cylindrical protrusions having periodicity is formed by conventional step-and-repeat exposure, a reticle that draws a mask pattern composed of a circular dot pattern having the same periodicity is used. The mask pattern is demarcated by a light-shielding region surrounding the light-transmitting region, and the dot pattern located on the outermost periphery of the mask pattern is a light-shielding region. Since there are no adjacent dot patterns in the peripheral portion of the mask pattern, the optical interference effect between the dot patterns is reduced, and the resolution of the dot pattern is lowered. In particular, since the interval from the dot pattern located on the outermost periphery to the light shielding region is usually set to about 1/2 of the pitch between dots, it is relatively smaller than other dot patterns inside this. Resolution will deteriorate. Due to such a decrease in resolution, there has been a problem that the diameter dimension of the cylindrical protrusion of the PSS formed by the dot pattern in the peripheral portion of the mask pattern becomes small.

  Further, there is a method in which the boundary of the light shielding area defining the mask pattern is offset by an amount corresponding to the positioning error of the stage so that the connecting portion between the substrate patterns exposed in the previous and subsequent shots is not a non-exposed area. However, if this method is applied to the formation of PSS as it is, the exposure areas of the front and rear shots overlap at the joint portion, and the joint portion is double-exposed. For this reason, when the object of exposure is a positive resist, there arises a problem that the diameter dimension of the columnar protrusion formed near the joint portion becomes small. As a result, the cylindrical protrusions constituting the PSS become non-uniform as a whole, which causes a problem of quality problems such as crystal defects.

  The present invention has been made in view of the above problems, and can improve or reduce molding defects near the joint portion of the substrate pattern due to positioning errors and mask pattern structures in step-and-repeat exposure, An object of the present invention is to provide a substrate pattern manufacturing method and an exposure apparatus capable of accurately and uniformly forming a substrate pattern having periodicity such as PSS.

<Problems related to throughput and productivity>
On the other hand, in the above-described conventional stepper for manufacturing a semiconductor, the exposure area of one shot in step-and-repeat exposure is generally a square area having a side of about 22 mm. However, as described above, when such a semiconductor manufacturing stepper is applied to the formation of a substrate pattern having periodicity such as PSS, the wafer substrate must be warped at a shallow depth of focus. In other words, the exposure area of one shot must be narrowed down to about 7 mm per side. For this reason, the number of shots is increased by about three times in one direction as compared with normal semiconductor manufacturing, resulting in a problem that throughput is lowered and productivity is deteriorated.

  Actually, not only the wafer substrate but also the wafer substrate holding surface of the substrate stage may be warped in the Z direction. In some cases, the mask pattern of the reticle has an in-plane drawing error. In addition, if all the various in-plane errors during exposure are taken into consideration, the exposure area of the stepper must be further reduced, and the deterioration of productivity due to a decrease in throughput becomes more remarkable.

  In addition, when a wafer substrate is exposed with a stepper for semiconductor manufacturing, there is a problem that throughput decreases in proportion to the diameter of the wafer substrate. For example, when a 2 inch diameter wafer substrate is subjected to step-and-repeat exposure with a typical stepper whose exposure area of one shot is a square having a side of 7 mm, the throughput is about 50 sheets / hour. However, when a wafer substrate having a diameter of 4 inches is subjected to step-and-repeat exposure with the same stepper, the throughput is about a dozen sheets / hour. As described above, when the wafer substrate has a large diameter, the throughput is greatly reduced. The wafer substrate tends to have a larger diameter year by year, and may increase in size from 4 inches to 6 inches in the future, and accordingly, the throughput tends to decrease significantly.

  In addition to these, when forming a PSS composed of cylindrical projections having periodicity, each dimensional accuracy and shape accuracy as a diffraction grating for improving light condensing properties must be satisfied. In addition, fine control processing in photolithography processing such as etching is required.

  The present invention has been made in view of the above problems, and can improve the productivity by expanding the exposure area in the step-and-repeat exposure, and reduce the variable elements of the photolithography process to ensure accuracy. An object of the present invention is to provide a substrate pattern manufacturing method and an exposure apparatus capable of easily and accurately forming a substrate pattern having periodicity by simplifying the control process for this purpose.

  In order to achieve the above object, according to one aspect of the substrate pattern manufacturing method of the present invention, a wafer substrate is repeatedly exposed with a reticle mask pattern, and a large number of components have periodicity in a plurality of directions at a predetermined pitch. A method of manufacturing a substrate pattern arranged in a plurality of steps, comprising: a multiple exposure step in which an exposure region on the wafer substrate that has already been exposed with the mask pattern is exposed by overlapping the mask pattern; Then, the mask pattern is shifted by an integral multiple of the pitch between the constituent elements of the substrate pattern with respect to the exposure area on the wafer substrate, and at least two exposures including the already-exposed exposure are performed. The amount of light is reduced in accordance with a plurality of amounts.

  According to the above aspect, the multiple exposure is performed by overlapping the high resolution portion of the same mask pattern in the exposure region of the exposure region on the wafer substrate that has already been exposed with the low resolution portion of the mask pattern. be able to. Thereby, the accuracy and uniformity of the substrate pattern finally formed on the wafer substrate can be improved through the subsequent development process and the like.

  Preferably, in the multiple exposure step, exposure is performed by overlapping a portion inside the boundary of the mask pattern near the boundary of the exposure region on the wafer substrate.

  According to the above aspect, the inner portion of the same mask pattern having high resolution is overlapped with the region exposed in the peripheral portion having low resolution of the mask pattern among the exposed regions on the wafer substrate that have already been exposed. Multiple exposure can be performed. As a result, it is possible to accurately and uniformly form a substrate pattern in the vicinity of the joint portion where the exposure regions on the wafer substrate are adjacent to each other, and it is possible to prevent a defective formation of the substrate pattern in the vicinity of the joint portion. Therefore, according to the above aspect, it is possible to improve or reduce the phenomenon in which the diameter dimension of the cylindrical projection of the PSS formed by the dot pattern in the peripheral portion of the mask pattern is reduced.

  In carrying out one aspect of the method described above, preferably, the mask pattern has a plurality of dot patterns arranged with periodicity in a plurality of directions at a predetermined pitch, or the mask pattern, One having a plurality of parallel line segment patterns extending in one direction of the periodicity may be used.

  When using a mask pattern having a plurality of dot patterns, for example, the substrate stage is moved stepwise relative to the mask pattern, and then a plurality of dot patterns are collectively exposed on the wafer substrate at a stop position. Implement the method. Such step-and-repeat exposure is repeated to form a large number of dot patterns arranged with a periodicity in a plurality of directions at a predetermined pitch on the entire surface of the wafer substrate. When a mask pattern having a plurality of line segment patterns is used, for example, the present method is performed by a scanning exposure method in which the mask stage is exposed by scanning the substrate stage in the line segment pattern extending direction. . The mode of the present method using such a mask pattern having a plurality of line segment patterns will be described in detail below.

  Preferably, a plurality of types of the mask patterns respectively corresponding to the plurality of periodic directions are prepared, and each of the plurality of types of the mask patterns includes a plurality of parallel lines extending in any one direction of the periodicity. The multiple exposure step includes a plurality of exposure steps of exposing the wafer substrate with each of a plurality of types of the mask patterns, and the exposure step includes either the wafer substrate or the mask pattern. By exposing one of them while scanning in the extending direction of the line segment pattern, a plurality of parallel linear patterns extending in any one direction of the periodicity are projected onto the wafer substrate, and the plurality of times. The linear patterns projected on the wafer substrate through the exposure step may be crossed with each other.

  In the above aspect, for example, the entire wafer substrate is subjected to scanning exposure by scanning the substrate stage in the extending direction of the line segment pattern with respect to the line segment pattern extending in one direction of periodicity. By performing the same scanning exposure for all the line segment patterns extending in the other direction of the periodicity, a large number of linear patterns extending in each direction of the periodicity are projected on the entire wafer substrate. If the photosensitive agent on the wafer substrate is a positive resist, the intersection of the linear patterns that have never been exposed by the above scanning exposure becomes a wafer substrate as a large number of dot patterns (cylindrical protrusions) having periodicity. Will remain on top.

  According to such an aspect, by performing scanning exposure of the line segment pattern on the wafer substrate, the exposure area of one scanning exposure can be greatly expanded, and the number of exposures for exposing the entire surface of the wafer substrate. Thus, it is possible to efficiently form a substrate pattern having periodicity. Thereby, productivity of patterned substrates, such as a diffraction grating, can be improved.

  In addition, the linear pattern projected by scanning exposure has higher optical resolution than the dot pattern projected by batch exposure, and the resolution of the dot pattern (cylindrical protrusion) that is finally formed on the wafer substrate is improved. It becomes possible to improve. Thereby, the precision of patterned substrates, such as a diffraction grating, can be improved.

  Further, by adopting the line segment pattern as the mask pattern, it is possible to reduce the variation factors of the photolithography process regarding the extending direction of the line segment pattern. As a result, it is possible to reduce control processing for ensuring accuracy, and it is possible to form a substrate pattern having periodicity with high accuracy while simplifying the control processing. As a result, a patterned substrate such as a diffraction grating can be manufactured easily and with high accuracy.

  In addition, when scanning exposure of a wafer substrate with a plurality of parallel line segment patterns, the resolution of the outer line segment pattern is lower than that of the inner line segment pattern, so it is formed on the wafer substrate. A phenomenon occurs in which the width dimension of the outer linear pattern is reduced. This phenomenon is caused by overlapping the inner part with high resolution of the same mask pattern in the exposed area on the wafer substrate that has already been scanned and exposed to the outer part with low resolution of the mask pattern. By performing multiple exposure, it is possible to improve or reduce.

  Preferably, when the adjacent areas on the wafer substrate are exposed with the mask pattern, the transparent area of the mask pattern is defined by a predetermined dimension based on a positioning error value larger than 0 that may occur between the exposed areas. The boundary of the light shielding area to be retreated is good.

  According to the above aspect, for example, even when a positioning error greater than 0 occurs between adjacent exposure regions on the wafer substrate (= the connecting portion of the substrate pattern) due to the positioning error of the substrate stage, An unexposed blank pattern is not formed at the joint portion of the substrate pattern within the predetermined dimension range. Further, for example, when a positioning error smaller than 0 occurs between adjacent exposure areas on the wafer substrate due to a positioning error of the substrate stage, the vicinity of the joint portion of the substrate pattern is double-exposed. By the multiple exposure process, the formation defect of the substrate pattern is improved or reduced. Therefore, in the above-described method, when the above-described aspect is adopted, the formation defect of the substrate pattern in the vicinity of the joint portion is improved or reduced even if the positioning error of the substrate stage is larger or smaller than 0. .

  In order to achieve the above object, one aspect of the exposure apparatus of the present invention is an exposure apparatus for carrying out the above-described substrate pattern manufacturing method of the present invention, wherein exposure light for exposing the wafer substrate is provided. Exposing at least the wafer substrate, a light source to emit, a movable substrate stage on which the wafer substrate is placed, a reticle having one or more mask patterns disposed between the light source and the substrate stage, and And a control unit that performs a control process for performing the multiple exposure process by controlling the amount of the exposure light and the movement of the substrate stage.

  Further, the patterned substrate of the present invention is a substrate pattern in which a large number of convex or concave patterns are arranged with a periodicity in a plurality of directions at a predetermined pitch by the substrate pattern manufacturing method of the present invention described above. It is characterized by the formation. Furthermore, a light emitting device or the like manufactured according to the present invention is characterized by including the patterned substrate of the present invention.

  If a patterned substrate is manufactured by applying the above-described method, molding defects near the joint portion of the substrate pattern are improved or reduced in the exposure process. As a result, it is possible to provide a high-quality patterned substrate having a large number of high-precision and uniform convex or concave patterns, a light-emitting element having such a patterned substrate, and the like.

  According to the substrate pattern manufacturing method and the exposure apparatus of the present invention, it is possible to improve or reduce molding defects near the joint portion of the substrate pattern due to the positioning error and the mask pattern structure in the step-and-repeat exposure. As a result, a substrate pattern having periodicity such as PSS can be formed with high accuracy and uniformity. For example, a high-quality patterned substrate having high-precision and uniform columnar protrusions, and such a pattern. A product such as a light-emitting element including a chemical substrate can be provided.

  In addition, according to the substrate pattern manufacturing method and exposure apparatus of the present invention, it is possible to expand the exposure area in one step and repeat exposure to improve productivity, and to reduce the variability of photolithography processing. Therefore, it is possible to simplify the control process for ensuring accuracy, and to easily and accurately form a substrate pattern having periodicity such as PSS.

It is the schematic which shows the exposure apparatus for enforcing the manufacturing method of the substrate pattern which concerns on 1st Embodiment of this invention. The substrate pattern formed by the method of this embodiment is shown. FIG. 2A is a plan view showing a substrate pattern formed by exposure of a plurality of adjacent shots including the peripheral boundary line of each shot. FIG. 2B is a partially enlarged view of FIG. FIG. 4A shows the vicinity of the peripheral boundary line when the substrate stage positioning error is 0. From the top, the plan view of the vicinity of the peripheral boundary line, a partially enlarged view of this plan view, It is a conceptual diagram of a state where regions are adjacent with a positioning error of 0. FIG. 2B shows the vicinity of the peripheral boundary line when the positioning error of the substrate stage is larger than 0. From the top, a plan view of the vicinity of the peripheral boundary line, a partially enlarged view of this plan view, It is a conceptual diagram of the state where the areas of each shot are separated by positioning errors. FIG. 4A shows the vicinity of the peripheral boundary line when the positioning error of the substrate stage is smaller than 0. From the top, a plan view of the vicinity of the peripheral boundary line, a partially enlarged view of this plan view, and each shot It is a conceptual diagram of the state where these areas overlapped due to positioning errors. FIG. 4B shows a phenomenon in which the size of the outermost dot pattern is reduced when the exposure is actually performed in the state shown in FIG. FIG. 3 is a plan view of FIG. 1, a partially enlarged view of the plan view, and a conceptual diagram in a state where regions of respective shots are overlapped due to positioning errors. It is the elements on larger scale which show the mask pattern of the reticle used for the method of this embodiment. An example of the method of this embodiment is shown. FIG. 4A is a plan view in which shots A and B in the first exposure process overlap with shot C in the second exposure process in order from the top, a partially enlarged view of this plan view, and each shot A It is a conceptual diagram of the state with which -C overlapped. FIG. 5B is a conceptual diagram showing an example in which the arrangement of the shot C in the second exposure process is changed. It is the schematic which shows the exposure apparatus for enforcing the manufacturing method of the substrate pattern which concerns on 2nd Embodiment of this invention. 3 shows a method for manufacturing a substrate pattern according to a second embodiment of the present invention. FIG. 6A is an explanatory diagram showing three sets of mask patterns drawn on a reticle and the scanning direction of scanning exposure. FIG. 2B is an explanatory view showing a substrate pattern formed by this method. FIG. 4A is a plan view of each mask pattern. FIG. 4B is a plan view of a substrate pattern formed when scanning exposure is performed using the mask pattern. FIG. 6C is an explanatory diagram showing a phenomenon that the width dimension of the outermost substrate pattern is reduced when scanning exposure is performed using the mask pattern. It is the elements on larger scale which show the line segment mask pattern of the said reticle. 2 shows a multiple exposure method for making a substrate pattern uniform. FIG. 4A is a plan view of a substrate pattern formed by the first set of scanning exposure. FIG. 3C is a plan view of a substrate pattern formed by the second set of scanning exposure. FIG. 2B is a partially enlarged view showing the positional relationship between the substrate pattern formed by the first set of scanning exposure and the substrate pattern formed by the second set of scanning exposure. FIG. 4A is a microscope observation image showing a comparative example of a dot pattern formed by conventional step-and-repeat exposure. FIG. 2B is a microscope observation image showing an example of a dot pattern formed by the substrate pattern manufacturing method of the present invention.

<First Embodiment>
First, a substrate pattern manufacturing method and an exposure apparatus according to a first embodiment of the present invention will be described with reference to FIGS.

<< Overview of exposure apparatus >>
In FIG. 1, the exposure apparatus 1 according to the first embodiment of the present invention mainly includes a light source 11, a reticle 21, an optical system 31, a substrate stage 51, and a control unit 91. A wafer substrate 41 such as a sapphire substrate is placed on the substrate stage 51.

  The light source 11 emits exposure light for exposing the resist film on the wafer substrate 41. On the reticle 21, a dot-shaped mask pattern 61 having periodicity in a plurality of directions is drawn. The optical system 31 includes a lens that projects the mask pattern 61 on the reticle 21 onto the substrate. The wafer substrate 41 is exposed by a photolithography technique to form a substrate pattern 81 having periodicity. The substrate stage 51 has a substantially horizontal plane on which the wafer substrate 41 is placed, and the wafer substrate 41 placed on this plane is moved with high accuracy in the X, Y, and Z directions in the drawing orthogonal to each other. It is the composition which makes it. The controller 91 controls the amount of exposure light emitted from the light source 11 and controls the operation of the substrate stage 51 in the X, Y, and Z directions so that the exposure light emitted from the light source 11 is on the wafer substrate 41. A predetermined position is irradiated. In the present embodiment, a positive resist is formed on the wafer substrate 41 so that the exposed portion is not developed. However, the method of the present invention also applies to the negative resist where the exposed portion remains in the development. It is possible to apply.

<< mask pattern on reticle >>
The mask pattern 61 on the reticle 21 shown in FIG. 1 is a shot of the substrate pattern 81 projected on the wafer substrate 41 shown in FIG. 2A (regions 81a to 81e surrounded by a substantially hexagonal peripheral boundary line). 1). Therefore, the configuration of the mask pattern 61 will be described below by replacing the substrate pattern 81 shown in FIGS. 2A and 2B with the mask pattern 61 in FIG.

  Note that the terms “substrate pattern” and “dot pattern” constituting the same in the following description are a planar pattern projected on a resist film on a wafer substrate in an exposure process, or exposure depending on the content of the description. It means any one of the three-dimensional patterns finally formed through the development process after the process.

  In FIG. 2B, as can be understood from the configuration of the substrate pattern 81 projected onto the wafer substrate 41, the mask pattern 61 includes a large number of dot patterns 101, 101, 101. The design is arranged so as to have periodicity in the three directions of the second direction 72 and the third direction 73. In the present embodiment, the angle difference between the first direction 71 and the second direction 72 and the angle difference between the second direction 72 and the third direction 73 are each 60 °. The three dot patterns 101, 101, 101 adjacent to each other are located at the vertices of an equilateral triangle whose side length is equal to a predetermined pitch. When the wafer substrate 41 is exposed using such a mask pattern 61, a substrate pattern 81 composed of a large number of dot patterns 101, 101, 101... Having the same periodicity at the same pitch is formed on the wafer substrate 41.

  In addition, the dot pattern 101 which comprises the mask pattern 61 is not restricted to equilateral triangle arrangement | positioning like this embodiment, For example, four adjacent dot patterns 101, 101, 101, 101 are located in each vertex of a square. It is good also as arrangement. Further, the dot patterns 101 shown in FIGS. 2A and 2B are merely examples, and for example, the number of dot patterns 101 constituting the mask pattern 61 may be increased or decreased as compared with these drawings. The shape of the dot pattern 101 is not limited to a circle, and may be a polygon such as a quadrangle, a triangle, or a hexagon.

  Here, as shown in FIGS. 1 and 5, the outer side of the mask pattern 61 on the reticle 21 from the translucent area 60A is a light-shielding area 60B having a light-shielding chrome part. This light shielding area 60B blocks exposure light from the light source 11, and prevents areas other than the mask pattern 61 from being exposed. In the present embodiment, considering the positioning error S> 0 of the substrate stage 51 shown in FIG. 3B, the boundary line 60b (solid line in the figure) of the light shielding region 60B is set to the dimension Q as shown in FIG. It is configured to be retracted (offset).

  This point will be described in detail. Originally, the boundary line 60b of the light shielding region 60B coincides with the peripheral boundary line 60a (dotted line in the drawing) between shots in step-and-repeat exposure. The theoretical value P of the dimension from the outermost peripheral dot pattern 101 of the mask pattern 61 to the peripheral boundary line 60 a is ½ of the pitch O between the dot patterns 101 and 101.

  However, when the boundary line 60b of the light shielding region 60B is provided according to the theoretical value P, if the positioning error S> 0 of the substrate stage 51 shown in FIG. 3B occurs, the peripheral boundary line 60a of each adjacent shot, An unexposed area is formed during 60a, and this unexposed area remains on the wafer substrate 41 as a blank pattern in a process after exposure and development. Therefore, in the present embodiment, the boundary line 60b of the light shielding region 60B is retracted by a dimension Q considering the positioning error S> 0 of the substrate stage 51. If the positioning error S is within the range of the dimension Q, it is adjacent. An unexposed area is not formed between the peripheral boundary lines 60a and 60a of each shot.

<< Problems related to substrate stage positioning errors >>
Here, the problem regarding the positioning error of the substrate stage 51 including FIG. 3B described above will be described in detail with reference to FIGS. 3A, 3B, 4A, and 4B. 3 (a), 3 (b), 4 (a), and 4 (b) are reference diagrams for explaining a problem related to the positioning error of the substrate pattern, for example, the substrate pattern of FIG. 2 (a). As in 81a and 81b, only the vicinity of the peripheral boundary line 60a between adjacent substrate patterns A and B is shown.

<<< Substrate Stage Positioning Error S = 0 >>>
FIG. 3A shows a case where the positioning error S of the substrate stage 51 shown in FIG. The top view of FIG. 6A is a plan view showing a dot pattern near the peripheral boundary line 60a of the substrate patterns A and B formed by the previous and subsequent shots. In this plan view, dot patterns other than the vicinity of the peripheral boundary line 60a of the substrate patterns A and B are omitted. Actually, as shown in FIG. 2A, the dot pattern 101 is formed on the entire substrate patterns A and B (the same applies to FIGS. 4B, 4A, and 4B).

  The center diagram in FIG. 3A is a partially enlarged view showing a part near the peripheral boundary line 60a in the top diagram. In this partially enlarged view, the peripheral boundary line 60a of the substrate patterns A and B is shown as a zigzag fine line for convenience of explanation, but when the positioning error of the substrate stage 51 is 0, the zigzag peripheral boundary line 60a is It hardly occurs.

  3A shows, for example, the substantially hexagonal substrate patterns 81a and 81b shown in FIG. 2A as simplified rectangular substrate patterns A and B. FIG. 7B conceptually shows a state in which the vicinity of the peripheral boundary line 60a of B is in contact with each other with a positioning error S = 0 without overlapping each other.

  In this way, when the positioning error S of the substrate stage 51 is 0, as shown in the center diagram of FIG. 3A, the connecting portion of the substrate patterns A and B does not occur, so the dot pattern in the connecting portion The dimensional accuracy of 101 does not extremely decrease. However, as described above, adjacent dot patterns disappear in the peripheral portion of the mask pattern 61 near the light shielding region 60B (see FIG. 5), so that the optical interference effect between the dot patterns is reduced and the dot pattern solution is reduced. The image quality is lowered. For this reason, even if the positioning error of the substrate stage 51 is 0, the diameter dimension of the dot pattern 101 near the peripheral boundary line 60a shown in FIG.

<<< When the substrate stage positioning error S> 0 >>>>
FIG. 3B shows a case where the positioning error S of the substrate stage 51 shown in FIG. In such a case, as shown in the uppermost drawing of FIG. 6B, exposure is performed in a state where a gap is generated between the peripheral boundary lines 60a of the adjacent substrate patterns A and B. It will be.

  The center diagram in FIG. 3B is a partially enlarged view showing a part near the peripheral boundary line 60a in the top diagram. When the exposure is performed with a gap between the peripheral boundary lines 60a of the adjacent substrate patterns A and B, an unexposed area is formed as shown by the zigzag thick line in the figure.

  3B shows the substantially hexagonal substrate patterns 81a and 81b as simplified rectangular substrate patterns A and B, as in FIG. 3A, and these substrate patterns A are shown in FIG. , B conceptually shows a state in which the peripheral boundary line 60a is separated without being in contact with each other with a positioning error S> 0.

  Thus, when the positioning error S> 0 of the substrate stage 51, an unexposed region is formed between the peripheral boundary lines 60a of the substrate patterns A and B, and this region is the region after the exposure and development. In the process, it remains on the wafer substrate 41 as a blank pattern. For example, if the substrate patterns A and B shown in FIG. 3B are PSS, an irrelevant pattern will be mixed in the diffraction grating-like substrate pattern 81 having periodicity, which becomes a serious defect. . Similarly to FIG. 3A, the diameter dimension of the dot pattern 101 in the vicinity of the peripheral boundary line 60a shown in FIG. 3B due to the effect of lower resolution in the peripheral portion of the mask pattern 61 near the light shielding region 60B. May become smaller.

<<< Position error S <0 of substrate stage >>>
FIG. 4A shows a case where the positioning error S of the substrate stage 51 shown in FIG. In such a case, as shown in the uppermost drawing of FIG. 9A, exposure is performed with the vicinity of the peripheral boundary line 60a of the adjacent substrate patterns A and B overlapping each other. .

  The center diagram of FIG. 4A is a partially enlarged view showing a part near the peripheral boundary line 60a in the top diagram. When exposure is performed in the state where the vicinity of the peripheral boundary line 60a of the adjacent substrate patterns A and B overlap each other, a double-exposed region is formed as shown by two zigzag thin lines in the drawing.

  4A shows the substantially hexagonal substrate patterns 81a and 81b as simplified rectangular substrate patterns A and B, as in FIG. 3A, and these substrate patterns A are shown in FIG. , B conceptually represents a state where the vicinity of the peripheral boundary line 60a overlaps each other with a positioning error S <0.

  As described above, when the positioning error S <0 of the substrate stage 51, the vicinity of the peripheral boundary line 60a of the substrate patterns A and B overlap each other, and a double-exposed region is formed. Since the double-exposed region is overexposed, the diameter dimension of the dot pattern 101 near the peripheral boundary line 60a of the substrate patterns A and B may be significantly reduced. In addition, the diameter dimension of the dot pattern 101 may be reduced due to the effect of lower resolution in the peripheral portion of the mask pattern 61 near the light shielding region 60B.

  Here, FIG. 4B shows a case where the diameter dimension of the dot pattern 101 is significantly reduced due to the influence of the double-exposed region. 4B, even if the positioning error S <0 of the substrate stage 51, the double-exposed area is merely increased or decreased, and the blank pattern as shown in FIG. 3B is not etched. It will not remain. However, the diameter dimension of the dot pattern 101 in the vicinity of the peripheral boundary line 60a between the adjacent substrate patterns A and B is the diameter dimension of the dot pattern 101 formed on the inner side due to the influence of the double exposure region. Will be smaller than.

<< Substrate Pattern Manufacturing Method According to the Present Embodiment >>
Next, a substrate pattern manufacturing method according to this embodiment for solving the above problem will be described with reference to FIGS. 1, 2A, 6A, and 6B. In the substrate pattern manufacturing method according to the present embodiment, a first exposure process in which the mask pattern 61 is subjected to step-and-repeat exposure on the entire unexposed wafer substrate 41, and a connecting portion between the shots in the first exposure process. And a second exposure step in which the mask pattern 61 is subjected to multiple exposure in a step-and-repeat manner.

<<< First Exposure Step >>>
The wafer substrate 41 is placed on the substrate stage 51 of the exposure apparatus 1 shown in FIG. 1, and the mask pattern 61 of the reticle 21 is sequentially projected onto the wafer substrate 41, and each shot of the mask pattern 61 (see FIG. 2A). Step-and-repeat exposure is performed so that reference numerals 81a to 81e are adjacent to each other.

  In such a first exposure step, the control unit 91 first sets adjacent dot patterns arranged on the outermost periphery of each mask pattern 61 exposed on the wafer substrate 41 in the previous and subsequent shots, for example, FIG. The pitch between the dot pattern 101, 101, 101 ... at the right end of the reference numeral 81a shown in (a) and the dot pattern 101, 101, 101 ... at the left end of the reference numeral 81b is the pitch between the dot patterns 101, 101 shown in FIG. The substrate stage 51 is moved with high accuracy so as to be equal to O.

  Next, the control unit 91 causes the light source 11 shown in FIG. 1 to emit exposure light having a light amount corresponding to ½ of the total exposure amount of the photosensitive agent used on the wafer substrate 41, and causes a reticle on the wafer substrate 41. 21 mask patterns 61 are exposed. Here, the amount of exposure light in each of the first and second exposure steps is determined according to the total exposure amount of the photosensitive agent and the number of overlapping exposure steps (multiple number). For example, in this embodiment, since the exposure process is performed twice in total, the amount of exposure light in each exposure process is set to ½ of the light amount corresponding to the total exposure amount of the photosensitive agent. Similarly, if the exposure process is performed three times, four times or five times in total, the light amount of the exposure light in each exposure step is 1/3, 1/4 of the light amount corresponding to the total exposure amount of the photosensitive agent. Or it can be set to 1/5. However, the light amount of the exposure light in each exposure step may be a light amount finally corresponding to the total exposure amount of the photosensitive agent as a result of performing the multiple exposure steps. Therefore, as in this embodiment, the amount of exposure light in each exposure step may not be equal.

  Further, in the present embodiment, as shown in FIG. 5, the boundary line 60b of the light shielding region 60B that delimits the light transmitting region 60A of the mask pattern 61 is set back by the dimension Q considering the positioning error S> 0 of the substrate stage 51. It is as the structure made to do. As a result, when the positioning error S is within the range of the dimension Q, the problem that an unexposed area is formed between the peripheral boundary lines 60a and 60a of the adjacent shots (see FIG. 3B) does not occur. Further, the problem of a decrease in the diameter dimension of the dot patterns 101, 101, 101... Near the peripheral boundary line 60a of the adjacent substrate patterns A and B due to a decrease in resolution is the second exposure step described below. It is improved or reduced by performing.

<<< Second Exposure Step >>>
FIGS. 6A and 6B show a second exposure process performed subsequent to the first exposure process described above. As shown in the uppermost drawing of FIG. 6A, in the second exposure process, the central portion of the mask pattern 61 is overlapped with the connecting portions of the adjacent substrate patterns A and B in the first exposure process. Multiple exposure is performed. This multiple exposure can be called “shift exposure” because the center of the mask pattern 61 is shifted from the first exposure process.

  In the uppermost drawing of FIG. 5A, a substrate pattern that is subjected to multiple exposure in the second exposure step is denoted by reference symbol C. Although only one set of substrate patterns A, B, and C is shown in the drawing, all the adjacent substrate patterns A, B, A, B... On the wafer substrate 41 are shown in the second exposure step. The substrate pattern C, C, C... Is subjected to multiple exposure step by step with the central portion of the mask pattern 61 overlapping the connecting portion.

  In such a second exposure process, the controller 91 first causes the dot patterns 101, 101, 101... Of the substrate patterns A and B and the dot patterns 101, 101, 101. In other words (that is, the periodicity of each dot pattern 101 is maintained), the substrate stage 51 is moved with high accuracy, and the vicinity of the center of the mask pattern 61 is overlapped with the connecting portions of the substrate patterns A and B. Thereafter, as in the first exposure step, the control unit 91 emits exposure light whose light amount has been reduced to ½ from the light source 11 and puts the substrate pattern C on the connecting portion of the substrate patterns A and B. Multiple exposure. Thereafter, such multiple exposure of the substrate pattern C is repeated step by step.

<<< Action and effect >>>
The center diagram in FIG. 6A is a partially enlarged view showing the vicinity of the peripheral boundary line 60a in the top diagram. As shown in the figure, according to the substrate pattern manufacturing method according to the present embodiment, the dot pattern 101, 101, 101 near the peripheral boundary line 60a of each of the adjacent substrate patterns A, B due to a decrease in resolution. The problem of reducing the diameter dimension of ... is improved or reduced. Hereinafter, the effect of this method will be described in detail with reference to FIG.

  In the top view and the center view of FIG. 6A, dot patterns 101, 101, 101... Around the peripheral boundary line 60a of the substrate patterns A, B are concentric circles 101A, 101B having a small diameter and a large diameter, respectively. Show. First, the diameter dimensions of the dot patterns 101A, 101A, 101A,... In the vicinity of the peripheral boundary line 60a in the first exposure step are the other dot patterns 101, 101, 101,. It becomes smaller than the diameter dimension. As described above, the diameter dimension of each dot pattern 101A near the peripheral boundary line 60a is reduced because the resolution of the dot pattern 101 of the mask pattern 61 is reduced in the peripheral part near the light shielding region 60B shown in FIG. Because it does.

  Next, in the second exposure process, the dot patterns 101A, 101A, 101A,... Near the peripheral boundary line 60a of the substrate patterns A, B are added to the dot patterns 101, 101, 101 near the center where the mask pattern 61 is high in resolution. 101 ... are overlapped for exposure. As a result, each dot pattern 101A having a small diameter dimension is restored to dot patterns 101B, 101B, 101B,... Having regular diameter dimensions, as indicated by the large-diameter circle in FIG. As a result, when the wafer substrate 41 is developed, the dot pattern (cylindrical protrusion) formed in the vicinity of the peripheral boundary line 60a of the substrate patterns A and B can be greatly reduced.

  Here, the dot pattern 101, 101, 101... In the vicinity of the peripheral boundary line 60a of the substrate pattern C in the second exposure step has a reduced diameter size due to the above-described decrease in resolution. However, the dot patterns 101, 101, 101,... Of the substrate patterns A, B, where the dot patterns 101 in the vicinity of the peripheral boundary line 60a of the substrate pattern C overlap, resolve the mask pattern 61 in the first exposure process. Since the dot pattern 101, 101, 101... Near the center having high properties is exposed, the diameter dimension is a regular size. Thereby, when the wafer substrate 41 is developed, the dot pattern (cylindrical protrusion) formed near the peripheral boundary line 60a of the substrate pattern C can be greatly reduced.

  Further, the lowermost drawing of FIG. 6A simplifies the substrate patterns A, B, and C of the uppermost drawing into rectangles, and the peripheral boundaries of the substrate patterns A and B in the first exposure process. This conceptually shows a state in which the vicinity of the center of the substrate pattern C in the second exposure process overlaps with the vicinity of the line 60a. In the figure, even when the positioning error S of the substrate stage 51 is smaller than 0, the vicinity of the peripheral boundary line 60a of each of the substrate patterns A and B is double-exposed. In this case, each dot pattern 101 in the vicinity of the peripheral boundary line 60a of each substrate pattern A, B is affected by double exposure, but the diameter dimension of each dot pattern 101 is reduced by the second exposure process. It can be greatly reduced.

  As already described, in the present embodiment, as shown in FIG. 5, the boundary line of the light shielding region 60B that defines the light transmitting region 60A of the mask pattern 61 by the dimension Q in consideration of the positioning error S> 0 of the substrate stage 51. The configuration is such that 60b is retracted. Accordingly, if the positioning error S is within the range of the dimension Q, the blank pattern as shown in FIG. 3B is not left unetched.

  FIG. 6A shows the case where the vicinity of the center of one substrate pattern C is superimposed on the entire vicinity of the peripheral boundary line 60a of each of the substrate patterns A and B, but the method of the present invention is applied to this. It is not limited. For example, as shown in FIG. 6B, a half of the vicinity of the center of one substrate pattern C is overlapped with a half of the vicinity of the peripheral boundary line 60a of each of the substrate patterns A and B so that a total of two substrate patterns C are subjected to multiple exposure. It may be. Even in this case, the same effect as the present embodiment can be obtained.

  As described above, in the substrate pattern manufacturing method and the exposure apparatus according to this embodiment, the dot pattern 101 near the peripheral boundary line 60a of each substrate pattern A, B is changed to the dot pattern 101 near the center of the substrate pattern C. The dot pattern 101 with high resolution is subjected to multiple exposure (shift exposure). As a result, the dot pattern 101 can be uniformly formed at the connecting portion of the substrate patterns A and B, and a large number of patterned substrates that require high accuracy such as PSS can be efficiently produced. .

Second Embodiment
Next, a substrate pattern manufacturing method and exposure apparatus according to a second embodiment of the present invention will be described with reference to FIGS. In the present embodiment, the same parts as those in the first embodiment described above are denoted by the same reference numerals in the drawings, and detailed description thereof is omitted.

  In FIG. 7, the exposure apparatus 1 of the present embodiment is configured to include a light source 11, a reticle 21, an optical system 31, a substrate stage 51, and a control unit 91, as in the first embodiment described above. A wafer substrate 41 similar to that of the first embodiment is placed on the substrate stage 51. This embodiment is different from the first embodiment in the configuration of the three mask patterns 65, 66, and 67 drawn on the reticle 21 and the method of manufacturing the substrate pattern 85 executed by the control unit 91. ing. In the present embodiment, the final substrate pattern 85 formed on the wafer substrate 41 is a dot pattern (see reference numeral 154 in FIG. 8A) having the same periodicity as in the first embodiment. As in the first embodiment, a positive resist is provided on the wafer substrate 41. However, the method and apparatus of the present invention can also be applied to a negative resist.

<< mask pattern on reticle >>
7 and 9A, the mask patterns 65, 66, and 67 used in this embodiment are each composed of a plurality of line segment patterns that are parallel to each other. These mask patterns 65, 66, and 67 are different from each other in the angle of the line segment pattern that is a component thereof. With reference to the line segment pattern of the mask pattern 66, the line segment pattern of the mask pattern 65 is tilted 60 ° counterclockwise, and the line segment pattern of the mask pattern 67 is tilted 60 ° clockwise.

  The extending directions of the line segment patterns constituting the mask patterns 65, 66, and 67 coincide with the three directions of the periodicity of the dot pattern that is finally formed on the substrate pattern 85. That is, the line segment pattern of the mask pattern 65 extends in the first direction 71, the line segment pattern of the mask pattern 66 extends in the second direction 72, and the line segment pattern of the mask pattern 67 extends in the third direction 73. The mask patterns 65, 66, and 67 of the present embodiment are each composed of four parallel line segment patterns. The number of line segment patterns is the exposure area (area surrounded by the dotted line in FIG. 9A). It can be changed according to the width.

  Further, the outer side of the mask pattern 65, 66, 67 on the reticle 21 is a light shielding region 60B similar to that of the first embodiment. As shown in FIG. 10, the boundary line 60b (solid line in the figure) of the light shielding region 60B that defines the light transmitting region 60A of the mask patterns 65, 66, and 67 is a dimension that takes into account the positioning error S> 0 of the substrate stage 51. Only Q is configured to be set back (offset) from the theoretical value P of the peripheral boundary line 60a (dotted line in the figure).

<< Substrate Pattern Manufacturing Method According to the Present Embodiment >>
Next, a method for manufacturing a substrate pattern according to this embodiment will be described. 8A and 8B are drawings for explaining an exposure process in the method of manufacturing a substrate pattern according to the present embodiment. As shown in FIG. 6A, in the substrate pattern manufacturing method according to the present embodiment, the substrate stage 51 is scanned along the three directions 71, 72, 73 of the mask patterns 65, 66, 67, and unexposed. The mask patterns 65, 66, and 67 are sequentially scanned and exposed on the entire wafer substrate 41.

  As described above, each line segment pattern constituting the mask pattern 65, 66, 67 of the reticle 21 extends in the same direction as the three directions 71, 72, 73 of the periodicity of the dot pattern formed on the wear substrate 41. ing. In the present embodiment, scanning exposure of the entire surface of the wafer substrate 41 is performed using such mask patterns 65, 66, and 67 in order. For example, in the A scanning exposure process, the entire surface of the wafer substrate 41 is subjected to scanning exposure using the mask pattern 65 in each scanning direction. In the B-scan exposure process, scanning exposure is performed on the entire surface of the wafer substrate 41 using the mask pattern 66. In the C scanning exposure process, scanning exposure is performed on the entire surface of the wafer substrate 41 using the mask pattern 67. These AC scanning exposure steps are executed by the control unit 91 shown in FIG.

  Hereinafter, a specific example of scanning exposure using the mask pattern 67 will be described with reference to FIGS. 9B and 9C. As shown in the upper left diagram of FIG. 5B, the control unit 91 projects the mask pattern 67 onto the wafer substrate 41, and in the third direction 73, which is the same as the extending direction of the line segment pattern, the substrate stage 51. To scan. As a result, the wafer substrate 41 is exposed straight along the third direction 73 with the width of the mask pattern 67 as shown in the lower right diagram of FIG. As a result, four linear patterns 102a, 102b, 102c, and 102d are formed in the exposure area 67a of the first scanning exposure, which are parallel to each other and traverse the wafer substrate 41 from one to the other. All of these four linear patterns 102 a to 102 d extend in the third direction 73.

  Here, the moving speed of the substrate stage 51 in scanning exposure depends on the light amount of the light source 11 and the length of the mask pattern to be subjected to multiple exposure in the scanning direction according to the total exposure amount of the photosensitive agent used on the wafer substrate 41. Determined by. The controller 91 moves the substrate stage 51 at a speed at which the total light amount in the A to C scanning steps becomes the total exposure amount of the photosensitive agent used on the wafer substrate 41.

  Next, the control unit 91 forms a straight line pattern (see reference numeral 102d in FIG. 9C) of the current exposure area 67a and a straight line formed at the left end of the next exposure area 67d in the figure. The substrate stage 51 is moved stepwise so that the pitch between the patterns (see reference numeral 102a in FIG. 9C) is equal to the pitch O shown in FIG. 10 and the linear patterns are parallel to each other. Thereafter, the control unit 91 scans the substrate stage 51 in the third direction 73 and performs the same scanning exposure as described above.

  Thereafter, the control unit 91 repeatedly performs scanning exposure for scanning the substrate stage 51 in the third direction 73 by the same control process as described above, and extends in the third direction 73 to the exposure regions 67c, 67d... On the wafer substrate 41. A linear pattern 102 is formed. By repeating such scanning exposure, a large number of linear patterns 102, 102, 102... Extending in the third direction 73 are finally formed over the entire surface of the wafer substrate 41. In this way, the A-scan exposure process is completed.

  Subsequently, the control unit 91 uses the mask patterns 65 and 66 to execute the B and C scanning exposure processes by the same control process as described above. As a result of such AC scanning exposure process, a large number of linear patterns 102, 102, 102... Extending in the first, second, and third directions 71, 72, 73 are formed over the entire surface of the wafer substrate 41. The

  As shown in FIG. 8B, the photosensitive agent on the wafer substrate 41 is not exposed only at the intersections of the linear patterns 102, 102, 102 extending in the three directions 71, 72, 73, and other portions. Are subjected to multiple exposure. After the subsequent development process, the finally remaining unexposed intersection portions are a large number of dot patterns (cylindrical protrusions) 151, 152, 153, 154, 155, 156 having the same periodicity as in the first embodiment. 157 ... The outlines of the dot patterns 151 to 157 shown in FIG. 5B are hexagonal, but in reality, the corners of the dot patterns 151 to 157 are rounded by a photolithography technique such as multiple exposure or etching. Finally, a substantially circular dot pattern similar to that of the first embodiment is formed.

<<< Action and effect >>>
In the exposure apparatus 1 and the substrate pattern manufacturing method of the present embodiment described above, the mask pattern 65, 66 is moved by moving the substrate stage 51 in the three directions 71, 72, 73 of the periodicity of the dot pattern to be finally formed. , 67 are subjected to scanning exposure on the wafer substrate 41. As a result, the exposure area of one scanning exposure (see the range surrounded by the dotted line in FIG. 9) can be greatly expanded, the number of exposures for exposing the entire surface of the wafer substrate 41 can be reduced, and the period It is possible to efficiently form a substrate pattern having the property. As a result, the productivity of a patterned substrate such as a diffraction grating can be improved.

  Further, according to the scanning exposure employed in the present embodiment, the linear pattern 102 having a higher optical resolution than the circular dot pattern formed by batch exposure as in the first embodiment can be formed on the wafer substrate 41. it can. This makes it possible to form a circular dot pattern (cylindrical protrusion) with higher resolution than that of the first embodiment on the wafer substrate 41, and improve the accuracy of a patterned substrate such as a diffraction grating.

  Furthermore, by adopting the line segment pattern as the mask patterns 65, 66, and 67, it is possible to reduce the variation factors of the photolithography process regarding the extending direction of the line segment pattern. As a result, it is possible to reduce control processing for ensuring accuracy, and it is possible to form a substrate pattern having periodicity with high accuracy while simplifying the control processing. As a result, a patterned substrate such as a diffraction grating can be manufactured easily and with high accuracy.

  In addition, as shown in FIG. 10, in this embodiment as well, as in the first embodiment, the light transmission of the mask patterns 65, 66, and 67 is performed only by the dimension Q considering the positioning error S> 0 of the substrate stage 51. The boundary line 60b of the light shielding region 60B that defines the region 60A is set back. Accordingly, if the positioning error S is within the range of the dimension Q, the blank pattern as shown in FIG. 3B is not left unetched.

  Also in the present embodiment, similarly to the first embodiment, when the positioning error S <0 of the substrate stage 51, the area near the peripheral boundary line 60a shown in FIG. 10 is double-exposed. As a result, as shown in FIG. 9C, a phenomenon occurs in which the width dimension of the linear patterns 102a and 102d formed on the outermost side becomes thinner than the linear patterns 102c and 102d formed on the inner side. However, the width dimensions of the linear patterns 102a, 102b, 102c, and 102d can be made uniform by the multiple exposure method described below. Therefore, even if the positioning error of the substrate stage 51 is any of S = 0, S> 0, or S <0, the problem of molding defects in the joint portion of the substrate pattern is improved or reduced.

<<< Multiple exposure method for uniformly forming a substrate pattern >>>
Hereinafter, a multiple exposure method for uniformly forming the above-described substrate pattern will be described with reference to FIGS. This multiple exposure method applies the multiple exposure (shift exposure) of the first embodiment to the second embodiment described above, and performs a total of two scanning exposures in each of the above-described AC exposure steps. Thus, a linear pattern is formed on the wafer substrate 41.

  FIG. 11A shows a linear pattern formed in the exposure areas 67a, 67b, 67c... Of the first scanning exposure. This first scanning exposure is performed in accordance with the same control process as in FIG. A total of six linear patterns are formed in the exposure area 67a (67b, 67c) of the first scanning exposure. The width dimension of these six linear patterns becomes narrower toward the outside where the above-described double exposure occurs (that is, closer to the peripheral boundary line 60a shown in FIG. 10).

  On the other hand, FIG. 11C shows a straight line pattern formed in the exposure areas 67p, 67q, 67r... Of the second scanning exposure. Here, as shown in the partially enlarged view of FIG. 5B, the second scanning exposure is performed by shifting the exposure area by ½ with respect to the first scanning exposure. .., So that the central portions of the second exposure areas 67p, 67q, 67r,... Overlap with the connecting portions (see the dotted lines in the drawing) of the first exposure areas 67a, 67b, 67c,. The substrate 41 is subjected to multiple exposure (shift exposure).

  Further, as described above, the control unit 91 moves the substrate stage 51 at a speed at which the total light amount of the A to C scanning exposure steps becomes the total exposure amount of the photosensitive agent used for the wafer substrate 41. When this multiple exposure method is adopted, scanning exposure is performed twice in each of the A to C scanning exposure steps. Therefore, one scanning exposure is controlled so that the final exposure amount is 1/6 of the total exposure amount required.

  In such multiple exposure, as shown in FIG. 11 (b), the second exposure area 67p is changed into a linear pattern (thin linear pattern) located at each connecting portion of the first exposure areas 67a, 67b, 67c. , 67q, 67r,..., 67q, 67r... As a result, the linear pattern with a narrow width dimension located at each connecting portion of the first exposure areas 67a, 67b, 67c... Is restored to the normal width dimension by the second scanning exposure. As a result, the reduction in the final dot pattern (cylindrical protrusion) after development can be greatly reduced.

<Other changes>
The substrate pattern manufacturing method and the exposure apparatus of the present invention are not limited to the first and second embodiments described above. For example, as the mask pattern 61, 65 to 67 of the reticle 21 used in the method and apparatus of the present invention, a halftone phase shift mask having a partial transmittance and having a phase inverted by 180 ° may be used. In such a halftone phase shift mask, the transmittance of the light shielding region in the binary mask is increased to such an extent that a pattern is not formed (about 6%), and the phase is shifted by 180 °, so that the light passing through the opening is shifted. It is possible to improve the resolution performance by interfering with the amplitude and the amplitude of the transmitted light around the opening. If such a halftone phase shift mask is used to carry out the multiple exposure method at the connecting portion of the substrate pattern described above, the half of the exposure light that passes through the peripheral portion of the mask pattern and the light shielding region around the outer periphery thereof. The uniformity of the substrate pattern in the vicinity of the joint portion can be improved by interfering with the tone transmission light.

  FIG. 12A is a microscope observation image showing a comparative example of a dot pattern formed by conventional step-and-repeat exposure. FIG. 2B is a microscope observation image showing an example of a dot pattern formed by the substrate pattern manufacturing method of the present invention. As shown in FIG. 5A, in the conventional step-and-repeat exposure, a molding defect occurs near the connecting portion of the dot pattern due to the positioning error of the substrate stage. On the other hand, in the embodiment of the present invention shown in FIG. 5B, no defective molding is observed near the connecting portion of the dot pattern, and the connecting portion itself is not recognized. Further, the size and shape of the dot pattern in the vicinity of the connecting portion are formed with high accuracy as prescribed, and all the dot patterns are formed substantially uniformly.

DESCRIPTION OF SYMBOLS 1 Exposure apparatus 11 Light source 21 Reticle 31 Optical system 41 Wafer substrate 51 Substrate stage 60A Light transmission area 60B Light shielding area 60a One shot boundary line 60b Light shielding area boundary line 61 Mask pattern (dot pattern)
65, 66, 67 Mask pattern (line segment pattern)
67a, 67b, 67c Exposure area 67p, 67q, 67r Exposure area 71 First direction 72 Second direction 73 Third direction 81a-81e, 85 Substrate pattern 91 Control unit 101 Dot pattern 102, 102a-102d Linear pattern 151-155 dots pattern

Claims (9)

A method of manufacturing a substrate pattern in which a wafer substrate is repeatedly exposed with a reticle mask pattern, and a large number of components are arranged with a periodicity in a plurality of directions at a predetermined pitch,
Including an exposure process on the wafer substrate that has already been exposed with the mask pattern, the multiple exposure step of exposing the mask pattern in an overlapping manner,
In the multiple exposure step, the mask pattern is shifted by an integral multiple of the pitch between the components of the substrate pattern with respect to the exposure region on the wafer substrate, and at least two exposures including the exposure already performed are performed. A method of manufacturing a substrate pattern, wherein the light intensity is reduced in accordance with the number of exposures.   2. The substrate pattern manufacturing method according to claim 1, wherein, in the multiple exposure step, exposure is performed by overlapping a portion inside the boundary of the mask pattern in the vicinity of the boundary of the exposure region on the wafer substrate.   3. The method of manufacturing a substrate pattern according to claim 1, wherein the mask pattern has a plurality of dot patterns arranged with a periodicity in a plurality of directions at a predetermined pitch.   The substrate pattern manufacturing method according to claim 1, wherein the mask pattern has a plurality of parallel line segment patterns extending in any one direction of the periodicity. Preparing a plurality of types of the mask patterns corresponding respectively to a plurality of directions of the periodicity;
Each of the plurality of types of the mask pattern has a plurality of line segment patterns parallel to each other extending in any one direction of the periodicity,
The multiple exposure step includes a plurality of exposure steps of exposing the wafer substrate with each of a plurality of types of the mask patterns,
In the exposure step, either one of the wafer substrate or the mask pattern is exposed while scanning in the extending direction of the line segment pattern, thereby extending on the wafer substrate in any one direction of the periodicity. 4. The substrate according to claim 1, wherein a plurality of linear patterns parallel to each other are projected, and the linear patterns projected on the wafer substrate through a plurality of times of the exposure step intersect each other. Pattern manufacturing method.   When exposing adjacent areas on the wafer substrate with the mask pattern, a light-shielding area that defines a light-transmitting area of the mask pattern by a predetermined dimension based on a positioning error value larger than 0 that may occur between the exposure areas. The manufacturing method of the substrate pattern of any one of Claims 1-5 which retreated the boundary of these.   An exposure apparatus for carrying out the substrate pattern manufacturing method according to claim 1, wherein a light source that emits exposure light for exposing the wafer substrate and the wafer substrate are mounted. A movable substrate stage, a reticle having one or a plurality of the mask patterns arranged between the light source and the substrate stage, and a control unit for performing a control process for exposing at least the wafer substrate; An exposure apparatus characterized in that the control unit controls the amount of the exposure light and the movement of the substrate stage to execute the multiple exposure step.   A substrate pattern in which a number of convex or concave patterns are arranged with periodicity in a plurality of directions at a predetermined pitch is formed by the method for manufacturing a substrate pattern according to any one of claims 1 to 6. A patterned substrate characterized by that.   A light emitting device comprising the patterned substrate according to claim 8.