JP2012129784A - Random number generation circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a random number generation circuit that can generate high randomness true random numbers even at initial sampling just after a start of circuit operation.SOLUTION: The random number generation circuit includes: M1 first ring oscillators 10-1 comprising odd logic gate stages; M2 second ring oscillators 10-2 comprising even inverter stages and one logic gate stage; (M1+M2)input XOR 21 for computing an exclusive disjunction of intermediate node outputs of the first ring oscillators 10-1 and intermediate node outputs of the second ring oscillators 10-2; a D-FF 22 for latching outputs with a sampling clock to output random values; and a control section 100 for generating the sampling clock. An inverter is connected to the output of each logic gate constituting the first ring oscillator 10-1, and an output of any one inverter is the intermediate node output of the ring oscillator.

Description

  The present invention relates to a random number generation circuit that generates a high-quality intrinsic random number with a low-gate circuit configuration based on a ring oscillator including a digital logic gate circuit. In particular, the present invention relates to a technique for improving the quality of a generated random number immediately after turning on the power in a random number generating circuit having a power ON / OFF control function.

  In the security field based on cryptographic technology, random number generation plays an important role. A condition for random numbers used in cryptographic techniques such as challenge-response authentication and key sharing is unpredictable. In the application to cryptographic technology based on the unpredictability of random numbers, an intrinsic random number generation circuit that generates random numbers using physical phenomena with randomness such as fluctuation phenomena existing in nature plays an important role. Fulfill.

  As shown in FIG. 10, the conventional true random number generation circuit shown in Non-Patent Document 1 takes XOR (exclusive OR) of intermediate node outputs of a plurality of ring oscillators composed of odd-numbered inverters, and outputs the output as D It is configured to latch by -FF (D-type flip-flop) and output as a random value. Since the plurality of ring oscillators self-oscillate independently of each other with a constant amount of jitter in the oscillation period, the XOR output of the intermediate node value of these independent ring oscillators has unpredictable randomness. . By performing a sampling operation on the XOR output at a constant period by D-FF, an unpredictable true random number sequence can be extracted.

  By the way, when it is not necessary to generate a random number in the random number generation circuit, it is necessary to stop the circuit operation in order to save power consumption. In this case, for example, ON / OFF control of the oscillation operation of the ring oscillator can be performed by performing gating by using one of an odd number of inverters constituting the ring oscillator as a NAND gate or a NOR gate.

Sunar B., Martin W., Stinson D., “A provably secure true random number generator with built-in tolerance to active attacks”, IEEE Trans. Computers 56 (1), pp.109-119 (2007)

  For example, in a ring oscillator using a NAND gate as shown in FIG. 11, when the operation ON / OFF control signal input to the NAND gate is Low, the NAND gate output is fixed to High, and the operation ON / OFF control signal is set to Low. When switching from high to high, the NAND gate functions as an inverter and starts oscillating. However, the oscillation operation at this time always starts from the NAND gate as a starting point, with the output potential being high as the initial state.

  In the initial stage of the oscillation operation, the circuit operation is started from the same initial operation state every time the power is turned on, starting from the NAND gate. Therefore, for a while after the power is turned on, the oscillation jitter of the ring oscillator has not yet been sufficiently acquired. The probability that a random number sequence having the same pattern is generated every time the power is turned on tends to increase. If the first few bits after the power is turned on are the same random number sequence every time, it is considered that the original true random number that is not reproducible is contrary to an important condition that should be satisfied, and that security in challenge response authentication and the like is reduced. . For this reason, when outputting as a valid random number to the outside, there is a problem that it is necessary to discard the first several tens of bits after the power is turned on, and in some cases 100 bits or more.

  In addition, since the sampling interval is shortened when the sampling frequency is high, the conventional ring oscillator based on the free-running operation has a problem that the generated random numbers before and after the sampling have some correlation with each other and the random number quality is deteriorated. .

  An object of the present invention is to provide a random number generation circuit capable of generating a genuine random number with high randomness even in initial sampling immediately after the start of circuit operation.

  According to a first aspect of the present invention, in the random number generation circuit that generates a random number using the output of one or more ring oscillators, the at least one ring oscillator has an odd number of logic stages in which one input is connected to the output of the other logic gate. An operation ON / OFF control signal for turning the inverter operation of the logic gate ON or OFF is connected to the other input of each logic gate, and an inverter is connected to the output of each logic gate. Any one of the outputs is used as the output of the ring oscillator.

  According to a second aspect of the present invention, there are provided M1 (M1 is an integer of 1 or more) first ring oscillators composed of odd-numbered logic gates having one input connected to the output of the other logic gate, A second ring oscillator of M2 (M2 is an integer of 0 or more, M1 + M2 is an integer of 2 or more), an intermediate node output of the first ring oscillator, and a second ring oscillator, each including an inverter and a one-stage logic gate; A (M1 + M2) input XOR that takes an exclusive OR of the intermediate node outputs of the two, a D-FF that latches the output of the (M1 + M2) input XOR with a sampling clock and outputs it as a random value, and a control unit that generates the sampling clock; ON / OF which turns ON or OFF the inverter operation of the logic gate at the other input of each logic gate constituting the first ring oscillator Control signal is connected, respectively inverter to the output of each logic gate constituting the first ring oscillator is connected to one of the output of the inverter is configured to an intermediate node output of the ring oscillator.

  According to a third aspect of the present invention, there are provided M1 (M1 is an integer of 1 or more) first ring oscillators composed of odd-numbered logic gates having one input connected to the output of the other logic gate, A second ring oscillator of M2 (M2 is an integer of 0 or more, M1 + M2 is an integer of 2 or more), an intermediate node output of the first ring oscillator, and a second ring oscillator, each including an inverter and a one-stage logic gate; A (M1 + M2) input XOR that takes an exclusive OR of the intermediate node outputs of the two, a D-FF that latches the output of the (M1 + M2) input XOR with a sampling clock and outputs it as a random value, and a control unit that generates the sampling clock; ON / O which turns ON or OFF the inverter operation of the logic gate at the other input of each logic gate constituting the first ring oscillator An AND output of the F control signal and the inverted signal of the sampling clock is connected, an inverter is connected to the output of each logic gate constituting the first ring oscillator, and any one output of the inverter is connected to the middle of the ring oscillator. This is a node output.

  According to a fourth aspect of the present invention, there are provided M1 (M1 is an integer of 1 or more) first ring oscillators composed of odd-numbered logic gates having one input connected to the output of the other logic gate, A second ring oscillator of M2 (M2 is an integer of 0 or more, M1 + M2 is an integer of 2 or more), an intermediate node output of the first ring oscillator, and a second ring oscillator, each including an inverter and a one-stage logic gate; (M1 + M2) of the preceding stage D-FF that latches the intermediate node output of each of the intermediate node outputs by the sampling clock, and (M1 + M2) the input XOR that takes the exclusive OR of the latch outputs of the preceding stage D-FF, M1 + M2) includes a post-stage D-FF that latches the output of the input XOR with a sampling clock and outputs it as a random value, and a control unit that generates the sampling clock. An operation ON / OFF control signal for turning the inverter operation of the logic gate ON or OFF is connected to the other input of each logic gate constituting the ring oscillator of the first ring oscillator, and the output of each logic gate constituting the first ring oscillator is connected to the other input. Each of the inverters is connected, and the output of any one of the inverters is used as the intermediate node output of the ring oscillator.

  According to a fifth aspect of the present invention, there are provided M1 (M1 is an integer of 1 or more) first ring oscillators composed of odd-numbered logic gates having one input connected to the output of the other logic gate, A second ring oscillator of M2 (M2 is an integer of 0 or more, M1 + M2 is an integer of 2 or more), an intermediate node output of the first ring oscillator, and a second ring oscillator, each including an inverter and a one-stage logic gate; (M1 + M2) of the preceding stage D-FF that latches the intermediate node output of each of the intermediate node outputs by the sampling clock, and (M1 + M2) the input XOR that takes the exclusive OR of the latch outputs of the preceding stage D-FF, M1 + M2) includes a post-stage D-FF that latches the output of the input XOR with a sampling clock and outputs it as a random value, and a control unit that generates the sampling clock. An AND output of an operation ON / OFF control signal for turning ON or OFF the inverter operation of the logic gate and an inverted signal of the sampling clock is connected to the other input of each logic gate constituting the ring oscillator of the first oscillator. An inverter is connected to the output of each logic gate constituting the ring oscillator, and any one output of the inverter is used as an intermediate node output of the ring oscillator.

  According to a sixth aspect of the present invention, there is provided a ring oscillator composed of an odd-numbered logic gate having one input connected to the output of another logic gate, and a first latch that latches an intermediate node output of the ring oscillator with a sampling clock having a frequency S. Front stage D-FF, a second front stage D-FF that latches an input signal with a sampling clock of frequency S, a latch output of the second front stage D-FF, and a latch output of the first front stage D-FF, The output of the first preceding D-FF is selected at a frequency of once every M times of the sampling clock (M is an integer equal to or greater than 2) by the 2-input XOR that takes the exclusive OR of and the selector control signal, and sampling The (M-1) times of the clock selects a 2-input XOR output, and outputs a selector for inputting to the second preceding stage D-FF and a frequency S / M output obtained by dividing the sampling clock of the frequency S by M. A latch that latches the output of the second preceding stage D-FF and outputs it as a random value; a control unit that generates a sampling clock of frequency S, a selector control signal, and an output clock of frequency S / M; And an operation ON / OFF control signal for turning the inverter operation of the logic gate ON or OFF is connected to the other input of each logic gate constituting the ring oscillator, and the output of each logic gate constituting the ring oscillator is respectively An inverter is connected, and any one output of the inverter is used as an intermediate node output of the ring oscillator.

  According to a seventh aspect of the present invention, there is provided a ring oscillator composed of an odd number of logic gates having one input connected to an output of another logic gate, and a first latch that latches an intermediate node output of the ring oscillator with a sampling clock having a frequency S. Front stage D-FF, a second front stage D-FF that latches an input signal with a sampling clock of frequency S, a latch output of the second front stage D-FF, and a latch output of the first front stage D-FF, The output of the first preceding D-FF is selected at a frequency of once every M times of the sampling clock (M is an integer equal to or greater than 2) by the 2-input XOR that takes the exclusive OR of and the selector control signal, and sampling The (M-1) times of the clock selects a 2-input XOR output, and outputs a selector for inputting to the second preceding stage D-FF and a frequency S / M output obtained by dividing the sampling clock of the frequency S by M. A latch that latches the output of the second preceding stage D-FF and outputs it as a random value; a control unit that generates a sampling clock of frequency S, a selector control signal, and an output clock of frequency S / M; And an AND output of an operation ON / OFF control signal for turning on or off the inverter operation of the logic gate and an inverted signal of the sampling clock of frequency S is connected to the other input of each logic gate constituting the ring oscillator An inverter is connected to the output of each logic gate constituting the ring oscillator, and any one output of the inverter is used as an intermediate node output of the ring oscillator.

  The logic gate may be a NAND gate or a NOR gate.

  In the ring oscillator composed of odd-numbered logic gates (NAND gates or NOR gates) used in the random number generation circuit of the present invention, which logic gate is the starting point of the oscillation operation by the ON control of the operation ON / OFF control signal Is randomly determined based on thermal fluctuations. That is, since the initial state is randomly determined after the circuit operation starts and the oscillation operation is started, a true random number with low reproducibility and high randomness can be generated even in the first sampling immediately after the circuit operation starts.

  Furthermore, since the random number generation circuits according to the sixth and seventh aspects have a serial processing type configuration, an effect equivalent to the case where a plurality of ring oscillators are used with only a single ring oscillator can be obtained. As a result, high-quality intrinsic random numbers can be generated at a level equivalent to the circuit configuration of a plurality of ring oscillators with a small gate scale.

It is a figure which shows the structural example of the random number generation circuit of Example 1 of this invention. 3 is a time chart illustrating an operation example of a control unit 100 according to the first embodiment. It is a figure which shows the other structural example of the random number generation circuit of Example 1 of this invention. It is a figure which shows the structural example of the random number generation circuit of Example 2 of this invention. It is a figure which shows the structural example of the random number generation circuit of Example 3 of this invention. It is a figure which shows the structural example of the random number generation circuit of Example 4 of this invention. It is a figure which shows the structural example of the random number generation circuit of Example 5 of this invention. 10 is a time chart illustrating an operation example of a control unit 200 according to a fifth embodiment. It is a figure which shows the structural example of the random number generation circuit of Example 6 of this invention. It is a figure which shows the structural example 1 of the conventional random number generation circuit. It is a figure which shows the structural example 2 of the conventional random number generation circuit.

FIG. 1 shows a configuration example of a random number generation circuit according to the first embodiment of the present invention.
Referring to FIG. 1, in the first embodiment, one (in this case, 10-1) of a plurality (M) of ring oscillators 10-1 to 10-M of the conventional random number generation circuit shown in FIG. N represents an odd number) NAND gate. That is, an example of M1 = 1 and M2 = (M−1) in the claims is shown.

  In the ring oscillator 10-1, the inverters are equally connected to the output node of the NAND gate in order to equalize the load capacity of the intermediate node. The output of one inverter is connected to the D-FF 22 via the M input XOR 21 for sampling. The operation ON / OFF control signal is equally distributed and input to each NAND gate via the buffer 11 of the ring oscillator 10-1, and is further input to the NAND gates of the other ring oscillators 10-2 to 10-M. In this configuration, the oscillator is switched ON (operation) and OFF (non-operation). Ring oscillator 10-1 and ring oscillators 10-2 to 10-M may be configured using NOR gates instead of NAND gates.

FIG. 2 illustrates an operation example of the control unit 100 according to the first embodiment.
The control unit 100 inputs an operation ON / OFF control signal and a system clock, and divides the system clock (here, divided by 4) when the operation ON / OFF control signal is High, and gives the sampling clock to the D-FF 22 And a random number valid display signal is generated as necessary.

  Here, the circuit operation of the ring oscillator 10-1 composed of N NAND gates will be described. First, in the circuit operation OFF state, the common operation ON / OFF control signal to the NAND gate input is set to Low. In this state, all N NAND gate outputs are fixed to High, and the oscillation operation is stopped. When the operation ON / OFF control signal switches to High, the NAND gate starts to function as an inverter, but when the operation ON / OFF control signal switches to High, the output voltages of the N NAND gates are all High. Then, the operation of transitioning the output to the Low side occurs from any NAND gate. Since the load capacity of the nodes is equalized by adding an inverter to the NAND gate output, which NAND gate of the N NAND gates is the starting point of the oscillation operation has a thermal fluctuation. Randomly determined. Therefore, it is possible to avoid the oscillation operation starting from a specific NAND gate as a starting point as in the other ring oscillators 10-2 to 10-M. Thereby, a random value with high randomness can be taken out from the output of the D-FF 22 via the M input XOR 21.

  In the configuration of the first embodiment shown in FIG. 1, there is one ring oscillator composed of N NAND gates among the M ring oscillators constituting the random number generation circuit, and the remaining (M−1 ) Is a conventional ring oscillator, but as shown in FIG. 3, the number of ring oscillators composed of N NAND gates may be any number between 1 and M. Good. In the configuration of FIG. 3, since the present invention is applied to all ring oscillators (M1 = M, M2 = 0), the initial sampling immediately after the start of the circuit operation is less reproducible than the configuration of FIG. It is possible to generate a highly reliable intrinsic random number. The same applies to the embodiments described below.

Next, the random number effective display signal will be described.
In general, in a ring oscillator using one NAND gate, it is considered that an oscillation jitter component is not sufficiently accumulated immediately after the start of a self-oscillation operation and the effect of randomness is insufficient. Therefore, the control unit 100 counts the number of sampling clocks, and when the counter value reaches a certain number, the random number valid display signal is validated to obtain a random value with sufficient randomness from the D-FF. To do. The counter value for validating this random number valid display signal is determined as an empirical value from the actual evaluation result. For example, the first 100 bits are discarded and valid from the 101st bit.

  On the other hand, the random number generation circuit of the present invention using a ring oscillator composed of N NAND gates, in principle, needs to discard only the first value set in the D-FF when the circuit operation is ON. It is also possible to omit the valid display signal. However, in an actual circuit, it is difficult to completely randomize from the first generated bit because an unbalance between the driving power of the NAND gate and the wiring length cannot be avoided. Therefore, the random number valid display signal may be validated at a predetermined timing. However, even in such a case, the timing for validating the random number valid display signal can be set to be, for example, from the fifth bit earlier than the 101st bit.

FIG. 4 shows a configuration example of a random number generation circuit according to the second embodiment of the present invention.
4, in the second embodiment, the operation ON / OFF control signal of the first embodiment shown in FIG. 1 or FIG. 3 is inverted by an inverter 31 instead of the buffer 11 that distributes to each NAND gate of the ring oscillator 10-1. This is a configuration using an AND circuit 12 that distributes a logical product output of a sampling clock and an operation ON / OFF control signal to each NAND gate.

  As a result, when the operation ON / OFF control signal is Low or the sampling clock is High, the NAND gate output of the ring oscillator 10-1 is fixed to High, and the operation ON / OFF control signal is High and the sampling clock is Low. Start operation. At this time, the oscillation operation starts from any NAND gate determined at random instead of a specific NAND gate. Therefore, not only can random random numbers without reproducibility be generated immediately after the start of operation, but also the configuration of this embodiment generates a random random number that has no correlation with the generated random numbers around one clock because a reset operation is performed every clock. be able to.

FIG. 5 shows a configuration example of a random number generation circuit according to the third embodiment of the present invention.
In FIG. 5, when at least one of the M ring oscillators 10-1 to 10-M is configured with N NAND gates as in the first embodiment, the intermediate node output of each ring oscillator Are respectively latched by the preceding D-FFs 23-1 to 23-M synchronized with the sampling clock. Further, each output of the front stage D-FFs 23-1 to 23-M is input to the M input XOR 21 and the output thereof is input to the rear stage D-FF 24. The rear stage D-FF 24 latches the output of the M input XOR 21 by a sampling clock synchronized with the front stage D-FFs 23-1 to 23-M, and outputs it as a random value. The basic operation is the same as in the first embodiment.

FIG. 6 shows a configuration example of a random number generation circuit according to the fourth embodiment of the present invention.
In FIG. 6, the fourth embodiment has a sampling clock inverted by an inverter 31 instead of the buffer 11 that distributes the operation ON / OFF control signal of the third embodiment shown in FIG. 5 to each NAND gate of the ring oscillator 10-1. This is a configuration using an AND circuit 12 that distributes the logical product output of the operation ON / OFF control signal to each NAND gate.

  As a result, when the operation ON / OFF control signal is Low or the sampling clock is High, the NAND gate output of the ring oscillator 10-1 is fixed to High, and the operation ON / OFF control signal is High and the sampling clock is Low. Start operation. At this time, the oscillation operation starts from any NAND gate determined at random instead of a specific NAND gate. Therefore, not only can random random numbers without reproducibility be generated immediately after the start of operation, but also the configuration of this embodiment generates a random random number that has no correlation with the generated random numbers around one clock because a reset operation is performed every clock. be able to.

  FIG. 7 shows a configuration example of a random number generation circuit according to the fifth embodiment of the present invention. In this embodiment, the circuit of the third embodiment is serialized.

  In FIG. 7, as in the first and third embodiments, the intermediate node output of the ring oscillator 10 composed of N NAND gates is latched by the preceding stage D-FF 23-1 synchronized with the sampling clock of the frequency S. Further, the output selected by the selector 26 between the output of the previous stage D-FF 23-1 and the output of the 2-input XOR 25 is latched by the previous stage D-FF 23-2 synchronized with the sampling clock of the frequency S. The 2-input XOR 25 inputs the output of the previous stage D-FF 23-1 and the output of the previous stage D-FF 23-2, and outputs the XOR output to the selector 26. Further, the output of the front stage D-FF 23-2 is input to the rear stage D-FF 24. The rear stage D-FF 24 latches the output of the front stage D-FF 23-2 with an output clock having a frequency S / M obtained by dividing the sampling clock having the frequency S by M, and outputs the result as a random value.

  The control unit 200 receives an operation ON / OFF control signal and a system clock, divides the system clock, provides a sampling clock to the preceding D-FFs 23-1 and 23-2, a selector control signal to be supplied to the selector 26, and a subsequent D An output clock to be supplied to the FF 24 and a random number valid display signal are generated.

FIG. 8 illustrates an operation example of the control unit 200 according to the fifth embodiment.
A sampling clock generated by dividing the system clock by 4 when the operation ON / OFF control signal is High is supplied to the preceding D-FFs 23-1 and 23-2. Further, when the operation ON / OFF control signal is High, a selector control signal and an output clock are generated from the sampling clock. The selector control signal for controlling the selector 26 selects the latch output of the preceding stage D-FF 23-1 at a frequency of once every M sampling clocks, and (M-1) times the latch output of the preceding stage D-FF 23-1. And the XOR output of the latch output of the preceding stage D-FF 23-2. This is equivalent to latching the outputs for each sampling of the M ring oscillators 10-1 to 10-M of the third embodiment by the preceding stage D-FFs 23-1 to 23-M and inputting them to the M input XOR21. is there. The output clock is a clock having a frequency S / M obtained by dividing the sampling clock having the frequency S by M. The subsequent stage D-FF 22 latches the output of the previous stage D-FF 23-2 with this output clock and outputs it as a random value.

  As described above, when M sampling clocks of the frequency S have elapsed, a circuit equivalent to the configuration for obtaining the XOR output of the intermediate nodes of the M ring oscillators 10-1 to 10-M shown in the third embodiment is a serial circuit. Realized. The random number valid display signal may be configured to be valid at a predetermined timing, as described in the first embodiment.

FIG. 9 shows a configuration example of a random number generation circuit according to the sixth embodiment of the present invention.
In FIG. 9, in the sixth embodiment, instead of the buffer 11 that distributes the operation ON / OFF control signal of the fifth embodiment shown in FIG. 7 to each NAND gate of the ring oscillator 10, the sampling clock inverted by the inverter 31 and the operation ON The AND circuit 12 distributes the logical product output of the / OFF control signal to each NAND gate.

  As a result, when the operation ON / OFF control signal is Low or the sampling clock is High, the NAND gate output of the ring oscillator 10 is fixed to High, and the oscillation operation is performed when the operation ON / OFF control signal is High and the sampling clock is Low. Start. At this time, the oscillation operation starts from any NAND gate determined at random instead of a specific NAND gate. Therefore, not only can random random numbers without reproducibility be generated immediately after the start of operation, but also the configuration of this embodiment generates a random random number that has no correlation with the generated random numbers around one clock because a reset operation is performed every clock. be able to.

10 Ring oscillator 11 Buffer 12 AND circuit 21 M input XOR
22 D-FF
23 First stage D-FF
24 latter stage D-FF
25 2-input XOR
26 Selector 31 Inverter 100, 200 Control unit

Claims (8)

In a random number generation circuit that generates a random number using the output of one or more ring oscillators,
At least one ring oscillator is composed of an odd number of logic gates having one input connected to the output of another logic gate, and the inverter operation of the logic gate is turned ON or OFF at the other input of each logic gate. An operation ON / OFF control signal is connected, an inverter is connected to the output of each logic gate, and one of the outputs of the inverter is used as an output of the ring oscillator. M1 (M1 is an integer of 1 or more) first ring oscillators composed of odd-numbered logic gates, one input of which is connected to the output of the other logic gate;
M2 (M2 is an integer greater than or equal to 0, M1 + M2 is an integer greater than or equal to 2) second ring oscillator configured with an even number of stages of inverters and one stage of logic gates;
(M1 + M2) input XOR for exclusive-ORing the intermediate node output of the first ring oscillator and the intermediate node output of the second ring oscillator;
D-FF which latches the output of the (M1 + M2) input XOR with a sampling clock and outputs it as a random value;
A control unit for generating the sampling clock,
An operation ON / OFF control signal for turning ON or OFF the inverter operation of the logic gate is connected to the other input of each logic gate constituting the first ring oscillator,
An inverter is connected to the output of each logic gate that constitutes the first ring oscillator,
A random number generation circuit, characterized in that any one output of the inverter is used as an intermediate node output of the ring oscillator. M1 (M1 is an integer of 1 or more) first ring oscillators composed of odd-numbered logic gates, one input of which is connected to the output of the other logic gate;
A second ring oscillator of M2 (M2 is an integer greater than or equal to 0 and M1 + M2 is an integer greater than or equal to 2) composed of an even number of inverters and one logic gate;
(M1 + M2) input XOR for exclusive-ORing the intermediate node output of the first ring oscillator and the intermediate node output of the second ring oscillator;
D-FF which latches the output of the (M1 + M2) input XOR with a sampling clock and outputs it as a random value;
A control unit for generating the sampling clock,
An AND output of an operation ON / OFF control signal for turning the inverter operation of the logic gate ON or OFF and an inverted signal of the sampling clock is connected to the other input of each logic gate constituting the first ring oscillator. ,
An inverter is connected to the output of each logic gate that constitutes the first ring oscillator,
A random number generation circuit, characterized in that any one output of the inverter is used as an intermediate node output of the ring oscillator. M1 (M1 is an integer of 1 or more) first ring oscillators composed of odd-numbered logic gates, one input of which is connected to the output of the other logic gate;
A second ring oscillator of M2 (M2 is an integer greater than or equal to 0 and M1 + M2 is an integer greater than or equal to 2) composed of an even number of inverters and one logic gate;
(M1 + M2) preceding stage D-FFs that latch the intermediate node output of the first ring oscillator and the intermediate node output of the second ring oscillator, respectively, with a sampling clock;
(M1 + M2) input XOR for taking the exclusive OR of the latch outputs of the (M1 + M2) previous stage D-FFs;
A subsequent stage D-FF that latches the output of the (M1 + M2) input XOR with the sampling clock and outputs it as a random value;
A control unit for generating the sampling clock,
An operation ON / OFF control signal for turning ON or OFF the inverter operation of the logic gate is connected to the other input of each logic gate constituting the first ring oscillator,
An inverter is connected to the output of each logic gate that constitutes the first ring oscillator,
A random number generation circuit, characterized in that any one output of the inverter is used as an intermediate node output of the ring oscillator. M1 (M1 is an integer of 1 or more) first ring oscillators composed of odd-numbered logic gates, one input of which is connected to the output of the other logic gate;
A second ring oscillator of M2 (M2 is an integer greater than or equal to 0 and M1 + M2 is an integer greater than or equal to 2) composed of an even number of inverters and one logic gate;
(M1 + M2) preceding stage D-FFs that latch the intermediate node output of the first ring oscillator and the intermediate node output of the second ring oscillator, respectively, with a sampling clock;
(M1 + M2) input XOR for taking the exclusive OR of the latch outputs of the (M1 + M2) previous stage D-FFs;
A subsequent stage D-FF that latches the output of the (M1 + M2) input XOR with the sampling clock and outputs it as a random value;
A control unit for generating the sampling clock,
An AND output of an operation ON / OFF control signal for turning the inverter operation of the logic gate ON or OFF and an inverted signal of the sampling clock is connected to the other input of each logic gate constituting the first ring oscillator. ,
An inverter is connected to the output of each logic gate that constitutes the first ring oscillator,
A random number generation circuit, characterized in that any one output of the inverter is used as an intermediate node output of the ring oscillator. A ring oscillator composed of an odd number of logic gates with one input connected to the output of the other logic gate;
A first pre-stage D-FF that latches an intermediate node output of the ring oscillator with a sampling clock having a frequency S;
A second preceding stage D-FF that latches an input signal with a sampling clock of frequency S;
A two-input XOR that performs an exclusive OR of the latch output of the second previous stage D-FF and the latch output of the first previous stage D-FF;
According to the selector control signal, the output of the first preceding D-FF is selected once every M times of the sampling clock (M is an integer of 2 or more), and (M-1) times of the sampling clock. A selector for selecting an output of the two-input XOR and inputting the output to the second previous stage D-FF;
A second stage D-FF that latches an output of the second front stage D-FF with an output clock having a frequency S / M obtained by dividing the sampling clock of the frequency S by M;
A control unit for generating a sampling clock of the frequency S, the selector control signal, and an output clock of the frequency S / M;
An operation ON / OFF control signal for turning on or off the inverter operation of the logic gate is connected to the other input of each logic gate constituting the ring oscillator,
An inverter is connected to the output of each logic gate that constitutes the ring oscillator,
A random number generation circuit, characterized in that any one output of the inverter is used as an intermediate node output of the ring oscillator. A ring oscillator composed of an odd number of logic gates with one input connected to the output of the other logic gate;
A first pre-stage D-FF that latches an intermediate node output of the ring oscillator with a sampling clock having a frequency S;
A second preceding stage D-FF that latches an input signal with a sampling clock of frequency S;
A two-input XOR that performs an exclusive OR of the latch output of the second previous stage D-FF and the latch output of the first previous stage D-FF;
According to the selector control signal, the output of the first preceding D-FF is selected once every M times of the sampling clock (M is an integer of 2 or more), and (M-1) times of the sampling clock. A selector for selecting an output of the two-input XOR and inputting the output to the second previous stage D-FF;
A second stage D-FF that latches an output of the second front stage D-FF with an output clock having a frequency S / M obtained by dividing the sampling clock of the frequency S by M;
A control unit for generating a sampling clock of the frequency S, the selector control signal, and an output clock of the frequency S / M;
Connected to the other input of each logic gate constituting the ring oscillator is an AND output of an operation ON / OFF control signal for turning ON or OFF the inverter operation of the logic gate and an inverted signal of the sampling clock of the frequency S. ,
An inverter is connected to the output of each logic gate that constitutes the ring oscillator,
A random number generation circuit, characterized in that any one output of the inverter is used as an intermediate node output of the ring oscillator. In the random number generation circuit according to any one of claims 1 to 7,
The random number generation circuit, wherein the logic gate is a NAND gate or a NOR gate.

Images