JP2012129221A - Ebg structure and substrate - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an EBG structure capable of obtaining bandgap characteristics in a low frequency band and capable of being reduced in size, and a substrate including the EBG structure.SOLUTION: An EBG structure shown in one embodiment of the present invention comprises: a conductor layer 101; a conductor layer 102 forming the conductor layer 101 and a capacitance; and a conductor layer 103 connected to the conductor layer 102 via a via 104a. The conductor layer 103 comprises conductor plates 113a, 113b, 113c and 113d, and the conductor plates 113a, 113b, 113c and 113d are connected to the via 104a via conductor wires 105a, 105b, 105c and 105d, respectively, so that bandgap characteristics in a low frequency band can be obtained.

Description

  The present invention relates to an EBG structure that suppresses noise propagation on a substrate, and a substrate including the same.

  In recent years, electronic devices and mobile communication devices with built-in antennas and tuners that receive video signals have been researched and developed for downsizing for convenience of installation and carrying. In these electronic devices, a plurality of electronic circuits such as analog circuits and digital circuits are mounted on the same substrate in order to realize various functions. The plurality of electronic circuits on the substrate have different operating frequencies, and electromagnetic interference between the electronic circuits due to unnecessary electromagnetic radiation generated from the plurality of electronic circuits occurs. Since electromagnetic interference propagates to the signal input unit as noise and interferes with reception of signals in the reception frequency band, measures to suppress noise propagation are necessary.

  Therefore, as one of noise countermeasure methods related to unnecessary electromagnetic radiation, a countermeasure by an electromagnetic band gap structure (EBG: Electromagnetic Band Gap, hereinafter referred to as “EBG structure”) is attracting attention. By using the EBG structure, it is possible to obtain characteristics (band gap characteristics) that suppress electromagnetic waves and currents of a specific frequency that propagate as noise, and therefore are expected to be applied as unnecessary noise suppression filters on main boards and IC package boards. .

  FIG. 22 is a cross-sectional view of a conventional EBG structure. Here, the unit structures 1a, 2a, and 3a are illustrated, and the unit structure 2a and the unit structure 3a have the same configuration as the unit structure 1a, and thus description thereof is omitted. The unit structure 1 a includes a conductor layer 2, a conductor layer 3 parallel to the conductor layer 2, a conductor plate 4 a that forms a capacitance component C with the conductor layer 2, and a via 5 a that connects the conductor plate 4 a and the conductor layer 3. . By arranging the unit structures one-dimensionally or two-dimensionally, an inductance component L is formed in a current path including via 5a → conductor layer 3 → via 5b between two adjacent unit structures 1a and 1b. An LC resonance circuit is formed from the inductance component L and the capacitance component C, and a band gap is generated in the vicinity of the resonance frequency. That is, by controlling the inductance component L and the capacitance component C, it is possible to suppress noise propagation at a desired frequency. It is known that the inductance component L and the capacitance component C need to be increased in order to obtain a band gap characteristic in a low frequency band necessary for recent digital equipment. In order to increase the inductance component L, it is known to lengthen the path for forming the inductance component L. To increase the capacitance component C, the area of the conductor plate that forms the capacitance component C is reduced. It is known to increase.

  For example, in Patent Document 1, a hole is formed in a conductor layer, one end of a via is disposed in the hole, and the conductor layer and the via are connected by a metal wire, thereby increasing the current path of the inductance. A technique for increasing the component L is disclosed.

JP 2009-4791 A

  However, since Patent Document 1 extends a metal wire in a hole, there is a limit to the length that can be extended, and in order to obtain a band gap characteristic in a low frequency band (100 MHz to 1 GHz), as in the prior art. In order to increase the inductance component L, it is necessary to widen the interval between vias, and as a result, the EBG structure becomes large.

  The present invention has been made to solve the above problems, and an object of the present invention is to provide an EBG structure and a substrate that can obtain a band gap characteristic in a low frequency band and can be miniaturized. is there.

  In order to solve the above problems, an EBG structure according to the present invention includes a first conductor layer and a second conductor layer connected to the first conductor layer via a first via, and the second conductor layer. The conductor layer is composed of a plurality of first conductor patterns, and the first conductor pattern and the first via are connected through a first connection pattern.

  According to the above configuration, the band gap characteristic is obtained by having the capacitance portion including the first conductor layer and the inductance portion including the second conductor layer, and the second conductor layer is configured by a plurality of first conductor patterns. By connecting the first conductor pattern and the first via with the first connection pattern, a large inductance component L can be obtained by lengthening the current path of the inductance section. There is an effect to change.

  The EBG structure according to the present invention preferably has a third conductor layer that forms a capacitance with the first conductor layer.

  According to the above configuration, since the large capacitance component C can be obtained by having the third conductor layer facing the first conductor layer with the dielectric layer in between, the effect of lowering the band gap characteristic can be achieved.

  The EBG structure according to the present invention has a fourth conductor layer that forms a capacitance with the second conductor layer, and the fourth conductor layer and the third conductor layer are connected via a second via. preferable.

  According to the above configuration, the EBG has the first capacitance portion formed from the first conductor layer and the third conductor layer, and the second capacitance portion formed from the second conductor layer and the fourth conductor layer. There is an effect of reducing the mounting area of the structure.

  Preferably, the third conductor layer includes a plurality of second conductor patterns, and the second conductor pattern and the second via are connected via a second connection pattern.

  According to the above configuration, the first inductance portion including the first conductor pattern and the first connection pattern, and the second inductance portion including the second conductor pattern and the second connection pattern are provided, and are larger than the two inductance portions. Since the inductance component L can be obtained, there is an effect of lowering the band gap characteristics.

  Preferably, the first connection pattern surrounds a part of at least one of the first conductor patterns.

  According to the above configuration, since the large inductance component L can be obtained by extending the first connection pattern so as to surround a part of the first conductor pattern, the effect of lowering the band gap characteristic can be obtained. Play.

  Preferably, the first conductor pattern has a notch, and a part of the first connection pattern is disposed in the notch.

  According to the above configuration, the first conductor pattern has a notch, and by using the notch to extend the first connection pattern, a large inductance component L can be obtained. There is an effect of frequency.

  It is preferable that the plurality of conductor patterns constituting the first conductor layer and the plurality of conductor patterns constituting the fourth conductor layer are arranged so as to partially overlap in the thickness direction.

  According to the above configuration, the first capacitance portion formed from the conductor pattern and the second conductor pattern constituting the first conductor layer, and the conductor pattern and the first conductor pattern constituting the fourth conductor layer are formed. Since the second capacitance portion is arranged so as to overlap in the thickness direction, the mounting area of the EBG structure is reduced.

  The first connection pattern is preferably arranged so as not to overlap with a plurality of conductor patterns constituting the fourth conductor layer in the thickness direction.

  According to the above configuration, a large inductance component L can be obtained by preventing the magnetic field generated in the first connection pattern from being attenuated by the current flowing in the conductor pattern constituting the fourth conductor layer. There is an effect of reducing the frequency of the gap characteristic.

  The area in which one of the plurality of conductor patterns constituting the fourth conductor layer and one of the plurality of first conductor patterns overlap in the thickness direction is the plurality of conductor patterns constituting the fourth conductor layer. Is preferably equal to the area of one of these.

  According to the above configuration, by increasing the area in which the first conductor pattern and the conductor pattern constituting the fourth conductor layer overlap in the thickness direction, a large capacitance component C can be obtained, and the band gap characteristics can be reduced. There is an effect to change.

  In the substrate according to the present invention, it is preferable that the above-described EBG structure is periodically arranged at least partly around the electronic circuit.

  According to the above configuration, the malfunction of the electronic circuit due to the influence of noise can be prevented by arranging the EBG structure in the noise propagation path.

  ADVANTAGE OF THE INVENTION According to this invention, the band gap characteristic of a low frequency band can be obtained, and the EBG structure which can be reduced in size, and a board | substrate using the same can be provided.

It is a perspective view of a unit structure of an EBG structure for explaining Example 1 of the present invention. It is sectional drawing of the EBG structure for demonstrating Example 1 of this invention. It is a top view of the EBG structure for demonstrating Example 1 of this invention. It is a top view of the EBG structure for demonstrating the other example of a conductor wire. It is explanatory drawing for demonstrating the inductance part of Example 1 of this invention. 6 is a plan view of an EBG structure for explaining another example of a conductor layer 103. FIG. It is the simulation result which analyzed the characteristic of the EBG structure of Example 1 of this invention. It is sectional drawing of the EBG structure for demonstrating Example 2 of this invention. It is a top view of the EBG structure for demonstrating Example 2 of this invention. It is a perspective view of the EBG structure for demonstrating Example 2 of this invention. It is explanatory drawing for demonstrating the capacitance part of Example 2 of this invention. (A) is sectional drawing of the EBG structure of Example 2, (b) is a top view of the EBG structure of Example 2. FIG. It is a top view of the EBG structure for demonstrating the form which the conductor plate 214 has a notch. It is sectional drawing of the EBG structure for demonstrating Example 3 of this invention. It is a top view of the EBG structure for demonstrating Example 3 of this invention. It is a perspective view of the EBG structure for demonstrating Example 3 of this invention. It is sectional drawing of the EBG structure for comparing a characteristic with the EBG structure of Example 3 of this invention. It is a simulation result for confirming the characteristic of the EBG structure of Example 3 of the present invention. (A) is the simulation result which analyzed the characteristic of the EBG structure of Example 3, (b) is the simulation result which analyzed the characteristic of the EBG structure of FIG. It is sectional drawing of the EBG structure for performing comparison with the suitable EBG structure of Example 3 of this invention. It is a simulation result for confirming the characteristic of the suitable EBG structure of Example 3 of this invention. (A) is the simulation result which analyzed the characteristic of the suitable EBG structure of Example 3, (b) is the simulation result which analyzed the characteristic of the EBG structure of FIG. It is sectional drawing of the main board | substrate for demonstrating Example 4 of this invention. It is sectional drawing of the package board | substrate and main board | substrate for demonstrating Example 4 of this invention. It is sectional drawing of the EBG structure of a prior art. It is explanatory drawing for demonstrating the inductance part of the EBG structure of a prior art. It is explanatory drawing for demonstrating the capacitance part of the EBG structure of a prior art. (A) is sectional drawing of a prior art EBG structure, (b) is a top view of a prior art EBG structure. It is the simulation result which analyzed the characteristic of the EBG structure of a prior art.

  Embodiment 1 of the present invention will be described below with reference to FIGS. FIG. 1 is a perspective view of a unit structure of the EBG structure of this embodiment. The unit structure 100a includes a conductor layer 101, a conductor layer 102 that forms a capacitance with the conductor layer 101, and a conductor layer 103 connected to the conductor layer 102 via a via 104a. Here, the conductor layer 103 includes conductor plates 113a, 113b, 113c, and 113d, and the conductor plates 113a, 113b, 113c, and 113d and the via 104a are connected to each other through conductor wires 105a, 105b, 105c, and 105d. Yes. In the EBG structure of the present embodiment, unit structures having the same configuration as the unit structure 100a are arranged one-dimensionally or two-dimensionally. Here, a plane parallel to the substrate is defined as an xy plane, a thickness direction of the substrate, that is, a direction perpendicular to the xy plane is defined as a z-axis direction, and a positive z-axis direction is defined as an upward direction on the substrate. Here, the conductor line 105a and the conductor line 105c are arranged on a straight line parallel to the x-axis, and the conductor line 105b and the conductor line 105d are arranged on a straight line parallel to the y-axis.

  FIG. 2 is a cross-sectional view of the EBG structure of the present embodiment cut along the xz plane. Here, the unit structures 100a, 100b, and 100c including the unit structure 100a of FIG. 1 are illustrated, and the unit structure 100b and the unit structure 100c have the same configuration as the unit structure 100a, and thus description thereof is omitted. The conductor layer 102 is composed of conductor plates 112a, 112b,... (Hereinafter referred to as conductor plate 112), and the conductor layer 103 is provided as conductor plates 113a, 113b,. .) (Hereinafter referred to as the conductor line 105), via lands 106a, 106b,... (Hereinafter referred to as the via land 106). One end of each of the vias 104 a, 104 b,... (Hereinafter referred to as the via 104) is connected to the conductor plate 112, and the other end is connected to the via land 106. The conductor line 105 connects the via land 106 and the conductor plate 113. A dielectric layer 114 is provided between the conductor layer 101 and the conductor layer 102, and a dielectric layer 115 is provided between the conductor layer 102 and the conductor layer 103. The capacitance part is formed by the conductor layer 101 and the conductor plate 112 facing each other with the dielectric layer 114 interposed therebetween.

  A method for forming the EBG structure of the present embodiment is as follows. First, the conductor plate 112 is formed as the conductor layer 102 on the dielectric layer 115. Next, the via 104 that penetrates the dielectric layer 115 and is connected to the conductor plate 112 is formed. Next, the conductor plate 113, the conductor wire 105, and the via land 106 are formed as the conductor layer 103 below the dielectric layer 115. Finally, the dielectric layer 114 and the conductor layer 101 are laminated on the conductor layer 102.

  Here, the conductor plate 112, the conductor plate 113, the conductor wire 105, and the via land 106 can be formed by using a general substrate manufacturing method such as masking, exposure, etching, and development. The via 104 is formed by filling the conductive layer or plating the inner wall after the dielectric layer 115 is drilled by laser processing or the like. When the inner wall is plated, the central portion may be filled with a dielectric material or air.

  The method for forming the EBG structure is an example, and the present invention is not limited to this. For example, after the configuration other than the via 104 is formed in the same manner as described above, the via 104 may be formed by drilling all layers from the conductor layer 101 to the conductor layer 103 by drilling or the like. However, in this case, it is necessary to provide a clearance around the via 104 on the conductor layer 101 so that the conductor layer 101 and the via 104 are not connected.

  FIG. 3 is a plan view of an EBG structure for explaining the conductor layer 103 of the present embodiment. Via land 106 is disposed between a plurality of conductor plates, and is connected to a conductor plate disposed around via conductor line 105. For example, the via land 106a is disposed between the conductor plates 113a, 113b, 113c, and 113d, and the conductor plates 113a, 113b, 113c, and 113d are connected to the via land 106a through the conductor wires 105a, 105b, 105c, and 105d, respectively. The conductor line 105 may be a straight line as shown in FIG. 3, but may be a curved line or a broken line. For example, the conductor wire 105a may be connected after extending along one side of the conductor plate 113a as shown in FIG. 4A, or the conductor wire 105a may be connected to the conductor plate 113a as shown in FIG. 4B. The conductor wire 105a may be connected to the other side of the conductor plate 113a while surrounding one side. The conductor wire 105a may go around the conductor plate 113a one or more times. The same applies to the other conductor lines 105b, 105c,. Further, instead of connecting one conductor plate 113a to the via land 106a by one conductor line 105a, for example, the conductor line 105a and the conductor line 105b are configured by one conductor line, and the conductor plate 113a and the conductor are formed by the conductor lines. The plate 113b may be connected to the via land 106a.

  The inductance part of the EBG structure of this embodiment is compared with the inductance part of the conventional EBG structure with reference to FIGS. FIG. 5 is a plan view of an EBG structure for explaining the inductance portion of the present embodiment. In the EBG structure of this embodiment, one end of the via 104a is connected to the via land 106a, one end of the via 104d is connected to the via land 106d, and the inductance portion is the via 104a → the via land 106a → the conductor line 105a → the conductor plate 113a → the conductor line 105m → It is formed by a current path including via land 106d → via 104d. By the inductance part and the capacitance part described above, the EBG structure of this embodiment functions as an LC resonance circuit, and a band gap characteristic is obtained. A part of the inductance part of the EBG structure of the present embodiment is formed in the region 121.

FIG. 23 is a plan view of the EBG structure for explaining the inductance part of the prior art. In the EBG structure of the prior art, one end of the via 5a and the via 5b is connected to the conductor layer 3, and the inductance part is the via 5a → conductor layer. 3 → formed by a current path including the via 5b. That is, a part of the inductance portion of the conventional EBG structure is formed in the region 122, and the length of the region 122 is the shortest distance between the two adjacent vias 5a and 5b. As shown in FIG. 5, since the length of the region 121 can be larger than the shortest distance between two adjacent via lands 106a and 106d, the length of the via 104a and the via 104d of the present embodiment and the prior art via 5a and via 5b When the lengths are equal and the distance between the vias 104a and 104d is equal to the distance between the vias 5a and 5d, the current path of the inductance portion can be made longer in the present embodiment than in the prior art. Further, in the present embodiment, by extending the lengths of the conductor wire 105a and the conductor wire 105m, the current path of the inductance portion can be further lengthened. Therefore, by obtaining a large inductance component L, a low frequency band is obtained. Gap characteristics can be obtained.

  FIG. 6 is a diagram for explaining another example of the conductor layer 103 of the present embodiment. For example, all the conductor plates 113a, 113b, 113c, and 113d arranged around the via land 106a may not be connected to the via land 106a using the conductor wires 105a, 105b, 105c, and 105d. That is, as shown in FIG. 6A, the conductor plates 113a, 113b, and 113d are connected to the via land 106a via the conductor lines 105a, 105b, and 105d, and the conductor line 105c may be omitted. However, the conductor plate 113c is connected to the via land 106a through the conductor line 105r, the via land 106e, the conductor line 105o, the conductor plate 113b, and the conductor line 105b. Further, the via land 106a may not be disposed between the four conductor plates 113a, 113b, 113c, and 113d. Up to this point, the unit structure has been arranged two-dimensionally. However, for example, as shown in FIG. 6B, the unit structure is arranged one-dimensionally, and the via land 106a includes two conductor plates 113a and 113d. You may arrange | position between. The form of the conductor plate 113, the conductor wire 105, and the via land 106 constituting the conductor layer 103 is not limited to this. If the via land 106a is connected to two conductor plates and conductor lines, the unit structure can be arranged one-dimensionally. If the via land 106a is connected to three or more conductor plates and conductor wires, the unit structure can be two-dimensionally arranged. Can be arranged. Conductor plates other than the conductor plates 113a, 113b, 113c, and 113d arranged around the via land 106a may be connected to the via land 106a by a conductor line, and the current paths between adjacent via lands are connected periodically. As long as the conductor wire 105 is arranged so that all the conductor plates 113 constituting the conductor layer 103 and the via land 106 are connected, any form may be used.

  The characteristics of the EBG structure of this embodiment are compared with those of the conventional EBG structure with reference to FIGS. FIG. 7 is a graph showing a simulation result obtained by analyzing the characteristics of the EBG structure of the present embodiment, and FIG. 25 is a graph showing a simulation result obtained by analyzing the characteristics of the EBG structure of the prior art. Here, the X axis represents frequency (GHz) and the Y axis represents attenuation (dB). When the range of frequencies where the absolute value of the attenuation is 40 dB or more is set as the band gap range, and the lower limit frequency of the band gap is confirmed, the lower limit frequency 123 of FIG. 7 is 1.0 GHz, and the lower limit frequency 124 of FIG. Thus, it can be confirmed that the EBG structure of the present embodiment can obtain a low-frequency band gap characteristic. That is, in this embodiment, since the large inductance component L is obtained by configuring the conductor layer 103 with the conductor plate 113 and the conductor wire 105, it can be confirmed that a band gap characteristic in a low frequency band can be obtained.

  In this embodiment, the conductor layer 103 includes the conductor line 105 and the via land 106, but the conductor layer 103 may not include at least one of the conductor line 105 and the via land 106. For example, the via land 106 may be disposed between the conductor layer 102 and the conductor layer 103 or below the conductor layer 103, and the conductor wire 105 may be extended in the same layer as the via land 106. Further, a conductor wire 105 is disposed in a layer between the conductor layer 102 and the conductor layer 103, and one end of the conductor wire 105 is connected to the via 104, and the other end is connected to the conductor plate 113 through a via formed separately. Good.

  In the present embodiment, the conductor layer 101 is disposed above the conductor layer 102, but the conductor layer 101 may be disposed below the conductor layer 102. In this case, the conductor layer 101 is provided with a clearance, and the via 104 is disposed in the clearance so as not to contact the conductor layer 101.

  In this embodiment, one end of the via 104 is connected to the via land 106, and the via land 106 is connected to the conductor plate 113 via the conductor wire 105. However, the via land 106 is not necessarily required. The conductor line 105 may be directly connected to the via 104.

  Although this embodiment has three layers of the conductor layer 101, the conductor layer 102, and the conductor layer 103, the conductor layer 101 is not necessarily required. When the conductor layer 101 is not provided, the capacitance portion is formed between two adjacent conductor plates in the conductor plate 112.

  Next, a second embodiment of the present invention will be described with reference to FIGS. Here, a plane parallel to the substrate is defined as an xy plane, a thickness direction of the substrate is defined as a z-axis direction, and a positive z-axis direction is defined as an upward direction on the substrate.

  FIG. 8 is a cross-sectional view in the xz plane of the EBG structure of this embodiment. Here, a part of the unit structure 200a, the unit structure 200b, and the unit structure 200c is illustrated. Since the unit structure 200b and the unit structure 200c have the same configuration as the unit structure 200a, the description thereof is omitted. The unit structure 200a includes a conductor layer 201, a conductor layer 202 that forms a capacitance with the conductor layer 201, a conductor layer 204 that is connected to the conductor layer 202 via a via 205a, and a conductor layer 204 that forms a capacitance with the conductor layer 204. 201 has a conductor layer 203 connected via a via 207a.

  The conductor layer 202 is composed of conductor plates 212a, 212b,... (Hereinafter referred to as a conductor plate 212), and the conductor plate 212 is referred to as vias 207a, 207b,. It is arranged not to touch. The conductor layer 204 includes conductor plates 214a, 214b,... (Hereinafter referred to as conductor plates 214), via lands 208a, 208b,... (Hereinafter referred to as via lands 208), conductor wires 206a, 206b,. ... (hereinafter referred to as conductor wire 206). One end of each of vias 205a, 205b,... (Hereinafter referred to as via 205) is connected to conductor plate 212, and the other end is connected to via land 208. The conductor plate 214 and the via land 208 are connected via a conductor line 206. The conductor layer 203 includes conductor plates 213a, 213b,... (Hereinafter referred to as a conductor plate 213), and the conductor plate 213 is disposed so as not to contact the via 205. In addition, the conductor plate 212 and the conductor plate 213 are disposed so as to partially overlap in the z-axis direction. For example, the conductor plate 212a is disposed so as to overlap a part of the conductor plate 213a and a part of the conductor plate 213b in the z-axis direction. Here, overlapping in the z-axis direction means not overlapping physically but overlapping when the substrate is viewed in the z-axis direction, and not overlapping in the z-axis direction means that the substrate is z This means that they do not overlap when viewed in the axial direction. One end of the via 207 is connected to the conductor plate 213, and the other end is connected to the conductor layer 201. A dielectric layer 215 is provided between the conductor layer 201 and the conductor layer 202, a dielectric layer 216 is provided between the conductor layer 202 and the conductor layer 203, and between the conductor layer 203 and the conductor layer 204. The layer is provided with a dielectric layer 217.

  The unit structure 200a forms a first capacitance portion from the conductor layer 201 and the conductor plate 212a that are opposed to each other with the dielectric layer 215 interposed therebetween, and includes the conductor plate 213a and the conductor plate 214a that are opposed to each other with the dielectric layer 217 interposed therebetween. In order to form the second capacitance portion, the two capacitance portions are formed to overlap each other. The conductor plate 212a is arranged so that a part of the conductor plate 213b included in the unit structure 200b overlaps in the z-axis direction, and the conductor plate 213a is partly connected to the conductor plate 212c included in the unit structure 200c in the z-axis direction. Arranged to overlap. That is, the unit structure 200a is disposed so as to overlap the unit structure 200b and the unit structure 200c.

  A method for forming the EBG structure of the present embodiment is as follows. First, the conductor plate 212 is formed as the conductor layer 202 on the dielectric layer 216. Next, a conductor plate 213 is formed as a conductor layer 203 below the dielectric layer 216. Next, a dielectric layer 215 is laminated on the conductor layer 202. Next, a via 207 that penetrates the dielectric layer 215 and the dielectric layer 216 and is connected to the conductor layer 203 is formed. Next, the conductor layer 201 is laminated on the upper layer of the dielectric layer 215. Next, a dielectric layer 217 is laminated below the conductor layer 203. Next, a via 205 that penetrates the dielectric layer 216 and the dielectric layer 217 and is connected to the conductor plate 212 is formed. Finally, the conductor plate 214, the conductor line 206, and the via land 208 are formed as the conductor layer 204 under the dielectric layer 217.

  Here, the conductor plate 212, the conductor plate 213, the conductor plate 214, the conductor wire 206, and the via land 208 can be formed using a general substrate manufacturing method such as masking, exposure, etching, and development. The vias 205 and 207 are formed by filling the dielectric layer 215, the dielectric layer 216, and the dielectric layer 217 with laser processing or the like and then filling the inner wall with a conductive material. When the inner wall is plated, the central portion may be filled with a dielectric material or air.

  The method for forming the EBG structure is an example, and the present invention is not limited to this. For example, the via 205 and the via 207 may be formed by drilling all the layers from the conductor layer 201 to the conductor layer 204 after forming the configuration other than the via 205 and the via 207 in the same manner as described above. . However, in this case, a clearance is provided around the via 205 on the conductor layer 201 so that the conductor layer 201 and the via 205 are not connected, and the via 207 on the conductor plate 214 is not connected so that the conductor plate 214 and the via 207 are not connected. It is necessary to provide clearance around

  FIG. 9 is a plan view of the EBG structure of the present embodiment, and FIG. 9A is a plan view for explaining the conductor layer 204 of FIG. Via land 208 is disposed between a plurality of conductor plates, and is connected to a conductor plate disposed around via conductor line 206. For example, the via land 208a is disposed between four conductor plates 214a, 214b, 214d, and 214e, and the conductor plates 214a, 214b, 214d, and 214e are connected to the via land 208a through conductor wires 206a, 206b, 206g, and 206h, respectively. The In the present embodiment, as in the first embodiment, for example, between the via land 208a and the via land 208e, a part of the inductance portion is formed by the current path of the conductor wire 206h → the conductor plate 214e → the conductor wire 206r. A large inductance component L can be obtained by lengthening the current path. The conductor wire 206 can take the same form as the conductor wire 105 of the first embodiment. For example, the conductor wire 206a may be extended so as to surround a part of the conductor plate 214a. Further, instead of connecting one conductor plate 214a to the via land 208a by one conductor line 206a, the conductor line 206a and the conductor line 206g are constituted by one conductor line, and the conductor lines 214a and 214d are formed by the conductor lines. May be connected to the via land 208a. The number of conductor plates arranged around the via land 208a or the number of conductor wires connected to the via land 208a may be changed to an arbitrary number, and the conductors are connected so that the current path between adjacent via lands is periodic. As long as the conductor wire 206 is arranged so that all the conductor plates 214 constituting the layer 204 and the via land 208 are connected, any form may be used.

  FIG. 9B is a plan view for explaining the conductor layer 203 of FIG. The conductor plate 213 is disposed so as not to contact the via 205. For example, the conductor plate 213b is disposed so as not to contact between the vias 205a, 205b, 205d, and 205e. The conductor plate 213a is disposed so as to overlap with the conductor plate 214a in the upper layer of 214a in order to form the second capacitance portion. The conductor wire 206 is disposed so as not to overlap the conductor plate 213 in the z-axis direction. For example, when the conductor wire 206a is arranged at a position overlapping the conductor plate 213a, the magnetic field generated in the conductor wire 206a is canceled by the current flowing through the conductor plate 213a, and the effect of increasing the inductance component L by the conductor wire 206a is weakened. . Therefore, the conductor wire 206a is preferably arranged so as not to overlap the conductor plate 213a.

  In order to obtain a large capacitance component C, it is necessary to increase the area where the conductor plate 213a and the conductor plate 214a overlap in the z-axis direction. Therefore, it is preferable that the area of the conductor plate 214a is at least equal to the area of the conductor plate 213a, and the area where the conductor plate 214a and the conductor plate 213a overlap in the z-axis direction is equal to the area of the conductor plate 213a. By arranging the conductor plate 213a and the conductor plate 214a in this way, the conductor wire 206a does not overlap with the conductor plate 213a in the z-axis direction regardless of the arrangement of the conductor layer 204, and the capacitance component C and the inductance component L can be generated efficiently.

  FIG. 10 is a perspective view of the EBG structure of this embodiment. As described above, the first capacitance portion is formed of the conductor layer 201 and the conductor plate 212a, and the second capacitance portion is formed of the conductor plate 213a and the conductor plate 214a. Further, between the adjacent unit structures, the first inductance portion is formed by a current path including the via 205a → the via land 208a → the conductor wire 206h → the conductor plate 214e → the conductor wire 206r → the via land 208e → the via 205e, and the second inductance is formed. The portion is formed by a current path including via 207a → conductor layer 201 → via 207e. Since the capacitance part and the inductance part function as an LC resonance circuit, band gap characteristics can be obtained.

  The effect of overlapping the unit structures will be described with reference to FIGS. 11 and 24. FIG. FIG. 24A is a diagram for explaining a capacitance portion of the conventional EBG structure, and is a cross-sectional view taken along the line B-B ′ in FIG. FIG. 24B is a plan view of the A-A ′ plane of FIG. 24A, and is a diagram for explaining an EBG structure when twelve capacitance portions are formed by the conventional technique. Capacitance portion 221.1 is formed of conductor layer 2 and conductor plate 4.01, capacitance portion 221.2 is formed of conductor layer 2 and conductor plate 4.02, and capacitance portion 221.3 is formed of conductor layer 2 and conductor plate. Formed from 4.03. In the EBG structure of the prior art, since the capacitance part is formed from the conductor layer 2 and the conductor plates 4.01, 4.02,..., 4.12, when 12 capacitance parts are formed, FIG. It is necessary to arrange 12 conductor plates on the same plane as shown in FIG.

  FIG. 11A is a diagram for explaining the capacitance part of the EBG structure of the present embodiment, and is a cross-sectional view taken along the line C-C ′ in FIG. FIG. 11B is a plan view of the conductor layer 202 of FIG. 11A, and is a diagram for explaining an EBG structure when twelve capacitance portions are formed in the present embodiment. However, the broken line of FIG.12 (b) represents the conductor plates 213.1, 213.2, ..., 213.6 of the conductor layer 203 of Fig.12 (a). Capacitance portion 222.1 is formed of conductor layer 201 and conductor plate 212.1, capacitance portion 222.2 is formed of conductor layer 201 and conductor plate 212.2, and capacitance portion 222.3 is formed of conductor plate 213.1. It is formed from conductor plate 214.1. In the EBG structure of this embodiment, six capacitance parts are formed from the conductor layer 201 and the conductor plates 212.1, 212.2, ..., 212.6, and the conductor plates 213.1, 213.2,. .. Are formed from the conductor plates 214.1, 214.2,..., 214.6 facing each other with the dielectric layer sandwiched between 213.6 and FIG. 6 conductor plates are arranged on the same plane as shown above, 6 conductor plates are arranged on another plane, and 12 capacitance parts are formed so that the conductor plates on each plane overlap in the z-axis direction. it can.

  Conductor plates 4.01, 4.02,..., 4.12, conductor plates 212.1, 212.2,..., 212.6, and conductors of FIG. When the plates 213.1, 213.2,..., 213.6 have the same area and the intervals between adjacent conductor plates are equal, the prior art EBG structure in which the conductor plates are arranged on the same plane In comparison, the EBG structure of the present embodiment in which the conductor plates can be arranged on two different planes so as to overlap each other in the z-axis direction can reduce the mounting area.

  FIG. 12 shows a plan view of the conductor layer 204 of the present embodiment, and is a diagram for explaining the case where the conductor plate 214 has a notch. FIG. 12A shows an example in which the conductor plate 214 has a notch in the center of the side. For example, the conductor plate 214a has a notch 209a, and a part of the conductor wire 206a is disposed in the notch 209a. Although the area of the conductor plate 214a is reduced by having the notch 209a, the width of the conductor wire 206a is small, and the width of the notch 209a is extremely small compared to the length of the conductor wire 206a extended by the notch 209a. Since the inductance component L obtained by extending the conductor wire 206a becomes larger than the capacitance component C reduced by having the notch 209a, the band gap characteristic can be reduced in frequency. The conductor plate 214a may not have the notch 209a at the center of the side, but may have at the end of the side as shown in FIG.

  In the present embodiment, the conductor layer 204 includes the conductor line 206 and the via land 208, but the conductor layer 204 may not include at least one of the conductor line 206 and the via land 208. For example, the via land 208 may be disposed between the conductor layer 203 and the conductor layer 204 or below the conductor layer 204, and the conductor wire 206 may be extended in the same layer as the via land 208. In addition, the conductor wire 206 is disposed in a layer between the conductor layer 203 and the conductor layer 204, and one end of the conductor wire 206 is connected to the via 205 and the other end is connected to the conductor plate 214 via a separately formed via. Good.

  In this embodiment, the conductor layer 201 is disposed on the upper layer of the conductor layer 202, but the conductor layer 201 may be disposed on the lower layer of the conductor layer 202. In this case, the conductor layer 201 is provided with a clearance, and the via 205 is disposed in the clearance so as not to contact the conductor layer 201. Further, although the conductor layer 203 is disposed on the upper layer of the conductor layer 204, the conductor layer 203 may be disposed on the lower layer of the conductor layer 204. In this case, the conductor plate 214 is provided with a clearance, and the via 207 is disposed in the clearance so as not to contact the conductor plate 214.

  In this embodiment, one end of the via 205 is connected to the via land 208, and the via land 208 is connected to the conductor plate 214 via the conductor line 206. However, the via land 208 is not necessarily required. The conductor line 214 may be directly connected to the via 205.

  The conductor plate 212, the conductor plate 213, and the conductor plate 214 may have the same shape, but may have different shapes or different areas. The lengths of the via 205 and the via 207 may be the same or different.

  Next, Embodiment 3 of the present invention will be described with reference to FIGS. Here, the same numbers are assigned to the same components as those in the second embodiment, and detailed description thereof is omitted. A plane parallel to the substrate is defined as an xy plane, a thickness direction of the substrate is defined as a z-axis direction, and a positive z-axis direction is defined as an upward direction on the substrate.

  FIG. 13 is a cross-sectional view in the xz plane of the EBG structure of Example 3 of the present invention. Here, the unit structure 300a, the unit structure 300b, and a part of the unit structure 300c are illustrated, and the unit structure 300b and the unit structure 300c have the same configuration as the unit structure 300a, and thus description thereof is omitted. The unit structure 300a includes a conductor layer 301, a conductor layer 202 that forms a capacitance with the conductor layer 301, a conductor layer 204 that is connected to the conductor layer 202 via a via 205a, and a conductor layer 204 that forms a capacitance with the conductor layer 204. 301 has a conductor layer 203 connected via via 207a.

  The conductor layer 301 includes conductor plates 311a, 311b,... (Hereinafter referred to as conductor plate 311), conductor wires 305a, 305b,... (Hereinafter referred to as conductor wires 305), and via lands 306a, 306b. ,... (Hereinafter referred to as via land 306). One end of the via 207 is connected to the conductor plate 213, and the other end is connected to the via land 306. The conductor plate 311 and the via land 306 are connected via a conductor line 305.

  The unit structure 300a forms a first capacitance portion from the conductor plate 311a and the conductor plate 212a that are opposed to each other with the dielectric layer 215 interposed therebetween, and is formed from the conductor plate 213a and the conductor plate 214a that are opposed to each other with the dielectric layer 217 interposed therebetween. A second capacitance portion is formed, and the two capacitance portions are formed so as to overlap each other. The conductor plate 212a is disposed so as to partially overlap the conductor plate 213b included in the unit structure 300b, and the conductor plate 213a is disposed so as to partially overlap the conductor plate 212c included in the unit structure 300c. That is, since the unit structure 300a is arranged so as to overlap the unit structure 300b and the unit structure 300c, the present embodiment can obtain the effect of reducing the mounting area of the EBG structure as in the second embodiment.

  The EBG structure of this embodiment can be formed by the same procedure as in Example 2. That is, in the step of laminating the conductor layer 201 of Example 2, the EBG structure of this embodiment can be formed by forming the conductor plate 311, the conductor wire 305, and the via land 306 as the conductor layer 301. Here, the conductor plate 311, the conductor wire 305, and the via land 306 can be formed using a general substrate manufacturing method such as masking, exposure, etching, and development.

  FIG. 14 is a plan view of the EBG structure of the present embodiment, and FIG. 14A is a plan view for explaining the conductor layer 301 of FIG. The via land 306 is disposed between the conductor plates 311 and is connected to a conductor plate disposed around through the conductor wire 305. For example, the via land 306a is disposed between the conductor plates 311a, 311c, 311g, and 311h, and the conductor plates 311a, 311c, 311g, and 311h are connected to the via land 306a via the conductor wires 305a, 305b, 305g, and 305h, respectively. In the present embodiment, as in the first embodiment, for example, between the via land 306a and the via land 306e, a part of the inductance portion is formed in the current path of the conductor wire 305b → the conductor plate 311a → the conductor wire 305o. By doing so, a large inductance component L can be obtained. The conductor wire 305 can take the same form as the conductor wire 206. For example, the conductor wire 305a may be extended so as to surround a part of the conductor plate 311c. Further, instead of connecting one conductor plate 311c to the via land 306a by one conductor line 305a, for example, the conductor wire 305a and the conductor line 305g are configured by one conductor line, and the conductor plate 311c and the conductor are formed by the conductor wires. The plate 311g may be connected to the via land 306a. Similar to the conductor plate 214a, the conductor plate 311a may have a notch in part. The number of conductor plates arranged around the via land 306a and the number of conductor wires connected to the via land 306a may be changed to an arbitrary number, and the conductors are connected so that the current path between adjacent via lands is periodic. As long as the conductor wire 305 is disposed so that all the conductor plates 311 constituting the layer 301 and the via land 306 are connected, any form may be used.

  FIG. 14B is a plan view for explaining the conductor layer 202 of FIG. The conductor plate 212 is disposed so as not to contact the via 207. For example, the conductor plate 212a is disposed so as not to contact between the vias 207a, 207b, 207d, and 207e. The conductor plate 212a is arranged so as to overlap with the conductor plate 311a in the lower layer of 311a in order to form the first capacitance portion. The conductor wire 305 is arranged so as not to overlap the conductor plate 212. For example, when the conductor wire 305a is arranged at a position overlapping the conductor plate 212c in the z-axis direction, the magnetic field generated in the conductor wire 305a is canceled by the current flowing through the conductor plate 212c, and the inductance component L due to the conductor wire 305a is increased. The effect is weakened. Therefore, the conductor wire 305a is preferably arranged so as not to overlap the conductor plate 212c in the z-axis direction.

  In order to obtain a large capacitance component C, it is necessary to increase the area where the conductor plate 311a and the conductor plate 212a overlap in the z-axis direction. Therefore, the area of the conductor plate 311a is preferably at least equal to the area of the conductor plate 212a, and the area where the conductor plate 311a and the conductor plate 212a overlap in the z-axis direction is preferably equal to the area of the conductor plate 212a. By arranging the conductor plate 311a and the conductor plate 212a in this manner, the conductor wire 305b does not overlap the conductor plate 212a regardless of the arrangement of the conductor layer 204, and the capacitance component C and the inductance component L can be efficiently obtained. Can be generated.

  FIG. 15 is a perspective view of the EBG structure of this embodiment. As described above, the first capacitance portion is formed of the conductor plate 311a and the conductor plate 212a, and the second capacitance portion is formed of the conductor plate 213a and the conductor plate 214a. Further, between the adjacent unit structures, the first inductance portion is formed by a current path including via 205a → conductor line 206h → conductor plate 214e → conductor line 206r → via 205e. Here, the via land to which the via 205a is connected and the via land to which the via 205e is connected are omitted. The second inductance portion is formed by a current path including via 207a → via land 306a → conductor line 305b → conductor plate 311a → conductor line 305o → via land 306e → via 207e. Since the capacitance part and the inductance part function as an LC resonance circuit, band gap characteristics can be obtained. In this embodiment, since the conductor layer 301 is composed of a plurality of conductor plates 311, the capacitance component C obtained from the second capacitance section is smaller than that in the second embodiment. However, since the inductance component L equal to or more than the reduction of the capacitance component C can be obtained from the second inductance portion including the conductor plate 311a and the conductor wires 305b and 305o, the band gap characteristic can be reduced in frequency.

  FIG. 16 is a cross-sectional view of an EBG structure for comparing characteristics with the EBG structure of the present embodiment. The conductor layer 301 of this embodiment is a conductor layer 201 of Example 2, and the conductor layer 204 of this embodiment is a conductor layer 307 similar to the conductor layer 201. The EBG structure of FIG. 16 has a first capacitance part including a conductor layer 201 and a conductor plate 212a, and a second capacitance part including a conductor plate 213a and a conductor layer 307, and these two capacitance parts are arranged vertically. The point arrange | positioned so that it may overlap is the same as that of this embodiment. However, the first and second inductance portions of the EBG structure in FIG. 16 do not include conductor wires, and the current path of these inductance portions cannot be lengthened.

  FIG. 17 is a diagram for comparing the characteristics of the EBG structure of this embodiment and the EBG structure shown in FIG. FIG. 17A is a graph showing a simulation result obtained by analyzing the characteristics of the EBG structure of the present embodiment, and FIG. 17B is a graph showing a simulation result obtained by analyzing the characteristics of the EBG structure shown in FIG. . Here, the X axis represents frequency (GHz) and the Y axis represents attenuation (dB). When the range of frequencies where the absolute value of the attenuation is 40 dB or more is set as the band gap range, and the lower limit frequency of the band gap is confirmed in FIG. 17, the lower limit frequency 321 of FIG. 17A is 1.0 GHz, and FIG. ) Is 1.2 GHz, and it can be confirmed that the EBG structure of the present embodiment can obtain a low-frequency band gap characteristic. That is, by configuring the conductor layer 301 and the conductor layer 204 with a plurality of conductor plates and conductor wires, a large inductance component is obtained from the first inductance portion and the second inductance portion, thereby providing a band gap characteristic in a low frequency band. Can be confirmed.

  FIG. 18 is a cross-sectional view of the EBG structure for comparing the characteristics with the EBG structure of the preferred embodiment of the present invention. For example, the conductor wire 206a is arranged so as to overlap the conductor plate 213a, and the conductor wire 305b is the conductor plate. It arrange | positions so that 212a may overlap. Compared to the preferred embodiment of the present invention of FIG. 13, the conductor wire 206a and the conductor wire 305b are made longer. However, as described above, the conductor wire 206a overlaps the conductor plate 213a in the z-axis direction, so that the inductance is increased. The effect of increasing the component L is weakened. Similarly, the effect of increasing the inductance component L by the conductor wire 305b is weakened. Further, since the capacitance component C is reduced by reducing the areas of the conductor plate 214a and the conductor plate 311a, the structure shown in FIG. 18 is not preferable for obtaining a band gap frequency in a low frequency band.

  FIG. 19 is a diagram for comparing the characteristics of an EBG structure according to a preferred embodiment of the present embodiment and an unfavorable form of EBG structure. FIG. 19A is a graph showing a simulation result obtained by analyzing the characteristics of the preferred embodiment of the present invention, and FIG. 19B is a graph showing a simulation result obtained by analyzing the characteristics of the EBG structure shown in FIG. is there. Here, the X axis represents frequency (GHz) and the Y axis represents attenuation (dB). When the range of the frequency where the absolute value of the attenuation is 40 dB or more is set as the band gap range, and the lower limit frequency at which the band gap characteristic appears is confirmed from FIG. 19, the lower limit frequency 323 of FIG. The lower limit frequency 324 of (b) is 3.1 GHz. Although the band gap characteristic appears even in the EBG structure shown in FIG. 18, the band gap characteristic in the high frequency band is obtained. In order to obtain band gap characteristics in the low frequency band, the areas of the conductor plate 214a and the conductor plate 311a are increased, and the conductor wire 206a, the conductor plate 213a, the conductor wire 305b, and the conductor plate 212a do not overlap each other in the z-axis direction. Can be confirmed.

  In the present embodiment, the conductor layer 301 includes the conductor line 305 and the via land 306, but the conductor layer 301 may not include at least one of the conductor line 305 and the via land 306. For example, the via land 306 may be disposed between the conductor layer 301 and the conductor layer 202 or above the conductor layer 301, and the conductor wire 305 may be extended in the same layer as the via land 306. Alternatively, the conductor wire 305 may be disposed in a layer between the conductor layers 301 and 202, and one end of the conductor wire 305 may be connected to the via 207 and the other end may be connected to the conductor plate 311 via a via formed separately.

  In this embodiment, the conductor layer 301 is disposed above the conductor layer 202, but the conductor layer 301 may be disposed below the conductor layer 202. In this case, the conductor plate 311 is provided with a clearance, and the via 205 is disposed in the clearance so as not to contact the conductor plate 311.

  In this embodiment, one end of the via 207 is connected to the via land 306, and the via land 306 is connected to the conductor plate 311 via the conductor wire 305. However, the via land 306 is not necessarily required. The conductor line 306 may be directly connected to the via 207.

  The conductor plate 212, the conductor plate 213, the conductor plate 214, and the conductor plate 311 may have the same shape, but may have different shapes or different areas. The conductor wire 206 and the conductor wire 305 may have different shapes and different lengths.

  A fourth embodiment of the present invention will be described with reference to FIGS. FIG. 20 is a cross-sectional view of a substrate on which the EBG structure described in any one of Embodiments 1 to 3 of the present invention is formed. The main board 401 is a board constituting various electronic devices. An electronic circuit 402 such as an LSI is connected to the main board 401 via a connection unit 403. In the main substrate 401, an EBG structure is periodically formed in an EBG region 404 around the electronic circuit 402. Since the noise 405 propagating on the main board 401 is suppressed by passing through the EBG region 404, malfunction of the electronic circuit 402 due to the influence of noise can be prevented.

  FIG. 21 is a cross-sectional view of a package substrate on which the EBG structure described in any one of Embodiments 1 to 3 of the present invention is formed and a main substrate on which the package substrate is mounted. The electronic circuit 402 is disposed on the package substrate 406, and an EBG structure is periodically formed in the EBG region 404 around the electronic circuit 402. The package substrate 406 is connected to the main substrate 401 by the connection portion 403. The present invention is not limited to the main substrate and the package substrate, but can be applied to various other substrates.

  Here, the EBG region 404 in FIGS. 20 and 21 does not need to cover the entire periphery of the electronic circuit 402, and may be a part of the periphery of the electronic circuit that can block the noise propagation path. There is no fixed number of unit structures of the EBG structure, and it may be changed as appropriate.

  The conductor layer, conductor plate, and conductor wire that constitute the embodiment of the present invention described above are formed of a metal material such as copper, palladium, aluminum, platinum, or chromium, but may be a conductor other than metal and conductive. The resin may be used. Here, the conductor layer is formed by laminating a metal plate or metal foil made of the conductive material or the like on the dielectric layer. Moreover, although the conductor plate is shown as a square, it is not limited to this, and is composed of a conductor pattern having an arbitrary shape such as a polygon, a circle, or a line. Furthermore, the conductor wire is a connection pattern for connecting the via and the conductor plate in various forms, and is composed of a metal foil printed on a dielectric or a soldered conductor. However, the conductor wire need not be linear, and may be formed of a polygonal metal plate or the like.

  The EBG structure and the substrate of the present invention have the same effect even if the configurations of the above-described embodiments are upside down, and the upside down configuration is also included in the scope of the right. Further, the present invention is not limited to the above-described embodiments, and various modifications can be made within the scope shown in the claims, and the embodiments can be obtained by appropriately combining technical means disclosed in different embodiments. The form is also included in the technical scope of the present invention.

  According to the present invention, a band gap characteristic in a low frequency band can be obtained with an EBG structure that can be miniaturized, so that it can be used for any electronic devices and substrates that generate noise.

100a, 200a, 300a Unit structure 101, 201, 301 Conductor layer (third conductor layer)
102, 202 Conductor layer (first conductor layer)
203 conductor layer (fourth conductor layer)
103, 204 Conductor layer (second conductor layer)
311a Conductor plate (second conductor pattern)
112a, 212a Conductor plate (conductor pattern constituting the first conductor layer)
213a Conductor plate (conductor pattern constituting the fourth conductor layer)
113a, 214a Conductor plate (first conductor pattern)
104a, 205a, via (first via)
207a Via (second via)
105a, 206a Conductor wire (first connection pattern)
305a Conductor wire (second connection pattern)
106a, 208a, 306a Via land 209a Notch 401 Main substrate 402 Electronic circuit 403 Connection portion 404 EBG region 405 Noise 406 Package substrate

Claims (12)

A first conductor layer;
An EBG structure having a second conductor layer connected to the first conductor layer via a first via,
The EBG structure, wherein the second conductor layer includes a plurality of first conductor patterns, and the first conductor patterns and the first vias are connected through a first connection pattern. A capacitance portion including a first conductor layer;
An EBG structure including an inductance portion including a second conductor layer connected to the first conductor layer via a first via,
The second conductor layer is composed of a plurality of first conductor patterns, and the current path of the inductance portion is lengthened by connecting the first conductor pattern and the first via via the first connection pattern. EBG structure characterized by   The EBG structure according to claim 1, further comprising a third conductor layer that forms a capacitance with the first conductor layer. A fourth conductor layer forming a capacitance with the second conductor layer;
The EBG structure according to claim 3, wherein the fourth conductor layer and the third conductor layer are connected via a second via.   5. The EBG according to claim 4, wherein the third conductor layer includes a plurality of second conductor patterns, and the second conductor pattern and the second via are connected via a second connection pattern. Construction.   6. The EBG structure according to claim 1, wherein the first connection pattern surrounds a part of at least one of the first conductor patterns.   The EBG structure according to claim 1, wherein the first conductor pattern has a notch.   The EBG structure according to claim 7, wherein a part of the first connection pattern is disposed in the notch.   6. The plurality of conductor patterns constituting the first conductor layer and the plurality of conductor patterns constituting the fourth conductor layer are arranged so as to partially overlap in the thickness direction. The EBG structure described in 1.   6. The EBG structure according to claim 4, wherein the first connection pattern is arranged so as not to overlap with a plurality of conductor patterns constituting the fourth conductor layer in a thickness direction.   The area in which one of the plurality of conductor patterns constituting the fourth conductor layer and one of the plurality of first conductor patterns overlap in the thickness direction is the area of the conductor pattern constituting the fourth conductor layer. 6. EBG structure according to claim 4 or 5, characterized in that they are equal. A substrate, wherein the EBG structure according to any one of claims 1 to 11 is periodically arranged at least partly around an electronic circuit.