JP2012128712A - Activated path extraction program, activated path extraction device, and activated path extraction method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To quickly extract an activated path through which a signal propagates in the case of the delay test of an actual chip.SOLUTION: This activated path extraction device includes: a simulation part 11 for specifying a signal value change pin whose signal value has changed in the case of a delay test by performing the simulation of the delay test on the basis of a test pattern in the case of the delay test and the net list of an actual chip; and a path trace part 12 for tracing the activated path by following the signal value change pin on the basis of the signal value change pin specified by the simulation part 11 and the net list of the actual chip.

Description

  The present invention relates to a program, an apparatus, and an apparatus for extracting an activation path through which a signal has propagated during a delay test on an actual chip.

  In recent years, when designing and manufacturing a chip, for example, an integrated circuit such as an LSI (Large Scale Integration), an actual chip actually manufactured has a reference performance value, that is, a specification at the design stage as the process is miniaturized. The number of cases that cannot be satisfied is increasing. In other words, a “deviation” occurs between the path delay predicted value in the design target chip calculated by a simulation tool or the like in the design stage and the path delay value (true value) actually obtained in the actual chip. Often fail to meet the specifications at the design stage.

  For this reason, a delay test for a real chip is indispensable when designing and manufacturing the chip. FIG. 12 is a flowchart for schematically explaining a general chip design and manufacturing procedure including a delay test. As shown in FIG. 12, when the design target chip is designed (step S1), a prototype chip of the designed chip, that is, an actual chip is created (step S2). Then, a delay test (step S3) is performed on the actual chip, and it is determined whether or not the result of the delay test satisfies a predetermined specification.

  If the result of the delay test satisfies a predetermined specification (YES route in step S3), production of an actual chip based on the design result in step S1 (step S4) is started. On the other hand, when the result of the delay test does not satisfy the predetermined specification (NO route of step S3), failure analysis, that is, analysis of the delay factor (step S5) is performed based on the result of the delay test. Then, returning to step S1, the design target chip is designed again according to the analysis result in step S5.

  Here, the delay test is performed by measuring at what clock frequency or clock period the actual chip operates, and the following processing is performed in one delay test. FIG. 13 is a diagram illustrating an example of a circuit configuration on an actual chip to be tested in order to explain the delay test. In FIG. 13, 101 is an input side flip-flop (or latch) on the actual chip, and 102 is an output side flip-flop (or latch) on the same chip. Hereinafter, the “flip-flop” is referred to as “FF”. A combinational circuit including various gates is arranged between these FF101 and FF102. The connection relationship of the combinational circuit is specified based on the net list of the circuit to be designed.

  First, two sets of test vectors are prepared, and signals based on these two sets of test vectors are propagated from the input side FF101 of the actual chip to the output side FF102. That is, after a value based on the first test vector is set to the input pin and output pin of each gate in the actual chip, two clocks with a predetermined time interval are generated. As a result, the second test vector is launched from the input side FF 101 onto the path at the first clock edge to activate the path, and the signal is propagated from the input side FF 101 to the output side FF 102. At the subsequent second clock edge, the signal value propagated to the output FF 102 is captured by the output FF 102. Then, the value in the output FF 102 is compared with the expected value (predicted value) that should be obtained in the output FF 102 when the two test vectors are input, and a match / mismatch between these values is determined.

  When the value at the output side FF102 matches the predicted value, the predetermined time interval is reduced by a fixed amount, for example, 20 MHz, and the two test vectors are input again, and the value at the output side FF102 and the expected value are expected. A match / mismatch with the value is determined. The above processing is repeatedly executed until it is determined that the value at the output side FF 102 does not match the expected value, and the time interval (cycle) immediately before the determination is made is the result of the delay test, that is, the current delay test. It is measured as a measured value of the delay time.

  If it is determined whether or not the measurement value obtained in this way satisfies a predetermined specification, and if it is determined that the predetermined chip satisfies the predetermined specification, that is, if the prototyped actual chip operates normally in the target clock cycle, As described above, production of actual chips (step S4) is started. On the other hand, if it is determined that the measured value does not satisfy the predetermined specification, the delay factor is analyzed (step S5) and redesigned (step S1) based on the result of the delay test as described above.

  In step S5, for example, a failure analysis method called speed path analysis is used to analyze a delay factor. In the following, a path in which a signal is propagated by the input of the two test vectors in the delay test, that is, an “activated path” is referred to as an “activation path”. In FIG. 13, the activation path is indicated by a bold line.

  In the speed path analysis, the measurement of the delay time obtained by the delay test is assigned to each activation path that reaches the failed output side FF 102 for analysis. The failed output FF 102 is the output FF 102 that is determined in step S3 that the measured value does not satisfy the predetermined specification. Here, a general speed path analysis will be described with reference to FIGS. 14 is a diagram showing the definition of each vector component of the feature vector set for each analysis target path, FIG. 15 is a diagram showing a specific example of the feature vector shown in FIG. 14, and FIG. 16 is an example of the speed path analysis result. FIG.

  First, “features” in the speed path analysis will be described with reference to FIGS. 14 and 15. In speed path analysis, the features of each path are represented by vectors. Here, the vector is referred to as a feature vector V. The feature vector V is set for each path to be analyzed, and the feature vector V of the path px is denoted as V (px). Each vector component of the feature vector V (px) is a feature value in the path px, and is defined and given as shown in FIG. 14, for example. A plurality of features included as vector components in the feature vector V (px) are, as shown in equation (2) described later, an actual measurement value d_silicon (px) of a delay time allocated to each analysis target path px and a prediction of the delay time. This is a cause (delay factor) of generating a difference D (px) from the value d_predict (px).

  The definition of each feature is as follows, for example, as shown in FIG. The feature g_low (px) is the number of low power transistors (low_vth) on the path px, and the feature loc1 (px) is “1” when the path px passes through the specified region 1 (loc1) / when it does not pass This value is “0”. The feature loc2 (px) is “1” when the path px passes through the designated area 2 (loc2) / “0” when it does not pass, and the feature len (px) is the value of the path px. Wiring length. In the feature vector V (pi) related to the path pi shown in FIG. 15, the number of low-power transistors on the path pi is 2, and the path pi passes through the designated area 2 but does not pass through the designated area 1. The path pi has a wiring length of 6. In the feature vector V (pj) related to the path pj shown in FIG. 15, the number of low-power transistors on the path pj is 4, and the path pj passes through the designated area 1 but does not pass through the designated area 2. The wiring length of the path pj is 15.

As described above, when the feature vector V (px) is extracted for each analysis target path px, the speed path analysis is executed as follows.
Here, the measurement value of the delay time acquired by the delay test and assigned to each analysis target path px is “d_silicon (Pi)”, and the predicted delay time calculated by a tool or the like for each analysis target path px is “d_predict”. Assuming that (Pi) ″, the difference D (px) between these measured values and predicted values is given by the following equation (1).
d_silicon (px) = d_predict (px) + D (px) (1)

  In the above equation (1), D (px) << d_predict (px), that is, D (px) is sufficiently smaller than d_predict (px). Therefore, the difference D (px) is linear with respect to a plurality of features g_low (px), loc1 (px), loc2 (px),..., Len (px) indicating a phenomenon that has been modeled only in a simplified manner. Since it can be approximated, the following equation (2) is established for each analysis target path px. In the following equation (2), the analysis target path px is, for example, p3, p7,.

D (p3) = W_g_low * g_low (p3) + W_loc1 * loc1 (p3) + W_loc2 * loc2 (p3) +… + W_len * len (p3)
D (p7) = W_g_low * g_low (p7) + W_loc1 * loc1 (p7) + W_loc2 * loc2 (p7) +… + W_len * len (p7)
:: (2)
D (pn) = W_g_low * g_low (pn) + W_loc1 * loc1 (pn) + W_loc2 * loc2 (pn) +… + W_len * len (pn)
Here, W_g_low, W_loc1, W_loc2,..., W_len correspond to the vector components g_low (px), loc1 (px), loc2 (px),..., Len (px) of the feature vector V (px) of the path px, respectively. Weight coefficient [ps].

  Then, the weighting coefficient W_g_low is obtained by solving the expression (2) derived for each analysis target path px with respect to the weighting coefficients W_g_low, W_loc1, W_loc2, ..., W_len by linear regression analysis such as SVM (Support Vector Machine) regression. , W_loc1, W_loc2, ..., W_len values are obtained. It can be considered that a feature corresponding to a large value among the weighting coefficients obtained in this way is a factor causing the error D (px). More specifically, it is assumed that, for example, values as shown in FIG. 16 are acquired as the weighting factors W_g_low, W_loc1, W_loc2,. In FIG. 16, each value is normalized by setting the weighting factor W_g_low indicating the maximum value to 100. In the example of the speed path analysis result shown in FIG. 16, it is analyzed that the feature g_low, that is, the low power transistor is the largest cause of the error D (px).

By the way, as described above, in the speed path analysis, the measurement of the delay time obtained in the delay test is assigned to each activation path that reaches the failed output side FF 102 for analysis. For this reason, when performing the speed path analysis, it is necessary to extract and specify the activation path in advance.
Normally, in the delay test, two input test vectors, an expected value to be obtained at the output FF 102 when these two test vectors are input, and a measured value of the delay time are obtained as test patterns. Further, a fail list in which information (FF name or the like) specifying the failed output side FF 102 is listed is also obtained.

  However, in the delay test, information for identifying an activation path required for speed path analysis, specifically, information for identifying a pin or a net through which the activation path passes between the input side FF and the output side FF Is not acquired or stored. The reason for this is that analysis methods such as speed path analysis that require information on activation paths have recently attracted attention, and there is a need to acquire information for identifying activation paths. It was mentioned that there was nothing. Another reason is that acquiring information for identifying an activation path during execution of a delay test results in an enormous amount of time for the delay test and an enormous amount of data to be acquired. It is done.

Japanese Patent Laid-Open No. 04-055776 Japanese Patent Laid-Open No. 04-038568

P. Bastani, N. Callegari, Li-C. Wang, et al., “Statistical Diagnosis of Unmodeled Systematic Timing Effects”, DAC’08, 22.1, pp.355-360 P. Bastani, K. Killpack, et al., “Speedpath Prediction Based on Learning from a Small Set of Examples”, DAC’08, 12.3, pp.217-222

  In one aspect, the object of the present invention is to quickly extract an activation path through which a signal has propagated during a delay test of an actual chip.

  The activation path extraction program of the present case is a computer that extracts an activation path through which a signal has been propagated during a delay test on an actual chip, and the delay path based on the test pattern in the delay test and the net list of the actual chip. By performing a test simulation, a signal value change pin whose signal value has changed during the delay test is specified, and the signal value is determined based on the signal value change pin specified by the simulation and a netlist of the actual chip. By tracing the change pin, the process of tracing the activation path is executed.

  In addition, the activation path extraction apparatus of the present case extracts an activation path through which a signal has propagated during a delay test on an actual chip, and is required to have the following simulation unit and path trace unit. Here, the simulation unit performs a simulation of the delay test based on a test pattern at the time of the delay test and a net list of the real chip, thereby changing a signal value at which the signal value has changed at the time of the delay test. Identify the pin. The path trace unit traces the activation path by tracing the signal value change pin based on the signal value change pin specified by the simulation unit and the net list of the real chip.

  Further, the activation path extraction method of the present invention is to extract an activation path through which a signal has propagated during a delay test for an actual chip by a computer, and the test pattern and the net of the actual chip are extracted from the delay test. By performing simulation of the delay test based on the list, a signal value change pin whose signal value has changed during the delay test is specified, and the signal value change pin specified by the simulation and the netlist of the actual chip are Based on the signal value change pin, the activation path is traced.

  An activation path through which a signal propagates during a delay test of an actual chip is extracted at high speed based on a test pattern in the delay test.

It is a block diagram which shows the function structure of the activation path | pass extraction apparatus of this embodiment. It is a figure which shows the example of the signal value change pin information obtained by the simulation part in the activation path | pass extraction apparatus of this embodiment. It is a figure which shows the example of the clock control system pin information obtained by the simulation part in the activation path | pass extraction apparatus of this embodiment. It is a figure for demonstrating a clock control system path | route and a clock control system pin. It is a figure for demonstrating a glitch. It is a figure for demonstrating the glitch detection method in the activation path | pass extraction apparatus of this embodiment. It is a figure which shows the principal part description of a cell library (Verilog source code) in order to demonstrate the function as an indefinite value setting means in the activation path | pass extraction apparatus of this embodiment. It is a figure for demonstrating the trace operation | movement by the path trace part in the activation path | pass extraction apparatus of this embodiment. It is a flowchart for demonstrating the flow of a process in the activation path | pass extraction apparatus of this embodiment. It is a flowchart for demonstrating operation | movement of the path trace part in the activation path | pass extraction apparatus of this embodiment. (A)-(H) is a figure for demonstrating the depth priority search and counting operation | movement of the activated path by the path trace part in the activated path extracting device of this embodiment. It is a flowchart for demonstrating roughly the procedure of the design and manufacture of the general chip | tip containing a delay test. It is a figure which shows the example of the circuit structure on the real chip | tip of a test object in order to demonstrate a delay test. It is a figure which shows the definition of each vector component of the feature vector set for every analysis object path. It is a figure which shows the specific example of the feature vector shown in FIG. It is a figure which shows the example of a speed path analysis result.

Hereinafter, embodiments will be described with reference to the drawings.
[1] Configuration and Function of Activation Path Extraction Device of this Embodiment [1-1] Overall Configuration FIG. 1 is a block diagram showing a functional configuration of the activation path extraction device 1 of this embodiment. The activation path extraction apparatus 1 shown in FIG. 1 functions to extract an activation path through which a signal has propagated during a delay test for a real chip. In order to realize this function, the activation path extraction device 1 is composed of a computer such as a general personal computer, and has a processing unit 10 and a storage unit 20 and is operated by a designer to store various information in the device 1. It has a man-machine interface (not shown) for inputting. The processing unit 10 is a CPU (Central Processing Unit) or the like, and the storage unit 20 may be an internal storage device such as a RAM (Random Access Memory), a ROM (Read Only Memory), a hard disk, or the like. It may be a storage device.

The processing unit 10 functions as a simulation unit 11 and a path trace unit 12 described later by executing the activation path extraction program.
The storage unit 20 stores a delay test result database 21, a net list 22, a toggle pin information list 23, a clock control system pin information list 24, and an activation path trace result database 25, which will be described later, and is set by the designer. Various information and the activation path extraction program are also stored.

[1-2] Stored Data in the Storage Unit The delay test result database 21 stores the delay test results obtained by the procedure described above with reference to FIGS. The delay test result obtained by one delay test includes a set of test patterns 211 and a fail list 212. The set of test patterns 211 and the fail list 212 is stored in the database 21 in association with identification information (ID) that identifies the one-time delay test.

  In the test pattern 211, as described above, the two test vectors used in the delay test, the expected value to be obtained at the output FF 102 when these two test vectors are input, and the delay test obtained Delay time measurements. Here, the measured value of the delay time is a measured value of the time for the signal to reach from the input side FF 101 to the output side FF 102 in the activation path on the actual chip (“t [ps]” in FIG. 1).

  The fail list 212 lists information (such as FF name) that identifies the output FF 102 that has failed in the delay test. Here, as described above, the failed output FF 102 is the output FF 102 for which it is determined in step S3 in FIG. 12 that the value in the output FF 102 does not satisfy the predetermined specification. In other words, the output-side FF 102 registered in the fail list 212 is an FF that did not obtain an expected value within a predetermined time as a result of the delay test, in other words, a value different from the expected value in the delay test of the actual chip. It is FF which output. Such an output FF is hereinafter referred to as “fail FF”.

  The netlist 22 is design data obtained by design (step S1 in FIG. 12), and holds connection information between terminals including information on circuit elements such as cells on the chip to be designed, and cell connection relationships. ing. The netlist 22 is Verilog source code that hierarchically describes circuits to be designed as cell libraries, submodules, modules, and chips (see, for example, FIG. 7).

  The toggle pin information list 23 stores information on signal value change pins specified by the simulation unit 11 as described later. The signal value change pin is a pin whose signal value has changed during the delay test, and is also referred to as a “toggle pin” or “toggle pin”. Here, the change of the signal value means that the signal value is from 0 to 1, from 1 to 0, from 0 to x (indefinite value), from x to 0, from 1 to x, from x to 1. It is to show any one change. In the toggle pin information list 23, for example, as shown in FIG. 2, the pin name or identification information (ID) of the toggle pin is listed and registered as information for identifying the toggle pin. FIG. 2 is a diagram illustrating an example of toggle pin information (list 23) obtained by the simulation unit 11.

  As will be described later, the clock control system pin information list 24 indicates the value 1 or 0 of the clock control system pin specified by the simulation unit 11, for example, as shown in FIG. ID). Here, for example, as shown in FIG. 4, the clock control system pin is an IH (inhibit) pin to which a signal value for controlling whether or not to input the clock signal CK to the clock terminal of each output FF 102 is set. . 3 is a diagram illustrating an example of clock control system pin information (list 24) obtained by the simulation unit 11, and FIG. 4 is a diagram for explaining a clock control system path and clock control system pins. .

  In the example shown in FIG. 4, an OR gate 103 that outputs a logical sum of the clock signal CK and the signal value of the IH pin is connected to the clock terminal of the output side FF102. Therefore, when the signal value of the IH pin is set to 1, the clock signal CK cannot be passed through the OR gate 103 and is prohibited from being input to the clock terminal of the output side FF102. On the other hand, when the signal value of the IH pin is set to 0, the clock signal CK passes through the OR gate 103 and is input to the clock terminal of the output side FF102.

  The IH pin is connected to the input side FF 101 via a combinational circuit (not shown) including various gates, and a path reaching the IH pin from the input side FF 101 is called a clock control system path or an IH path. In the present embodiment, the above-described IH path and the data path through which data propagates from the input FF 101 to the data pin of the output FF 102 are targets to be identified and extracted as activation paths.

  The activation path trace result database 25 stores information about the activation path obtained by the path trace unit 12 tracing the activation path as described later. The information on the activation path is, for example, the pin name (pin ID) of the pin through which the activation path has passed or the net name (net ID) of the net through which the activation path has passed. The data is stored in the database 25 in association with the path name (path ID) to be specified. The database 25 also stores the number of activation paths obtained by the counting function of the path trace unit 12 as described later.

[1-3] Functions of Processing Unit Next, functions of the simulation unit 11 and the path tracing unit 12 realized by the processing unit 10 will be described.
[1-3-1] Basic Function of Simulation Unit The simulation unit 11 performs a delay test simulation based on the test pattern 211 at the time of the delay test for the real chip and the net list 22 of the real chip, thereby delaying the delay. The signal value changing pin whose signal value has changed during the test is specified. At this time, the simulation unit 11 performs a delay test simulation without considering the timing, that is, without using an SDF (Standard Delay Format) file that holds information about the delay time.

  Specifically, the simulation unit 11 reads two sets of test vectors used in the delay test for the actual chip from the database 21 (test pattern 211). The simulation unit 11 then performs a series of delay test operations in which signals based on these two sets of test vectors are propagated from the input-side FF 101 to the output-side FF 102 based on the net list 22 of the database 21 without considering timing. Run by simulation. That is, the simulation unit 11 sets a value based on the first test vector to the input pin and the output pin of each gate by simulation, and then generates two clocks with a predetermined time interval. Further, the simulation unit 11 activates the path by launching the second test vector from the input side FF 101 on the path at the first clock edge by simulation, and the signal is output from the input side FF 101 to the output side. Propagate to FF102. The simulation unit 11 captures the signal value propagated to the output side FF102 at the second clock edge that follows, and compares the value in the output side FF102 with the expected value read from the test pattern 211. The match / mismatch of these values is determined.

  At this time, the simulation unit 11 identifies the toggle pin whose signal value has changed while performing the simulation of propagating the signal from the input side FF101 to the output side FF102, and the pin name of the identified toggle pin is shown in FIG. Saved in the toggle pin information list 23. Here, the target pins for which the simulation unit 11 determines whether or not the signal value has changed are, for example, the output pins of the input side FF101, the input pins of the output side FF102, and between the input side FF101 and the output side FF102. These include input pins and output pins of various gates, the IH pins described above, and the like.

  Further, the simulation unit 11 identifies and identifies the value of the IH pin, particularly the value set in the IH pin (see FIG. 4) of the OR gate 103 at the second clock edge in the present embodiment, by the above-described simulation. The value is associated with the pin name of the IH pin and stored in the clock control system pin information list 24 as shown in FIG. As described later, the information stored in the clock control system pin information list 24 and the information stored in the toggle pin information list 23 are determined according to the determination process (step of FIG. 10) for narrowing the activation paths to be traced. S31).

  The simulation unit 11 compares the output value of each output-side FF 102 obtained by the simulation with the expected value included in the test pattern 211, and if the output value and the expected value all match, the simulation unit 11 specifies by simulation. The activation path information stored in the lists 23 and 24 is validated. Thereby, the simulation part 11 is checking the reliability of the information obtained by simulation. In other words, the simulation unit 11 determines that the reliability of the simulation is ensured when the output value and the expected value all match, validates the information obtained in this simulation, and uses it in the following processing. . On the other hand, if the output value and the expected value do not match, the simulation unit 11 determines that the reliability of the simulation is not ensured, invalidates the information obtained in the current simulation, performs the simulation again, or notifies an error. To the designers.

  As described above, the simulation unit 11 simply performs a delay test simulation for an actual chip without considering the delay time, and sets each pin between the input FF 101 and the output FF 102 during the delay test. The change in signal value is being followed. As described above, the delay test simulation performed without considering the timing is executed at a very high speed as compared with the delay test simulation performed while calculating the delay time in consideration of the timing.

[1-3-2] Glitch detection method and function of indeterminate value setting means By the way, when a plurality of signals are input to the gate, the glitch ( A noise waveform called glitch) may appear.
Here, the glitch appearing in the output signal of the AND gate 104 will be described with reference to FIG. FIG. 5 is a diagram for explaining the glitch. The AND gate 104 shown in FIG. 5 receives two input signals from the two input pins a and b, and outputs the logical product result of these two input signals from the output pin c as an output signal. When the first input signal rising from 0 to 1 and the second input signal falling from 1 to 0 are input from the input pins a and b to the AND gate 104 at the same timing, respectively. Think.

  At this time, even if the rising timing of the first input signal and the rising timing of the second input signal are matched as much as possible on the actual chip, a slight timing deviation always occurs. Therefore, there is a possibility that a glitch that changes from 0 → 1 → 0 at a minute time interval appears in the signal output from the output pin c of the AND gate 104 on the actual chip as shown in the upper right of FIG. There is.

  On the other hand, when the simulation unit 11 performs the delay test simulation without considering the timing, the rising timing of the first input signal and the rising timing of the second input signal are handled as completely the same. For this reason, the signal output from the output pin c of the AND gate 104 remains 0 and does not show any change as shown in the lower right of FIG. That is, in the following simulation, the path following the output pin c of the AND gate 104 is treated as a logical signal that no signal is propagated, and the presence of the glitch is ignored and the glitch propagation is activated. The existence of the path is also ignored.

  The glitch itself described above is not actively used to operate the circuit. However, since the appearance of a glitch may cause a failure in the circuit, the glitch cannot be ignored when performing a failure analysis. Therefore, while performing a delay test simulation that does not consider the timing, it is necessary to reliably identify the toggle pin whose signal value changes due to the glitch and extract the path where the glitch may appear as the activation path There is.

  Therefore, in this embodiment, an indefinite value setting means is provided. When the signal value of the output pin of the input side FF 101 changes during execution of the simulation, the indefinite value setting means sets the indefinite value x between the signal value before the change of the output pin and the signal value after the change for a predetermined time. Only tx is set. Then, the simulation unit 11 performs a delay test simulation without considering the timing based on the signal value for which the indeterminate value x is set by the indeterminate value setting means. As a result, as described later, the simulation unit 11 can specify not only a toggle pin whose signal value changes due to normal signal propagation but also a toggle pin whose signal value changes due to a glitch.

  Here, the glitch detection method in the present embodiment will be specifically described with reference to FIGS. 6 and 7. FIG. 6 is a diagram for explaining the glitch detection method in the present embodiment, and FIG. 7 is a diagram showing a main part description of the cell library for explaining the function as the indefinite value setting means in the present embodiment. .

  When the signal value of the output pin of the input side FF rises from 0 to 1 or falls from 1 to 0, for example, as shown on the left side of FIG. An indefinite value x is set between the signal values 1 and 0 for a predetermined time tx. That is, when the signal value of the output pin of the input side FF rises from 0 to 1, the signal value of the output pin changes to 1 after maintaining the indefinite value x for a predetermined time tx after showing 0 (0 → x → 1). Further, when the signal value of the output pin of the input side FF falls from 1 to 0, the signal value of the output pin changes to 0 after maintaining the indefinite value x for a predetermined time tx after showing 1 (1 → x → 0). At this time, the predetermined time tx is set to be longer than the internal delay value of each cell in the netlist 22 and shorter than the clock cycle (time interval of two clocks) in the simulation, and the reason will be described later. .

  The function as the indefinite value setting means is realized by the description of the Verilog source code that defines the input-side FF as shown in FIG. This description is included in the net list 22 of the actual chip. In the description shown in FIG. 7, the description of the area indicated by the symbol A is a description for realizing the function as the indefinite value setting means. Specifically, in this region A, when the output m and the input d are different, that is, when the value of the output pin of the FF changes, the indefinite value x is substituted for the output m for 10 unit time, and then the input d is output m It is defined to be assigned to.

  The description defining the indefinite value setting means defines the input side FF when the simulation unit 11 reads the definition description of the input side FF from the netlist (cell library) 22 to execute the delay test simulation. It is newly added to the description or added by modifying the definition description of the input side FF (see step S10 in FIG. 9). The function of determining that the definition description of the input-side FF has been read in this way and automatically adding a description defining the indefinite value setting means to the definition description is, for example, that the processing unit 10 extracts the activation path. It is realized by executing the program. The simulation unit 11 simulates the operation of the input-side FF based on the definition description of the input-side FF to which the description defining the indefinite-value setting unit is added, thereby functioning as the above-described indefinite-value setting unit. Is realized in the simulation unit 11.

  As shown in FIG. 6, when the first input signal and the second input signal set with the indefinite value x by the indeterminate value setting means are input to the AND gate 104 from the input pins a and b, respectively, the AND gate A signal waveform corresponding to the glitch is output from the output pin c 104. The signal value by the signal waveform corresponding to the glitch returns to 0 after maintaining 0 at an indefinite value x for a predetermined time tx after indicating 0 (0 → x → 0). Thus, the signal waveform including the indefinite value x propagates through the path after the AND gate 104, and the pin through which the signal waveform including the indefinite value x passes is specified as a toggle pin by the simulation unit 11. Become.

Here, the reason why the indefinite value x is set between the pre-change signal value and the post-change signal value of the output pin of the input side FF as in the first input signal and the second input signal described above will be described. To do.
For example, the document R. Guo, W.-T. Cheng, K.-H. Tsai, “Speed-Path Debug Using At-Speed Scan Test Patterns”, IEEE Conference 2009 Papers (URL: http: //www.mentor. com / products / silicon-yield / ieee_conference_papers /) When the signal value on the input side changes from 0 to 1 or from 1 to 0 (0 → 1 or 1 → 0), the destination of the change of the signal value is indefinite It is described that a simulation is performed by replacing x and a data path in which an indefinite value x is propagated is searched as a path in which a signal including noise is propagated.

  However, when searching for a path through which the indefinite value x has been propagated by changing the signal value on the input side to the indefinite value x as described in the above document, the data path can be searched, but the IH path can be searched. The clock control system path cannot be searched. For example, in the circuit configuration shown in FIG. 4, when the indefinite value x propagates through the IH path from the input side and reaches the IH pin and is maintained, the indefinite value x is input to the clock terminal of the output side FF102. The simulation unit 11 cannot normally execute the simulation.

  Therefore, in this embodiment, when the signal value output from the input side FF 101 to each path changes, the function of the indefinite value setting means sets an indefinite value x between the pre-change signal value and the post-change signal value. Only time tx is set. As a result, the signal value propagated through each path does not remain at the indefinite value x, and always changes to 0 or 1 after the indefinite value x is maintained for the predetermined time tx.

  That is, the signal value output from the input side FF 101 to each path shows a change of either 0 → x → 1 or 1 → x → 0, so that the signal value propagating through each path passes through various gates. Accordingly, the data pin or the IH pin is reached while showing any change of 0 → x → 1, 1 → x → 0, 0 → x → 0, 1 → x → 1.

  Therefore, in this activation path extraction device 1, since the signal value that has reached the data pin or the IH pin does not continue to be maintained at the indefinite value x, the data path and the IH path can be prevented without hindering the normal operation of the simulation. Both can be specified and extracted as activation paths.

Next, the time for maintaining the indefinite value x between the pre-change signal value and the post-change signal value, that is, the predetermined time tx will be described.
When the predetermined time tx is less than or equal to the internal delay value of each cell in the netlist 22, a signal waveform including an indefinite value x, for example, a signal waveform (0 → x → 0) corresponding to the glitch shown in FIG. Absorbed by delay. For this reason, the signal waveform including the indefinite value x disappears from the cell output signal. Therefore, the internal delay value of each cell in the Verilog source code in the netlist 22 is checked, and the predetermined time tx is determined so as to be longer than the maximum internal delay value. Thereby, it is possible to prevent the signal waveform including the indefinite value x from disappearing in each cell, and the signal waveform including the indefinite value x reliably propagates through each path.

  If the predetermined time tx is equal to or longer than the clock period T in the simulation, that is, the time interval T between the two clocks described above, the indefinite value x is maintained throughout the time interval T. In this case, the indefinite value x is input from the IH path and the IH pin to the clock terminal of the output FF 102, and the simulation unit 11 cannot normally execute the simulation. Therefore, the predetermined time tx is determined so as to be shorter than the clock cycle T. As a result, the indefinite value x can be prevented from being input to the clock terminal of the output side FF102, and both the data path and the IH path can be identified and extracted as activation paths without hindering the normal operation of the simulation. Can be targeted.

  As described above, in the present embodiment, the glitch appears as a signal waveform that maintains the indefinite value x for a predetermined time in a simulation that does not consider timing. As a result, the simulation unit 11 reliably identifies the signal value change pin (toggle pin) without overlooking the signal value change due to the glitch while performing a high-speed simulation, and lists the pin name in the toggle pin information list 23. be able to. Similarly, the value set in the IH pin of the OR gate 103 at the second clock edge is surely specified, and the value is associated with the pin name of the IH pin and stored in the clock control system pin information list 24. can do.

[1-3-3] Function of Path Trace Unit The path trace unit 12 is activated by tracing the toggle pin based on the pin name of the toggle pin listed in the toggle pin information list 23 and the net list 22 of the actual chip. Trace of the activation path.

  Specifically, the path trace unit 12 selects one target fail FF (output FF) from the fail list 212, searches the toggle pin information list 23 for the toggle pin of the selected fail FF, and selects one toggle pin (data pin). Or, IH pin) is selected as the starting point. As shown in FIG. 8, the path trace unit 12 performs backward tracing from the toggle pin selected as the starting point toward the input side FF. FIG. 8 is a diagram for explaining the trace operation by the path trace unit 12. For tracing, for example, depth priority search is used. This depth priority search will be described later with reference to FIG.

  At this time, the path trace unit 12 searches the net list 22 for pins physically connected to the starting point, and searches for the pins registered in the toggle pin information list 23 as toggle pins among the searched pins. . Hereinafter, similarly, the path trace unit 12 searches the netlist 22 for a pin physically connected to the toggle pin on the input side with respect to the searched toggle pin, and toggle pin information as a toggle pin among the searched pins. The pins registered in the list 23 are searched. The path trace unit 12 repeatedly performs the same processing until the activation path being traced reaches the input pin of the input side FF.

  In this way, the path trace unit 12 performs backward tracing of the activation path by following the toggle pin. Further, the path trace unit 12 acquires the pin name / net name of the pin / net through which the activation path has passed while performing backward tracing. Then, the path trace unit 12 uses the acquired pin name / net name as information about one activation path from the input pin of the fail FF to the output pin of the input side FF, and specifies the activation path. The name is stored in the activation path trace result database 25 in association with the name.

[Judgment function of path trace part]
The path trace unit 12 may have a determination function described below to narrow down activation paths to be traced. Hereinafter, a case where the path trace unit 12 performs the above-described narrowing down with the above-described determination function will be described.

  The determination function is based on the toggle pin information in the toggle pin information list 23 and the value at each IH pin in the clock control system pin information list 24, and any of the data path to the fail FF and the IH path may be involved in the failure. It has a function to determine whether there is Then, the path trace unit 12 starts from the toggle pin of the fail FF connected to the path determined to be related to the failure by the determination function, and the backward trace of the path from the start point is described above. Do the same.

The determination function of the path trace unit 12 described above will be described in more detail.
As shown in FIG. 4, there are two paths that cause failure of the fail FF: a data path connected to the D pin of the fail FF 102 and an IH path connected to the clock terminal of the fail FF 102 via the IH pin and the OR gate 103. One of them. The following three cases 1 to 3 can be considered as cases where the output side FF 102 fails in the delay test.

Case 1: When signal propagation from the data path to the D pin is not in time, that is, when the data path is a failure factor.
Case 2: When signal propagation from the IH path to the IH pin is not in time, that is, when the IH path is a failure factor.
Case 3: Case 1 or Case 2 cannot be determined, that is, the data path or the IH path can be a failure factor.

  The determination function determines whether the fail FF corresponds to any of the cases 1 to 3 described above based on the toggle pin information in the toggle pin information list 23 and the value at each IH pin in the clock control system pin information list 24. To do. As described above, the value at each IH pin in the clock control system pin information list 24 is the value set in the IH pin at the second clock edge (see FIG. 3; hereinafter referred to as “IH2”). .

  Here, for example, consider the case where the output side FF 102 stores data when the clock CK falls (1 → 0) in the circuit configuration shown in FIG. In such a case, the determination of cases 1 to 3 by the determination function is performed as follows. Note that the determination example described here is merely an example, and the determination reference value such as IH2 in the determination program varies depending on the circuit specifications.

  When IH2 = 0 and the IH pin is toggled, that is, when the IH pin value IH2 stored in the clock control pin information list 24 is 0 and the pin name of the IH pin is registered in the toggle pin information list 23 , Fail FF is determined to correspond to case 3. At this time, the determination function determines that both the data path and the IH path can be a failure factor, and sets both the data path and the IH path trace as activation paths to be traced.

  When IH2 = 0 and the IH pin is not toggled, that is, when the IH pin value IH2 stored in the clock control system pin information list 24 is 0 and the pin name of the IH pin is not registered in the toggle pin information list 23 , Fail FF is determined to correspond to case 1. At this time, the determination function determines that the data path can be a failure factor, and determines that the data path is an activation path to be traced.

  When IH2 = 1, that is, when the IH pin value IH2 stored in the clock control system pin information list 24 is 1, regardless of whether the pin name of the IH pin is registered in the toggle pin information list 23 or not. , Fail FF is determined to correspond to case 2. At this time, the determination function determines that the IH path can be a failure factor, and determines that the IH path is an activation path to be traced.

  As described above, since the activation path to be traced is narrowed down by the determination function of the path trace unit 12 and tracing is performed for the narrowed activation path, information on the activation path necessary for performing the speed path analysis is performed. Are extracted at high speed and reliably.

[Counting function of path trace part]
Based on the pin name of the toggle pin listed in the toggle pin information list 23 and the net list 22 of the actual chip, the path trace unit 12 traces the toggle pin to input from the number of activation paths, that is, one fail FF. It has a function of counting the number of activation paths reaching the side FF. The count value obtained by this count function is stored in the activation path trace result database 25.

The path number counting process by the counting function may be executed simultaneously with the trace process in which the path trace unit 12 performs backward tracing of the activation path to acquire information on the pin / net through which the activation path has passed.
The counting process may be executed separately from the tracing process. For example, only the counting process is executed before the tracing process is executed, and the number of activation paths to be traced is counted for each fail FF. As a result, the designer refers to the number of activation paths of each fail FF and makes various determinations such as which fail FF is targeted for activation path tracing before the start of the trace processing. be able to.

  Specifically, the counting function of the path trace unit 12 starts with the toggle pin of the fail FF as the starting point, and performs a depth-first search from the starting point, and is deeper than that pin for each pin. The number of activation paths is counted by following the toggle pin while giving the number of activation paths on the side as a label. This counting process will be described in detail with reference to FIG.

[2] Operation of Activation Path Extraction Device of the Present Embodiment Next, with reference to FIGS. 9 to 11 for specific functions and operations of the activation path extraction device 1 of the present embodiment configured as described above. While explaining.
[2-1] Process Flow in Activation Path Extraction Device First, the process flow in the activation path extraction device 1 will be described with reference to the flowchart (steps S10 to S30) shown in FIG.

  When the delay test is performed on the actual chip, the test pattern 211 used in the delay test and the fail list 212 obtained by the delay test are stored in the delay test result database 21 of the storage unit 20. Further, the storage unit 20 stores a net list 22 which is design data (Verilog source code) of an actual chip. The netlist 22 includes a cell library that defines each cell.

When various data is stored in the storage unit 20 in this way, the activation path is extracted by the simulation unit 11 and the path trace unit 12 in the following procedure.
First, the simulation unit 11 reads necessary data from the test pattern 211 and the netlist (cell library) 22 in order to execute a delay test simulation. At this time, when the definition description of the input-side FF is read from the netlist 22, the description defining the indefinite value setting means (see, for example, the area A in FIG. 7) by the simulation unit 11 is the description defining the input-side FF. Added / modified. That is, a source code description for detecting a glitch is added / modified (step S10).

  Thereafter, in step S20, the simulation unit 11 executes the delay test simulation without considering the timing based on the test pattern 211 at the time of the delay test for the actual chip and the net list 22 of the actual chip. As a result, the toggle pin whose signal value has changed during the delay test is specified by the simulation unit 11, and the pin name of the toggle pin is stored in the toggle pin information list 23 (see FIG. 2).

  At this time, the simulation unit 11 simulates the operation of the input side FF based on the definition description of the input side FF to which the description defining the indefinite value setting unit is added, thereby functioning as the indefinite value setting unit. Is realized in the simulation unit 11. That is, when the signal value of the output pin of the input side FF rises from 0 to 1 or falls from 1 to 0, the signal values 0 and 1 are set by the indefinite value setting means, for example, as shown on the left side of FIG. An indefinite value x is set for a predetermined time tx between the signal values 1 and 0.

  When the signal set with the indefinite value x by the indefinite value setting means is input to each path, as described above with reference to FIG. Appears as a signal waveform that maintains for a predetermined time. Thus, the signal waveform including the indefinite value x propagates the path after the cell where the glitch occurs. Therefore, the pin through which the signal waveform including the indefinite value x has passed is specified as a toggle pin by the simulation unit 11, and the pin name of the specified toggle pin is stored in the toggle pin information list 23.

  In step S20, the simulation unit 11 identifies the value set in the clock control system pin (for example, the IH pin; see FIG. 4) at the second clock edge, and the value is used as the pin name of the IH pin. The correspondence is stored in the clock control system pin information list 24 (see FIG. 3).

  When the simulation as described above is performed by the simulation unit 11, the output value of each output FF obtained by the simulation is compared with the expected value included in the test pattern 211. When all of these output values and expected values match, it is determined that the reliability of the simulation is ensured, and the activation path information specified by the simulation and stored in the lists 23 and 24 is the subsequent path trace. Used for processing. If these output values do not match the expected values, it is determined that the reliability of the simulation is not secured, the information obtained in this simulation is invalidated, and the simulation is performed again or an error notification is given. Or

  When necessary information is stored in the toggle pin information list 23 and the clock control system pin list 24 in the storage unit 20 by the simulation of the delay test by the simulation unit 11, the trace processing by the path trace unit 12 is performed on the fail FF. It is executed (step S30). The activation path information acquired by this trace processing, for example, the pin name / net name of the pin / net that the activation path has passed, and the number of activation paths are the path names that identify the activation path. Correspondingly stored in the activation path trace result database 25.

[2-2] Path Trace Process Next, the operation of the path trace unit 12, that is, the path trace process in step 30 of FIG. 9, will be described with reference to the flowchart (steps S31 and S32) shown in FIG.
As described above, when the simulation of the delay test is performed by the simulation unit 11 and necessary information is stored in the toggle pin information list 23 and the clock control system pin list 24, the path trace processing by the path trace unit 12 is started. The

  First, in step S31, the path trace unit 12 selects one target fail FF (output FF) from the fail list 212. The determination function of the path trace unit 12 determines whether the selected fail FF has failed due to a data path or a clock control system path (IH path). This determination is performed based on the toggle pin information in the toggle pin information list 23 and the value at each IH pin in the clock control system pin information list 24 as described above. By this determination, the trace target of the activation path is narrowed down to at least one of the data path and the IH path determined to be the cause of the failure.

  In step S32, the backward trace of the path is executed from the start point of the toggle pin of the fail FF connected to the path determined to be the cause of the failure by the determination function. At this time, the path trace unit 12 searches the net list 22 for pins physically connected to the starting point, and searches for the pins registered in the toggle pin information list 23 as toggle pins among the searched pins. The Similarly, the path trace unit 12 searches the netlist 22 for pins that are physically connected to the toggle pin on the input side of the searched toggle pin, and toggle pin information as a toggle pin among the searched pins. The pins registered in the list 23 are searched. Similar processing is repeatedly executed until the activation path in the trace reaches the input pin of the input side FF.

  In this way, the path trace unit 12 traces the toggle pin to perform backward trace of the activation path. At this time, the path trace unit 12 acquires the pin name / net name of the pin / net through which the activation path has passed while performing backward tracing. The acquired pin name / net name is used as a path name for identifying the activation path by the path trace unit 12 as information on one activation path from the input pin of the fail FF to the output pin of the input side FF. Correspondingly stored in the activation path trace result database 25.

[2-3] Activation Path Depth Priority Search and Counting Processing Next, the activation path depth priority executed by the path trace unit 12 will be described with reference to FIGS. 11 (A) to 11 (H). The search and counting operation (counting function) will be specifically described. FIG. 11A is a diagram illustrating an example of the entire configuration of the activation path that is the target of the depth-first search and the counting process in the following description. FIG. 11B to FIG. 11H illustrate an example of the depth priority search and counting operation procedure performed by the path trace unit 12 performed on the activation path shown in FIG. 11A. FIG. However, the depth priority search and the count processing target and procedure in this case are not limited to the examples shown in FIGS. 11 (A) to 11 (H).

  11A to 11H, the right rectangular block indicates a fail FF having a toggle pin as a starting point of the backward trace, and the left rectangular block has an activation path due to the backward trace. The input side FF to be reached is shown. A circle block indicates a toggle pin through which the activation path has passed. The code in each block indicates an FF name or a pin name. That is, the FF name of the fail FF is F0, and the FF names of the seven input side FFs are F1 to F7, respectively. The pin name of the toggle pin of the fail FF is p0, and the pin names of the five pins through which the activation path passes between the fail FF and the seven input side FFs are p1 to p5, respectively.

  Further, the thick solid lines in FIG. 11B and FIG. 11D to FIG. 11H indicate paths searched for first in each procedure of depth-first search. In FIG. 11C to FIG. 11H, the blowing block attached to each circular block indicating a pin is filled in by the path trace unit 12 with the number of activation paths deeper than the pin. Label. Each label is actually stored in the storage unit 20 in association with the pin name of each pin.

  First, as indicated by an arrow A1 in FIG. 11B, the path trace unit 12 searches for a toggle pin from the toggle pin p0 of the fail FF (F0) as a starting point toward the depth direction (left direction in the figure; input side). To reach the input side FF (F1) via the pins p1 and p3. Thereby, the path p0 → p1 → p3 → F1 is traced as the first activation path. Then, as indicated by an arrow A2 in FIG. 11C, the path trace unit 12 returns to the pin p3 connected to the input side FF (F1), enters the count value 1 on the label of the pin p3, and then returns to the pin p3. The input side FF or toggle pin other than F1 on the deeper side is searched.

  In the example shown in FIG. 11A, since F2 is connected to the pin p3 in addition to F1, the path trace unit 12 searches for F2, as indicated by an arrow A3 in FIG. As a result, the path p0 → p1 → p3 → F2 is traced as the second activation path. Then, the path trace unit 12 returns to the pin p3 as indicated by the arrow A4 in the figure, and adds 1 to the count value 1 at the pin p3, so that the label of the pin p3 has a deeper side than the pin p3. Enter the number 2 of activation paths.

  Since no input side FF or toggle pin other than F1 and F2 is connected to the pin p3, the path trace unit 12 returns to the pin p1 as indicated by an arrow A5 in FIG. After entering the count value 2 at the pin p3, a search is made for a toggle pin other than the pin p3 on the deeper side than the pin p1. In the example shown in FIG. 11A, since the pin p4 is connected to the pin p1 in addition to the pin p3, the path trace unit 12 searches for the pin p4 and further uses arrows A6 to A8 in FIG. 11E. As shown, F3 and F4 on the deeper side than the pin p4 are searched. Accordingly, the path p0 → p1 → p4 → F3 and the path p0 → p1 → p4 → F4 are regarded as the third and fourth activation paths. At this time, the number of activation paths 2 deeper than the pin p4 is entered in the label of the pin p4.

  Since no input side FF or toggle pin other than F3 and F4 are connected to the pin p4, the path trace unit 12 returns to the pin p1 as indicated by an arrow A9 in FIG. Then, the path trace unit 12 adds the count value 2 at the pin p4 to the count value 2 at the pin p1, thereby adding the activation path number 4 deeper than the pin p1 to the label of the pin p1. Fill out. Further, since no toggle pins other than the pins p3 and p4 are connected to the pin p1, the path trace unit 12 returns to the pin p0 as indicated by an arrow A10 in FIG. After the count value 4 is entered, a toggle pin other than the pin p1 on the deeper side than the pin p0 is searched. In the example shown in FIG. 11A, since the pin p2 is connected to the pin p0 in addition to the pin p1, the path trace unit 12 searches for the pin p2 as indicated by an arrow A11 in FIG. 11F. .

  When searching for the pin p2, the path trace unit 12 sequentially searches for the three pins p3 to p5 on the deeper side than the pin p2, as indicated by arrows A12 to A14 in FIG. When the path trace unit 12 searches for the pin p3, the search for the activation path deeper than the pin p3 has already been completed. Therefore, the search is not performed, and the count value 2 at the pin p3 is the label of the pin p2. To fill in. Next, when the path trace unit 12 searches for the pin p4, the search for the activation path deeper than the pin p4 has already been completed. Therefore, the search is not performed, and the count value 2 at the pin p4 is set to the pin p2. Is added to the count value 2 and 4 is entered as the count value in the label of the pin p2.

  Further, when searching for the pin p5, the path trace unit 12 sequentially searches the three input side FFs (F5 to F7) on the deeper side than the pin p5 as indicated by arrows A15 to A18 in FIG. . Thereby, the path p0 → p2 → p5 → F5, the path p0 → p2 → p5 → F6 and the path p0 → p2 → p5 → F7 are traced as activation paths. At this time, the number of activation paths 3 on the deeper side than the pin p5 is entered in the label of the pin p5.

  Since no input side FF or toggle pin other than F5 to F7 is connected to the pin p5, the path trace unit 12 returns to the pin p2 as indicated by an arrow A19 in FIG. By adding the count value 3 at the pin p5 to the numerical value 4, the number 7 of activation paths deeper than the pin p2 is entered on the label of the pin p2. Further, since no toggle pins other than the pins p3 to p5 are connected to the pin p2, the path trace unit 12 returns to the pin p0 as indicated by an arrow A20 in FIG. The path trace unit 12 adds the count value 7 at the pin p0 to the count value 4 at the pin p0, thereby adding the number 11 of activation paths deeper than the pin p0 to the label of the pin p0. Fill out. Since no toggle pins other than the pins p1 and p2 are connected to the pin p0, the path trace unit 12 completes the activation path depth priority search and count processing for the fail FF (F0) at this time. To do. That is, 11 is counted as the number of activation paths for the fail FF (F0) shown in FIG.

  In this manner, the path trace unit 12 performs a depth-first search from the toggle pin of the fail FF to be counted, and assigns the number of activation paths deeper than that pin to each pin as a label. And count the number of activation paths. At this time, if the path trace unit 12 reaches the pin assigned the label with the count value by the backward trace, the path trace unit 12 fills in the label attached to the pin without performing the trace after the pin. The counted value is read and added to the counted value written on the label of the pin shallower than the pin. As a result, the activation path can be counted very quickly. The count value thus counted, that is, the number of activation paths, is stored in the activation path trace result database 25.

[3] Effect of Activation Path Extraction Device of this Embodiment In this embodiment, the simulation unit 11 simply performs a delay test simulation for an actual chip without considering the delay time, and at the time of the delay test, The change of the signal value of each pin between the input side FF101 and the output side FF102 is followed. As a result, the activation path through which the signal propagates during the delay test of the actual chip is extracted at high speed based on the test pattern during the delay test. In particular, by setting the fail FF as a trace target, an activation path that is highly likely to be related to a delay of the fail FF, that is, a failure, necessary for performing the speed path analysis can be extracted quickly and reliably. Thereby, the time and cost required for failure diagnosis can be significantly reduced. At this time, since the simulation unit 11 validates the information obtained by the simulation when the output value and the expected value all match, the reliability of the simulation is ensured.

  In the present embodiment, in a simulation that does not consider timing, a glitch appears as a signal waveform that maintains the indefinite value x for a predetermined time. As a result, the simulation unit 11 can reliably identify the toggle pin and list the pin name in the toggle pin information list 23 without overlooking the signal value change due to the glitch while performing the high-speed simulation. Therefore, it is possible to perform failure diagnosis taking glitches into account, and the reliability of failure diagnosis is improved.

  Furthermore, in this embodiment, since the signal value that has reached the data pin or the IH pin is not maintained at the indefinite value x, both the data path and the IH path can be performed without hindering the normal operation of the simulation. The target can be specified and extracted as an activation path. Further, the activation function to be traced is narrowed down by the determination function of the path trace unit 12, and tracing is performed for the narrowed activation path. Therefore, information on the activation path necessary for speed path analysis is obtained. Extracted faster and more reliably.

  Further, the activation path counting process is executed before the trace process is executed, and the number of activation paths to be traced is counted for each fail FF, so that the designer can activate each fail FF. By referring to the number of paths, various determinations such as which fail FFs are targeted for activation path tracing can be performed before the start of the tracing process.

  In the counting process, when the path trace unit 12 reaches a pin assigned with a count value in a backward trace based on a depth-first search, the path trace unit 12 assigns the pin to the pin without performing the trace after the pin. The count value written on the label is read and added to the count value written on the label of the pin shallower than the pin. As a result, the activation path can be counted very quickly.

[4] Others While the preferred embodiment of the present invention has been described in detail above, the present invention is not limited to such a specific embodiment, and various modifications and changes can be made without departing from the spirit of the present invention. It can be changed and implemented.
In the above-described embodiment, the path trace unit 12 traces the activation path by the backward trace from the output side FF102 to the input side FF101, but by the forward trace from the input side FF101 to the output side FF102. The activation path may be traced. In the above-described embodiment, the path trace unit 12 traces the activation path by the depth-first search. However, the path trace unit 12 may trace the activation path by the width-first search.

  In addition, all or a part of the functions as the simulation unit 11 and the path trace unit 12 described above and the function for automatically adding the description defining the indefinite value setting means are implemented by a computer (CPU, information processing apparatus, various terminals). Are implemented) by executing a predetermined application program (activation path extraction program).

  The program is, for example, a flexible disk, CD (CD-ROM, CD-R, CD-RW, etc.), DVD (DVD-ROM, DVD-RAM, DVD-R, DVD-RW, DVD + R, DVD + RW, Blu-ray disc, etc.) And the like recorded in a computer-readable recording medium. In this case, the computer reads the program from the recording medium, transfers it to the internal storage device or the external storage device, and uses it.

  Here, the computer is a concept including hardware and an OS (operating system), and means hardware operating under the control of the OS. Further, when the OS is unnecessary and the hardware is operated by the application program alone, the hardware itself corresponds to the computer. The hardware includes at least a microprocessor such as a CPU and means for reading a computer program recorded on a recording medium. The activation path extraction program includes program code for realizing the functions of the simulation unit 11 and the path trace unit 12 and the function of automatically adding the description defining the indefinite value setting means in the computer as described above. Yes. Also, some of the functions may be realized by the OS instead of the application program.

[5] Supplementary Notes The following supplementary notes are further disclosed regarding the embodiment including the above-described embodiment.
(Appendix 1)
In the computer that extracts the activation path that the signal propagated during the delay test on the actual chip,
By performing a simulation of the delay test based on the test pattern at the time of the delay test and the net list of the actual chip, the signal value change pin that has changed the signal value at the time of the delay test,
Tracing the activation path by following the signal value change pin based on the signal value change pin specified by the simulation and the netlist of the real chip;
Activation path extraction program that executes processing.

(Appendix 2)
When the signal value of the output pin of the input side flip-flop or latch changes during the execution of the simulation, an indefinite value is set for a predetermined time between the signal value before the change of the output pin and the signal value after the change,
The signal value change pin is identified by performing the simulation without considering timing based on the signal value set with the indefinite value.
The activation path extraction program according to appendix 1, which causes the computer to execute processing.

(Appendix 3)
The activation path extraction program according to appendix 2, wherein the function of setting the indefinite value is realized by a description of source code defining the input-side flip-flop or latch included in the netlist of the real chip.
(Appendix 4)
The activation path extraction program according to appendix 2 or appendix 3, wherein the predetermined time is set longer than an internal delay value of each cell in the netlist and shorter than a clock cycle in the simulation.

(Appendix 5)
The output value obtained by the simulation is compared with the expected value included in the test pattern, and when the output value and the expected value match, the information on the activation path specified by the simulation is validated. The activation path extraction program according to any one of Supplementary Note 1 to Supplementary Note 4, which causes the computer to execute processing to be performed.

(Appendix 6)
Supplementary notes 1 to 5 that cause the computer to execute the process of performing the trace starting from a signal value change pin of an output side flip-flop or latch that outputs a value different from an expected value in the delay test of the real chip The activation path extraction program according to any one of the above.

(Appendix 7)
By the simulation, specify the value of the clock control system pin of the output side flip-flop or latch,
A data path to an output-side flip-flop or latch that outputs a value different from an expected value in the delay test of the real chip based on the value of the signal value change pin and the clock control system pin specified by the simulation, and Determine which path of the clock control system path may be involved in the failure, and use the signal value change pin for the path that may be involved in the failure as the starting point. Tracing
The activation path extraction program according to any one of supplementary notes 1 to 5, which causes the computer to execute processing.

(Appendix 8)
The activation path extraction program according to appendix 6 or appendix 7, which causes the computer to execute a process of performing the trace by depth-first search from the starting point.
(Appendix 9)
The activation path extraction program according to any one of appendix 1 to appendix 8, which causes the computer to execute a process of counting the number of activation paths by tracing the signal value change pin.

(Appendix 10)
A depth-first search is performed from the signal value change pin of the target flip-flop or latch, and the signal value change pin is traced to each pin while giving the number of activation paths deeper than that pin as a label. The activation path extraction program according to appendix 9, which causes the computer to execute a process of counting the number of the activation paths.

(Appendix 11)
An activation path extraction device that extracts an activation path through which a signal has propagated during a delay test on an actual chip,
A simulation unit for identifying a signal value change pin whose signal value has changed during the delay test by performing a simulation of the delay test based on a test pattern in the delay test and a net list of the real chip;
An activation path extraction device comprising: a path trace unit that traces the activation path by tracing the signal value change pin based on the signal value change pin specified by the simulation unit and a net list of the real chip. .

(Appendix 12)
When the signal value of the output pin of the input side flip-flop or latch changes during the execution of the simulation, an indefinite value is set for a predetermined time between the signal value before the change of the output pin and the signal value after the change. Further comprising value setting means,
The activity according to claim 11, wherein the simulation unit specifies the signal value change pin by performing the simulation without considering timing based on the signal value for which the indeterminate value is set by the indeterminate value setting unit. Path extractor.

(Appendix 13)
The activation path extraction device according to appendix 12, wherein the function as the indefinite value setting means is realized by a description of source code defining the input side flip-flop or latch included in the net list of the real chip.
(Appendix 14)
14. The activation path extraction device according to appendix 12 or appendix 13, wherein the predetermined time is set longer than an internal delay value of each cell in the net list and shorter than a clock cycle in the simulation.

(Appendix 15)
The simulation unit compares an output value obtained by the simulation with an expected value included in the test pattern, and if the output value and the expected value match, the activation path specified by the simulation The activation path extraction device according to any one of Supplementary Note 11 to Supplementary Note 14, which validates the information.

(Appendix 16)
Any one of appendix 11 to appendix 15, wherein the path trace unit performs the trace from a signal value change pin of an output flip-flop or a latch that outputs a value different from an expected value in the delay test of the real chip. The activation path extracting device according to claim 1.

(Appendix 17)
The simulation unit specifies the value of the clock control system pin of the output side flip-flop or latch by the simulation,
The path trace unit is an output side flip-flop that outputs a value different from an expected value in the delay test of the real chip based on the value of the signal value change pin and the clock control system pin specified by the simulation unit. Or, determine which of the data path to the latch and the clock control system path may be involved in the failure, and use the signal value change pin related to the path that may be involved in the failure as a starting point. The activation path extraction device according to any one of appendix 11 to appendix 15, which traces a possible activation path.

(Appendix 18)
The activation path extraction device according to appendix 16 or appendix 17, wherein the path trace unit performs the trace by depth-first search from the starting point.
(Appendix 19)
The path trace unit performs a depth-first search from the signal value change pin of the target flip-flop or latch, and assigns the number of activation paths deeper than the pin to each pin as a label. The activation path extraction device according to any one of appendix 11 to appendix 18, wherein the number of the activation paths is counted by tracing a change pin.

(Appendix 20)
An activation path extraction method in which an activation path through which a signal propagates during a delay test on an actual chip is extracted by a computer,
By performing a simulation of the delay test based on the test pattern at the time of the delay test and the netlist of the actual chip, the signal value change pin that has changed the signal value during the delay test is specified,
An activation path extraction method for tracing the activation path by tracing the signal value change pin based on the signal value change pin specified by the simulation and a net list of the real chip.

DESCRIPTION OF SYMBOLS 1 Activation path extraction apparatus 10 Processing part (computer)
DESCRIPTION OF SYMBOLS 11 Simulation part 12 Path trace part 20 Memory | storage part 21 Delay test result database 211 Test pattern 212 Fail list 22 Net list (Verilog source code; undefined value setting means)
23 Toggle pin information list (Signal value change pin information list)
24 Clock control system pin information list 25 Activation path trace result database 101 Input side flip-flop (or latch)
102 Output side flip-flop (or latch)
103 OR gate 104 AND gate

Claims (7)

In the computer that extracts the activation path that the signal propagated during the delay test on the actual chip,
By performing a simulation of the delay test based on the test pattern at the time of the delay test and the net list of the actual chip, the signal value change pin that has changed the signal value at the time of the delay test,
Tracing the activation path by following the signal value change pin based on the signal value change pin specified by the simulation and the netlist of the real chip;
Activation path extraction program that executes processing. If the signal value of the output pin of the input side flip-flop or latch changes during the execution of the simulation, an indefinite value is set for a predetermined time between the signal value before the change of the output pin and the signal value after the change And
The signal value change pin is identified by performing the simulation without considering timing based on the signal value set with the indefinite value.
The activation path extraction program according to claim 1, which causes the computer to execute processing.   The activation path extraction program according to claim 2, wherein the function of setting the indefinite value is realized by a description of a source code that defines the input-side flip-flop included in the net list of the real chip.   4. The activation path extraction program according to claim 2, wherein the predetermined time is set longer than an internal delay value of each cell in the net list and shorter than a clock cycle in the simulation. By the simulation, specify the value of the clock control system pin of the output side flip-flop or latch,
A data path to an output-side flip-flop or latch that outputs a value different from an expected value in the delay test of the real chip based on the value of the signal value change pin and the clock control system pin specified by the simulation, and Determine which path of the clock control system path may be involved in the failure, and use the signal value change pin for the path that may be involved in the failure as the starting point. Tracing
The activation path extraction program according to any one of claims 1 to 4, which causes the computer to execute processing. An activation path extraction device that extracts an activation path through which a signal has propagated during a delay test on an actual chip,
A simulation unit for identifying a signal value change pin whose signal value has changed during the delay test by performing a simulation of the delay test based on a test pattern in the delay test and a net list of the real chip;
A path trace unit that traces the activation path by tracing the signal value change pin based on the signal value change pin specified by the simulation unit and the netlist of the real chip; apparatus. An activation path extraction method in which an activation path through which a signal propagates during a delay test on an actual chip is extracted by a computer,
By performing a simulation of the delay test based on the test pattern at the time of the delay test and the netlist of the actual chip, the signal value change pin that has changed the signal value during the delay test is specified,
An activation path extraction method for tracing the activation path by tracing the signal value change pin based on the signal value change pin specified by the simulation and a net list of the real chip.

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