JP2012120355A - Power supply device and semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the reliability of a multiphase-type power supply device.SOLUTION: A power supply device comprises, for example, a plurality of inductors L[1] to L[m] and a plurality of driving units DRIC[1] to DRIC[m] for driving the inductors. Each driving unit DRIC[n] has a short-circuit detection circuit SDETC[n]. The SDETC[n] drives an external terminal (SDET[n]) through a short-circuit detection output circuit SDETIF[n] when an excessive current flows into a high-side transistor QH[n] (or a low-side transistor QL[n]). The external terminal (SDET[n]) of each DRIC[n] is commonly connected to a bus SBS, and each DRIC[n] can recognize through the SBS that a short circuit is detected in any of the DRIC [1] to DRIC[m].

Description

  The present invention relates to a power supply device and a semiconductor device, for example, to a technology effective when applied to a multiphase switching power supply device that converts a high voltage to a low voltage and a semiconductor device that is one of its components.

  For example, Patent Document 1 describes a semiconductor device in which a power MOSFET, a drive circuit that drives the power MOSFET, and a control circuit that transmits a switching control signal to the drive circuit are mounted in one package. This semiconductor device is capable of multi-phase operation. Patent Document 2 discloses a MOS power element with a load short-circuit protection function. Japanese Patent Application Laid-Open No. 2003-228561 discloses a configuration in which power supply to a driver is interrupted when a driver element for driving a solenoid load fails. In the failure diagnosis of the driver element, the drive control signal of the driver element is compared with the output, and the diagnosis is performed based on a predetermined correspondence relationship.

JP 2008-17620 A JP-A-5-327442 JP 2003-47148 A

  For example, in various electronic devices such as personal computers (hereinafter referred to as PCs) and electrical devices, a desired DC voltage (for example, 12V, 5V, 3.3V, etc.) is obtained from an AC voltage (for example, 100V) as a commercial power source. An AC / DC converter is provided. In a notebook PC or the like, a DC voltage having a specific value is supplied by a battery. In various semiconductor components used for PCs or the like, a stable power supply voltage is required, and in some cases, a plurality of power supply voltage values are required. For this reason, the voltage generated by the AC / DC converter and the battery is converted into a predetermined voltage (eg, 1.0 V) and a stable voltage by a step-down non-insulated DC / DC converter (buck converter). It is supplied to various load circuits such as a CPU (Central Processing Unit). These are generally called a POL (point of load) converter or the like. For example, in the case of a PC, they are mounted in the vicinity of various load circuits on a PCB (Printed Circuit Board) such as a motherboard.

  In recent years, with such POL converters, demands for higher current, faster response, and stabilization are increasing with the reduction in voltage and speed of various load circuits. In order to satisfy such a requirement, for example, as disclosed in Patent Document 1, it is beneficial to use a multi-phase technique that supplies power to a load circuit from a plurality of inductors in different phases. 20A and 20B show a multi-phase type power supply device studied as a premise of the present invention, in which FIG. 20A is a schematic diagram showing a configuration example thereof, and FIG. 20B shows a schematic operation example of FIG. It is a waveform diagram. 20A includes a PWM (Pulse Width Modulation) control unit PCTLIC, a plurality (four in this case) of drive units DRIC ′ [1] to DRIC ′ [4], and a plurality of inductors L [ 1] to L [4]. Each of these components is appropriately mounted on the same PCB, for example.

  The PWM control unit PCTLIC outputs a PWM signal (pulse width modulation signal) PWM [n] to each drive unit DRIC ′ [n] (n = 1 to 4). As shown in FIG. 20 (b), PWM [n] and PWM [n + 1] are 90 degrees out of phase. As a result, DRIC '[n] distributes and supplies power to the load circuit LOD (and output capacitance Cld) in different phases (multiphase) via the corresponding inductor L [n]. The PCTLIC receives the current information flowing through L [n] and the voltage information of the output power supply node VO connected to the LOD as the feedback signal FB, and based on this, supplies the power supplied to the LOD (Cld) to each phase. The duty of PWM [n] is appropriately controlled so that it can be evenly distributed.

  FIGS. 21A and 21B are diagrams illustrating an example of an internal configuration of each drive unit DRIC ′ [n] in FIG. 20 and an example of the problem thereof. FIG. 22 is a supplementary diagram of FIGS. 21A and 21B and is a top view showing a package configuration example of each drive unit DRIC ′ [n]. As shown in FIGS. 21A and 21B, the DRIC ′ [n] includes transistors QH [n] and QL [n] and a control unit CTLU ′ [n]. QH [n] is provided between a power supply voltage VIN (for example, 12V or 19V) and an external output terminal (switch signal VSWH [n]), and QL [n] is connected to an external output terminal (VSWH [n]). Provided between ground power supply voltage PGND. The external output terminal (VSWH [n]) is connected to a corresponding inductor L [n] as shown in FIG. CTLU '[n] complementarily controls on / off of QH [n] and QL [n] in accordance with PWM [n] from PCTLIC.

  In such a configuration, as shown in FIG. 21A, for example, when the external output terminal (VSWH [n]) and the ground power supply voltage PGND are short-circuited by the failure path FP1, QH [n] is controlled to be on. At this time, a through current flows along a route of VIN → QH [n] → FP1, and QH [n] may be thermally destroyed. Similarly, as shown in FIG. 21B, for example, when the power supply voltage VIN and the external output terminal (VSWH [n]) are short-circuited by the failure path FP2, VIN → There is a possibility that a through current flows through the route of FP2 → QL [n], and QL [n] is thermally destroyed. In this case, when QL [n] is off, excessive power is supplied to the load circuit through the path VIN → FP2, and the load circuit may be destroyed.

  Here, such failure paths FP1 and FP2 are, for example, as shown in FIG. 22, a solder bridge (FP2) between the VIN external terminal P14 and the VSWH external terminal P15 adjacent to each other, or the VSWH adjacent to each other. This may occur at a solder bridge (FP1) between the external terminal P29 for PND and the external terminal P28 for PGND. Since such external terminal allocation methods are universally determined to some extent, it is difficult to take measures by devising external terminal allocation methods. Although not shown, for example, a heat sink or the like may be mounted on each drive unit DRIC '[n], and it is considered that failure paths FP1 and FP2 occur due to misalignment of the heat sink.

  If such a failure path FP1, FP2 occurs, for example, the drive unit DRIC ′ [n] detects its own failure and controls the transistors QH [n], QL [n] to turn off. It is conceivable to protect this. However, in the case of the multi-phase type power supply device as shown in FIG. 20, the PWM control unit PCTLIC performs control so that the output current flows evenly in each phase, and thus one or more DRIC ′ [n When the protection described above is performed, there are concerns about the following. First, since the output current increases in DRIC ′ [n] other than the protected DRIC ′ [n], an overcurrent state occurs and QH [n] and QL [n] in the DRIC ′ [n] There is a risk of being destroyed. In addition, in DRIC ′ [n] other than the protected DRIC ′ [n], the output current becomes non-uniform, the PWM [n] from the PCTLIC malfunctions, and the voltage of the output power supply node VO is controlled to a desired value. There is a fear that it cannot be done. In this case, the load circuit may be destroyed in the worst case.

  The present invention has been made in view of the above, and one of its purposes is to provide a multi-phase power supply device capable of improving reliability and a semiconductor device as one of its components. There is to do. The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of a typical embodiment will be briefly described as follows.

  The power supply device according to the present embodiment drives a plurality of inductors, a PWM control unit that generates a plurality of pulse width modulation signals with different phases, and a plurality of inductors with different phases according to the plurality of pulse width modulation signals. A plurality of drive units, a power supply unit that supplies a power supply voltage for driving the inductor to the plurality of drive units, and a common bus. Each drive unit includes a high-side transistor that connects one end of the inductor to the power supply voltage for driving the inductor, a low-side transistor that connects one end of the inductor to the ground power supply voltage, and a current flowing through the high-side transistor has a predetermined value. And a short-circuit detection circuit that drives the common bus to the first logic level via the external terminal when it is greater than

  Using such a configuration example, each drive unit can recognize that a short circuit has occurred in any of the plurality of drive units via the wired OR logic of the common bus, for example, its own high-side transistor It is possible to perform appropriate protection such as controlling the power off. Also, the power supply unit can recognize the presence or absence of a short circuit in each drive unit via the wired or logic of the common bus, and can perform appropriate protection such as stopping the supply of power supply voltage for driving the inductor. It becomes possible. In addition, since each drive unit is configured by one semiconductor package, a predetermined value that is a determination condition of the short circuit detection circuit can be set with high accuracy. For these reasons, it is possible to improve the reliability of the multi-phase power supply device.

  Further, the semiconductor device according to the present embodiment includes a first chip in which the above-described high-side transistor is formed, a second chip in which the low-side transistor is formed, a short-circuit detection circuit, and a driver in one semiconductor package. A third chip on which a circuit or the like is formed, first to third die pads on which the first to third chips are mounted, a first connection portion, and the like are provided. The high-side transistor and the low-side transistor are formed by vertical MISFETs, and the high-side transistor receives the power supply voltage for driving the inductor supplied from the first die pad at the back electrode (drain electrode) and is driven on by the driver circuit. Then, the power supply voltage is connected to the surface electrode (source electrode). The first connection portion connects the surface electrode to the second die pad, and a power supply voltage for driving the inductor is supplied from the second die pad to the inductor. Here, the short-circuit detection circuit short-circuits by monitoring the potential difference between the voltage drawn from the surface electrode (source electrode) of the high-side transistor via the bonding wire and the voltage drawn from the second die pad via the bonding wire. Perform detection.

  When such a configuration example is used, since the area of the second die pad is usually large, the bonding wire can be easily mounted. In addition, since the short circuit is detected using the parasitic components (parasitic resistance, parasitic inductor) of the first connection portion and the second die pad, for example, the detection can be performed using a transient state due to the parasitic inductor. Can be sufficiently dealt with even when the power is small (that is, when the power loss is small).

  Of the inventions disclosed in the present application, the effects obtained by the representative embodiments will be briefly described. As a result, it is possible to improve the reliability of the multiphase power supply device.

BRIEF DESCRIPTION OF THE DRAWINGS The power supply device by Embodiment 1 of this invention is shown, (a) is the schematic which shows the structural example of the principal part, (b) is the schematic which shows the structural example of each drive unit in (a). is there. (A), (b) shows the structural example which expanded the power supply device of FIG. 1, and is the schematic which shows an example of the process of the PWM control unit according to the short circuit detection in FIG. (A) is the schematic which shows the structural example of the PWM control unit in Fig.2 (a), (b) is a wave form diagram which shows the operation example of Fig.3 (a). In the power supply device by Embodiment 2 of this invention, it shows the structural example which expanded the power supply device of FIG. 1, and is the schematic which shows an example of the process of the power supply unit according to the short circuit detection in FIG. . It is a block diagram which shows the detailed structural example of the power supply unit in FIG. In the power supply device by Embodiment 3 of this invention, it is a block diagram which shows an example of the whole structure. It is a block diagram which shows the detailed structural example of each drive unit in FIG. FIG. 8 shows a detailed package configuration example of the drive unit of FIG. 7, (a) is a top view thereof, (b) is a top view showing an example of the internal configuration of (a), and (c) is each of FIG. It is a top view which shows the example of a pad arrangement | positioning of a semiconductor chip. FIGS. 7 and 8 are cross-sectional views showing examples of the device structure of a semiconductor chip on which a high-side transistor is formed. FIG. 8 shows details of a high-side driver circuit and a short-circuit detection circuit in the drive unit of FIG. 7, (a) is a circuit diagram showing a configuration example thereof, and (b) and (c) are operation examples of (a). FIG. FIG. 11 is a supplementary diagram of FIG. 10, and is a top view illustrating a package configuration example of a drive unit including the configuration example of FIG. 10. FIG. 8 shows details of a high-side driver circuit and a short-circuit detection circuit in the drive unit of FIG. 7 in the power supply device according to Embodiment 4 of the present invention, (a) is a circuit diagram showing a configuration example thereof, (b). (A) is a circuit diagram showing a configuration example of the delay circuit in (a), (c) is a waveform diagram showing an operation example of (a). FIG. 8 shows details of a high-side driver circuit and a short-circuit detection circuit in the drive unit of FIG. 7 in the power supply device according to Embodiment 5 of the present invention, (a) is a circuit diagram showing a configuration example thereof, (b). FIG. 6 is a waveform diagram showing an example of operation of (a). FIG. 8 shows details of a high-side driver circuit and a short-circuit detection circuit in the drive unit of FIG. 7 in the power supply device according to Embodiment 6 of the present invention, (a) is a circuit diagram showing a configuration example thereof, (b). And (c) are waveform diagrams showing an operation example of (a). FIG. 15 is a supplementary diagram of FIG. 14, and is a top view illustrating a package configuration example of a drive unit including the configuration example of FIG. 14. FIG. 8 shows details of a low-side driver circuit and a short-circuit detection circuit in the drive unit of FIG. 7 in the power supply device according to Embodiment 7 of the present invention, where (a) is a circuit diagram showing a configuration example thereof, (b) and (C) is a wave form diagram which shows the operation example of (a). FIG. 17 is a supplementary diagram of FIG. 16, and is a top view illustrating a package configuration example of a drive unit including the configuration example of FIG. 16. In the power supply device by Embodiment 8 of this invention, it is a top view which shows the structural example of the one part board | substrate layout. It is a top view which shows the structural example of the board | substrate layout of the multiphase type power supply device formed by extending FIG. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 illustrates a multi-phase power supply device studied as a premise of the present invention, where (a) is a schematic diagram illustrating a configuration example thereof, and (b) is a waveform diagram illustrating a schematic operation example of (a). . (A), (b) is a figure which shows an example of an internal structure of each drive unit in FIG. 20, and an example of the problem. It is a supplementary figure of Drawing 21 (a) and (b), and is a top view showing an example of package composition of each drive unit.

  In the following embodiment, when it is necessary for the sake of convenience, the description will be divided into a plurality of sections or embodiments. However, unless otherwise specified, they are not irrelevant, and one is the other. Some or all of the modifications, details, supplementary explanations, and the like exist. Further, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), especially when clearly indicated and when clearly limited to a specific number in principle, etc. Except, it is not limited to the specific number, and may be more or less than the specific number.

  Further, in the following embodiments, the constituent elements (including element steps and the like) are not necessarily indispensable unless otherwise specified and apparently essential in principle. Needless to say. Similarly, in the following embodiments, when referring to the shapes, positional relationships, etc. of the components, etc., the shapes are substantially the same unless otherwise specified, or otherwise apparent in principle. And the like are included. The same applies to the above numerical values and ranges.

  The circuit elements constituting each functional block of the embodiment are not particularly limited, but are formed on a semiconductor substrate such as single crystal silicon by a known integrated circuit technology such as a CMOS (complementary MOS transistor). . Note that in the embodiment, when a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) (or abbreviated as a MOS transistor) is described, a non-oxide film is not excluded as a gate insulating film.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiment, and the repetitive description thereof will be omitted.

(Embodiment 1)
<< Basic configuration of power supply (main part) >>
FIG. 1 shows a power supply device according to Embodiment 1 of the present invention. FIG. 1 (a) is a schematic diagram showing a configuration example of a main part thereof, and FIG. 1 (b) is a diagram of FIG. 1 (a). It is the schematic which shows the structural example of a drive unit. The power supply device shown in FIG. 1A includes m drive units DRIC [1] to DRIC [m] (m is an integer of 2 or more), and m inductors having one end commonly connected to the output power supply node VO. L [1] to L [m], a bus SBS commonly connected to DRIC [1] to DRIC [m], and a resistor Rp that pulls up SBS to the power supply voltage VCC. L [1] to L [m] are driven in different phases (multiphase) by DRIC [1] to DRIC [m], respectively, and supply power to a load circuit (not shown) in different phases via VO. Supply. Here, DRIC [1] to DRIC [m] are realized by independent semiconductor packages, and are mounted on a wiring board (PCB) such as a mother board together with L [1] to L [m]. The SBS is realized by a wiring pattern on the PCB.

  Each drive unit (semiconductor device) DRIC [n] (n = 1, 2,..., M) includes transistors (power transistors) QH [n], QL [n], as shown in FIG. A driver circuit DV [n], a short circuit detection circuit SDETC [n], and a short circuit detection output circuit SDETIF [n] are provided. Here, n-channel MOSFETs (power MOSFETs) are used for QH [n] and QL [n]. QH [n] forms a source / drain path between the power supply voltage VIN and the external output terminal (switch signal VSWH [n]), and QL [n] connects to the external output terminal (VSWH [n]) and the ground power supply voltage PGND. A source / drain path is formed between the two. DV [n] controls on / off of QH [n] and QL [n].

  The short circuit detection output circuit SDETIF [n] includes a resistor R1 [n] and an n-channel MOS transistor MNd [n]. The short-circuit detection circuit SDETC [n] determines the presence / absence of the failure paths (short-circuit paths) FP1 and FP2 as shown in FIGS. 21A and 21B. n] is turned on. MNd [n] has a source connected to the ground power supply voltage GND and a drain connected to an external terminal (short-circuit detection signal SDET [n]) via R1 [n] (R1 [n] can be omitted). The The external terminal (SDET [n]) is commonly connected to the bus SBS as shown in FIG. Therefore, when one or more DRIC [n] detects a short circuit (when one or more of MNd [n] in each DRIC [n] is controlled to be on), the DRIC [n] SDET [n] is driven to the GND level, and SBS is pulled down from the VCC level to the GND level accordingly.

  A short-circuit detection result from each DRIC [n] output on the bus SBS is used as an enable signal EN by a PWM control unit PCTLIC, a power supply unit PWRCTL, or the like which will be described later. This EN can also be used as a control signal for DRIC [n] itself. For example, as shown in FIG. 1B, each DRIC [n] receives EN as a driver enable signal EN_D [n], and DV_n in each DRIC [n] is EN_D [n] is GND. When the level is reached, both QH [n] and QL [n] are controlled by turning off both QH [n] and QL [n]. In this case, when a short circuit is detected in at least one DRIC [n], all the DRIC [n] can recognize the detection result at an early stage via the bus SBS and have their own QH [n], QL [n] can be protected. In addition, when each DRIC [n] includes an external terminal (DRIC enable terminal) for controlling activation / deactivation of the entire DRIC [1] to DRIC [m], the external terminal Can also be used as an external terminal (SDET [n]) for short circuit detection.

  In this way, by using a configuration in which the detection result of the presence or absence of a short circuit in each DRIC [n] is output on the bus SBS by wired OR logic, it is possible to reduce the number of short circuits detected in at least one DRIC [n]. It is possible to notify all DRIC [n], the PWM control unit PCTLIC, and the power supply unit PWRCTL with the number (small area). For example, when a failure is detected in a certain phase, adverse effects such as destruction may occur in other phases other than the phase as described with reference to FIGS. 20 to 22, but the configuration example shown in FIG. 1 is used. Thus, the occurrence of a short circuit can be recognized in all phases at an early stage before destruction or the like occurs. As a result, appropriate protection can be achieved in all phases, and the reliability of the multiphase power supply apparatus can be improved.

  In this example, a pull-down configuration using MNd [n] as a switch is used as the wired OR logic. However, a pull-up configuration using a p-channel MOS transistor or the like can also be used. is there. However, since it is usually easier to increase the discharge rate than to increase the charge rate, the pull-down type configuration is better from the viewpoint of increasing the response speed of the enable signal EN (to protect early). desirable. Here, each DRIC [n] is configured by an independent semiconductor package. However, for example, two DRIC [n] may be configured by one semiconductor package.

<< Processing content when short circuit is detected [1] >>
2A and 2B show an example of a configuration in which the power supply device of FIG. 1 is expanded, and are schematic diagrams showing an example of processing of the PWM control unit PCTLIC in response to short circuit detection in FIG. . The power supply device in FIG. 2A has a configuration in which a PWM control unit PCTLIC is added to the power supply device in FIG. The PCTLIC outputs PWM signals (pulse width modulation signals) PWM [1] to PWM [m] to DRIC [1] to DRIC [m], respectively. However, when the PCTLIC detects the GND level of the enable signal ENp output via the bus SBS as described in FIG. 1, all the PWM [1] to PWM [m] are fixed to the off level. On the other hand, the power supply apparatus of FIG. 2B is further added with a CPU (Central Processing Unit) (or ASIC (Application Specific Integrated Circuit)) that controls the PCTLIC in addition to the power supply apparatus of FIG. It has a configuration. When the CPU (or ASIC) detects the GND level of the enable signal ENc output via the bus SBS, the CPU (or ASIC) controls the enable signal ENp of the PCTLIC to the off level, and the PCTLLIC responds to PWM [1]. -All PWM [m] are fixed to the off level.

  When these configuration examples are used, the output of PWM [n] from PCTLIC to DRIC [1] to DRIC [m] stops, and the entire power supply apparatus including PCTLIC and DRIC [1] to DRIC [m] Can be deactivated. As a result, the reliability of the multi-phase power supply device can be further improved.

  3A is a schematic diagram illustrating a configuration example of the PWM control unit PCTLIC in FIG. 2A, and FIG. 3B is a waveform diagram illustrating an operation example of FIG. 3A. The PWM control unit PCTLIC shown in FIG. 3A includes a comparator circuit CMPen and a pulse width modulation circuit PWMMOD. CMPen drives the PWM enable signal EN_PWM to the 'H' level when the voltage of the external terminal (enable signal ENp) falls below the comparison voltage Vr (eg, 1.0 V). Here, when no short circuit is detected in any of DRIC [1] to DRIC [m], the external terminal (ENp) is pulled up to the power supply voltage VCC (for example, 3.3 V) via the resistor Rp. Has been. In this case, EN_PWM is driven to the “L” level, and accordingly, PWMMOD outputs the pulse width modulation signals PWM [1] to PWM [m] in different phases toward DRIC [1] to DRIC [m]. Output. On the other hand, when a short circuit is detected in any one of DRIC [1] to DRIC [m], the external terminal (ENp) is pulled down to the GND level (0V). In this case, EN_PWM is driven to the 'H' level, and in response, PWMMOD fixes all of PWM [1] to PWM [m] to the 'L' level (off level).

  As described above, by using the power supply device according to the first embodiment, typically, it is possible to notify all phases of a failure of one or more phases at an early stage, thereby improving the reliability of the multiphase power supply device. It becomes feasible. In addition, since the area overhead associated with this failure notification is small, the multiphase power supply apparatus can be downsized.

(Embodiment 2)
In the second embodiment, processing contents different from those shown in FIGS. 2A and 2B performed when a short circuit is detected will be described.

<< Processing content when short circuit is detected [2] >>
FIG. 4 shows a configuration example in which the power supply device of FIG. 1 is expanded in the power supply device according to the second embodiment of the present invention, and an example of processing of the power supply unit PWRCTL corresponding to the short circuit detection in FIG. FIG. The power supply device of FIG. 4 has a configuration in which a power supply unit PWRCTL is added to the power supply device of FIG. PWRCTL includes a regulator circuit VREG. VREG supplies the power supply voltage VIN to the drive units DRIC [1] to DRIC [m] when the enable signal ENv output via the bus SBS as described in FIG. 1 is at the VCC level. On the other hand, VREG stops the operation of supplying VIN toward DRIC [1] to DRIC [m] when it detects the GND level of ENv.

  FIG. 5 is a block diagram showing a detailed configuration example of the power supply unit PWRCTL in FIG. The power supply unit PWRCTL shown in FIG. 5 is an AC / DC converter. PWRCTL converts a commercial power supply VAC such as 100 Vrms into a DC power supply while performing power factor correction (PFC). Further, with this DC power supply as an input, a plurality of regulator circuits VREG1, VREG2 and VREG3 are used to generate power supply voltages having different voltage values. In this example, VREG1 supplies a switch power supply voltage VIN (for example, 12V) toward DRIC [n] (n = 1, 2,..., M), and VREG2 is used for internal operation toward DRIC [n]. Power supply voltage VCIN (for example, 5 V) is supplied. In this example, VREG3 generates the power supply voltage VCC (for example, 3.3 V) as the pull-up voltage of the bus SBS described above. Here, VREG1 stops the supply operation of VIN when detecting the GND level of the enable signal ENv output on the bus SBS. The other regulator circuits VREG2 and VREG3 maintain the ENv state and thereby maintain the VREG1 stopped state, and thus continue the power supply operation.

  When such a configuration example is used, when the short circuit occurs in any one of DRIC [1] to DRIC [m], the power supply voltage VIN for the switch can be cut off, so that the reliability of the multiphase power supply device is further improved. Can be improved. That is, for example, when a failure path FP2 as shown in FIG. 21B occurs, each DRIC [n] is controlled by controlling QH [n] and QL [n] to be off as described in FIG. However, since the power supply to the load circuit LOD connected to the output power supply node VO continues, the LOD may not be sufficiently protected. Therefore, LOD can be sufficiently protected by blocking VIN. Note that the configuration example of FIG. 4 can be used in combination with the configuration example of FIG.

(Embodiment 3)
In the third embodiment, details of the entire power supply apparatus including the power supply apparatus of FIG. 1 will be described.

<< Configuration of power supply unit (overall) >>
FIG. 6 is a block diagram showing an example of the overall configuration of a power supply device according to Embodiment 3 of the present invention. The power supply device shown in FIG. 6 includes a PWM control unit PCTLIC, a power supply unit PWRCTL, m drive units DRIC [1] to DRIC [m], and m inductors L [1] to L [m]. Yes. One end of L [1] to L [m] is commonly connected to the output power supply node VO. Each DRIC [n] (n = 1, 2,..., M) includes transistors QH [n] and QL [n] and a control unit CTLU [that controls ON / OFF of QH [n] and QL [n]. n], and QH [n] and QL [n] are switching-controlled according to the pulse width modulation signal PWM [n]. Then, using this switching control, power is supplied to the load circuit LOD (and output capacitance Cld) via L [n] and VO. Each DRIC [n] is externally connected to a bootstrap capacitor Cb [n] for driving QH [n] sufficiently on.

  The PCTLIC includes a pulse width modulation circuit PWMMOD, a current detection circuit CSDET, a digital / analog conversion circuit DAC, and an error amplifier circuit EA. The DAC receives a digital signal representing a set value of the power supply voltage from a load circuit LOD such as a CPU, converts it into an analog signal, and outputs it to one of the two inputs in the EA. The voltage of the output power supply node VO is input to the other of the two inputs of EA as a feedback signal FB via a phase compensation circuit PHC provided outside. The EA amplifies the potential difference between the two inputs and outputs an error amplifier signal EO. CSDET detects, for example, currents flowing through L [1] to L [m], respectively, and outputs the detection result to PWMMOD. PWMMOD receives the output signals from EO and CSDET, determines the duty ratio so that the voltage of VO becomes the above-mentioned set value, and the current flowing through L [1] to L [m] is equal, and each has a different phase. PWM [1] to PWM [m] that are held are output. The PWRCTL supplies the switch power supply voltage VIN (for example, 12V) and the internal operation power supply voltage VCIN (for example, 5V) toward DRIC [1] to DRIC [m], and supplies the power supply voltage VDD ( For example, 3.3V) is supplied.

  In such a configuration, DRIC [1] to DRIC [m] are commonly connected to the short-circuit detection bus SBS as described above. SBS is pulled up by a power supply voltage VCC (for example, 3.3 V) supplied from PWRCTL via a resistor Rp. Here, when any of DRIC [1] to DRIC [m] detects a short circuit, SBS is pulled down to the GND level. Each DRIC [n] receives the GND level of the SBS and controls, for example, both QH [n] and QL [n] to be off as described in FIG. Further, the PWRCTL receives the SBS voltage as the enable signal ENv and cuts off the power supply voltage VIN as described in FIG. 4 when the GND level of ENv is detected. Further, the PCTLIC receives the SBS voltage as the enable signal ENp, and when detecting the GND level of the ENp, the PWM [1] to PWM [m] are set to the “L” level (off level) as described in FIG. ). As a result, as described in the first and second embodiments, it is possible to improve the reliability of the multiphase power supply device.

<< Detailed circuit configuration of drive unit DRIC >>
FIG. 7 is a block diagram showing a detailed configuration example of each drive unit DRIC [n] (DRIC) in FIG. The drive unit (semiconductor device) DRIC shown in FIG. 7 includes eight external terminals, and includes a control unit CTLU, transistors QH and QL, and diodes D1 and D2. The eight external terminals are for power supply voltage VIN, for switch signal VSWH, for ground power supply voltage PGND, for ground power supply voltage CGND, for pulse width modulation signal PWM, for short circuit detection signal SDET, for power supply voltage VCIN, For boosted voltage BOOT. Here, QH and QL are n-channel MOS transistors. QH has a drain connected to the external terminal (VIN), a source connected to the external terminal (VSWH), and QL has a drain connected to the external terminal (VSH). The source is connected to the external terminal (PGND). D1 and D2 are body diodes of MOS transistors, D1 has an anode connected to the source of QH, a cathode connected to the drain of QH, and D2 has an anode connected to the source of QL and a cathode connected to the drain of QL. The

  The control unit CTLU is operated by the power supply voltage VCIN and the ground power supply voltage CGND, and includes two sets of driver circuits and short circuit detection circuits DVh & SDETCh, DVl & SDETCl, a short circuit detection output circuit SDETIF, a level shift circuit LS, a PWM control circuit PWMCTL, A penetration prevention circuit DTCTL is provided. The PWMCTL receives a pulse width modulation signal of VDD (for example, 3.3 V) / GND level from the external terminal (PWM), and outputs a complementary signal of VCIN (for example, 5 V) / CGND level. One of the complementary signals is output to DVl & SDETCl as a pulse width modulation signal PWMl, and the other is output to DVh & SDETCh via LS as a pulse width modulation signal PWMh. At this time, PWMCTL makes a difference between PWMh transition timing and PWMl transition timing via DTCTL so that PWMh and PWMl do not simultaneously turn on (that is, no through current flows through QH and QL). Control to give it. The LS converts the VCIN / CGND level signal from the PWMCTL into a BOOT / VSWH level signal.

  The driver circuit and the short circuit detection circuit DVh & SDETCh control QH on / off by a BOOT / VSWH level gate signal in accordance with PWMh. At this time, DVh & SDECh monitors the current value flowing between VIN and VSWH, and when it is larger than a predetermined value, fixes QH to OFF and outputs a short circuit detection signal SDETh. The driver circuit and the short circuit detection circuit DVl & SDETCl control on / off of QL by a gate signal of VCIN / CGND level according to PWMl. At this time, DV1 & SDETCl monitors the value of the current flowing between VSWH and PGND, and when it is larger than a predetermined value, fixes QL, for example, and outputs a short circuit detection signal SDETl. For example, in the case shown in FIG. 21B, it is assumed that an excessive current flows through QL. From the viewpoint of protecting the load circuit LOD, QL is not fixed off but is fixed on. It is also possible to do.

  The short-circuit detection output circuit SDETIF pulls down the short-circuit detection signal SDET to the CGND level as described in FIG. 1B or the like when either one of the short-circuit detection signals SDETh and SDETl is output. Although not particularly limited, for example, a switch (MNd [n]) is provided in parallel in FIG. 1B and one of them is controlled by SDETh and the other is controlled by SDETL. In FIG. 7, SDET is also used as the driver enable signal EN_D, and when the PWM control circuit PWMCTL receives the CGND level of EN_D, both of the output signals (PWMh, PWMl) are fixed to the off level. . Therefore, as described in FIG. 1, it is possible to achieve appropriate protection not only when the own short circuit is detected but also when a short circuit is detected in a drive unit other than the own through this EN_D. In addition, although it was set as the structure provided with the short circuit detection circuit in both high side and low side here, depending on the case, it is also possible to set it as the structure provided only with one of them.

<< Detailed package structure of drive unit DRIC >>
8 shows a detailed package configuration example of the drive unit of FIG. 7, FIG. 8 (a) is a top view thereof, and FIG. 8 (b) is a top view showing an internal configuration example of FIG. 8 (a). FIG. 8C is a top view showing a pad arrangement example of each semiconductor chip in FIG. 8B. As shown in FIG. 8A, the drive unit (semiconductor device) DRIC includes, for example, a QFN (Quad Flat Non-leaded package) type surface mount type semiconductor package (sealing body) PKG. The material of PKG is, for example, an epoxy resin. As shown in FIG. 8B, the PKG has three die pads DP_HS, DP_LS, DP_CT mainly made of metal such as copper, and different semiconductor chips CP1 to CP3 are provided on each die pad. It is installed. That is, the drive unit DRIC shown in FIG. 8 is configured by a so-called MCP (Multi Chip Package).

  DP_HS has a structure integrated with an external terminal (lead) for the power supply voltage VIN, and the semiconductor chip CP1 on which the transistor QH in FIG. 7 is formed is mounted. DP_LS has a structure integrated with an external terminal (lead) for the switch signal VSWH, and the semiconductor chip CP2 on which the transistor QL in FIG. 7 is formed is mounted. The DP_CT has a structure integrated with an external terminal (lead) for the ground power supply voltage CGND, and the semiconductor chip CP3 on which the control unit CTLU in FIG. 7 is formed is mounted. DP_HS and DP_CT are arranged side by side in an approximately half region of PKG, and DP_LS is disposed in the remaining approximately half region of PKG. In the POL converter, since the on-period is usually several times longer than that of QH, here, CP2 (QL) is formed to be about twice as large as CP1 (QH), thereby reducing the loss due to on-resistance. We are trying to reduce it.

  In the semiconductor chip CP1, the transistor QH is formed as a vertical MOS transistor. The back surface of CP1 serves as a QH drain electrode, and VIN is supplied to the drain electrode via an external terminal for VIN and DP_HS. Further, as shown in FIG. 8C, pads PD_H_S1 to PD_H_S4 serving as QH source electrodes and pads PD_H_G serving as gate electrodes are formed on the surface of CP1. As shown in FIG. 8B, PD_H_S1 and PD_H_S2 are connected from above to a part of the metal plate MB1 having a material having high conductivity and heat conductivity such as copper. PD_H_S3 is connected to an external terminal (lead) for VSWH arranged around DP_HS via a bonding wire. PD_H_S4 is connected to a pad on the semiconductor chip CP3 (CTLU) via a bonding wire BW3, and PD_H_G is connected to a pad on the CP3 (CTLU) via a bonding wire BW1.

  In the semiconductor chip CP2, the transistor QL is formed as a vertical MOS transistor. The back surface of CP2 is a QL drain electrode, and this drain electrode is connected to an external terminal for VSWH via DP_LS. Further, on the surface of CP2, as shown in FIG. 8C, pads PD_L_S1 to PD_L_S4 serving as QL source electrodes and pads PD_L_G serving as gate electrodes are formed. As shown in FIG. 8B, PD_L_S1 to PD_L_S3 are connected from above to a part of the metal plate MB2 having a material having high conductivity and heat conductivity such as copper. PD_L_S4 is connected to a pad on the semiconductor chip CP3 (CTLU) via a bonding wire BW4, and PD_L_G is connected to a pad on the CP3 (CTLU) via a bonding wire BW2. In addition, the other part of the metal plate MB1 described above is connected to DP_LS, and the other part of the metal plate MB2 is connected to an external terminal for PGND arranged around DP_LS.

  CGND is supplied to the back surface of the semiconductor chip CP3 (CTLU) via an external terminal for CGND and DP_CT. A plurality of pads are formed on the surface of CP3 (CTLU), a part of which is connected to CP1 (QH) and CP (QL) via the aforementioned BW1 to BW4, and the other part is a bonding wire. Are connected to various external terminals (leads) for CTLU arranged around DP_CT. The various external terminals for CTLU include an external terminal (lead) for short circuit detection signal SDET, as shown in FIG. Although not shown, the back surfaces of DP_HS, DP_LS, and DP_CT are exposed from PKG (resin), and can be used as external electrodes in addition to external terminals (leads). As described above, DP_HS is an external electrode for VIN, DP_LS is an external electrode for VSWH, and DP_CT is an external electrode for CGND.

<< Device structure of drive unit >>
FIG. 9 is a cross-sectional view showing a device structure example of the semiconductor chip CP1 in which the high-side transistor QH is formed in FIGS. Here, the high-side transistor (power transistor) QH is taken as an example, but the low-side transistor QL has the same structure. The transistor QH is formed on the main surface of the semiconductor substrate 21 having a substrate body 21a made of n + type single crystal silicon or the like and an epitaxial layer 21b made of n− type silicon single crystal. A field insulating film (element isolation region) 22 made of, for example, silicon oxide is formed on the main surface of the epitaxial layer 21b.

  A plurality of unit transistor cells constituting QH are formed in the active region surrounded by the field insulating film 22 and the underlying p-type well PWL1. QH is formed by connecting a plurality of unit transistor cells in parallel. Each unit transistor cell is formed of, for example, an n-channel MOS transistor having a trench gate structure. The substrate body 21a and the epitaxial layer 21b have a function as the drain region of the unit transistor cell described above. A back electrode BE for the drain electrode is formed on the back surface of the semiconductor substrate 21. For example, the back electrode BE is formed by stacking a titanium (Ti) layer, a nickel (Ni) layer, and a gold (Au) layer in this order from the back surface of the semiconductor substrate 21. In the DRIC shown in FIG. 8, the back electrode BE is joined and electrically connected to DP_HS via an adhesive layer.

  Further, the p-type semiconductor region 23 formed in the epitaxial layer 21b has a function as a channel formation region of the unit transistor cell described above. Further, the n + type semiconductor region 24 formed on the p type semiconductor region 23 has a function as a source region of the unit transistor cell. In addition, a groove 25 extending from the main surface of the semiconductor substrate 21 in the thickness direction of the semiconductor substrate 21 is formed. The trench 25 is formed so as to penetrate the n + type semiconductor region 24 and the p type semiconductor region 23 from the upper surface of the n + type semiconductor region 24 and terminate in the epitaxial layer 21 b below the n + type semiconductor region 24. A gate insulating film 26 made of, for example, silicon oxide is formed on the bottom and side surfaces of the groove 25.

  A gate electrode 27 is embedded in the trench 25 via a gate insulating film 26. The gate electrode 27 is made of, for example, a polycrystalline silicon film to which an n-type impurity is added. The gate electrode 27 has a function as the gate electrode of the unit transistor cell described above. In addition, a gate lead-out wiring portion 27a made of a conductive film in the same layer as the gate electrode 27 is formed on a part of the field insulating film 22, and the gate electrode 27 and the gate lead-out wiring portion 27a Are integrally formed and electrically connected to each other. In the region not shown in the cross-sectional view of FIG. 9, the gate electrode 27 and the gate lead-out wiring portion 27a are integrally connected. The gate lead-out wiring part 27a is electrically connected to the gate wiring 30G through a contact hole 29a formed in the insulating film 28 covering it.

  On the other hand, the source line 30 </ b> S is electrically connected to the source n + type semiconductor region 24 through a contact hole 29 b formed in the insulating film 28. Further, the source wiring 30S is electrically connected to a p + type semiconductor region 31 formed between the n + type semiconductor region 24 and adjacent to the n + type semiconductor region 24 above the p type semiconductor region 23, thereby forming a channel. The p-type semiconductor region 23 is electrically connected. In the gate wiring 30G and the source wiring 30S, a metal film (for example, an aluminum film) is formed on the insulating film 28 in which the contact holes 29a and 29b are formed so as to fill the contact holes 29a and 29b, and the metal film is patterned. Can be formed.

  The gate wiring 30G and the source wiring 30S are covered with a protective film (insulating film) 32 made of polyimide resin or the like. This protective film 32 is the uppermost film (insulating film) of the semiconductor chip CP1. An opening 33 is formed in a part of the protective film 32 so as to expose a part of the gate wiring 30G and the source wiring 30S in the lower layer, and the portion of the gate wiring 30G exposed from the opening 33 is described above. The portion of the source wiring 30S exposed from the opening 33 is the source electrode described above. Thus, although the source electrodes are separated by the protective film 32 in the uppermost layer, they are electrically connected to each other through the source wiring 30S.

  A metal layer 34 is formed on the surface of the gate electrode and the source electrode (that is, on the gate wiring 30G and the source wiring 30S exposed at the bottom of the opening 33) by plating or the like. The metal layer 34 is formed by a laminated film of a metal layer 34a formed on the gate wiring 30G and the source wiring 30S and a metal layer 34b formed thereon. The lower metal layer 34a is made of nickel (Ni), for example, and mainly has a function of suppressing or preventing oxidation of aluminum in the underlying gate wiring 30G and the source wiring 30S. Further, the upper metal layer 34b is made of, for example, gold (Au) and mainly has a function of suppressing or preventing oxidation of nickel in the underlying metal layer 34a.

  The operating current of the unit transistor cell in the high-side transistor QH is such that the side surface of the gate electrode 27 (that is, the side surface of the trench 25) is between the epitaxial layer 21b for drain and the n + type semiconductor region 24 for source. Along the thickness direction of the substrate 21. That is, the channel is formed along the thickness direction of the semiconductor chip CP1. Thus, the semiconductor chip CP1 is a semiconductor chip on which a vertical MOSFET (power MOSFET) having a trench gate structure is formed. Here, the vertical MOSFET corresponds to a MOSFET in which a current between the source and the drain flows in the thickness direction of the semiconductor substrate 21 (a direction substantially perpendicular to the main surface of the semiconductor substrate).

<< Detailed configuration of high-side driver circuit and short-circuit detection circuit [1A] >>
FIG. 10 shows details of the high-side driver circuit and short circuit detection circuit DVh & SDECh in the drive unit DRIC of FIG. 7, and FIG. 10 (a) is a circuit diagram showing a configuration example thereof, FIG. 10 (b) and FIG. 10 (c) is a waveform diagram showing an operation example of FIG. 10 (a). FIG. 11 is a supplementary diagram of FIG. 10, and is a top view illustrating a package configuration example of the drive unit including the configuration example of FIG. 10. The driver circuit and short circuit detection circuit DVh & SDETCh1 shown in FIG. 10A includes a comparator circuit CMP10, resistors R10, R11, R20, and R21, and AND operation circuits AD10 and AD11. The CMP 10 detects, for example, a potential difference between voltages extracted from two different locations in the VSWH node via two bonding wires BW3 and BW5, with the power supply node connected to the boost voltage BOOT and the ground node connected to the switch signal VSWH. To do. Here, the CMP 10 outputs an “L” level when the voltage value obtained by resistance-dividing BW3 and BW5 with R10 and R11 exceeds the voltage value obtained by adding the comparison voltage Vr10 to the voltage of BW5.

  As shown in FIG. 8B, the bonding wire BW3 connects the source pad (PD_H_S4) of the semiconductor chip CP1 (transistor QH) and the pad on the semiconductor chip CP3 (CTLU). On the other hand, as shown in FIG. 11, the bonding wire BW5 connects the pad on CP3 (CTLU) and the die pad DP_LS. PD_H_S4 and DP_LS are both nodes for the switch signal VSWH, but strictly speaking, parasitic components (parasitic resistance Rm and parasitic inductor Lm) exist in the path from PD_H_S4 to DP_LS (one end of BW5). This parasitic component is generated particularly by the metal plate MB1 or DP_LS. Therefore, in FIG. 10, the potential difference proportional to the magnitude of the current flowing between VIN and VSWH (between the source and drain of QH) is actually between BW3 and BW5 due to the parasitic components (Rm, Lm). Arise. For example, to simplify the explanation, Lm is ignored and Rm = 2 mΩ, the comparison voltage Vr10 = 0.2 V, R10 and R11 are 10 kΩ (R10 and R11 are high resistances, and the current flowing through the path is If the current between VIN and VSWH exceeds 200 A, the CMP 10 determines that there is a short circuit and outputs an “L” level.

  Resistors R20 and R21 divide the voltage between the boosted voltage BOOT and the output node of CMP10, and this resistance voltage dividing node Na is connected to one of the two inputs of AD11 and one of the two inputs of AD10. However, an inverted signal of Na is input on the AD10 side. The resistance values of R20 and R21 are, for example, R20 >> R21, and Na is a BOOT level (“H” level) when CMP10 outputs “H” level, and CMP10 is “L” level. Is almost at the VSWH level ('L' level). R21 can be omitted. In the AD 11, for example, the power supply node is connected to BOOT, the ground node is connected to VSWH, the pulse width modulation signal PWMh is input to the other of the two inputs, and the gate of QH is driven based on the AND operation result with Na. AD11 corresponds to the driver circuit DVh. In the AD 10, for example, a power supply node is connected to BOOT, a ground node is connected to VSWH, PWMh is input to the other of the two inputs, and a short circuit detection signal SDETh is output based on an AND operation result with an inverted signal of Na.

  The driver circuit and the short circuit detection circuit DVh & SDETCh1 in FIG. 10A perform the operation shown in FIG. 10B during normal operation (when there is no failure path (short circuit path)). First, when PWMh is at VSWH level ('L' level or off level), the gate voltage of QH is driven to VSWH level via AD11, and QH is turned off. At this time, since the current flowing through QH is zero, the CMP 10 outputs the “H” level, and the voltage of Na becomes the “H” level (BOOT level). Further, the output of the AD 10 (short circuit detection signal SDETh) is set to the “L” level. When QH is in the OFF state, as shown in FIG. 10A, the voltage value of VSWH is substantially at the PGND level as QL is turned on, and the voltage value of BOOT is set to the “VSWH + VCIN” level ( (Approximately VCIN level).

  Here, when PWMh transits to the BOOT level ('H' level or on level), since the voltage of Na is also at the 'H' level, the gate voltage of QH is driven to the BOOT level via AD11, QH is turned on. At this time, a current corresponding to the load circuit flows through QH, and the potential difference between BW3 and BW5 increases accordingly by “Rm × (QH current)” (Lm is assumed to be zero). Does not reach the level. Accordingly, the output of the CMP 10 is maintained at the “H” level, and the short circuit detection signal SDETh from the AD 10 is maintained at the “L” level. When QH is in the ON state, the voltage value of VSWH becomes VIN level via QH, and the voltage value of BOOT becomes “VSWH + VCIN” level (VIN + VCIN level) obtained by adding VCIN level previously stored in Cb to VSWH. .

  On the other hand, DVh & SDETCh1 in FIG. 10A performs an operation as shown in FIG. 10C when a short circuit is detected (for example, when the failure path FP1 shown in FIG. 10A exists). First, when PWMh is at VSWH level ('L' level or off level), the gate voltage of QH is driven to VSWH level via AD11, and QH is turned off. At this time, since the current flowing through QH is zero, the CMP 10 outputs the “H” level, and the voltage of Na becomes the “H” level (BOOT level). Further, the output of the AD 10 (short circuit detection signal SDETh) is set to the “L” level. Here, when PWMh transits to the BOOT level ('H' level or on level), the voltage of Na is also initially at the 'H' level, so the QH gate voltage is driven to the BOOT level via AD11. , QH is turned on. At this time, the short-circuit current Is flows through QH, and accordingly, the potential difference between BW3 and BW5 increases by “Rm × Is” (Lm is assumed to be zero).

  Here, since there is the failure path FP1, a large Is flows, and accordingly, the potential difference between BW3 and BW5 exceeds the determination level of CMP10, the output of CMP10 transitions to the 'L' level, and the voltage of Na also changes to 'L'. 'Transition to level. As a result, SDETh transitions to the “H” level via the AD 10. Further, the gate voltage of QH transits to the VSWH level via AD11, and QH is driven off, thereby protecting QH. When SDETh becomes “H” level, PWMh is fixed to “L” level (off level) via PWM control unit PCTLIC described in FIG. 2 or the like or based on driver enable signal EN_D described in FIG. The When QH is turned off, the potential difference between BW3 and BW5 decreases. Therefore, until PWMh is fixed at the “L” level, the output of CMP10 returns to the “H” level again, and QH is turned on again. There is a risk of being driven by. However, in this case as well, QH is driven off again through the same detection operation, so there is no particular problem. However, in order to avoid repetition of such detection operation, a latch circuit or the like is inserted into the output of CMP10. It is also possible to do.

  When the configuration examples as shown in FIGS. 10 and 11 are used, for example, the following effects can be obtained. First, it is possible to improve the accuracy of short circuit detection. This is obtained because the transistors QH and QL and the control unit CTLU are mounted on one semiconductor package as shown in FIGS. In this case, since the durability of QH and QL and the size of the parasitic components of the die pad DP_HS and the metal plate MB1 are estimated with high accuracy in advance in the design stage, the conditions for determining a short circuit (resistance values of R10 and R11 and Vr10 Can be determined with high accuracy. As a comparative example, when QH, QL and CTLU are realized by individual semiconductor packages, for example, there is a possibility that such high accuracy cannot be achieved depending on the combination, mounting state, and the like. Further, since FIG. 10A is a method for detecting the short-circuit current Is (strictly, Is is detected and converted into a voltage), it is possible to improve the accuracy of short-circuit detection also from this method. Become. As a comparative example, for example, it is conceivable to use a voltage detection method in which the voltage value of VSWH is detected at one point, and the case where the original value that should be VIN is at a level close to PGND is detected. However, in such a voltage detection method, for example, when the failure path FP1 is short-circuited with a slightly high resistance instead of a low resistance, the resistance is divided between the on-resistance having a very small QH and the high resistance of FP1. Since a value close to the original value (VIN level) is obtained as VSWH, FP1 may not be detected.

  Second, short circuit detection with a small area (low cost) can be realized. From the viewpoint of mounting, for example, as shown in FIG. 11, for example, bonding wires BW3 and BW5 may be provided (in practice, BW5 may be added). In particular, when a semiconductor package as shown in FIG. 11 or FIG. 8 is used, as can be seen from FIG. 11, a wide mounting space can be secured around the BW 5, so that mounting is easy. Further, from the viewpoint of the circuit, as shown in FIG. 10A, since a die pad or a metal plate is used, it is not necessary to separately provide a series resistor (which causes a loss) for current verification, and further, a detection circuit. This is because it itself does not incur a significant area overhead. As a comparative example, for example, a method in which a sense MOS transistor that forms a current mirror with QH is provided in a semiconductor chip CP1 (QH), and a current of the MOS transistor is detected (for example, Patent Document 1). However, in this method, in addition to the comparator circuit for detecting the current value, various amplifier circuits for making the source-drain voltage of the sense MOS transistor equal to the source-drain voltage of QH are required. The area may increase.

  As described above, by using the power supply device of the third embodiment, typically, in addition to the various effects described in the first and second embodiments, more accurate short-circuit detection or short-circuit detection in a small area can be performed. It becomes feasible. Here, the metal plates MB1 and MB2 are used to connect between the semiconductor chip and the external terminal or between the semiconductor chip and the die pad. However, in some cases, a bonding wire such as gold (Au) may be used instead. Is possible.

(Embodiment 4)
In the fourth embodiment, a modified example of the driver circuit and the short circuit detection circuit described in FIG. 10 of the third embodiment will be described.

<< Detailed configuration of high-side driver circuit and short-circuit detection circuit [1B] >>
FIG. 12 shows details of the high-side driver circuit and the short-circuit detection circuit DVh & SDECh in the drive unit DRIC of FIG. 7 in the power supply device according to Embodiment 4 of the present invention. FIG. FIG. 12B is a circuit diagram showing a configuration example of the delay circuit in FIG. 12A, and FIG. 12C is a waveform diagram showing an operation example of FIG. The driver circuit and short circuit detection circuit DVh & SDETCh2 shown in FIG. 12A has a configuration in which a delay circuit DLY is added to the driver circuit and short circuit detection circuit DVh & SDETCh1 shown in FIG. Since other configurations are the same as those in FIG. 10A, detailed description thereof is omitted.

  The delay circuit DLY operates with the connection node Na of the resistors R20 and R21 as an input and the node Nb as one of the two inputs of the AND operation circuit AD11 and one of the two inputs of the AND operation circuit AD10 as an output. As for the AD10 side, an inverted signal of the signal at Nb is input as in the case of FIG. As shown in FIG. 12B, DLY includes an even number of inverter circuit blocks IVBK and a NOR operation circuit NR10, and the result of NOR operation of the input signal and a signal obtained by delaying the input signal by IVBK with NR10. Is output. In this case, after the input signal transitions from the “H” level to the “L” level, the DLY outputs from the “H” level when the state continues for a period longer than the delay time (Tdly) determined by IVBK. Transition to 'L' level. When such DVh & SDECh2 is used, the operation shown in FIG. 12C is performed when a short circuit is detected.

  In FIG. 12 (c), unlike FIG. 10 (c), the voltage at the node Na transitions from the BOOT level ('H' level) to the VSWH level ('L' level) due to short circuit detection, and the state is DLY. After continuing for the delay time (Tdly), the node Nb changes from the “H” level to the “L” level. In response to the transition of the Nb from the “H” level to the “L” level, the AD 11 drives the transistor QH off, and the AD 10 outputs the short circuit detection signal SDETh. The subsequent operation is the same as in FIG. The delay time (Tdly) is not particularly limited, but is 20 ns, for example.

  When the short-circuit detection circuit DVh & SDETCh2 as shown in FIG. 12 is used, in addition to the various effects described in DVh & SDETCh1 in FIG. 10, more accurate short-circuit detection can be realized. For example, even when the failure path FP1 does not exist, there may be a case where the voltage of the bonding wire BW3 instantaneously exceeds the determination level of the comparator circuit CMP10 due to the influence of power supply noise, parasitic inductor (Lm), or the like. In this case, in the configuration example of FIG. 10A, QH is instantaneously driven off, and an instantaneous 'H' pulse is output to SDETh, which may cause malfunction. Therefore, when the configuration example of FIG. 12A is used, a period exceeding the determination level of the CMP 10 is required for Tdly or more to be regarded as short-circuit detection, and thus such a malfunction can be prevented. It should be noted that the length of Tdly is appropriately determined according to the durability of QH that has been previously known at the design stage. As an example, when a voltage of VIN (= 12 V) is applied between the source and drain of QH in the on state, for example, QH may reach thermal destruction in a time of 45 ns. In such a case, by setting Tdly = 20 ns or the like, it is possible to prevent the above-described malfunction and prevent thermal destruction of QH.

(Embodiment 5)
In the fifth embodiment, a modified example of the driver circuit and the short circuit detection circuit described in FIG. 12 of the fourth embodiment will be described.

<< Detailed configuration of high-side driver circuit and short-circuit detection circuit [1C] >>
FIG. 13 shows details of the high-side driver circuit and short-circuit detection circuit DVh & SDECh in the drive unit DRIC of FIG. 7 in the power supply device according to Embodiment 5 of the present invention. FIG. FIG. 13B is a waveform diagram showing an operation example of FIG. 13A. The driver circuit and short-circuit detection circuit DVh & SDETCh3 shown in FIG. 13 is different from the driver circuit and short-circuit detection circuit DVh & SDETCh2 in FIG. 12A in that the resistors R10 and R11 and the comparator circuit CMP10 in FIG. The resistors R30 and R31 and the n-channel MOS transistor MN10 are replaced. Since other configurations are the same as those in FIG. 12A, detailed description thereof is omitted.

  The resistors R30 and R31 divide the resistance between the bonding wire BW3 and the bonding wire BW5 in the same manner as the resistors R10 and R11 described above. In the MN10, a gate is driven by a voltage obtained by resistance division by R30 and R31, a source is connected to the BW5, and a drain is connected to one end of the resistor R21. In this case, the MN 10 pulls down the node Na via R21 when the resistance divided value by R30 and R31 exceeds the threshold voltage Vth of MN10. Thus, in the configuration example of FIG. 12 (FIG. 10), the comparator circuit CMP10 makes a determination using the comparison voltage Vr10, whereas in the configuration example of FIG. 13, the MN10 has its own threshold voltage. The determination is performed using Vth. As a result, the CMP 10 can be replaced with the MN 10, so that the circuit area (cost) can be reduced.

  Incidentally, in FIG. 10 described above, the parasitic inductor Lm of the package is set to zero for ease of explanation, but in reality, the influence of Lm may not be ignored. In this case, the potential difference vs between BW3 and BW5 in the transition period in which the transistor QH is turned on is determined by “vs = (Rm × is) + (Lm × d (is) / dt)”. “Is” is a transient current flowing in QH (and Lm, Rm), and Rm is a parasitic resistance of the package. If the failure path FP1 does not exist, an inductor having a relatively large inductance value for driving the load (L [n] in FIG. 1 and the like) is connected to the node of the switch signal VSWH, so that QH is driven on. The value of the subsequent potential difference vs becomes approximately 0V. On the other hand, assuming that a fault path FP1 of 0Ω exists, the operation is as shown in FIG.

  First, when QH is driven to ON and a short-circuit current in a steady state after a lapse of a certain time is assumed to be Is, the transient current “is” increases exponentially from 0 A to Is, and conversely, BW3 The potential difference vs between −BW5 becomes approximately VIN (= 12V) at the moment when QH is driven on, and then decreases exponentially toward the voltage of (Is × Rm). The time constant at this time is proportional to the magnitude of Lm. For example, when Lm = 0.42 nH and Rm = 0.15 mΩ and the failure path FP1 exists, the potential difference vs of 1.2 V or more continues for 20 ns or more in the transition period described above. Therefore, in the example of FIG. 13, for example, the resistor R30 is set to 1 kΩ, the resistor R31 is set to 50 kΩ, the threshold voltage Vth of the MOS transistor MN10 is set to 1.4 V, and the delay time (Tdly) of the delay circuit DLY is set to 20 ns. Thus, the presence or absence of the failure path FP1 is detected. In other words, the presence of the Lm component is positively utilized, and short circuit detection is performed with a combination of a relatively high determination voltage (threshold voltage Vth) and its duration (delay time (Tdly)).

  For example, if a detection method as shown in FIG. 10 (ie, a method for detecting a potential difference generated in the parasitic resistance Rm in a steady state) is used, the potential difference to be detected becomes extremely small when Rm is extremely small. If a noise margin or the like is taken into account, the detection accuracy may be reduced. On the other hand, by using the method using the transition period in this way, even when Rm is extremely small, it is possible to perform short-circuit detection using a relatively high determination voltage, so that detection accuracy can be improved. In other words, a package having a very small parasitic resistance Rm can be used, and the power conversion efficiency of the entire power supply device can be improved.

  It should be noted that the method of using this transition period can be realized by using the configuration example of FIG. When the configuration example of FIG. 12A is used, the resistor R10 may be 1 kΩ, the resistor R11 may be 50 kΩ, the comparison voltage Vr10 may be 1.4 V, and the delay time (Tdly) of the delay circuit DLY may be 20 ns. In addition, these short-circuit determination conditions can be estimated with high accuracy because the size of the parasitic components (Rm, Lm) of the package can be estimated in advance as the drive unit DRIC is realized in one semiconductor package as described above. It is possible to determine.

  As described above, by using the power supply device of the fifth embodiment, in addition to the various effects described in the fourth embodiment, it is possible to realize short-circuit detection with a smaller area.

(Embodiment 6)
In the sixth embodiment, a configuration example in which short-circuit detection is performed using positions different from the driver circuit and the short-circuit detection circuit described in FIG. 10 of the third embodiment will be described.

<< Detailed configuration of high-side driver circuit and short-circuit detection circuit [2] >>
FIG. 14 shows details of the high-side driver circuit and short-circuit detection circuit DVh & SDECh in the drive unit DRIC of FIG. 7 in the power supply device according to Embodiment 6 of the present invention, and FIG. FIG. 14 (b) and FIG. 14 (c) are waveform diagrams showing an operation example of FIG. 14 (a). FIG. 15 is a supplementary diagram of FIG. 14 and is a top view showing a package configuration example of a drive unit having the configuration example of FIG. The driver circuit and short circuit detection circuit DVh & SDETCh4 shown in FIG. 14A includes a comparator circuit CMP10, resistors R40, R41, R20, and R21, AND operation circuits AD10 and AD11, and an n-channel MOS transistor MN20.

  MOS transistor MN20 has a source connected to node Nbw6 and a drain connected to bonding wire BW6 drawn from the drain of transistor QH. Resistors R40 and R41 divide the resistance between node Nbw6 and bonding wire BW3 drawn from the source of QH. The CMP 10 outputs an 'L' level when the voltage value divided by the resistors R40 and R41 exceeds the voltage value obtained by adding the comparison voltage Vr20 to the voltage of BW3. In this way, the driver circuit and short circuit detection circuit DVh & SDECh4 in FIG. 14 perform short circuit detection using two different locations in the node of VSWH, while the driver circuit and short circuit detection circuit DVh & SDECh1 in FIG. This is a method of detecting a short circuit using a source and a drain. Since the resistors R20 and R21 and the AND operation circuits AD10 and AD11 that operate appropriately according to the output of the CMP 10 are the same as those in FIG. 10, detailed description thereof is omitted. However, FIG. 14 is different from FIG. 10 in that AD11 (driver circuit DVh) drives the gate of MN20 in addition to driving the gate of QH as in FIG.

  As shown in FIG. 8B, the bonding wire BW3 connects the source pad (PD_H_S4) of the semiconductor chip CP1 (transistor QH) and the pad on the semiconductor chip CP3 (CTLU). On the other hand, as shown in FIG. 15, the bonding wire BW6 connects the pad on CP3 (CTLU) and the die pad DP_HS connected to the drain of QH.

  The driver circuit and short circuit detection circuit DVh & SDETCh4 in FIG. 14A perform the operation shown in FIG. 14B during normal operation (when there is no failure path (short circuit path)). First, when PWMh is at the VSWH level ('L' level or off level), the gate voltages of QH and MN20 are driven to the VSWH level via AD11, and QH and MN20 are turned off. At this time, since the voltage of the node Nbw6 becomes the VSWH level, the CMP 10 outputs the “H” level, and the voltage of the node Na which is one of the two inputs of the AD11 becomes the “H” level (BOOT level). Further, the output of the AD 10 (short circuit detection signal SDETh) is set to the “L” level. Here, when PWMh transits to the BOOT level ('H' level or on level), since the voltage of Na is also at the 'H' level, the gate voltages of QH and MN20 are driven to the BOOT level via AD11. Then, QH and MN20 are turned on. At this time, a current corresponding to the load circuit flows through QH, and accordingly, the voltage of BW6 slightly rises with reference to the voltage of BW3 (VSWH level). The voltage of BW6 is transmitted to the node Nbw6 through the switch (MN20) in the on state. However, since the potential difference between Nbw6 and BW3 does not reach the determination level of CMP10, the output of CMP10 maintains the 'H' level, and the short circuit detection signal SDETh from AD10 maintains the 'L' level. In this manner, the MN 20 detects the presence or absence of a short circuit for the QH on period.

  On the other hand, DVh & SDETCh4 in FIG. 14A performs the operation shown in FIG. 14C when a short circuit is detected (for example, when the failure path (short circuit path) FP1 shown in FIG. 14A exists). First, when PWMh is at the VSWH level ('L' level or off level), QH and MN20 are driven to the off state, and CMP10 outputs the 'H' level, as in FIG. 14B. , Na voltage becomes 'H' level (BOOT level). Further, the output of the AD 10 (short circuit detection signal SDETh) is set to the “L” level. Here, when PWMh transits to the BOOT level ('H' level or on level), the voltage of Na is also initially at the 'H' level, so the gate voltages of QH and MN20 are set to the BOOT level via AD11. Driven, QH and MN20 are turned on. At this time, a short circuit current Is flows through QH, and the voltage of BW6 rises with reference to the voltage of BW5 (VSWH level). The voltage of BW6 is transmitted to the node Nbw6 via the switch (MN20) in the on state.

  Here, unlike the case of FIG. 14B, since there is the failure path FP1, a large Is flows, and accordingly, the potential difference between Nbw6-BW3 exceeds the determination level of CMP10, and the output of CMP10 is set to the 'L' level. Transition occurs, and the voltage of Na also transitions to the “L” level. As a result, SDETh transitions to the “H” level via the AD 10. Further, the gate voltage of QH and MN20 transits to the VSWH level via AD11, and QH and MN20 are driven off to protect the QH. When SDETh becomes “H” level, PWMh is fixed to “L” level (off level) via PWM control unit PCTLIC described in FIG. 2 or the like or based on driver enable signal EN_D described in FIG. The When QH and MN20 are turned off, the potential difference between Nbw6-BW3 also decreases. Therefore, until PWMh is fixed at the “L” level, the output of CMP10 returns to the “H” level again, and QH is There is a risk of being driven on again. However, in this case as well, QH is driven off again through the same detection operation, so there is no particular problem. However, in order to avoid repetition of such detection operation, a latch circuit or the like is inserted into the output of CMP10. It is also possible to do.

  As described above, the configuration example of FIG. 14A is a method of detecting the short circuit by monitoring the value of the current flowing through QH using the on-resistance of the transistor QH. For example, when the on-resistance of QH is 5 mΩ, the resistance values of R40 and R41 are 10 kΩ, and the voltage value of Vr20 is 0.3 V, the output of CMP10 is “L” when the short-circuit current Is exceeds 120 A. Transition to level. When the configuration example of FIG. 14A is used, the on-resistance of QH is usually larger than the parasitic resistance Rm of the package as compared with the configuration example of FIG. A larger amount can be ensured, and accordingly, a margin for circuit characteristic variation, noise, and the like can be increased, and further higher accuracy can be realized. However, in order to further expand the potential difference associated with current detection, it is desirable to use, for example, a detection method utilizing a parasitic inductor as described in FIG. 13, but the configuration example in FIG. Not suitable for application.

  From the viewpoint of mounting, when the semiconductor package of FIG. 8 is used in the configuration example of FIG. 14A, the mounting space of the bonding wire BW6 is larger than the mounting space of the bonding wire BW5 of FIG. Therefore, the configuration example of FIG. 10A is more beneficial than FIG. 14A. Of course, the configuration example of FIG. 14A is not limited to this, and for example, as described in FIG. 12, a delay circuit DLY is added to prevent malfunction due to noise or the like, or FIG. As described above, it is possible to replace the comparator circuit CMP10 with a MOS transistor. However, when a MOS transistor is used, since it is not a detection method using a parasitic inductor as shown in FIG. 13, a relatively low threshold voltage is required.

(Embodiment 7)
<< Detailed configuration of low-side driver circuit and short-circuit detection circuit >>
FIG. 16 shows details of the low-side driver circuit and the short circuit detection circuit DVl & SDETCl in the drive unit DRIC of FIG. 7 in the power supply device according to the seventh embodiment of the present invention. FIG. FIG. 16B and FIG. 16C are waveform diagrams showing an operation example of FIG. FIG. 17 is a supplementary diagram of FIG. 16, and is a top view illustrating a package configuration example of the drive unit including the configuration example of FIG. 16. The driver circuit and short circuit detection circuit DVl & SDETCl1 shown in FIG. 16A includes a driver circuit DVl, a comparator circuit CMP20, and an AND operation circuit AD10. In the CMP 20, for example, the power supply node is connected to the power supply voltage VCIN, the ground node is connected to the ground power supply voltage PGND (or CGND), the voltage taken out from the source of the transistor QL via the bonding wire BW4, and the bonding wire BW7 from the drain of QL. The potential difference from the voltage taken out via is detected.

  As shown in FIG. 8B, the bonding wire BW4 connects the source pad (PD_L_S4) of the semiconductor chip CP2 (transistor QL) and the pad on the semiconductor chip CP3 (CTLU). On the other hand, as shown in FIG. 17, the bonding wire BW7 connects the pad on CP3 (CTLU) and the die pad DP_LS connected to the QL drain. Here, when combined with the configuration example of FIG. 11 (circuits of FIG. 10, FIG. 12, and FIG. 13), BW7 can also be used as the bonding wire BW5 as can be seen from FIG. As a result, mounting can be facilitated and costs can be reduced.

  With this configuration, the CMP 20 detects a potential difference generated between the source and drain of the QL via the on-resistance of the QL, and the voltage value of the BW7 exceeds the voltage value obtained by adding the comparison voltage Vr30 to the voltage of the BW4. When this occurs, the 'L' level is output to the node Nc. For example, if the on-resistance of QL is 1 mΩ and the voltage value of Vr30 is 0.2 V, the “L” level is output to Nc when 200 A flows through QL. In the AND operation circuit AD10, for example, a power supply node is connected to VCIN, a ground node is connected to PGND (or CGND), an inverted signal of the node Nc is input to one of two inputs, and a pulse width modulation signal PWM1 is input to the other. The short circuit detection signal SDETl is output according to the AND operation result. The driver circuit DVl drives the gate of the transistor QL according to PWMl.

  The driver circuit and short circuit detection circuit DVl & SDETCl1 in FIG. 16A perform the operation shown in FIG. 16B during normal operation (when there is no failure path (short circuit path)). First, when PWMl is at CGND level ('L' level or off level), the gate voltage of QL is driven to PGND level via DVl, and QL is turned off. At this time, the potential difference between BW7 and BW4 becomes the level of the power supply voltage VIN when the transistor QH is turned on, which exceeds the determination level of CMP20, so that CMP20 outputs the 'L' level to the node Nc. The AD 10 outputs “L” level as the short circuit detection signal SDETl because Nc is “L” level but PWMl is “L” level.

  Here, when the PWM1 transits to the VCIN level ('H' level or on level), the gate voltage of QL is driven to the VCIN level via DV1, and the QL is turned on. At this time, a current due to a commutation operation using an inductor (L [n] in FIG. 1 or the like) as an electromotive force flows through QL. Along with this, the potential difference between BW7 and BW4 is “(QL ON resistance) × ( QL current) ”. In this case, since the potential difference between BW7 and BW4 is lower than the determination level of CMP20, CMP20 outputs an 'H' level to Nc. In AD10, PWMl is at the "H" level, but Nc is at the "H" level, so SDETl is maintained at the "L" level. In this way, the AD 10 substantially detects the presence or absence of a short circuit for the QL ON period.

  On the other hand, DVl & SDETCl1 in FIG. 16A performs the operation shown in FIG. 16C when a short circuit is detected (for example, when the failure path (short circuit path) FP2 shown in FIG. 16A exists). First, when PWMl is at CGND level ('L' level or off level), the gate voltage of QL is driven to PGND level via DVl, and QL is turned off. At this time, as in the case of FIG. 16B, the CMP 20 outputs the 'L' level to the node Nc, and the AD 10 outputs the 'L' level as SDETl. Here, when the PWM1 transits to the VCIN level ('H' level or on level), the gate voltage of QL is driven to the VCIN level via DV1, and the QL is turned on. Then, a short circuit current Is flows through QL through the failure path FP2. In this case, the potential difference between BW7 and BW4 is “(QL on-resistance) × Is”, but since the value of Is is large, it does not fall below the determination level of CMP20. Therefore, the output (Nc) of the CMP 20 is maintained at the ‘L’ level. AD10 drives SDETl to the 'H' level because PWMl is at the 'H' level and Nc is at the 'L' level.

  When SDETl becomes “H” level, PWMl is fixed to “L” level (off level) via PWM control unit PCTLIC described in FIG. 2 or the like or based on driver enable signal EN_D described in FIG. The As a result, the QL is driven off via the DV1, and the QL is protected. Further, here, the QL is driven on for a certain period of time after the CMP 20 detects a short circuit until the PWM1 is fixed at the “L” level. This prevents a high voltage from being applied to the load circuit (LOD in FIG. 7) and protects the LOD. Then, during this fixed time, the power supply voltage VIN is cut off by the method described in FIGS. However, in the case where the response speed of the power shut-off is fast, a driver circuit using an AND operation circuit can be used instead of DVl as in FIG.

  As described above, by using the power supply device according to the seventh embodiment, typically, the protection of the low-side transistor and the load circuit can be protected, and the reliability of the multiphase power supply device can be improved. Of course, the configuration example of FIG. 16A is not limited to this. For example, a delay circuit DLY is added as shown in FIG. 12, or a comparator circuit is used as shown in FIG. It is also possible to replace the CMP 20 with a MOS transistor.

(Embodiment 8)
In the eighth embodiment, a mounting structure (substrate layout) of a power supply device configured using the drive unit (semiconductor device) DRIC shown in FIG. 8 of the third embodiment will be described.

<< Power supply board layout >>
FIG. 18 is a plan view showing a configuration example of a part of the board layout in the power supply device according to the eighth embodiment of the present invention. In the power supply device shown in FIG. 18, a drive unit DRIC [n] and a load circuit LOD (for example, a CPU) are mounted on a wiring board PCB having a plurality of wiring layers (for example, copper (Cu) wiring layers). . Here, the wiring pattern LP_VIN for the power supply voltage VIN, the wiring pattern LP_PGND for the ground power supply voltage PGND, the wiring pattern LP_VSWH for the switch signal VSWH, and the wiring pattern LP_VO for the output power supply node VO are formed in the wiring layer on the surface of the PCB. Has been.

  As described in FIG. 8, the drive unit DRIC [n] exposes the VIN electrode (die pad DP_HS), the VSWH electrode (die pad DP_LS), and the ground power supply voltage CGND electrode (die pad DP_CT) from the back surface. is doing. As shown in FIG. 18, this VIN electrode (die pad DP_LS) is connected to LP_VIN by a reflow process using solder paste SP together with an external terminal (lead LD) for VIN arranged around the VIN electrode. Similarly, an electrode for VSWH (die pad DP_LS) is connected to LP_VSWH by a reflow process or the like together with an external terminal for VSWH arranged around the VSWH electrode. Further, an external terminal for PGND is arranged around the electrode for VSWH (die pad DP_LS), and the external terminal is connected to LP_PGND by a reflow process or the like, and the external power supply terminal of the load circuit LOD is also reflowed. It is connected to the wiring pattern LP_VO by a process or the like. LP_VIN and LP_PGND are formed so that one side is adjacent to each other, and a bypass capacitor C1 for reducing power supply noise is mounted therebetween. LP_VO is formed such that one side is adjacent to one side of LP_PGND and the other side is adjacent to one side of LP_VSWH. A bypass capacitor C2 for reducing power supply noise is mounted between the LP_VOND and the inductor L [n ] Is implemented.

  In such a configuration example, a short circuit may occur between VSWH and PGND, between VSWH and VIN, or between VIN and PGND due to, for example, an excessive amount of solder paste SP during the reflow process. Further, for example, a short circuit between VIN and PGND may occur due to a mounting defect of the bypass capacitor C1. Therefore, it is beneficial to detect a short circuit using the power supply device of the present embodiment described above to protect it. In the above-described embodiment, the description when a short circuit between VIN and PGND occurs is omitted. Of course, this can also be detected by a high-side or low-side short circuit detection circuit.

  FIG. 19 is a plan view showing a configuration example of a substrate layout of a multiphase power supply device formed by extending FIG. In the power supply device shown in FIG. 19, a plurality (four in this case) of drive units DRIC [1] to DRIC [4], a load circuit LOD (for example, a CPU, etc.), and a PWM control unit PCTLIC are provided on the wiring board PCB. Has been implemented. DRIC [1] to DRIC [4] are arranged side by side in the X direction. The VIN die pad DP_HS in each DRIC [n] (n = 1 to 4) and the external terminals for VIN arranged in the periphery thereof are commonly connected by a wiring pattern LP_VIN formed on the PCB. The die pad DP_LS for VSWH in each DRIC [n] is connected to a wiring pattern LP_VSWH [n] individually formed on the PCB.

  The load circuit LOD (CPU) has an external power supply terminal connected to a wiring pattern LP_VO formed on the PCB, and an external ground power supply terminal connected to a wiring pattern LP_PGND formed on the PCB. LP_PGNDs are appropriately distributed on the surface of the PCB and connected in common via any wiring layer of the PCB. As described with reference to FIG. 18, the LP_PGND is used for the PGND of each DRIC [n] on the PCB surface. Are appropriately connected to the external terminals. Each wiring pattern LP_VSWH [n] is connected to one end of each inductor L [n] mounted side by side in the X direction. The other end of each L [n] is commonly connected to LP_VO. Similarly to FIG. 18, a bypass capacitor C1 is mounted between LP_VIN and LP_PGND, and a bypass capacitor C2 is mounted between LP_VO and LP_PGND. Here, the PWM control unit PCTLIC is appropriately connected to an external terminal of each DRIC [n] via any wiring layer of the PCB.

  In such a configuration example, since DRIC [1] to DRIC [4] generate a large amount of heat, for example, as shown in FIG. 19, a heat sink HSNK that covers each DRIC [n] in common may be mounted. . In addition to the reflow process as described above, the external terminals of each DRIC [n] may be short-circuited due to such misalignment of the HSNK mounting position. Therefore, it is beneficial to detect a short circuit using the power supply device of the present embodiment described above to protect it.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiments. However, the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the scope of the invention.

DESCRIPTION OF SYMBOLS 21 Semiconductor substrate 22 Field insulating film 23, 24, 31 Semiconductor region 25 Groove 26 Gate insulating film 27 Gate electrode 28 Insulating film 29 Contact hole 30G Gate wiring 30S Source wiring 32 Protective film 33 Opening 34 Metal layer AD and arithmetic circuit BE Back surface Electrode BW Bonding wire C Capacitance CMP Comparator circuit CP Semiconductor chip CSDET Current detection circuit CTLU Control unit D Diode DAC Digital / analog conversion circuit DLY Delay circuit DP Die pad DRIC Drive unit DTCTL Penetration prevention circuit DV Driver circuit EA Error amplifier circuit FP Fault path HSNK Heat sink IVBK Inverter circuit block L Inductor LD Lead LOD Load circuit LP Wiring pattern LS Level shift circuit MB Gold Plate MN n-channel MOS transistor NR NOR operation circuit P External terminal PCTLIC PWM control unit PD pad PHC phase compensation circuit PKG Semiconductor package PWL p-type well PWMCTL PWM control circuit PWMMOD Pulse width modulation circuit PWRCTL Power supply unit QH, QL Transistor R Resistance SBS bus SDETC short circuit detection circuit SDETIF short circuit detection output circuit SP solder paste VAC commercial power supply VO output power supply node VREG regulator circuit

Claims (16)

First and second drive units;
With bus,
First and second inductors having one end coupled in common;
A PWM control unit that outputs first and second pulse width modulation signals having different phases to the first and second drive units, respectively;
A power supply block that generates a power supply voltage for driving the inductor,
The first drive unit includes:
A first power supply terminal to which a power supply voltage for driving the inductor is supplied;
A first switch terminal coupled to the other end of the first inductor;
A first ground terminal to which a ground power supply voltage is supplied;
A first detection terminal connected to the bus;
A first high-side transistor in which a current path is formed between the first power supply terminal and the first switch terminal;
A first low-side transistor in which a current path is formed between the first switch terminal and the first ground terminal;
A first driver circuit for controlling on / off of the first high-side transistor and the first low-side transistor according to the first pulse width modulation signal;
A first high-side detection circuit configured to drive the bus from the second voltage level to the first voltage level via the first detection terminal when a current flowing through the first high-side transistor is larger than a predetermined current; ,
The second drive unit is
A second power supply terminal to which a power supply voltage for driving the inductor is supplied;
A second switch terminal coupled to the other end of the second inductor;
A second ground terminal to which the ground power supply voltage is supplied;
A second detection terminal connected to the bus;
A second high-side transistor in which a current path is formed between the second power supply terminal and the second switch terminal;
A second low-side transistor in which a current path is formed between the second switch terminal and the second ground terminal;
A second driver circuit for controlling on / off of the second high-side transistor and the second low-side transistor according to the second pulse width modulation signal;
A second high side detection circuit for driving the bus from the second voltage level to the first voltage level via the second detection terminal when a current flowing through the second high side transistor is larger than a predetermined current; With
The first drive unit is composed of one semiconductor package,
The second drive unit is composed of one semiconductor package,
The bus is driven by a wired OR logic of the first and second detection terminals. The power supply device according to claim 1, wherein
The first driver circuit controls the first high-side transistor to turn off when the bus is at the first voltage level;
The power supply device, wherein the second driver circuit controls the second high-side transistor to be off when the bus is at the first voltage level. The power supply device according to claim 2, wherein
The power supply block monitors the bus, and stops generating the power supply voltage for driving the inductor when the bus reaches the first voltage level. The power supply device according to claim 1, wherein
The PWM control unit monitors the bus and fixes the first and second pulse width modulation signals to a constant voltage level when the bus reaches the first voltage level. apparatus. The power supply device according to claim 1, wherein
The first driving unit further changes the bus from the second voltage level to the first voltage level via the first detection terminal when a current flowing through the first low-side transistor is larger than a predetermined current. A first low side detection circuit for driving,
The second driving unit further changes the bus from the second voltage level to the first voltage level via the second detection terminal when a current flowing through the second low-side transistor is larger than a predetermined current. A power supply apparatus comprising a second low side detection circuit for driving. Consists of one semiconductor package,
A first die pad to which a power supply voltage for driving the inductor is supplied;
A second die pad electrically connected to an external inductor;
A third die pad;
A first semiconductor chip mounted on the first die pad and having a back surface electrically connected to the first die pad;
A second semiconductor chip mounted on the second die pad and having a back surface electrically connected to the second die pad;
A third semiconductor chip mounted on the third die pad;
A first lead to which a ground power supply voltage is supplied;
A first connection part for electrically connecting the surface of the first semiconductor chip and the second die pad;
A second connection part for electrically connecting the surface of the second semiconductor chip and the first lead;
A second lead connected to the external bus;
Comprising first to fourth bonding wires;
In the first semiconductor chip, an n-channel high-side transistor having a drain electrode on the back surface and a gate electrode and a source electrode on the front surface is formed.
In the second semiconductor chip, an n-channel low-side transistor having a drain electrode on the back surface and a gate electrode and a source electrode on the front surface is formed.
The first connection portion connects a source electrode of the high-side transistor and the second die pad,
The second connection portion connects a source electrode of the low-side transistor and the first lead,
The third semiconductor chip includes
A driver circuit for controlling the gate electrodes of the high-side transistor and the low-side transistor through the first and second bonding wires, respectively;
Detecting a first potential difference between a first voltage extracted from the source electrode of the high-side transistor via the third bonding wire and a second voltage extracted from the second die pad via the fourth bonding wire And a high-side detection circuit configured to drive the external bus from the second logic level to the first logic level via the second lead when the first potential difference is larger than a predetermined value. A semiconductor device. The semiconductor device according to claim 6.
The high-side detection circuit includes a delay circuit in which a first period is set, and when the period in which the first potential difference is greater than the predetermined value continues for the first period, the external bus is connected to the second bus. A semiconductor device that is driven from a logic level to the first logic level. The semiconductor device according to claim 7.
The high-side detection circuit includes a detection transistor in which the second voltage is applied to a source and a voltage proportional to the first voltage is applied to a gate, and the first potential difference is greater than the predetermined value. A semiconductor device that performs detection using a threshold voltage of the detection transistor. The semiconductor device according to claim 6.
The high-side detection circuit controls the high-side transistor to be turned off via the driver circuit when the first potential difference is larger than the predetermined value. The semiconductor device according to claim 6.
The driver circuit controls the first high-side transistor to be off when the external bus is at the first voltage level. The semiconductor device according to claim 6.
The semiconductor device further includes a fifth bonding wire,
The third semiconductor chip further includes the second voltage taken out from the second die pad through the fourth bonding wire during a period when the low-side transistor is on, and the source electrode of the low-side transistor from the source electrode. A second potential difference from a third voltage taken out via a fifth bonding wire is detected, and when the second potential difference is larger than a predetermined value, the second bus is connected to the external bus via the second lead. A semiconductor device, wherein a low side detection circuit for driving from a logic level to the first logic level is formed. Consists of one semiconductor package,
A first die pad to which a power supply voltage for driving the inductor is supplied;
A second die pad electrically connected to an external inductor;
A third die pad;
A first semiconductor chip mounted on the first die pad and having a back surface electrically connected to the first die pad;
A second semiconductor chip mounted on the second die pad and having a back surface electrically connected to the second die pad;
A third semiconductor chip mounted on the third die pad;
A first lead to which a ground power supply voltage is supplied;
A first connection part for electrically connecting the surface of the first semiconductor chip and the second die pad;
A second connection part for electrically connecting the surface of the second semiconductor chip and the first lead;
A second lead connected to the external bus;
Comprising first to fourth bonding wires;
In the first semiconductor chip, an n-channel high-side transistor having a drain electrode on the back surface and a gate electrode and a source electrode on the front surface is formed.
In the second semiconductor chip, an n-channel low-side transistor having a drain electrode on the back surface and a gate electrode and a source electrode on the front surface is formed.
The first connection portion connects a source electrode of the high-side transistor and the second die pad,
The second connection portion connects a source electrode of the low-side transistor and the first lead,
The third semiconductor chip includes
A driver circuit for controlling the gate electrodes of the high-side transistor and the low-side transistor through the first and second bonding wires, respectively;
A first voltage extracted from the first die pad through the third bonding wire during a period in which the high-side transistor is on, and a second voltage extracted from the source electrode of the high-side transistor through the fourth bonding wire. A high side that detects a first potential difference from a voltage and drives the external bus from a second logic level to a first logic level via the second lead when the first potential difference is greater than a predetermined value. A semiconductor device, wherein a detection circuit is formed. The semiconductor device according to claim 12, wherein
The high-side detection circuit includes a delay circuit in which a first period is set, and when the period in which the first potential difference is greater than the predetermined value continues for the first period, the external bus is connected to the second bus. A semiconductor device that is driven from a logic level to the first logic level. The semiconductor device according to claim 12, wherein
The high-side detection circuit controls the high-side transistor to be turned off via the driver circuit when the first potential difference is larger than the predetermined value. The semiconductor device according to claim 12, wherein
The driver circuit controls the first high-side transistor to be off when the external bus is at the first voltage level. The semiconductor device according to claim 12, wherein
The semiconductor device further includes fifth and sixth bonding wires,
The third semiconductor chip further includes a third voltage extracted from the second die pad through the fifth bonding wire during a period in which the low-side transistor is on, and a third voltage extracted from the source electrode of the low-side transistor. 6 detects a second potential difference from the fourth voltage taken out through the bonding wire, and if the second potential difference is larger than a predetermined value, the second logic is connected to the external bus via the second lead. A semiconductor device comprising: a low-side detection circuit that drives from a level to the first logic level.

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