JP2012120179A - Image processing apparatus and method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a data processing apparatus and a method thereof capable of executing processing in response to a command between optional data in data transferring.SOLUTION: In an image processing apparatus, multiple processing blocks each having a processing part are connected in series by a common bus. Each of the multiple processing blocks performs image processing using data input to the processing block via the common bus by the processing part of the processing block, performs processing in response to a command input to the processing block for a processing part of the processing block via the common bus, delays, with respect to a first command input to a first processing block via the common bus, output of the first command from the first processing block until data output by data processing based on the data input to the first processing prior to the first command is completed.

Description

  The present invention relates to an image processing apparatus and method for multiplexing commands and data and inputting / outputting them through a common data bus.

  As a prior art, there is known an image processing apparatus in which a data bus for inputting / outputting data and a CPU bus for setting registers are separately provided. In this type of image processing apparatus, parameters used for processing are changed in a specific data unit (page, block, band, etc.) or a register reading operation indicating an internal state is performed by a control method using an interrupt signal. I was doing. During the execution of such interrupt processing, data transfer was stopped.

  In Patent Document 1, a control command is added to the head of the scan line of each frame of video data, and the control command is multiplexed with the video data for transmission, whereby control synchronized with each frame is performed.

JP-A-8-214267

  However, in the control method using the interrupt signal, parameters such as the filter coefficient used for image processing and the threshold for binarization are changed between arbitrary data being transferred, and the register read operation indicating the internal state is executed. It was difficult to do. Even if it can be done, it is necessary to stop the data transfer during the interrupt processing, which causes a problem that the processing becomes slow. Furthermore, in the technique described in Patent Document 1, it is possible to change a parameter and read a register for each frame, but to change a parameter and read a register between arbitrary data in a frame. Was difficult. Also in Patent Document 1, although a control command can be transmitted for each scan line, processing by a command cannot be executed at an arbitrary timing during data transfer.

  The present invention has been made in view of the above problems, and an object thereof is to provide an image processing apparatus and method capable of executing processing according to a command between arbitrary data during data transfer.

In order to achieve the above object, a data processing method according to an aspect of the present invention includes:
An image processing method executed by each of a plurality of processing blocks in an image processing apparatus in which a plurality of processing blocks each having a processing unit are connected in series by a common bus,
A data processing step in which image processing using data input to the processing block via the common bus is performed by a processing unit of the processing block;
A command processing step for performing processing corresponding to a command input to the processing block via the common bus to a processing unit of the processing block;
For the first command input to the first processing block via the common bus, the data output by the data processing based on the data input to the first processing block before the first command is completed. And a delay step for delaying the output of the first command from the first processing block.

  According to the present invention, it is possible to execute processing according to a command between arbitrary data during data transfer.

It is a block diagram which shows the structure of the image processing apparatus in embodiment. It is a figure which shows the format of the input command of embodiment. It is a figure which shows the format of the input data of embodiment. It is a figure which shows the format of the output command of embodiment. It is a figure which shows the format of the output data of embodiment. It is a figure which shows the timing of the register read and write operation of embodiment. It is a figure which shows the timing of the 1st image processing operation of embodiment. It is a figure which shows the timing of the 2nd image processing operation of embodiment. It is a figure which shows the detailed timing of the 2nd image processing operation of embodiment. It is a figure which shows the timing of the 3rd image processing operation of embodiment. It is a figure which shows the detailed timing of the 3rd image processing operation of embodiment. It is a figure which shows the structure of the image processing block of embodiment. FIG. 6 is a diagram illustrating timings of register read and write operations of the image processing block according to the embodiment. It is a figure which shows the timing of the image processing operation | movement of the image processing block of embodiment.

  Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings.

  FIG. 1 shows a configuration diagram of an image processing apparatus 10 according to the present embodiment as a data processing apparatus. Reference numeral 100 denotes a transmission unit that multiplexes and transmits a command word and a data word. Reference numerals 101 to 103 denote image processing blocks, which are connected in series as shown in the figure, and each perform predetermined image processing. Hereinafter, the processing blocks 101 to 103 are described. A receiving unit 104 receives a command word and a data word, and transmits an end signal 105 to the transmitting unit 100. Reference numeral 11 denotes a CPU that controls an apparatus in which the image processing apparatus 10 such as a printing apparatus is incorporated by using the image processing apparatus 10. A DRAM 12 stores image data to be processed. A DMAC 13 controls the direct transfer of image data from the DRAM 12 to the image processing apparatus 10.

  Next, the format of the command word and the data word will be described with reference to FIGS. Note that the command word and the data word have a predetermined bit length, and in this embodiment are assumed to be composed of 64 bits. Hereinafter, a command word is referred to as a command, and a data word is referred to as data.

  FIG. 2 shows an example of the format of the input command. In the input command format 200, the MSB is the 63rd bit and the LSB is the 0th bit. The 63rd bit is a mode flag 201 (attribute data) for identifying a command and data. The 56th to 60th bits are a processing block ID 202 indicating a processing block number to which the input command is applied. As will be described later, a processing block ID as identification data for specifying each processing block is assigned to the processing block, and the command is executed only in the processing block that matches the processing block ID 202. The 55th bit is an RW flag 203 for designating read / write of the register. The 32nd to 47th bits are the address 204 of the register. The 0th to 31st bits are a data area for the register data 205. Here, the value of the register data 205 is “0” at the time of a read command (when the RW flag 203 is 0), and is the register value to be written at the time of a write command (when the RW flag 203 is 1). The 48th to 54th bits and the 61st and 62nd bits are reserved areas 206 that cannot be used. As described above, the command instructs data writing to the register to be accessed or data reading from the register.

  FIG. 3 shows an example of the format of input data. In the input data format 300, the MSB is the 63rd bit and the LSB is the 0th bit. The 63rd bit is a mode flag 201 (attribute data) for identifying a command and data. When it is 0, it indicates data, and when it is 1, it indicates a command. The 56th bit is a start flag indicating the first data to be image-processed in a predetermined data unit (in a predetermined range of data such as page, block, band, etc.). The 55th bit is an end flag 303 indicating the last data to be image processed. The 0th to 47th bits are data 304 to be image processed. The 48th to 54th bits and the 57th to 62nd bits are reserved areas 305 that cannot be used.

  FIG. 4 shows an example of the format of the output command. In the output command format 400, the MSB is the 63rd bit and the LSB is the 0th bit. The 63rd bit is a mode flag 401 (attribute data) for identifying a command and data. When it is 0, it indicates data, and when it is 1, it indicates a command. The 56 to 60 bits are a processing block ID 402 indicating the processing block number to which the command is applied. The 55th bit is an RW flag 403 that is an RW flag 203 for designating read / write of a register. The 32nd to 47th bits are the address 404 of the register. The 0th to 31st bits are a data area for register data 405. Here, the value of the register data 405 is the read register value at the time of the read command (when the RW flag 403 is 0), and the register data of the input command format 200 at the time of the write command (when the RW flag 403 is 1). The value is 205. The 48th to 54th bits and the 61st and 62nd bits are a reserved area 406.

  FIG. 5 shows an example of the format of output data. In the output data format 500, the MSB is the 63rd bit and the LSB is the 0th bit. The 63rd bit is a mode flag 501 (attribute data) for identifying a command and data. When it is 0, it indicates data, and when it is 1, it indicates a command. The 56th bit is a start flag 502 indicating the first data subjected to image processing in a predetermined data unit (page, block, band, etc.). The 55th bit is an end flag 503 indicating the last data subjected to image processing. The 0th to 47th bits are data 504 subjected to image processing. The 48th to 54th bits and the 57th to 62nd bits are a reserved area 505.

  The processing blocks 101 to 103 convert input commands / input data into output commands / output data as will be described later. The input command and the input data have an input command format 200 and an input data format 300, respectively. The output command and the output data have an output command format 400 and an output data format 500, respectively. Usually, since the processing block does not change the mode flag, the values of the mode flag 201 and the mode flag 401 are equal before and after the conversion, and the values of the mode flag 301 and the mode flag 501 are equal. Similarly, the processing block ID 202 and the processing block ID 402 are equal, the RW flag 203 and the RW flag 403 are equal, and the address 204 and the address 404 are equal.

  Next, the read / write operation of the register of the image processing apparatus 10 shown in FIG. 1 will be described using the timing chart of FIG. In FIG. 6, 600 indicates a clock, 601 indicates an output of the transmission unit 100, and 602 to 604 indicate outputs of the processing blocks 101 to 103. Here, the latency for the command of each processing block is 2 clock cycles. Also, assume that values of 0 to 2 are assigned as processing block IDs to the processing blocks 101 to 103, respectively.

  First, a register address, write data, and a processing block number ID are set from the CPU 11 to the transmission unit 100. The transmission unit 100 generates a read register command or a write register command (these are called input commands) in accordance with the input command format 200 shown in FIG. 605 to 607 in FIG. 6 are write register commands for the processing blocks 101 to 103, respectively, and the processing block ID 202 is set to 0-2. 608, 610, and 612 are read register commands for the processing blocks 101 to 103, respectively, and the processing block ID 202 is set to 0 to 2.

  In accordance with the write register commands 605 to 607, the processing blocks 101 to 103 respectively write the register values. Thereafter, as shown in FIG. 6, the processing blocks 101 to 103 generate an output command equivalent to the input command from the write register commands 605 to 607 according to the output command format 400 described in FIG. Output. The receiving unit 104 receives an output command from each processing block. Thereafter, the CPU 11 confirms the write register command received by the receiving unit 104, thereby confirming that the register is normally written.

  Further, the processing block 101 performs a register read operation according to the read register command 608, and then generates an output command 609 according to the output command format 400 described with reference to FIG. 4 and outputs the output command 609 to the subsequent processing block 102. The output command 609 is obtained by setting the register data read from the address specified by the register command 608 in the data area of the register data of the read register command 608. The processing block 102 and the processing block 103 output the output command 609 as it is to the subsequent stage. Thus, the output command 609 is received by the receiving unit 104.

  The read register command 610 is output to the subsequent processing block 102 as it is in the processing block 101. The processing block 102 performs a register read operation according to the read register command 610, then generates an output command 611 according to the output command format 400 described with reference to FIG. 4, and outputs the output command 611 to the subsequent processing block 103. The output command 611 is obtained by setting the register data read from the address specified by the register command 610 in the data area of the register data of the read register command 608. The processing block 103 outputs the output command 611 as it is to the subsequent stage and receives it by the receiving unit 104.

  Further, the read register command 612 is output as it is to the subsequent processing block in the processing blocks 101 and 102. The processing block 103 performs a register read operation according to the read register command 612, then generates an output command 613 according to the output command format 400 described with reference to FIG. 4, and outputs it to the subsequent stage. The output command 613 is obtained by setting the register data read from the address specified by the register command 612 in the data area of the register data of the read register command 612. The output command 613 that is output is received by the receiving unit 104.

  Thereafter, the CPU 11 acquires a register value from the read register command received by the receiving unit 104. As described above, in a plurality of processing blocks connected in series, the output of the previous processing block is input as multiplexed data of the subsequent processing block, and the final processing result is received by the receiving unit 104. become.

  Next, referring to the timing chart of FIG. 7, an image when the image processing apparatus 10 shown in FIG. 1 does not read or write a register during image processing of a predetermined data unit (page, block, band, etc.). The processing operation will be described. In FIG. 7, 700 indicates the output of the transmission unit 100, and 701 to 703 indicate the outputs of the processing blocks 101 to 103, respectively. Here, the latency with respect to the command of each processing block is the value of the end flag 303 indicating that it is the last data after image processing is being performed (data in which the start flag 302 indicating the first data is set is transmitted) Since the command is not transmitted until the set data is transmitted), it is set to two clock cycles as described in FIG. The latency for the data of each processing block is 4 clock cycles.

  First, a register address, write data, and a processing block number ID are set from the CPU 11 to the transmission unit 100. Reference numerals 704 to 706 denote one or more write register commands for the processing blocks 101 to 103, respectively. In the same procedure as described with reference to FIG. 6, the processing blocks 101 to 103 perform a register write operation in accordance with these write registration commands, thereby setting image processing parameters in the processing block. Next, image data for the data unit is transferred from the storage medium such as the DRAM 12 to the transmission unit 100 via the DMAC 13. The transmission unit 100 creates data 707 according to the input data format 300 shown in FIG. 3 and outputs it to the processing block 101. The processing block 101 performs image processing on the input data 707 and then outputs the obtained data 708 to the processing block 102. Similarly, the processing block 102 performs image processing on the input data 708 and then outputs the obtained data 709 to the processing block 103. Further, the processing block 103 performs image processing on the input data 709 and outputs the obtained data 710 to the receiving unit 104. The receiving unit 104 transfers the image-processed data to the DRAM 12 via the DMAC 13.

  Reference numerals 711, 713, and 715 denote one or a plurality of read register commands for observing the internal state after image processing for the processing blocks 101 to 103, respectively. The processing blocks 101 to 103 perform a register read operation according to these read register commands 711, 713, and 715 in the same procedure as described with reference to FIG. The register read results for the processing blocks 101 to 103 are sent to the receiving unit 104 as read register commands 712, 714, and 716, respectively, and are received by the receiving unit 104.

  Thereafter, the CPU 11 acquires a register value from the read register command received by the receiving unit 104.

  Next, an image processing operation when the image processing apparatus 10 shown in FIG. 1 reads a register during image processing of a predetermined data unit (page, block, band, etc.) will be described with reference to the timing chart of FIG. explain. Reference numeral 800 denotes an output of the transmission unit 100, and reference numerals 801 to 803 denote outputs of the processing blocks 101 to 103, respectively. Here, the latency for the data of each processing block is 4 clock cycles. In addition, the latency for the command of each processing block is set in the end flag 303 indicating that it is the last data after image processing is in progress (the data in which the start flag 302 indicating the first data is set is transmitted) Before the transmitted data is transmitted) and when it is transmitted other than during image processing. The latency for the commands (804 to 806 and 816 to 821) transmitted other than during the image processing is two clock cycles as described in FIG. On the other hand, the latency of the commands (811 and 822) transmitted during the image processing is set to 4 clock cycles like the data to be processed.

  First, a register address, write data, and a processing block number ID are set from the CPU 11 to the transmission unit 100. Reference numerals 804 to 806 denote one or a plurality of write register commands for the processing blocks 101 to 103, respectively. In the same procedure as described with reference to FIG. 6, the processing blocks 101 to 103 perform a register write operation according to these register commands, and image processing parameters are set for each of the processing blocks 101 to 103.

  Next, image data for the data unit is transferred from the storage means such as the DRAM 12 to the transmission unit 100 via the DMAC 13. The transmission unit 100 creates data according to the input data format 300 shown in FIG. 3 and outputs the data to the processing block 101 as data 807 and data 812. The transmission unit 100 inserts a read register command 811 for observing the internal state during image processing for the processing block 103 between the data 807 and the data 812 and outputs the processing block 101 with the read register command 811. The processing block 101 performs image processing on the data 807 and 812 and outputs the obtained data 808 and 813 to the processing block 102. At this time, the read register command 811 is sandwiched between the data 808 and the data 813 and is output to the processing block 102 as it is.

  Similarly, the processing block 102 performs image processing on the input data 808 and 813 and outputs the obtained data 809 and 814 to the processing block 103. The read register command 811 is sandwiched between the data 809 and 814 and is output to the processing block 103 as it is. The processing block 103 performs image processing on the input data 809 and 814 and outputs the obtained data 810 and 815 to the receiving unit 104. Further, the processing block 103 executes the read register command 811 and outputs an output command 822 as a result of register reading to the receiving unit 104.

  Thereafter, the receiving unit 104 transfers the image-processed data to the DRAM 12 via the DMAC 13. The CPU 11 can observe the internal state during image processing in the processing block 103 by acquiring the register value from the register read result 815.

  Reference numerals 816, 818, and 820 denote one or a plurality of read register commands for observing the internal state after image processing for the processing blocks 101 to 103, respectively. These read register commands 816, 818, and 820 perform a register read operation on the processing blocks 101 to 107 in the same procedure as described with reference to FIG. The register read results for the processing blocks 101 to 103 are sent to the receiving unit 104 as output commands 817, 819, and 821, and are received by the receiving unit 104. The CPU 11 can observe the internal state after image processing in the processing blocks 101 to 103 by acquiring the register value from the output commands 817, 819, and 821 received by the receiving unit 104.

  Next, FIG. 9 shows a timing chart of data transfer before and after the read register command 811, showing FIG. 8 in more detail. 900 indicates a clock, 901 indicates an output of the transmission unit 100, and 902 to 904 indicate outputs of the processing blocks 101 to 103, respectively. Reference numerals 811 and 812 denote the read register command shown in FIG. 8 and an output command corresponding thereto. As described with reference to FIG. 8, the read register command 811 is a command for performing a register read to the processing block 103. Normally, the latency for the command of the processing block 103 is 2 clocks, but the read register command 811 is a command for reading the register value of the internal state of the processing block 103 when the input data Dn ″ is processed. . Therefore, the latency of the read register command 811 is the same 4 clocks as the data. And the output (output command 822)) maintains the context with the processed data Dn ′ ″ and Dn + 1 ′ ″, while Dn ′ ″, RC_ID2 ′, Dn + 1 ′ Output in the order of '' ...

  Next, referring to the timing chart of FIG. 10, the image processing operation when the image processing apparatus 10 shown in FIG. 1 performs register write during image processing of a predetermined data unit (page, block, band, etc.) will be described. explain. Here, components having the same operation and timing as those in FIG. 8 are denoted by the same reference numerals, and detailed description thereof is omitted. As in FIG. 8, the latency for the data of each processing block is 4 clock cycles. Further, the latency with respect to the command of each processing block is set in the end flag 303 indicating that it is the last data after transmitting the data in which the start flag 302 indicating that it is the first data is transmitted during image processing. Until the transmitted data is transmitted) and when it is transmitted elsewhere. That is, the write register commands (804 to 806 and 816 to 821) transmitted other than during image processing are two clock cycles as described with reference to FIG. On the other hand, the latency of the write register command (1000) transmitted during image processing is assumed to be 4 clock cycles like data.

  The difference from FIG. 8 is that the read register command 811 is replaced with the write register command 1000 for the processing block 103. As described above, the register setting value of the processing block 103 is changed during the image processing operation in units of data. The write register command 1000 is sent from the processing block 103 to the receiving unit 104 as it is, as described with reference to FIG.

  Next, FIG. 11 shows a timing chart of data transfer before and after the write register command 1000, showing FIG. 10 in more detail. In FIG. 11, operations and timings equivalent to those in FIG. 9 are denoted by the same reference numerals, and detailed description thereof is omitted. The difference from FIG. 9 is that the read register command 811 is replaced with the write register command 1000 shown in FIG.

  As described with reference to FIG. 10, the write register command 1000 causes the processing block 103 to perform register write. Usually, the latency for the command of the processing block 103 is 2 clocks. However, since the write register command 1000 is a command for changing the setting of the processing block 103 with respect to image processing after the input data Dn + 1 ″, the latency thereof is the same 4 clocks as the data. The output is in the order of Dn '' ', WC_ID2, Dn + 1' '' ... while maintaining the context with the processed data Dn '' 'and Dn + 1' ''. Is output. However, the register is updated before the data Dn + 1 ″ is processed.

  Next, the processing blocks 101 to 103 described above will be described in detail. FIG. 12 is a block diagram showing an internal configuration of the processing blocks 101 to 103. Reference numeral 1200 denotes a command and data input terminal. A decoder 1201 decodes commands and data input from the input terminal 1200. A register unit 1202 reads and writes register data according to commands from the decoder 1201. Here, the processing parameter is stored by the write operation and is given to the processing unit 1203 via the signal 1211. Further, by reading operation, the stored processing parameter is read or the internal status of the processing unit 1203 is received via the signal 1212 and the value is read. Reference numeral 1211 is a signal for transmitting the processing parameter value to the processing unit 1203, and 1212 is a signal for transmitting the internal status of the processing unit 1203 to the register unit 1202.

  A processing unit 1203 performs predetermined processing (image processing) on data (image data) from the decoder 1201. The decoder 1201 has a separation function that distributes data and commands in the transfer data to the processing unit 1203 and the register unit 1202 based on the mode flags 201, 301, 401, and 501. Reference numeral 1204 denotes a buffer, which guarantees the context of commands and data. A command holding signal 1205 is output from the decoder 1201 to the buffer 1204. Reference numeral 1206 denotes a delay adjustment flip-flop inserted into a system for outputting a command as it is when an input command does not match its own ID. Reference numeral 1207 denotes a delay adjustment flip-flop for the mode flag 201 and the processing block ID 202 decoded by the decoder 1201. Reference numeral 1208 denotes an encoder that generates an output command and data. Reference numeral 1209 denotes a select signal for the encoder 1208 to select an output. Reference numeral 1210 denotes an output terminal for outputting commands and data.

  In FIG. 12, a decoder 1201 separates multiplexed commands and data. The register unit 1202 stores values of image processing parameters, and the processing unit 1203 performs image processing. The buffer 1204 guarantees the time-series context, and the encoder 1208 selects the output of the buffer 1204, the output of the processing unit 1203, and the output of the decoder 1201.

  Next, register read and write operations by the processing block shown in FIG. 12 will be described with reference to FIG. Here, “2” is set in the processing block ID of FIG. 12, and during the image processing (the data with the start flag 302 indicating that it is the first data is transmitted, and then the last data is The operation in the case where the end flag 303 indicating that it is present is not transmitted) will be described. Reference numeral 1300 denotes a clock, and 1301 denotes the timing of input data at the command and data input terminal 1200. Reference numeral 1304 denotes a timing of input data of the register unit 1202, and 1305 denotes a timing of output data of the register unit 1202. 1306 indicates the contents of the command holding signal 1205, 1307 indicates the timing of the output data of the buffer 1204, and 1308 indicates the output data of the flip-flop 1206. 1309 indicates the contents of the select signal 1209, and 1310 indicates the timing of the output data of the encoder 1208 (ie, output data at the output terminal 1210). The encoder 1208 selects the output of the buffer 1204 when the select signal 1209 is “0”, and selects the output of the flip-flop 1206 when it is “2” to generate an output command.

As shown at 1301
In cycle C0, the write register command with processing block ID 202 = 2 and address 204 = 0 is
In cycle C1, the write register command with processing block ID 202 = 2 and address 204 = 1 is
In cycle C2, the read command with processing block ID 202 = 2 and address 204 = 0 is
In cycle C3, the read command with processing block ID 202 = 2 and address 204 = 1 is
-In cycle C4, the write command with processing block ID 202 = 0 is
It is assumed that a read command with processing block ID 202 = 1 is input in cycle C5.

  These input commands are decoded by the decoder 1201. With respect to a command whose processing block ID 202 is “2”, the contents of the RW flag 203, the address 204, and the register data 205 are output to the register unit 1202. If the image is not being processed and the ID is other than “2”, the command is output to the flip-flop 1206 as it is. Then, the signal is delayed by one clock by the flip-flop 1206 and output to the encoder 1208. Further, the mode flag 201 and the processing block ID 202 are input to the flip-flop 1207, delayed there by one clock, and output to the buffer 1204 as the mode flag 401 and the processing block ID 402. In cycles C0 to C5, only commands are input. Accordingly, the decoder 1201 outputs the select signal 1209 in accordance with the latency (2 clock cycles) for the command of the processing block as indicated by the signal content 1309.

That is, as shown at 1304,
In cycle C0, the RW flag 203 = 1, the address 204 = 0, and the register data 205 are output to the register unit 1202,
In cycle C1, the RW flag 203 = 1, the address 204 = 1 and the register data 205 are output to the register unit 1202,
In cycle C2, the RW flag 203 = 0, the address 204 = 0, and the register data 205 are output to the register unit 1202,
In cycle C3, the RW flag 203 = 0, the address 204 = 1, and the register data 205 are output to the register unit 1202.

Also, as shown at 1308,
The write command with the processing block ID 202 = 0 is output to the encoder 1208 in cycle C5,
The read command with the processing block ID 202 = 1 is output to the encoder 1208 in cycle C6.

The encoder 1208 selects the output of the buffer 1204 when the select signal 1209 is “0”, selects the output of the processing unit 1203 when it is “1”, and outputs the flip-flop 1206 when it is “2”. Select. The select signal is
-"0" for the command to be executed in the processing block,
-"1" for data to be processed by the processing block,
・ "2" is displayed for commands not executed in the processing block.
Set. Therefore, as shown in the signal content 1309, the select signal 1209 outputs “0” during the cycles C1 to C4 and “2” during the cycles C5 to C6.

  In the register unit 1202, when the value of the RW flag 203 is “0”, a register read operation of a desired address is performed, and at the same time, the RW flag 403 = 0, the address 404 and the register data 405 are output to the buffer 1204. . At this time, the register read operation is performed after the processing of data input immediately before the register command is completed. When the value of the RW flag 203 is “1”, a register write operation is performed, and the RW flag 403 and address 404 at that time and the register value of the desired address are output to the buffer 1204.

  At this time, the written register data is output to the processing unit 1203 as an image processing parameter. The register read data reflects an internal state or the like input from the processing unit 1203.

That is, as shown at 1305,
At the same time as performing the write operation to the address 204 = 0 in the cycle C1, the RW flag 403 = 1, the address 404 = 0 and the register data 405 are output to the buffer 1204.
In cycle C2, the write operation to the address 204 = 1 is performed, and at the same time, the RW flag 403 = 1, the address 404 = 1 and the register data 405 are output to the buffer 1204.
In cycle C3, the read operation to address 204 = 0 is performed, and at the same time, the RW flag 403 = 0, the address 404 = 0, and the register data 405 are output to the buffer 1204.
In cycle C4, the read operation to the address 204 = 1 is performed, and at the same time, the RW flag 403 = 0, the address 404 = 1, and the register data 405 are output to the buffer 1204.

  The buffer 1204 holds the input data when the command holding signal 1205 is “1”. The value of “1” is transferred by a decoder 1201 during command processing of a predetermined data unit (page, block, band, etc.), that is, during a data transfer, a command transfer such as a register read operation is performed. This is the case.

  In the example of FIG. 13, since no command is transferred during image processing, the command holding signal 1205 has a “0” value. Then, the input mode flag 401, processing block ID 402, RW flag 403, address 404 and register data 405 are output to the encoder 1208 as they are. The encoder 1208 generates an output command according to the output command format 400 shown in FIG. 4 according to the select signal 1209, and outputs it from the output terminal 1210 after one clock cycle.

That is, since the value of the select signal 1209 is “0” during the cycles C1 to C4, the encoder 1208 selects the output of the buffer 1204. Then, the encoder 1208, as shown at 1310,
In cycle C2 after one clock cycle, write command with processing block ID 402 = 2 and address 404 = 0 is
In cycle C3, write command with processing block ID 402 = 2 and address 404 = 1 is
In cycle C4, a read command with processing block ID 402 = 2 and address 404 = 0 is
In cycle C5, the read command with processing block ID 402 = 2 and address 404 = 1 is output to the output terminal 1210.

Since the value of the select signal 1209 is “2” during the cycles C5 to C6, the encoder 1208 selects the output of the flip-flop 1206. Then, the encoder 1208, as shown at 1310,
-In cycle C6 after one clock cycle, write command WC_ID0 with processing block ID 402 = 0 is
In cycle C7, the read command RC_ID1 with the processing block ID 402 = 1 is output to the output terminal 1210.

  Next, referring to FIG. 14, the processing block shown in FIG. 12 is performing image processing of a predetermined data unit (after transmitting the data in which the start flag 302 indicating the first data is set, the last data The image processing operation in the case where the register is read before the data in which the end flag 303 indicating this is set is transmitted) will be described. The predetermined data unit is a unit such as a page, a block, or a band. Here, the processing block ID in FIG. 12 is set to “2” as in FIG. 13, and the latency for the data in the processing block is 4 clock cycles. Further, the latency for the command of each processing block is set to 4 clock cycles as in the case of data when the command is transmitted during image processing.

  In FIG. 14, reference numeral 1400 denotes a clock, and reference numeral 1401 denotes a command and data input terminal 1200. 1402 indicates the timing of input data of the processing unit 1203, and 1403 indicates the timing of output data of the processing unit 1203. 1404 indicates the timing of input data of the register unit 1202, and 1405 indicates the timing of output data of the register unit 1202. Reference numeral 1406 denotes the state of the command holding signal 1205, and 1409 denotes the state of the select signal 1209. Reference numeral 1407 denotes the output data timing of the buffer 1204, and 1410 denotes the output data timing at the command and data output terminal 1210.

  As shown at 1401, the data Dn-1 in cycle C0, the data Dn in cycle C1, the read command of processing block ID 202 = 2 in cycle C2, and the data Dn + 1 to Dn in cycles C3 to C7. The case where +5 is input will be described. Among these input data and commands, the data is decoded by the decoder 1201, and the Start flag 302, the end flag 303, and the data 304 are output to the processing unit 1203 (1402). During image processing, the command RW flag 203, address 204, and register data 205 are output to the register unit 1202 regardless of the value of the processing block ID 202 (1404). This is because, even if the command processing block ID 202 is a value other than “2”, the data and the command are propagated to the subsequent processing block while maintaining the context of the data and the command.

  Further, the mode flag 401 and the processing block ID 402 are output to the flip-flop 1207, delayed by one clock in the flip-flop 1207, and output to the buffer 1204. Data is input to the decoder 1201 except for the period of the cycle C2. The decoder 1201 determines that image processing is being performed during a period in which data is input, and sets the select signal 1209 to “1”. The decoder 1201 sets the select signal 1209 to “0” when a command having its own processing block ID is input. However, the latency of the data of the processing block and the latency for the command received during the image processing are 4 clocks, and the select signal 1209 is output accordingly (1409).

  That is, as indicated by 1402, the start flag 302, the end flag 303, and the data 304 are input to the processing unit 1203 in cycles C0, C1, and C3 to C7. As indicated by 1404, the address 204 and the register data 205 are output to the register unit 1202 in the cycle C 2. The select signal 1209 is “1” during the cycles C0 to C4, C6, and C7 and “0” during the cycle C5, as indicated by 1409.

  The processing unit 1203 performs image processing on the input data with a latency of 4 clock cycles, and outputs a start flag 502, an end flag 503, and data 504 of output data to the encoder 1208 (1403).

  The register unit 1202 performs the register read operation described with reference to FIG. 13 in response to the register read command (RC_ID2) input from the input terminal 1200 in the cycle C2. In other words, as shown in 1405, the read operation to the address 204 is performed in cycle C3, and at the same time, the RW flag 403 = 0, the address 404 and the read register data 405 are output to the buffer 1204.

  As described with reference to FIG. 13, the register read command is detected during image processing of a predetermined data unit (page, block, band, etc.) by the decoder 1201, so that the command holding signal 1205 becomes “1” in cycles C3 and C4. Become. Therefore, the buffer 1204 outputs the mode flag 401, the processing block ID 402, the RW flag 403, the address 404, and the register data 405 input in cycle C3 to the encoder 1208 as they are, and holds those values in cycles C4 and C5. This situation is indicated by 1407.

  The encoder 1208 generates an output command / data having the output command format 400 or the output data format 500 shown in FIG. 4 according to the select signal 1209 indicated by 1409, and outputs it from the output terminal 1210. That is, since the value of the select signal 1209 is “1” during the cycles C0 to C4, C6, and C7, the encoder 1208 selects the output of the processing unit 1203 and sends data to the output terminal 1210 in the cycle after one clock cycle. Output. In cycle C5, since the value of the select signal 1209 is “0”, the encoder 1208 selects the buffer 1204, and outputs a read output command of the processing block ID 402 = 2 and the address 404 = 0 in the cycle one clock cycle later. Output to terminal 1210.

  In the example of FIG. 14, the case where the register read operation is performed during the image processing is shown. However, even when the register write operation is performed, the operation is equivalent to the register read operation. However, in the register write operation, the register update timing is performed before the start of processing for the next data of the register write command.

  Further, the latency adjustment has been described with the latency of the image processing unit being fixed to 4 cycles, but is not limited to this. For example, even when the latency of the image processing unit is variable, a signal indicating a command insertion location is added to the image processing unit, and the output is switched by the signal indicating the command insertion location, thereby changing the order of the command and data. The output can be maintained.

  As described above, according to the present embodiment, commands and data are multiplexed and transferred on a common data bus, and the processing block outputs the processing results while maintaining the order of the input commands and data. As a result, control synchronized with data can be performed between arbitrary data at high speed.

  In the present embodiment, an example is shown in which only one command is transferred with respect to an operation of reading and writing a register during image processing of a data unit (page, block, band, etc.). is not. It will be apparent to those skilled in the art from the description of the above embodiments that a plurality of commands can be transferred and a command can be inserted and transferred at a plurality of locations in the data unit.

In this embodiment, an example in which command transfer during image processing is performed only for one processing block is shown, but it goes without saying that it may be performed for a plurality of processing blocks.
In the above embodiment, an ID for specifying one processing block is described in one command. However, for example, in the case of 1FH (all bits of the processing block ID 202 are 1), all processing blocks are selected. You may do it. For example, a process for writing the same data to the same address in all the processing blocks can be realized with one command.
Moreover, although the case where the number of process blocks is three was demonstrated in the said embodiment, the number of process blocks may be one or more and how many. However, the number that can be represented by the processing block ID is the upper limit.

  Furthermore, in the embodiment, the case where the command for the data of each processing block and the latency for the data are the same has been described, but the present invention is not limited to this. Even when the latencies for commands and data of a plurality of processing blocks are different from each other, it can be coped with by appropriately changing the control of the clock cycle in which the decoder 1201 holds the command in the buffer 1204.

[Other Embodiments]
Although the embodiment has been described in detail above, the present invention can take an embodiment as a system, apparatus, method, program, storage medium, or the like. Specifically, the present invention may be applied to a system composed of a plurality of devices, or may be applied to an apparatus composed of a single device.

  In the present invention, the functions of the above-described embodiments are achieved by supplying a software program directly or remotely to a system or apparatus, and the computer of the system or apparatus reads and executes the supplied program code. Including the case. In this case, the supplied program is a computer program corresponding to the flowchart shown in the drawings in the embodiment.

  Accordingly, since the functions of the present invention are implemented by computer, the program code installed in the computer also implements the present invention. In other words, the present invention includes a computer program itself for realizing the functional processing of the present invention.

  In that case, as long as it has the function of a program, it may be in the form of object code, a program executed by an interpreter, script data supplied to the OS, or the like.

  Examples of the computer-readable storage medium for supplying the computer program include the following. For example, floppy (registered trademark) disk, hard disk, optical disk, magneto-optical disk, MO, CD-ROM, CD-R, CD-RW, magnetic tape, nonvolatile memory card, ROM, DVD (DVD-ROM, DVD- R).

  As another program supply method, a client computer browser is used to connect to a homepage on the Internet, and the computer program of the present invention is downloaded from the homepage to a recording medium such as a hard disk. In this case, the downloaded program may be a compressed file including an automatic installation function. It can also be realized by dividing the program code constituting the program of the present invention into a plurality of files and downloading each file from a different homepage. That is, a WWW server that allows a plurality of users to download a program file for realizing the functional processing of the present invention on a computer is also included in the present invention.

  Further, the program of the present invention may be encrypted, stored in a storage medium such as a CD-ROM, and distributed to users. In this case, a user who has cleared a predetermined condition is allowed to download key information for decryption from a homepage via the Internet, execute an encrypted program using the key information, and install the program on the computer. You can also.

  In addition to the functions of the above-described embodiment being realized by the computer executing the read program, the embodiment of the embodiment is implemented in cooperation with an OS or the like running on the computer based on an instruction of the program. A function may be realized. In this case, the OS or the like performs part or all of the actual processing, and the functions of the above-described embodiments are realized by the processing.

  Furthermore, the program read from the recording medium is written in a memory provided in a function expansion board inserted into the computer or a function expansion unit connected to the computer, so that part or all of the functions of the above-described embodiments are realized. May be. In this case, after a program is written in the function expansion board or function expansion unit, the CPU or the like provided in the function expansion board or function expansion unit performs part or all of the actual processing based on the instructions of the program.

Claims (12)

An image processing method executed by each of a plurality of processing blocks in an image processing apparatus in which a plurality of processing blocks each having a processing unit are connected in series by a common bus,
A data processing step in which image processing using data input to the processing block via the common bus is performed by a processing unit of the processing block;
A command processing step for performing processing corresponding to a command input to the processing block via the common bus to a processing unit of the processing block;
For the first command input to the first processing block via the common bus, the data output by the data processing based on the data input to the first processing block before the first command is completed. And a delaying step of delaying the output of the first command from the first processing block.   2. The process according to claim 1, wherein in the command processing step, processing corresponding to the command is performed on the processing unit that has completed processing using data input to the processing block before the command. Image processing method.   The image processing method according to claim 1, wherein, in the command processing step, a parameter is set in the processing unit that has completed processing using data input to the processing block before the command.   2. The image processing according to claim 1, wherein, in the command processing step, data indicating a state of the processing unit that has finished processing using data input to the processing block before the command is read out. Method.   In the command processing step, data indicating the state of the processing unit of the processing block is read, and in the delaying step, the output of the processing unit that has performed processing using data input to the processing block prior to the command The image processing method according to claim 1, wherein output of data indicating the read state is waited until the operation is completed.   The delaying step includes a storing step of storing, in a buffer, processing results of the command and identification data indicating whether the input of the processing block is data or a command. The image processing method as described. An image processing apparatus having a plurality of processing blocks connected in series by a common bus,
Each of the plurality of processing blocks is
First processing means for performing image processing using data input to the processing block;
Second processing means for performing processing corresponding to the command input to the processing block on the first processing means;
For the first command input to the first processing block via the common bus, the data output by the data processing based on the data input to the first processing block before the first command is completed. And an image processing apparatus comprising: control means for controlling to delay the output of the first command from the first processing block.   The second processing means performs processing according to the command on the first processing means that has finished processing using data input to the processing block before the command. The image processing apparatus according to claim 7.   The said 2nd processing means sets a parameter to the said 1st processing means which complete | finished the process using the data input into the said process block before the said command, The said Claim 7 characterized by the above-mentioned. Image processing device.   8. The second processing means reads data indicating a state of the first processing means that has finished processing using data input to the processing block before the command. An image processing apparatus according to 1.   The second processing unit reads data indicating the state of the first processing unit, and the control unit performs processing using data input to the processing block before the command. 8. The image processing apparatus according to claim 7, wherein the output of the data indicating the read state is waited until the output of the processing means is completed.   8. The image according to claim 7, wherein the control unit further includes a buffer for storing a processing result of the command and identification data indicating whether an input of the processing block is data or a command. Processing equipment.

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