JP2012119041A - Nonvolatile semiconductor memory device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a nonvolatile semiconductor memory device capable of performing erasure verification such that the erasure verification is passed even when an open bit line is present.SOLUTION: The nonvolatile semiconductor memory device includes a first memory cell block in which nonvolatile memory cells are arranged; a defective replacement circuit having a redundant bit line to replace a defective bit line of the first memory cell block; a page buffer including a latch provided for each bit line and storing data to be written to a memory cell selected by a word line or data read out of the memory cell; a batch determination circuit which determines data read out of bit lines and written to the latch of the page buffer together at a time in units of a plurality of bit lines in verification processing; and a second memory cell block in which nonvolatile memory cells are arranged and which stores dummy data written to a latch of the page buffer corresponding to the defective bit line in the verification processing.

Description

  The present invention relates to a nonvolatile semiconductor memory device.

A large-capacity nonvolatile semiconductor memory device such as an EEPROM (Electrically Erasable and Programmable Read Only Memory) has a large number of memory cells, so there is a high possibility that a defective memory cell exists, and a redundant circuit for repairing a defect is provided. Is provided.
This redundant circuit is provided with a redundant column cell array composed of a plurality of replacement bit lines in order to replace a defective bit line when, for example, a bit line becomes defective (see, for example, Patent Document 1).

  In the NAND type EEPROM, when data is read, data is simultaneously read from the memory cell in page units and serially output. When data is written, data is serially input in units of pages and memory is stored in page units. Data is written to the cell. In order to perform this data input / output operation, a large number of column lines, that is, bit lines are each connected to a page buffer having a data latch for temporarily latching read data.

Further, in the NAND type EEPROM, at the time of verify reading for reading write data, it is collectively determined whether or not writing to a memory cell has been sufficiently performed for each page.
Patent Document 1 is an EEPROM having a redundant circuit, and a rewrite / read circuit (page buffer) is connected to a common signal line arranged in common for each bit line in a column unit.
The common signal line is connected to a collective determination signal line (wired OR) in order to collectively determine whether or not writing has been performed in a plurality of columns in a verify read operation after writing. Constitution).

  By the way, in the NAND type EEPROM, data must be erased before data is written. Then, erase verify is performed to determine whether or not the memory cell from which data has been erased has been erased to have a predetermined threshold voltage. As a result of the erase verification, if any one of the memory cells from which data has been erased has failed to be erased, the re-erasure and re-erasure verification operations are repeated.

The erase of the NAND type EEPROM is performed for all of a large number of memory cells arranged in a matrix of rows and columns, a memory cell in one row, or a memory cell in one block in which a plurality of adjacent rows are combined. Done. Normally, a memory cell of a NAND type EEPROM is a floating gate type N channel type MOS transistor provided in a P type well formed on one surface of a semiconductor substrate. Each floating gate type N-channel MOS transistor includes a source and drain region formed in a P-type well apart from each other, and a tunnel oxide film formed on a channel region between the source region and the drain region. And a polycrystalline silicon floating gate (floating gate) formed on the tunnel oxide film, and a control gate formed on the floating gate via a dielectric insulating film.
Therefore, the entire memory cell is erased by applying an erase voltage (for example, about 18V) to the P-type well and simultaneously applying a reference voltage (for example, ground voltage 0V) to the word line connected to the control gate of the memory cell. Is called. As a result, electrons in the floating gate of the memory cell are discharged to the P-type well by an FN (Fowler-Nordheim) current, and are changed to a depletion type transistor having a negative threshold voltage. On the other hand, in the case of partial erasure of memory cells, for example, erasure of memory cells in a selected row block, a ground voltage is applied to a word line connected to a memory cell in the selected row block and a word line in an unselected row block is floated. And by applying an erase voltage to the P-type well. As a result, the word lines in the non-selected row block are almost erased by capacitive coupling and the erasure is automatically prevented, while the word lines in the selected row block maintain the ground voltage. Are erased as described above.

As a result of erasing, when the memory cell has been successfully erased so as to have a predetermined threshold voltage, the memory cell becomes conductive when a ground voltage is applied to the corresponding word line. . Therefore, the erase memory cell becomes an on-cell by erasing.
Erase verification using this is performed after erasure. That is, in the erase verify, for example, an erase verify voltage (for example, ground voltage) is applied to the word line in the selected row block, and the column line, that is, the bit line connected to the drain of the memory cell in the selected row block is supplied from the page buffer. This is done by passing a current.
If the memory cell in the selected row block has been successfully erased to a predetermined threshold voltage, the memory cell in the selected row block is turned on, and the page buffer connected to the bit line is in an initial reset state. maintain. As a result, a pass (success) signal is output to the batch determination signal line connected to the output of the page buffer, and it is determined that erasing of the memory cells in the selected row block is successful. On the other hand, if any one of the memory cells in the selected row block has not been erased successfully, the unerased memory cell operates as a non-conductive off-cell during erase verification. Therefore, the bit line connected to the memory cell is charged to a predetermined voltage by the current from the page buffer, and the page buffer connected to the bit line shows a complementary state to the initial reset state, that is, a fail (failure) state. Fail data is latched. As a result, a fail signal is output to the collective determination signal line, it is determined that the erase has failed, and the erase and erase verify operations are performed again.

JP 2001-250395 A

For example, if there is a defective bit line (open bit line) due to a disconnection that may occur during the manufacturing process of a NAND-type EEPROM, the page in the erase verification is independent of the erase state of the memory cell connected to the bit line. Since the buffer cannot supply current to the memory cell via the bit line, a fail state always appears in the latch of the page buffer.
In this case, even if erasure is repeated for several cycles, there is no pass in the erase verify. Such a fail state caused by the open bit line occurs even if the open bit line is replaced with a replacement bit line. The reason is that the data latch of the page buffer connected to the open bit line always latches fail data every time erase verification is performed. Therefore, if there is an open bit line, there is a problem that even if it is replaced with a replacement bit line, erase verification cannot be passed.

  Therefore, the problem to be solved by the present invention is to provide a nonvolatile semiconductor memory device capable of executing erase verify that passes erase verify even if an open bit line exists, and a nonvolatile semiconductor memory capable of improving yield by column replacement. To provide an apparatus.

  The present invention provides a first memory cell block in which each of a plurality of bit lines and a plurality of word lines intersects, and a nonvolatile memory cell is disposed at the intersecting portion, and a defect in the first memory cell block A defect replacement circuit including a redundant bit line that replaces a bit line, and a latch that is provided for each bit line and stores data to be written to or read from the memory cell selected by the word line A page buffer, a batch determination circuit that collectively reads data read from the bit line and written to the latch of the page buffer in units of a plurality of bit lines in the verify process, and at least one of the plurality of bit lines Each of the above word lines intersects, and a memory cell block in which a nonvolatile memory cell is arranged at the intersecting portion. Different from the first memory cell block, which stores pseudo data written in the verify process in the latch in the page buffer corresponding to the defective bit line replaced with the redundant bit line. A non-volatile semiconductor memory device comprising: a second memory cell block.

  In the nonvolatile semiconductor memory device of the present invention, in the latch of the page buffer corresponding to the defective bit line in the first memory cell block replaced with the redundant bit line, there is data indicating failure as a result of the verify process. The data indicating the defect is rewritten with pseudo data indicating normality stored in the second memory cell block. As a result, the determination in the collective determination circuit can be passed, and even if there is a bit line having an open result, the nonvolatile semiconductor memory device that can execute the erase verify that passes the erase verify, the yield by column replacement is improved A non-volatile semiconductor memory device can be provided.

1 is a block diagram illustrating a configuration example of a nonvolatile semiconductor memory device according to an embodiment of the present invention. FIG. 2 is a diagram illustrating a configuration example of a block BLCk and a spare block 22 in the memory cell array 11 and the redundant column cell array 12 in FIG. 1. It is a figure which shows the detailed structural example of the row decoder 14 in FIG. FIG. 5 is a diagram showing a signal connection relationship between the row decoder 14, the block BLCk, and the spare block 22. FIG. 4 is a diagram showing voltage levels of signals output from a row decoder 14 shown in FIG. 3 to a block BLCk in each operation mode. FIG. 2 is a diagram illustrating a detailed configuration example of a peripheral circuit of a page buffer group 13 in FIG. 1. It is a figure which shows the structural example of the subblock SUNIT in FIG. It is a figure explaining the influence which the open of the bit line BL in the block BLCk, or the short of the adjacent bit line BL has on the determination of the read, write verify process, and erase verify process. 8 is a table showing the states of connection points N1 and N2 in the latch LT of FIG. 7 in reading, writing, and erasing verification of data stored in a nonvolatile memory cell. 10 is a table showing an influence on determination of verify processing of a replacement column cell replaced with a redundant column cell when the bit line BL is open or short in the write verify processing and erase verify processing. FIG. 4 is a diagram showing voltage levels of signals output from the row decoder 14 shown in FIG. 3 to the surplus block 22 in each operation mode. 5 is a flowchart showing an operation example of an erase erase process in the nonvolatile semiconductor memory device in the embodiment. 13 is a timing chart showing the operation of the page buffer PB of FIG. 7 in the processing from step S2 to step S3 of FIG. 10 is a table showing a change in potential of the connection point N1 of the latch LT of the page buffer PB0 and a change in potential of the common verify determination signal line VERIFYPASS for each number of times of stress application.

Embodiments of the present invention will be described below with reference to the drawings.
FIG. 1 is a schematic block diagram showing a configuration example of a NAND type EEPROM which is a nonvolatile semiconductor memory device according to an embodiment of the present invention. FIG. 2 shows a block BLCk (where j is the number of bits of the block address BA, 0 ≦ k ≦ 2 ^j −1), and an arbitrary block is hereinafter referred to as a block BLCk. FIG.
In the memory cell array 11 and the redundant column cell array 12, block BLCk shown in FIG. 2, it is 2 ^j pieces arranged in the wiring direction of the bit line. In this embodiment, for example, j = 6, and 64 blocks BLCk are arranged in the bit line wiring direction.
This block BLCk is provided in units of data erased from the memory cell. As shown in FIG. 2, a plurality of stack gate transistors, that is, electrically rewritable (i + 1) non-volatile memory cells MC0. A NAND cell string NA in which nonvolatile memory cells MCi are connected in series in the column direction (column direction).
The NAND cell string NA is arranged for each of the n bit lines BL0 to BLn−1 in the row direction in the memory cell array 11.
As will be described later, n is a number determined by the number of bits of the column address input from the outside and the number of bits of the data input from the outside.
The NAND cell string NA is arranged for each of x bit lines BLR0 to BLRx-1 in the row direction in the redundant column cell array 12. Note that x is a number determined in consideration of the yield during design.
The bit lines BLR0 to BLRx-1 (redundant bit lines) are bit lines that are replaced with defective bit lines (replaced bit lines) in the memory cell array 11.
The block BLCk is composed of a plurality of NAND cell strings NA in the memory cell array 11 and the redundant column cell array 12.
In the configuration of the block BLCk, the word lines WL (word lines WL0 to WLi) orthogonal to the bit lines BL (bit lines BL0 to BLn−1) are connected to the gates of the nonvolatile memories arranged in the same row. ) Is connected.
i is 0 ≦ i ≦ 2 ^h −1, where ^h is the number of bits of the page address PA. Hereinafter, an arbitrary word line is represented as a word line WLi. In this embodiment, for example, h = 6, and each of the 64 word lines WLi is orthogonal to the n bit lines and the x bit lines.

Between the bit line BL (bit line BL0 to bit line BLn-1) and the redundant bit line BL (bit line BLR0 to bit line BLRx-1) and one end of each NAND cell string NA, A select transistor SG1 for connecting or disconnecting the bit line BL and one end of the NAND cell string NA is inserted.
Further, between the common source line SOURCE and the other end of each of the NAND cell strings NA, a selection transistor SG2 that connects or disconnects the bit line BL and one end of the NAND cell string NA is inserted. It is.
The selection transistors SG1 and SG2 are N-channel MOS transistors, and wirings of selection gate signals SSLk and SGLk arranged in parallel with the word lines WL are connected to the gate electrodes, respectively.
When the nonvolatile memory cell MC is accessed (data read / write), the selection gate signals SSLk and SGLk are set to the “H” level.
As a result, one end of the NAND cell string NA is connected to the bit line BL, and the other end is connected to the common source line SOURCE.
The range of the nonvolatile memory cell MC selected by the one word line WL described above is one page as a unit for writing and reading.

  Each of the cell transistors (nonvolatile memory cell MC0 to nonvolatile memory cell MCi) has a threshold voltage corresponding to data to be held. In the case of a NAND type EEPROM, normally, the state in which the cell transistor is in the depletion type (D type) is the “1” data holding state (erase state), and the cell transistor is in the enhancement type (E type). Is defined as a “0” data holding state (writing state). Further, shifting the threshold voltage of the cell transistor holding “1” data in the positive direction to hold “0” data is called a write operation, and the cell holding “0” data is called Shifting the threshold voltage of the transistor in the negative direction to hold “1” data is called an erasing operation.

Returning to FIG. 1, the memory cell array 11 and the redundant column cell array 12 are provided adjacent to each other, and the word line WL is commonly connected to the gates of the nonvolatile memory cells MC arranged in the same row.
The page buffer group 13 includes a plurality of page buffers PB (described later) provided for each bit line BL in order to write and read data in page units. Each of the page buffers PB in the page buffer group 13 includes a latch circuit that is connected to a corresponding bit line and is used as a sense amplifier circuit that amplifies and determines the potential of the connected bit line.
The row decoder 14 selects the word lines WL of the memory cell array 11 and the redundant column cell array 12.
The column decoder 15 selects the bit line BL and the page buffer PB of the memory cell array 11 and the redundant column cell array 12.
The voltage generation circuit 16 generates various voltages used for data rewriting, erasing, and reading with respect to the nonvolatile memory cell MC from a power supply voltage by a boosting operation or the like.

The input / output circuit 17 outputs an address supplied from the outside to the address register 19, outputs command data indicating a command supplied from the outside to the command register 18, and sends a control signal input from the outside to the control circuit 20. Output.
The input / output circuit 17 outputs data input from the outside to each page buffer of the page buffer group 13 or outputs data read from the nonvolatile memory cell MC to the outside via the page buffer group 13. .
The address register 19 holds an address input from the input / output circuit 17 and outputs the held address to the row decoder 14 and the column decoder 15.
The command register 18 holds command data represented by command data input from the input / output circuit 17.

The control circuit 20 controls operations such as data writing, reading, and erasing to the nonvolatile memory cell MC and a verifying operation according to a control signal input from the input / output circuit 17 and command data supplied from the command register 18. Do.
For example, the control signal is an external clock signal, a chip enable signal, a command latch enable signal, an address latch enable signal, a write enable signal, a read enable signal, or the like. Based on these control signals, the control circuit 20 outputs an internal control signal to each circuit according to the operation mode indicated by the command data.

The batch determination circuit 25 is provided in common for all the page buffers in the page buffer group 13, and collectively determines write and erase data in the page buffer group 13 including a plurality of page buffers, and uses the detection result as detection data. The data is output from the data input / output terminal of the input / output circuit 17.
That is, the collective determination circuit 25 collects whether or not the data indicating writing is written in the latch outputs of all the page buffers in the page buffer group 13 according to the OR configuration described later. To detect.

Next, FIG. 3 is a diagram showing a detailed configuration example of the row decoder 14 in FIG. FIG. 4 is a diagram showing a signal connection relationship between the row decoder 14 and the block BLCk. FIG. 5 is a diagram showing voltage levels of signals output from the row decoder 14 shown in FIG. 3 to the block BLCk in each operation mode.
Of the operation modes shown in FIG. 5, “Program Stress” and “Program Verify” are operation modes that are alternately repeated when the command data input from the input / output circuit 17 represents a “data write command”. They correspond to the data write operation and the write data verify operation after the write operation, respectively. “Erase Stress” and “Erase Verify” are operation modes that are alternately repeated when the command data input from the input / output circuit 17 represents a “data erasure command”. This corresponds to an erase data verify operation after the erase operation. “Read” corresponds to a data read operation when command data input from the input / output circuit 17 represents a “data read command”.

As shown in FIG. 3, the row decoder 14 includes a block decoder 14a and a page decoder 14b.
The block decoder 14a is configured to transfer a block selection signal BLKSELk obtained as a result of decoding the j-bit block address BA held in the address register 19 to each block BLCk (0 ≦ k ≦ 2 ^j −1). It outputs to the gate of 21.
Here, the voltage level of the block selection signal BLKSELk is the voltage level of the voltage generated by the control circuit 20 controlling the voltage generation circuit 16, and as shown in FIG. 5, in each operation mode, the selected block (Selected Block) is selected. ) And a voltage level corresponding to an unselected block (Unselected Block).
As shown in FIG. 3, the transfer transistor group 21 includes N-channel MOS transistors MT0 to MTi, an N-channel MOS transistor MTS, and an N-channel MOS transistor MTG. As shown in FIG. It is provided for.

Returning to FIG. 3, in the page decoder 14b, the address register 19 is input from the input / output circuit 17, the h-bit page address PA held is decoded, and the internal word signal PGi as a result of the decoding is transferred to the transfer transistor. A common output is provided to the drains of the transistors MTi of the group 21. The page decoder 14b outputs the internal selection gate signals iSSL and iSGL in common to the drains of the transistors MTS and MTG of each transfer transistor group 21.
Here, the voltage levels of the internal word signal PGi and the internal selection gate signals iSSL and iSGL are the voltage levels of the voltages generated by the control circuit 20 controlling the voltage generation circuit 16, and depending on each operation mode, FIG. The voltage level shown in FIG.
The transfer transistor group 21 provided for each block BLCk transfers the output of the page decoder 14b in accordance with the voltage level of the block selection signal BLKSELk, and each of the gates of the plurality of NAND cell strings in the block BLCk includes The selection gate signal SSLk and the selection gate signal SGLk having the voltage level shown in FIG. 5 are input, and the voltage levels of the word lines WL0 to WLi are also the voltages shown in FIG.

Next, the operation of the selected block and the non-selected block in each operation mode among the blocks BLCk to which the signals from the row decoder 14 as described above are input will be described. First, the write verification will be described with reference to FIG.
<During write verification>
"Program Stress" mode (writing operation) at the block decoder 14a, based on the block address BA, ² of the ^j blocks BLCK, one block BLCK (hereinafter, the selected block BLCK to) the transfer transistor group 21 In addition, the block selection signal BLKSELk having a voltage level higher than the program voltage Vpgm (for example, a high voltage of about 18 V) by a threshold voltage (Vt) of the transfer transistor of the transfer transistor group 21 is output. A 0V block selection signal BLKSELk is output to the remaining blocks BLCk (hereinafter referred to as non-selected blocks BLCk).
As a result, the output of the page decoder 14b is input only to the selected block BLCk.
The selection gate signal SSLk input to the non-selected block BLCk is set to 0 V by the N-channel MOS transistor MTN to which the logic inversion signal (/ BLKSELk) of the block selection signal BLKSELk output from the block decoder 14a is input to the gate. Fixed. Further, the selection gate signal SGLk input to the non-selected block BLCk and the voltage levels of the word lines WL0 to WLi are respectively floating voltages because the transfer transistor group 21 is turned off.

  The page decoder 14b has an internal word signal PGi of a high voltage VH (a high voltage lower than the program voltage Vpgm and a data write prohibiting voltage to the nonvolatile memory cell MC, for example, 8V), a low voltage VL (a power supply voltage VCC or higher). Internal selection gate signal iSSL of 0 V and internal selection gate signal iSGL of 0V are output to the transfer transistor group 21 of each block BLCk. Since the transfer transistor group 21 of the selection block BLCk is on, the selection gate signal SGLk input to the selection block BLCk and the voltage levels of the word lines WL0 to WLi are the same voltage level as the signal output by the page decoder 14b. It becomes.

Thereafter, the page buffer group 13 applies “H” level (voltage level of the power supply voltage VCC) as “1” data or “L” level (0 V) as “0” data to each bit line BL (details will be described later). ). The voltage generation circuit 16 supplies an arbitrary voltage (for example, the power supply voltage VCC) to the common source line SOURCE. Thereby, in the selected block BLCk, the channels of the non-volatile memory cells MC connected in series in each NAND cell string NA are precharged according to the voltage level applied to the bit line BL. Thereafter, the page decoder 14b applies a program voltage Vpgm to one of the word lines WL0 to WLi (a word line whose position is indicated by the page address PA: a selected word line Word). In the nonvolatile memory cell MC to which “0” data is applied, electrons are injected from the channel of 0 V to the floating gate, the threshold voltage moves in the positive direction, and “0” data is written. Further, in the nonvolatile memory cell MC to which “1” data is applied, electron injection does not occur and there is no threshold voltage change, and the “1” data is held (erased). Of the word lines WL0 to WLi, word lines other than the selected word line Word (referred to as non-selected word lines Word) are supplied with a high voltage VH lower than the program voltage Vpgm. Therefore, in the nonvolatile memory cell MC connected to the non-selected word line Word, electron injection does not occur and there is no threshold voltage change, and “0” data or “1” data is held.
On the other hand, in the non-selected block BLCk, since the selection transistor SG1 is turned off, the channels of the nonvolatile memory cells MC connected in series in each NAND cell string NA are not precharged and the word line WL0. The voltage level of the word line WLi is also a floating voltage. Therefore, the threshold voltage of the nonvolatile memory cell MC does not change, and the retention of “0” data or “1” data is maintained.
The page decoder 14b once sets the internal word signal PGi, the internal selection gate signal iSSL, and the internal selection gate signal iSGL to 0V. However, the block decoder 14a maintains the voltage level of each block selection signal BLKSELk. The voltage generation circuit 16 supplies 0 V to the common source line SOURCE.

In the “Program Verify” operation mode (write verify operation), the page buffer group 13 gives the “H” level to each bit line BL. Further, the page decoder 14b applies 0V to the selected word line Word and the pass voltage Vpass to the non-selected word line Word. Thereby, in the previous write operation, among the nonvolatile memory cells MC to which “0” data or “1” data is to be written, the NAND cell string NA including the nonvolatile memory cells MC to which “0” data has not been written. , A current path to the ground is formed, and the voltage level of the bit line becomes 0V. On the other hand, in the NAND cell string NA in which “0” data is written and includes the nonvolatile memory cell MC, a current path to the ground is not formed, and the voltage level of the bit line maintains the “H” level. As will be described later, in the determination in the page buffer, the former is determined as the data writing to the non-volatile memory cell MC is not performed normally, and the latter is the data writing to the non-volatile memory cell MC is performed normally. It is determined that
Further, in the previous write operation, “1” is given from the page buffer, and in the NAND cell string NA including the nonvolatile memory cell MC holding “1” data, “0” data is not written. Similar to the NAND cell string NA including the memory cell MC, a current path to the ground is formed, and the voltage level of the bit line becomes 0V. However, as will be described later, in this determination in the page buffer, it is determined that data has been normally written into the nonvolatile memory cell MC.

<During erase verification>
"Erase Stress" mode (erasing operation) at the block decoder 14a, based on the block address BA, one of ^{2 j} blocks BLCK, the transfer transistors 21 of one of the selected block BLCK, the block selection of the high voltage VH The signal BLKSELk is output. A 0V block selection signal BLKSELk is output to the remaining unselected blocks BLCk.
As a result, the output of the page decoder 14b is input only to the selected block BLCk.

  The page decoder 14b outputs the internal word signal PGi of 0V, the internal selection gate signal iSSL of the high voltage VH, and the internal selection gate signal iSGL of the high voltage VH to the transfer transistor group 21 of each block BLCk. Since the transfer transistor group 21 of the selection block BLCk is on, the selection gate signal SSLk and the selection gate signal SGLk input to the selection block BLCk are floating voltages that are lower than the high voltage VH by the threshold voltage of the transfer transistor. It becomes. Further, the voltage levels of the word lines WL0 to WLi input to the selected block BLCk are 0V.

Thereafter, the voltage generation circuit 16 sets the common source line SOURCE to a floating voltage, and applies a high voltage (for example, 20 V) to Pwell in which all the blocks including the selected block BLCk are formed. As a result, in the selected block BLCk, in all the nonvolatile memory cells MC, electrons are extracted from the floating gate to the Pwell, the threshold voltage is changed to a negative voltage, and “1” data is held (erased). . On the other hand, in the non-selected block BLCk, since the voltage level of the word lines WL0 to WLi is a floating voltage, the floating gate of the nonvolatile memory cell MC is also boosted, so that electrons are not pulled out by Pwell. That is, the threshold voltage does not change, and the holding state of “0” data or “1” data is maintained.
The page decoder 14b once sets the internal selection gate signal iSSL and the internal selection gate signal iSGL to 0V.
Then, the voltage generation circuit 16 returns the voltage of Pwell to a normal voltage (for example, 0 V or a negative voltage) and supplies 0 V to the common source line SOURCE.

In the “Erase Verify” operation mode (erase verify operation), the page buffer group 13 applies the “H” level to each bit line BL. The block decoder 14a outputs a block selection signal BLKSELk having a voltage higher than the high voltage VH by the threshold voltage of the transfer transistor to the transfer transistor group 21 of the selected block BLCk. Note that the block selection signal BLKSELk of 0V is output to the non-selected block BLCk. The page decoder 14b supplies the high voltage VH to the internal selection gate signal iSSL and the internal selection gate signal iSGL. Thereby, the selection gate signal SSLk and the selection gate signal SGLk input to the selection block BLCk become the high voltage VH. Further, the voltage levels of the word lines WL0 to WLi input to the selected block BLCk remain 0V. On the other hand, the selection gate signal SSLk input to the non-selected block BLCk becomes 0 V by the logical inversion signal (/ BLKSELk) of the block selection signal BLKSELk, as in the write operation and the write verify operation.
Thereby, in the previous erase operation, a current path to the ground is formed in the NAND cell string NA including the nonvolatile memory cells MC in which all “1” data is written, and the voltage level of the bit line becomes 0V. On the other hand, in the NAND cell string NA including at least one nonvolatile memory cell MC in which “1” data is not written, a current path to the ground is not formed, and the voltage level of the bit line maintains the “H” level. . As will be described later, in the determination in the page buffer, the former is determined to be successful in writing data to the nonvolatile memory cell MC, and the latter is not normally successful in writing data to the nonvolatile memory cell MC. It is determined that
In the non-selected block BLCk, since the input selection gate signal SSLk is 0 V, the NAND cell string NA is not connected to the bit line BL and does not form a current path to the ground.

<When reading>
In the “Read” operation mode (read operation), the block decoder 14a selects a block having a voltage level higher than the pass voltage Vpass by the threshold voltage of the transfer transistor in the transfer transistor group 21 of one selected block BLCk based on the block address BA. The signal BLKSELk is output. A 0V block selection signal BLKSELk is output to the remaining unselected blocks BLCk.
As a result, the output of the page decoder 14b is input only to the selected block BLCk.
The selection gate signal SSLk input to the non-selected block BLCk is set to 0 V by the N-channel MOS transistor MTN to which the logic inversion signal (/ BLKSELK) of the block selection signal BLKSELk output from the block decoder 14a is input to the gate. Fixed. Further, the selection gate signal SGLk input to the non-selected block BLCk and the voltage levels of the word lines WL0 to WLi are respectively floating voltages because the transfer transistor group 21 is turned off.
The page buffer group 13 applies an “H” level to each bit line BL. Further, the page decoder 14b applies 0V to the selected word line Word and a pass voltage Vpass to the non-selected word line Word. As a result, the NAND cell string NA in which “1” data is written in the nonvolatile memory cell MC to which the selected word line Word is connected by the write operation forms a current path to the ground, and the voltage level of the bit line is set. 0V. On the other hand, the NAND cell string NA in which “0” data is written in the nonvolatile memory cell MC to which the selected word line is connected does not form a current path to the ground, and the voltage level of the bit line is “ Maintain the “H” level. As described later, the page buffer outputs “0” data or “1” data according to the voltage level of the bit line.
In the non-selected block BLCk, since the input selection gate signal SSLk is 0V, the NAND cell string NA is not connected to the bit line BL, and does not affect the read voltage change of the bit line.

Returning to FIG. 1, the surplus block 22, which is a characteristic part of the present invention, is arranged between the plurality of blocks BLCk constituting the memory cell array 11 and the redundant column cell array 12 described above and the page buffer group 13.
As shown in FIG. 2, the surplus block 22 includes a plurality of NAND cell strings NA, and the bit line BL is shared with the bit lines of the plurality of blocks BLCk. Also. The surplus block 22 is configured to receive a signal corresponding to each signal input to each block BLCk. FIG. 4 is a diagram showing a relationship between each block BLCk and a signal input from the row decoder 14 to the surplus block 22. In the figure, only the page decoder 14b is shown, and the block decoder 14a is omitted. The block selection signal BLKSEL is input from the block decoder 14a to the transfer transistor group 21 of the surplus block 22. Further, in each of the operation modes described above, the page decoder 14b sends the internal selection gate signal iESSL, the internal selection gate signal iESGL, and the internal word signals EPG0 to EPGi to the transfer transistor group 21 of the surplus block 22, respectively. Output to the drains of the transistors MTS and MTG, MT0 to MTi.
Further, the transfer transistor group 21 provided for the surplus block 22 transfers the output of the page decoder 14b according to the voltage level of the block selection signal BLKSEL, and to each of the gates of a plurality of NAND cell strings in the surplus block 22. Are inputted with the selection gate signal ESSL and the selection gate signal ESGL. Further, each of the gates of the plurality of NAND cell strings is commonly connected to the word lines EWL0 to EWLi similarly to the plurality of NAND cell strings in the block BLCk.
Here, the voltage levels of the internal word signal EPGi and the internal selection gate signals iESSL and iESGL are the voltage levels of the voltages generated by the control circuit 20 controlling the voltage generation circuit 16, and change according to each operation mode. Is.
The voltage level in each operation mode will be described in detail together with the operation in each operation mode of the selected block BLCk after describing the configuration of the page buffer group 13.

Next, the detailed configuration and operation of the page buffer group 13 in FIG. 1 will be described with reference to FIGS.
FIG. 6 is a diagram showing a configuration example of peripheral circuits of the page buffer group 13 in FIG. FIG. 7 is a diagram illustrating a detailed configuration example of the page buffer group 13.
In this embodiment, the column decoder 15 divides the column address indicating the position of the bit line inputted from the outside into groups of p-bit, r-bit, and t-bit column addresses, and decodes them to 2 ^p (= q) column address signals DY1W [7: 0] and DY1W [7: 0], 2 ^r (= s) column address signals DY2 [7: 0], 2 ^t (= u) ) The column address signal DY3 [7: 0] is output. These correspond to the number of bit lines BL. If the number of bits of data input from the outside is w bits, the number of bit lines BL is w × q × s × u.
FIG. 6 shows a case where q = s = u = 8 and w = 64, and there are 32768 bit lines BL in total. That is, each of the NAND cell strings NA in the block BLCk described above is commonly connected to each of the bit lines BL (BL [32767: 0]). Further, the page buffer group 13 is divided into column unit CUNIT [63: 0] units composed of 512 bit lines, that is, 64 pieces. Further, the column unit CUNIT [63: 0] is divided into subunit SUNIT [63: 0] units composed of 8 bit lines, that is, 64 units.
That is, the column unit is composed of 64 subunits SUNIT. For example, each group of subunits SUNIT0 to SUNIT63, SUNIT64 to SUNIT127,..., SUNIT4032 to SUNIT4095 forms a column unit.

Each of the transfer circuits PBT is provided in each of the subunits SUNIT. For example, the transfer circuit PBT0 is provided in the subunit SUNIT0. The transfer circuit PBT1 is provided in the subunit SUNIT1, the transfer circuit PBT2 is provided in the subunit SUNIT2,..., And the transfer circuit PBT63 is provided in the subunit SUNIT63.
The transfer circuit PBT uses any of the page buffers PBx8 [7: 0] of the subunits SUNIT0 to SBLK4095 as a data write line DINBUS or data according to the column address signals DY2 [7: 0] and DY3 [7: 0]. It is selected whether to connect to the readout line DOUTBUS.
In addition, since one data write line DINBUS and one data read line DOUTBUS are provided for each column unit, there are 64 (DINBUS [63: 0], DOUTBUS [63: 0]).

The charge circuit 26 precharges each of the data read lines DOUTBUS [63: 0] to a predetermined voltage during reading in the normal operation mode, and outputs a common verify output as an OR configuration output when reading the detection result in the erase verify. The determination signal line VERIFYPASS is precharged to a predetermined voltage.
In FIG. 6, only one input / output circuit 17 and one pad 100 are shown, but actually, for example, eight pads 100 are provided for 64 column units. A multiplexer circuit (not shown) is provided between the input / output circuit 17. The input / output circuit 17 supplies 64-bit data input from the outside to each of DINBUS [63: 0] connected to 64 column units serially in units of 8 bits via a multiplexer circuit. The input / output circuit 17 outputs the data read from DOUTBUS [63: 0] connected to the 64 column units via the multiplexer circuit in 8-bit serial.

The column decoder 15 commonly uses a column address signal DY1W [7: 0], a column address signal DY1R [7: 0], a column address signal DY2 [7: 0], and a column address for each of the 64 column units CUNIT. The signal DY3 [7: 0] is supplied.
Further, the column addresses DY1W [7: 0] and DY1R [7: 0] are respectively supplied to the sub-uni and the page buffer PB [7: 0] in the sub-uni. For example, column addresses DY1W0 and DY1R0 are supplied to the page buffer PB0.
The column addresses DY1W [7: 0] and DY1R [7: 0] are used to select which page buffer group 13 in each subunit SUNIT is connected to the transfer circuit PBT (described later).

The column address signal DY1W [7: 0], the column address signal DY1R [7: 0], the column address signal DY2 [7: 0], and the column address signal DY3 [7: 0] described above, one for each column unit CUNIT. The bit line BL is selected, and the input / output circuit 17 reads data from the page buffer in the page buffer group 13 corresponding to the selected bit line BL, and outputs the data to the outside via the pad 100.
However, the common verify determination signal line VERIFYPASS is commonly connected to the page buffers in all the page buffer groups 13 in the 64 column units.

Next, FIG. 7 is a diagram illustrating a configuration example of one subunit SUNIT, for example, subunit SUNIT0.
The subunit SUNIT0 has page buffers PB0 to PB7 (that is, PB [7: 0]).
Bit line BL0 is connected to page buffer PB0, bit line BL1 is connected to page buffer PB1,..., Bit line BL7 is connected to page buffer PB7.

The page buffer PB has the same configuration, and the page buffer PB0 will be described below as an example.
The page buffer PB0 includes transistors 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, and 44, and a latch LT.
Here, the transistors 31 and 32 are P-channel MOS (Metal Oxide Semiconductor) transistors. On the other hand, the transistors 33 to 44 are N-channel MOS transistors.
The latch LT is composed of inverters IV1 and IV2. Here, the inverter IV1 has an output terminal connected to the input terminal of the inverter IV2 at the connection point N2, and an input terminal connected to the output terminal of the inverter IV2 at the connection point N1.

The transistor 31 has a source connected to the power supply wiring, a gate connected to the control signal PLOAD, and a drain connected to the gate of the transistor 33.
The transistor 32 has a source connected to the power supply wiring, a gate connected to the wiring of the control signal PBRST, and a drain connected to the drain of the transistor 33 at the connection point N1.
The source of the transistor 33 is connected to the drain of the transistor 34.
The transistor 34 has a gate connected to the wiring of the control signal PBLCH and a source grounded.

The transistor 35 has a drain connected to the common verify determination signal line VERIFYPASS, a gate connected to the connection point N1, and a source connected to the drain of the transistor 36.
The transistor 36 has a gate connected to the wiring of the control signal PVTR and a source grounded.
The transistor 37 has a drain connected to the common verify determination signal line VERIFYPASS, a gate connected to the connection point N2, and a source connected to the drain of the transistor 38.
The transistor 38 has a gate connected to the wiring of the control signal EVTR and a source grounded.

The transistor 41 has a drain connected to the bit line BL0, a gate connected to the control signal BLSLT, and a source connected to the source of the transistor 31 at a connection point SO.
The transistor 42 has a drain connected to the bit line BL0, a gate connected to the wiring of the control signal PDIS, and a source grounded.
The transistor 40 has a drain connected to the source of the transistor 41 at the connection point SO, a gate connected to the wiring of the control signal PBGM, and a source connected to the connection point N2.
The transistor 39 has a drain connected to the connection point N2, a gate connected to the wiring of the column address DY1W0, and a source connected to the transfer circuit PBT0.
The transistor 43 has a drain connected to the transfer circuit PBT0, a gate connected to the wiring of the column address DY1R0, and a source connected to the drain of the transistor 44.
The transistor 44 has a gate connected to the connection point N2, and a source grounded.
The page buffers PB1,..., PB7 have the same configuration as the above-described page buffer PB0.

The transfer circuit PBT0 is provided in the subunit SUNIT0, and controls connection and disconnection between the source of the transistor 39 and the write line DINBUS0 in the page buffers PB0 to PB7, and the drain of the transistor 43 and the data read line DOUTBUS0. To control connection and disconnection.
The transfer circuit PBT0 includes transistors 51 and 52, which are n-channel MOS transistors, and an AND circuit 50.
The transistor 51 has a drain commonly connected to the sources of the transistors 39 in the page buffers PB0 to PB7, a gate connected to the output of the AND circuit 50, and a source connected to the write line DINBUS0.
The transistor 52 has a drain commonly connected to the drains of the transistors 43 in the page buffers PB0 to PB7, and a source connected to the data read line DOUTBUS.
In the AND circuit 50, each of the column address signal DY2 [7: 0] and the column address signal DY3 [7: 0] is supplied from the column decoder 15 to the corresponding input terminal, and the column address is data indicating the subunit SUNIT0. The transistors 51 and 52 are turned on ("H" level signals are output to the gates of the transistors 51 and 52).

The charge circuit 26 includes transistors 53 and 54 that are P-channel MOS transistors.
The transistor 53 has a source connected to the power supply wiring, a gate connected to the control signal VERIFYB, and a drain connected to the common verify determination signal line VERIFYPASS.
The transistor 54 has a source connected to the power supply wiring, a gate connected to the control signal BUSPC, and a drain connected to the data data read line DOUTBUS0.

Next, FIG. 8 shows the writing of the column cell in the replacement bit line (defective bit line) replaced with the redundant column cell in the redundant bit line by the opening of the bit line BL in the selected block BLCk or the shorting of the adjacent bit line BL. It is a figure explaining the influence which it has on the determination of erasure verification.
FIG. 9 is a table showing the states of the connection points N1 and N2 in the latch LT of FIG. 7 in reading, writing and erasing verification of data stored in the nonvolatile memory cell.
The operation of the page buffer PB0 will be described below with reference to FIGS.

<When reading>
At the time of reading, command data indicating reading is input from the outside, data for setting the reading mode is set in the command register 18, and the control circuit 20 outputs a control signal for controlling each circuit based on this data. In the initial state, the control circuit 20 sets the control signals PDIS, BLSLT, PPGM, PBLCH, PVTR, EVTR to the “L” level, and sets the control signals PLOAD, PBRST to the “H” level.
Further, the column decoder 15 sets the column addresses DYIW0 and DY1R0 to the “L” level.
The control circuit 20 changes the control signal PBRST to the “L” level, forcibly applies the “H” level data to the connection point N1, and prepares a reset (RESET) operation before reading data from the nonvolatile memory cell MC. I do. As a result, the data at the connection point N1 at the “H” level and the data at the “L” level at the connection point N2 are written in the latch LT, and the data at the time of resetting is stored.
Then, the control circuit 20 changes the control signal PBRST to the “H” level, turns off the transistor 32, and ends the reset process as the data setting shown in FIG.

When reading data from the nonvolatile memory cell MC, the control circuit 20 sets the control signal PDIS to the “H” level, turns on the transistor 42, and temporarily changes the potential of the bit line BL to the ground level.
Then, the control circuit 20 changes the control signal PDIS and the control signal PLOAD to the “L” level, and changes the control signal BLSLT to the “H” level.
Thus, the transistor 42 is turned off, and the transistors 31 and 41 are turned on. Then, the bit line BL is precharged to the “H” level via the transistors 31 and 41.

Next, the control circuit 20 sets the control signal PLOAD to the “H” level and turns off the transistor 31.
Then, the control circuit 20 changes the control signal PBRST to the “L” level and changes the control signal PBLCH to the “H” level.
As a result, the transistors 32 and 33 are turned on, and data is read from the nonvolatile memory cell MC to which the word line WL selected by the row decoder 14 is connected to the gate. Here, the row decoder 14 selects one of the blocks BLCk, and sets the selected word line Word in the selected block BLCk to 0V. The row decoder 14 applies the pass voltage Vpass voltage generated by the voltage generation circuit 16 to all the non-selected word lines Word other than the selected word line WL, and the non-selected word lines Word other than the selected word line Word. All the nonvolatile memory cells MC connected to the gate are turned on.
Further, the control circuit 20 changes the control signal PBLCH to the “H” level to turn on the transistor 34.

As a result, when “0” data is written in the nonvolatile memory cell MC, the nonvolatile memory cell MC is in the off state, the bit line BL remains at the “H” level, and the transistor 33 is in the on state. is there.
For this reason, the potential at the connection point N1 changes to the “L” level as shown in FIG. 9 due to the current through the transistors 33 and 34. Further, the potential of the connection point N2 is at “H” level.
On the other hand, when “1” data is written in the non-volatile memory cell MC, the non-volatile memory cell MC is turned on, the bit line BL is changed to “L” level, and the transistor 33 remains off. .
For this reason, since the transistor 33 is in the OFF state, the potential at the connection point N1 does not flow to the ground point, and remains at the “H” level as shown in FIG. Similarly, the potential at the connection point N2 also remains at the “L” level.

Next, the control circuit 20 sets the control signal BUSPC to the “L” level, turns on the transistor 54, and precharges the data read line DOUTBUS0 to the “H” level.
Then, the control circuit 20 sets the control signal BUSPC to the “H” level, turns off the transistor 54, and ends the precharge process.
After the precharge is completed, the column decoder 15 sets the control signal DY1R0 to the “H” level in order to select the page buffer PB0 corresponding to the input address.
The column decoder 15 selects one of the subunits in each column unit corresponding to the input address, for example, the subunit SUNIT0, and the column addresses DY2 and DY3 from which the AND circuit 50 outputs the “H” level. Is output. Here, the transistors 51 and 52 are turned on. In the description of the present embodiment, in each of the 64 column units, any one subunit SUNIT is selected from the 64 subunits SUNIT. A column unit including units SUNIT0 to SUNIT63 is described.

Thus, when data “0” is written in the nonvolatile memory cell MC, the connection point N2 is at “H” level and the transistor 44 is turned on, so that the data read line DOUTBUS0 is connected to the transistors 52 and 43. And 44 are grounded to become “L” level, and data of this “L” level is output to the outside as “0” via the input / output circuit 17.
On the other hand, when data “1” is written in the nonvolatile memory cell MC, the connection point N2 is at the “L” level and the transistor 44 is turned off, so that the data read line DOUTBUS0 is not grounded. The “H” level is maintained, and this “H” level data is output to the outside as “1” via the input / output circuit 17.

<During write verification>
“0” data or “1” data is written to all the nonvolatile memory cells, and it is determined whether or not the data is normally written.
At the time of writing verify, command data indicating writing is input from the outside, data for setting the writing verify mode is set in the command register 18, and the control circuit 20 outputs a control signal for controlling each circuit based on this data. In the initial state, the control circuit 20 sets the control signals PDIS, BLSLT, PPGM, PBLCH, PVTR, EVTR to the “L” level, and sets the control signals PLOAD, PBRST to the “H” level.
Further, the column decoder 15 sets the column addresses DYIW0 and DY1R0 to the “L” level.

Control circuit 20 changes control signal PLOAD to “L” level and changes control signal PBLCH to “H” level. Thereby, the transistor 31 is turned on, the connection point SO is set to the “H” level, and the transistor 33 is turned on. Further, when the transistor 34 is turned on, “L” level data is forcibly applied to the connection point N1, and a pre-reset (RESET) operation for writing data from the nonvolatile memory cell MC is performed. As a result, the data at the connection point N1 at the “L” level and the data at the “H” level at the connection point N2 are written into the latch LT, and the data at the time of resetting is stored (INHIBIT state).
Then, the control circuit 20 changes the control signal PLOAD to the “H” level, changes the control signal PBLCH to the “L” level, turns off the transistors 31 and 34, and performs the reset process as the data setting shown in FIG. finish.

Next, the control circuit 20 supplies data of “L” level or “H” level to the write line DINBUS0 in order to write “0” data or “1” data to the nonvolatile memory cell MC.
Since the column decoder 15 selects the subunit SUNIT0 corresponding to the column address output from the address register 19, the AND circuit 50 corresponding to the subunit SUNIT0 outputs the column address signal DY2 and the column to which the “H” level is output. The address signal DY3 is output. Here, the transistors 51 and 52 are turned on.
Further, the column decoder 15 writes the control signal DY1W0 to “H” to write “L” level data as “0” data to the connection points N2 of the latches LT of all the page buffers PB0 to PB7 of the selected subunit SUNIT0. Level. As a result, the transistor 39 is turned on.
As described above, when “L” level data is written from the write line DINBUS0 to the connection point N2 via the transistor 39, as shown in FIG. The connection point N1 of the LT is at the “H” level, and the connection point N2 is at the “L” level. On the other hand, when writing “1” data, the connection point N1 of the latch LT is at the “L” level and the connection point N2 is at the “H” level, and this maintains the initial state.

Next, the control circuit 20 sets the control signal DY1W0 to the “L” level to turn off the transistors 39 of the page buffers PB0 to PB7.
In this process, data is written to the latch LT in the page buffer PB by sequentially changing the column address. That is, the control circuit 20 sequentially switches the column address signal DY2 [7: 0] and the column address signal DY3 [7: 0] generated from the address, and selects any one of the subunits SUNIT in the column unit. Then, the column address signal DY1W [7: 0] is sequentially changed to select one of the page buffers PB0 to PB7 in the selected subunit SUNIT, and the write operation to the selected latch LT is repeatedly performed. Here, for example, the control circuit 20 sequentially switches the column addresses DY2 [7: 0] and DY3 [7: 0], and sequentially selects the column address DY1W [7: 0] in the subunit SUNIT selected in this state. As a result, the “L” level data is written as the data “0” to the connection point N2 of the latch LT of the selected page buffer PB.
Then, the control circuit 20 sets the control signals PPGM and BLSLT to the “H” level.
In addition, the row decoder 14 selects one of the blocks BLCk and supplies the program voltage Vpgm to the selected word line Word in the selected block BLCk. The row decoder 14 supplies the high voltage VH to all non-selected word lines Word other than the selected word line Word.
As a result, the source, drain, and channel portions of the nonvolatile memory cell MC to which data “0” connected to the selected word line Word is to be written are set to the “L” level, and charges are written into the nonvolatile memory cell MC. , “0” data is stored.
Further, since the source, drain, and channel portions of the nonvolatile memory cell MC to which data “1” is to be written are at “H” level, no charge is written to the nonvolatile memory cell MC, and “1” data is maintained. The
Then, the row decoder 14 changes the selected word line Word and the unselected word line Word to 0 V, and the writing process is completed.

Next, in order to determine whether or not data has been normally written (write verify), the control circuit 20 reads the data of the nonvolatile memory cell MC into the page buffer PB.
That is, when reading data from the nonvolatile memory cell MC, the control circuit 20 sets the control signal PDIS to the “H” level, turns on the transistor 42, and changes the potential of the bit line BL to the ground level.
Then, the control circuit 20 changes the control signals PDIS and PLOAD to the “L” level and changes the control signal BLSLT to the “H” level.
Thus, the transistor 42 is turned off, and the transistors 31 and 41 are turned on. Then, the bit line BL is precharged to the “H” level via the transistors 31 and 41.

Next, the control circuit 20 sets the control signal PLOAD to the “H” level and turns off the transistor 31.
Then, the control circuit 20 changes the control signal PBRST to the “L” level and changes the control signal PBLGH to the “H” level.
As a result, the transistors 32 and 33 are turned on, and data is read from the nonvolatile memory cell MC to which the selected word line Word selected by the row decoder 14 is connected to the gate. Here, the row decoder 14 sets the selected word line Word to 0 V, applies the pass voltage Vpass generated by the voltage generation circuit 16 to all the unselected word lines Word other than the selected selected word line Word, and unselects the selected word line Word. All the nonvolatile memory cells MC to which the word line Word is connected to the gate are turned on.
Further, the control circuit 20 changes the control signal PBLCH to the “H” level to turn on the transistor 34.
Thereby, when “0” data is written in the nonvolatile memory cell MC to which “0” data is to be written, the connection point SO remains at the “H” level, so that the connection point N1 of the latch LT is at the “L” level. The connection point N2 becomes “H” level.
On the other hand, when “0” data is not written in the nonvolatile memory cell MC to which “0” data is to be written, the connection point SO becomes “L” level, the latch LT cannot be inverted, and the connection point N1 of the latch LT is The “H” level and the connection point N2 at the “L” level remain in the written state (a state opposite to the initial state).
In the case of the nonvolatile memory cell MC in which “1” data is written, the latch LT maintains the initial state even when the connection point SO becomes the “L” level. N1 is at “L” level and the connection point N2 is at “H” level.

After the data of the non-volatile memory cells MC sharing the word line WL of the block BLCk are read to all the latches LT, the control circuit 20 changes the control signal VERIFYB to “L” level to determine the common verify The signal line VERIFYPASS is precharged to “H” level.
Then, the control circuit 20 sets the control signal PVTR to the “H” level, and turns on the transistors 36 of all the page buffers PB of the column unit connected to the block BLCk.
At this time, when the connection points N1 in all the page buffers PB of the column units connected to the block BLCk are at the “L” level, all the transistors 35 are not turned on.
For this reason, when the transistors 35 of the page buffers PB of all the column units connected to the block BLCk are in the OFF state, the common verify determination signal line VERIFYPASS remains at the “H” level and the “H” level is output from the data terminal. It can be detected that data has been normally written to the nonvolatile memory cells MC of the block BLCk. The above-described operation is similarly performed in the other blocks BLCk.

On the other hand, when the connection point N1 in any page buffer PB of the page buffer group 13 is at “H” level, the transistor 35 in the page buffer PB at the connection point N1 at “H” level is turned on. .
For this reason, when the transistor 35 of any page buffer PB in the page buffer group 13 is turned on, the common verify determination signal line VERIFYPASS changes from “H” level to “L” level, and “L” is output from the data terminal. It is detected that data is not normally written to the nonvolatile memory cell MC of the block BLCk having the “level”.
The above-described operation is similarly performed in the other blocks BLCk.

<During erase verification>
The above-described erasing process is performed on all nonvolatile memory cells, and it is determined whether or not the data has been normally erased.
At the time of erase verify, command data indicating erase verify is input from the outside, data for setting an erase verify mode is set in the command register 18, and the control circuit 20 outputs a control signal for controlling each circuit based on this data. . In the initial state, the control circuit 20 sets the control signals PDIS, BLSLT, PPGM, PBLCH, PVTR, and EVTR to the “L” level, and sets the control signals PLOAD, PBRST, VERIFYB, and BUSPC to the “H” level.
Further, the column decoder 15 sets the column address signal DYIW0 and the column address signal DY1R0 to the “L” level.

The control circuit 20 causes the voltage generation circuit 16 to generate an erase voltage necessary for erasing data in the nonvolatile memory cell, and applies this erase voltage to the nonvolatile memory cell MC in the selected block BLCk (for erasure). Stress applied).
Thereby, as described above, the erasing process of the data in all the nonvolatile memory cells of all the blocks BLCk to which the erasing voltage is applied is performed at once.
Next, the control circuit 20 changes the control signal PBRST to the “L” level, turns on the transistor 32, and performs a reset operation for forcibly writing “H” level data to the connection point N1 of the latch LT. As a result, as shown in the table of FIG. 6, data at the connection point N1 of the latch LT is written at the “H” level, and data at the “L” level is written at the connection point N2.
Then, the control circuit 20 changes the control signal PBRST to the “H” level, turns off the transistor 32, and ends the reset process.

Next, the control circuit 20 changes the control signal PDIS to the “H” level, and once sets the potential of the bit line BL to the ground level.
Then, after changing the control signal PDIS to the “L” level, the control circuit 20 sets the control signal PLOAD to the “L” level, the control signal BLSLT to the “H” level, and turns on the transistors 31 and 41. .
As a result, the bit line BL is precharged to the “H” level via the transistors 31 and 41. At this time, the control circuit 20 controls the page decoder 14b to set the internal selection gate signal iSSL and the internal selection gate signal iSGL to 0V. Therefore, in the selection block BLCk, the input selection gate signal SSLk and selection gate signal SGLk are 0 V, and the NAND cell string NA is not connected to the bit line.
After a predetermined time has elapsed, the control circuit 20 changes the control signal PLOAD to the “H” level, turns the transistor 31 off, changes the control line BLSLT to the “L” level, turns the transistor 41 off, and connects The precharge of the point SO and the bit line BL is finished. This predetermined time is a time until the potential of the connection point SO and the bit line BL measured in advance is stabilized at a precharge voltage.

The row decoder 14 supplies the high voltage VH to the selection gate signal SSLk and the selection gate signal SGLk that are input in the selection block BLCk by the control signal from the control circuit 20, and the selection NAND cell string NA is connected to the bit line. The
Since the row decoder 14 sets all the word lines WL to 0 V, the data of all the nonvolatile memory cells MC in the block BLCk connected to each bit line BL is erased by applying the erase voltage. The NAND cell string NA becomes conductive, and if data is not erased in any one of the nonvolatile memory cells MC in the NAND cell string NA, the NAND cell string NA becomes non-conductive.
Next, the control circuit 20 sets the selection gate signals SSLk and SGLk in FIG. 2 to the “H” level, and turns on the selection transistors SG1 and SG2.
As a result, when all the nonvolatile memory cells MC of the NAND cell string NA connected to the bit line BL are in the ON state, the NAND cell string NA is in the conductive state, so that the bit line BL is at the ground level, that is, the “L” level. It becomes.
On the other hand, if writing of “0” data is not erased in any one of the nonvolatile memory cells MC of the NAND cell string NA connected to the bit line BL, the nonvolatile memory cell MC is not turned on, Since NAND cell string NA is rendered non-conductive, bit line BL remains in a precharged state, that is, “H” level.

Next, the control circuit 20 changes the control signal BLSLT to “H” level to turn on the transistor 41.
Thereby, “0” data is written in the non-volatile memory cell MC at the connection point SO. When the bit line BL is at the “H” level, the connection point SO remains at the “H” level. When the data is erased and the bit line BL is at the “L” level, the level changes from the “H” level to the “L” level. Here, since the ground capacitance of the bit line BL is larger than the ground capacitance of the connection point SO, the potential of the connection point SO becomes the potential of the bit line BL when the transistor 41 is turned on.

Next, the control circuit 20 changes the control signal PBLCH to “H” level to turn on the transistor 34.
As a result, when the “0” data in the nonvolatile memory cell MC is erased and the potential of the connection point SO is at the “L” level, the connection point N1 of the latch LT remains at the “H” level. If the “0” data in the cell MC is not erased, the connection point N1 of the latch LT is at the “L” level when the potential at the connection point SO is at the “H” level.
That is, when the “0” data of the nonvolatile memory cell MC is erased, the connection point N2 of the latch LT remains at the “L” level, and the “0” data of the nonvolatile memory cell MC is erased. If not, the connection point N2 of the latch LT changes to the “H” level.

After the data of the non-volatile memory cells MC sharing the word line WL of the selected block BLCk is read out to all the latches LT, the control circuit 20 changes the control signal VERIFYB to “L” level to perform common verification. Determination signal line VERIFYPASS is precharged to “H” level.
Then, the control circuit 20 sets the control signal EVTR to the “H” level, and turns on the transistors 38 of all the page buffers PB of the page buffer group 13.
At this time, when the connection points N2 in all the page buffers PB of the page buffer group 13 are at the “L” level, all the transistors 37 are not turned on.
For this reason, when the transistors 37 of all the page buffers PB of the page buffer group 13 are in the OFF state, the common verify determination signal line VERIFYPASS remains at the “H” level, and the “H” level is output from the data terminal. It can be detected that “0” data in the nonvolatile memory cell MC of BLCk has been normally erased. The above-described operation is similarly performed in the other blocks BLCk.

On the other hand, when the connection point N2 in any page buffer PB of the page buffer group 13 is at “H” level, the transistor 37 in the page buffer PB at the connection point N2 at “H” level is turned on. .
For this reason, when the transistor 37 of any page buffer PB in the page buffer group 13 is in the ON state, the common verify determination signal line VERIFYPASS changes from “H” level to “L” level, and “L” from the data terminal. It can be detected that data is not erased from the non-volatile memory cell MC of the block BLCk having the level.
The above-described operation is similarly performed in the other blocks BLCk.

Next, FIG. 10 shows that in the above-described write verify process and erase verify process, the bit line BL shown in FIG. 8 is open or a short circuit with an adjacent bit line exists, so that the redundant column cell in the redundant bit line is replaced. It is a table which shows the influence in the verification of the column cell (defective column cell) in a replacement bit line.
In the configuration of this embodiment, the common verify determination signal line VERIFYPASS is connected in common to the drains of the transistors 35 and 37 of each page buffer PB in the page buffer group 13 (including the page buffer of the redundant column cell array), and the transistor 35 Alternatively, an OR circuit is constituted by 37.
For this reason, even after replacement as a defective column cell, the data at the connection point N1 or N2 in the latch LT affects the level determination process of the common verify determination signal line VERIFYPASS when determining at the time of verification.

At the time of the write verify process, as shown in FIG. 8 “(1) BL-BL SHORT”, when the bit line BL is short-circuited to other adjacent bit lines BL, both are also connected to any one of the bit lines BL. When “0” data is not written in the connected nonvolatile memory cell MC, the potential of the bit line BL becomes “L” level. Further, as shown in “(2) BL-SOURCE SHORT” of FIG. 8, when the bit line BL is short-circuited with the common source line SOURCE, the potential of the bit line BL becomes “L” level. At these times, the transistor 33 is in the OFF state, the data at the connection point N1 of the latch LT is held at the “H” level, and there is no problem because it is in the PASS state shown in FIG.
Further, during the write verify process, as shown in “(3) BL OPEN” in FIG. 8, when the bit line BL is open, the potential of the bit line BL is at the “H” level. Since the point N1 is at the “L” level, the common verify determination signal line VERIFYPASS is maintained at the “H” level and is in the PASS state shown in FIG.

On the other hand, in the erase verify process, as shown in FIG. 8 “(1) BL-BL SHORT”, when the bit line BL is short-circuited with other adjacent bit lines BL, Both nonvolatile memory cells MC connected to are erased to become “1” data, and the bit line BL becomes “L” level in erase verify. Further, as shown in “(2) BL-SOURCE SHORT” of FIG. 8, when the bit line BL is short-circuited with the common source line SOURCE, the potential of the bit line BL becomes “L” level. At these times, the transistor 33 is in the OFF state, the data at the connection point N1 of the latch LT is held at the “H” level, and there is no problem because it is in the PASS state shown in FIG.
However, during the erase verify process, as shown in “(3) BL OPEN” in FIG. 8, when the bit line BL is open, the potential of the bit line BL is at the “H” level. Since the point N2 becomes “H” level, the common verify determination signal line VERIFYPASS becomes “L” level. For this reason, in the nonvolatile memory cells selected by the word line WL, all the nonvolatile memory cells (including the redundant column cells) other than the replaced column cell determined to be defective and replaced with the redundant column cell are PASS. Since the read result of the nonvolatile memory cell MC of the column cell to be replaced is FAIL, the verification result is in the FAIL state shown in FIG.

As described above, it can be seen that the column cell to be replaced that is replaced as having a defect affects the determination result of the erase verify.
Therefore, in the present embodiment, in the above-described erase verify process, the surplus block 22 writes data determined as PASS to the latch LT of the page buffer PB corresponding to the column cell to be replaced as follows. This prevents the common verify determination signal line VERIFYPASS from being set to the “L” level due to the influence of the column cell to be replaced.

Here, as described above, the surplus block 22 is a block having the same configuration as the block BLCk in the present embodiment, but is erased by an erase operation, a write operation, and a read operation as test operation modes (that is, Data “1” is written in all the nonvolatile memory cells MC in the surplus block 22), and data “0” is written in any nonvolatile memory cell MC, and the nonvolatile memory cell MC at any address The data is read out.
That is, in the erase operation as the test operation mode, the data of all the nonvolatile memory cells MC in the surplus block 22 are erased as in the selected block BLCk. That is, the control circuit 20 outputs a control signal to the row decoder 14 when a command instructing erasure as the test operation mode is input from the outside.
The row decoder 14 outputs a block selection signal BLKSEL having the same voltage level as that supplied to the selected block in the erase verify operation shown in FIG. 5 to the transfer transistor group 21 provided in the surplus block 22. The row decoder 14 also supplies signals having the same voltage level as the internal selection gate signal iSSL, the internal selection gate signal iSGL, and the internal word signal PGi supplied to the selected block of the erase verify operation in FIG. The internal selection gate signal iESGL is output to the transfer transistor group 21 provided in the surplus block 22 as the internal selection gate signal and the internal word signal EPGi.
In each NAND cell string NA of the surplus block 22, a selection gate signal SSLk and a selection gate signal ESGL having the same voltage level as the selection gate signal SSLk and the selection gate signal SGLk input to the selection block BLCk of the erase verify operation in FIG. Entered. Further, the voltage level of the word lines EWL0 to EWLi of each NAND cell string NA of the surplus block 22 is 0 V, as is the case with the word lines WL0 to WLi in the selected block BLCk of the erase verify operation in FIG.
Thereafter, in the surplus block 22, the erase operation is executed similarly to the erase operation in the selected block BLCk, and “1” data is written in all the nonvolatile memory cells MC in the surplus block 22.
Also in the write operation and the read operation as other test operation modes, the control circuit 20 receives a command instructing writing as the test operation mode and a command instructing reading as the test operation mode from the outside. , A control signal corresponding to the command is output to the row decoder 14. The row decoder 14 supplies the surplus block 22 with the voltage level signal described for the selected block BLCk using FIG. 5 in the write operation and the read operation as the test operation mode. The page buffer group 13 performs the same operations as the above-described write operation and read operation in the write operation and the read operation as the test operation mode.

In the test operation mode described above, a nonvolatile semiconductor memory device having an accessible surplus block 22 is manufactured, and a process of replacing a bit line to be replaced (defective bit line) with a redundant bit line by the semiconductor test apparatus (tester) is performed. After that, further processing described below is performed by a tester.
Each control signal is supplied to the nonvolatile semiconductor memory device together with the erase command as the test operation mode, and the data of all the nonvolatile memory cells MC in the surplus block 22 is erased. Thereby, all the nonvolatile memory cells MC in the surplus block 22 store the data “1” (erased state).
Next, each control signal is supplied to the nonvolatile semiconductor memory device together with the write command as the test operation mode, and each NAND cell string NA connected to the bit line other than the bit line to be replaced (defective bit line) in the surplus block 22 Data “0” is written to all the nonvolatile memory cells MC in FIG. As a result, all the nonvolatile memory cells MC in the NAND cell string NA connected to the replacement bit line (defective bit line) maintain the storage of data “0”.

FIG. 11 is a diagram illustrating voltage levels of signals output from the row decoder 14 to the surplus block 22 in a normal operation mode (write, erase, write verify, read, erase verify).
When the row decoder 14 selects the block BLCk in the write operation, the row decoder 14 outputs a 0V block selection signal BLKSEL to the transfer transistor group 21 of the surplus block 22 (surplus block). Thereby, in the write operation, the voltage levels of all the word lines EWL0 to EWLi in the surplus block 22 become the floating voltage. Further, the selection gate signal ESSL becomes 0 V, and each NAND cell string NA in the surplus block 22 is not connected to the corresponding bit line BL. Therefore, data is not written to the nonvolatile memory cell MC in the surplus block 22. Further, the surplus block 22 does not affect the above-described data write operation in the selected block BLCk.

  Further, when the row decoder 14 selects the block BLCk in the write verify operation, the row decoder 14 outputs a block selection signal BLKSEL of 0 V to the transfer transistor group 21 of the surplus block 22 (surplus block). Thereby, in the write operation, the voltage levels of all the word lines EWL0 to EWLi in the surplus block 22 become the floating voltage. Further, the selection gate signal ESSL becomes 0 V, and each NAND cell string NA in the surplus block 22 is not connected to the corresponding bit line BL. Therefore, data is not written to the nonvolatile memory cell MC in the surplus block 22. Further, the surplus block 22 does not affect the write verify operation that is executed following the above-described data write in the selected block BLCk.

  Further, when the row decoder 14 selects the block BLCk in the erasing operation, the row decoder 14 outputs a 0V block selection signal BLKSEL to the transfer transistor group 21 of the surplus block 22 (surplus block). Thereby, in the erase operation, the voltage levels of all the word lines EWL0 to EWLi in the surplus block 22 become the floating voltage. In addition, the selection gate signal ESSL also becomes a floating voltage, and each NAND cell string NA in the surplus block 22 is not connected to the corresponding bit line BL. For this reason, in the nonvolatile memory cells MC in the surplus block 22, data written after product manufacture is not erased. Further, the surplus block 22 does not affect the above-described erase operation in the selected block BLCk.

When the row decoder 14 selects the block BLCk in the erase verify operation, a block having a voltage higher than the high voltage VH by the threshold voltage of the transfer transistor is applied to the transfer transistor group 21 of the surplus block 22 (surplus block) as in the selected block BLCk. The selection signal BLKSEL is output. Further, the row decoder 14 sets the voltage levels of the selection gate signal ESSL and the selection gate signal ESGL to the voltage level of the high voltage VH, and sets the voltage levels of all the word lines EWL0 to EWLi in the surplus block 22 to 0V.
As a result, among the NAND cell strings NA in the surplus block 22, the NAND cell strings NA connected to the replacement bit line (defective bit line) are all “1” data in the nonvolatile memory cells MC connected in series. As a result, a current path to ground is formed. Therefore, in the erase verify operation, the initial state (the state where the connection point N1 of the latch LT is at “H” level and the connection point N2 is at “L” level) is maintained in the latch LT of the page buffer PB corresponding to the bit line to be replaced. Is done.
On the other hand, among the NAND cell strings NA in the surplus block 22, NAND cell strings NA connected to bit lines other than the bit line to be replaced (defective bit line) are all “0” in the nonvolatile memory cells MC connected in series. Since it holds data, it does not form a current path to ground. Therefore, these NAND cell strings NA do not affect the erase verify operation executed subsequent to the above-described data erase in the selected block BLCk.

Next, FIG. 12 is a flowchart showing an operation example of the erase erase process in the nonvolatile semiconductor memory device according to the present embodiment.
FIG. 13 is a timing chart showing the operation of the page buffer PB in FIG. 7 in the processing from step S2 to step S3 in FIG.
Hereinafter, the operation of the erase verify process in the present embodiment will be described with reference to FIGS. 6, 7, 12, and 13. Command data for instructing to perform erase verify processing from the outside is written into the address register 19, and the control circuit 20 executes verify processing by this command. At this time, the control circuit 20 resets the register of the number of times of applying stress to the word line WL for internal erasure to 0.

Step S1:
The control circuit 20 applies an erasing voltage for erasing data in the nonvolatile memory cell MC to the block BLCk to be erased, and performs an erasing process for all the nonvolatile memory cells MC in the corresponding block BLCk. In the initial state, the control circuit 20 sets the control signals PDIS, BLSLT, PPGM, PBLCH, PVTR, and EVTR to the “L” level, and sets the control signals PLOAD, PBRST, VERIFYB, and BUSPC to the “H” level. Further, the row decoder 14 is controlled by the control circuit 20, and the selection gate signals SSLk and SGLk input to the selection block BLCk shown in FIG.

Step S2:
At time t1, the control circuit 20 changes the control signal PBRST to the “L” level to turn on the transistor 32.
As a result, the reset process of the page buffer PB is performed, and the connection point N1 of the latch LT becomes the “H” level, and the connection point N2 becomes the “L” level.
Then, at time t2, the control circuit 20 changes the control signal PBRST to the “H” level, turns off the transistor 32, and ends the reset operation.
At this time, the control circuit 20 changes the control signal PLOAD to the “L” level, changes the control signal BLSLT to the “H” level, and precharges the connection point SO and the bit line BL.

Next, at time t3, the control circuit 20 changes the control signal PLOAD to the “H” level and changes the control signal BLST to the “L” level.
Then, the row decoder 14 supplies the high voltage VH to the selection gate signals SSLk and SGLk by the control signal from the control circuit 20, and turns on the selection transistors SG1 and SG2. The row decoder 14 supplies 0 V to all the word lines WL.
When the selection transistors SG1 and SG2 are turned on, when the data of all the nonvolatile memory cells MC of the NAND cell string NA connected to each bit line BL is erased, the NAND cell string NA becomes conductive. When the data is not erased in any one of the nonvolatile memory cells MC in the NAND cell string NA, the NAND cell string NA becomes non-conductive.
Thereby, in the selected block BLCk, when all the nonvolatile memory cells MC of the NAND cell string NA connected to the bit line BL are in the ON state, the NAND cell string NA is in the conductive state, and the bit line BL is at the ground level. That is, it becomes “L” level (dotted line).
On the other hand, in the selected block BLCk, writing of “0” data is not erased in any one of the nonvolatile memory cells MC of the NAND cell string NA connected to the bit line BL (when there is an OFF state cell) ), The non-volatile memory cell MC is not turned on, the NAND cell string NA is non-conductive, and the bit line BL remains in the precharged state, that is, the “H” level (solid line).
Further, in the surplus block 22, since all the nonvolatile memory cells MC of the NAND cell string NA connected to the bit line BL (replaced bit line) are in the ON state, the NAND cell string NA is in the conductive state. The bit line BL is at the ground level, that is, the “L” level (dotted line).

Next, after a predetermined time has elapsed at time t4, the control circuit 20 changes the control signal BLSLT to “H” level to turn on the transistor 41.
As a result, the voltage at the connection point SO changes to the “L” level when the voltage of the bit line BL is “L” level (dotted line), and “H” when the voltage of the bit line BL is “H” level. It will be maintained at the level (solid line). Further, since the voltage of the bit line BL (replaced bit line) becomes “L” level, it changes to “L” level (dotted line).
Then, at time t5, the control circuit 20 changes the control signal PBLCH to “H” level in order to write data to the latch LT.
Thereby, the transistor 33 is turned on when the potential of the connection point SO is at the “H” level, and changes the connection point N1 of the latch LT from the “H” level to the “L” level.
On the other hand, when the potential at the connection point SO is at “L” level, the transistor 33 is turned off and maintains the connection point N1 of the latch LT at “H” level. In the latch LT corresponding to the bit line BL (replaced bit line), since the potential of the connection point SO is at the “L” level, the initial state (the connection point N1 of the latch LT is at the “H” level and the connection point N2 is at the connection point N2). "L" level state) is maintained. In this way, pseudo data (data determined to be PASS) is written in the page buffer corresponding to the bit line BL whose position is indicated by the column address of the column cell to be replaced in the erase verify operation. More precisely, data that becomes FAIL is not written in any of the erase verify operations executed a plurality of times.
Further, the control circuit 20 changes the control signals BLSLT and PBLCH and the control signals VSSL and VGSL in FIG. 2 to the “L” level before time t6.

Step S3: (Verify determination)
At time t6, the control circuit 20 sets the control signal PDIS to “H” level for a predetermined period, turns on the transistor 42, discharges the bit line BL, and sets the bit line BL to “L” level.
Then, the control circuit 20 sets the control signal VERIFYB to “L” level for a predetermined time, and precharges the common verify determination signal line VERIFYPASS to “H” level.
After a predetermined time has elapsed, the control circuit 20 sets the control signal VERIFYB to the “H” level, and then sets the control signal EVTR to the “H” level for a predetermined time. This predetermined time is a time measured in advance until the potential of the common verify determination signal line VERIFYPASS is stabilized.

At this time, data indicating that “0” data has been erased is written as pseudo data to the latch in the page buffer PB of the replaced column cell to be replaced.
For this reason, even when the defect of the replaced column cell to be replaced is the open of the bit line BL, the transistor 37 of the page buffer PB corresponding to the bit line BL is not turned on. The potential of the common verify determination signal line VERIFYPASS is not changed to the “L” level.

On the other hand, if any nonvolatile memory cell MC in the nonvolatile memory cell selected by the word line is not erased, the bit line BL to which the nonvolatile memory cell MC is connected remains at the “H” level. The connection point N2 of the latch LT becomes the “H” level. As a result, as indicated by the dotted line in FIG. 9, the common verify determination signal line VERIFYPASS is at the “L” level, indicating that the data cannot be erased.
As described above, the potential of the common verify determination signal line VERIFYPASS changes to the “L” level because the “0” data in any of the nonvolatile memory cells MC selected by the word line is not erased. Only in some cases, an accurate erase verify process can be performed.

When all the word lines WL are selected and the common verify determination signal line VERIFYPASS is at the “H” level in the “L” level state, the control circuit 20 performs the verify process using the nonvolatile semiconductor memory device as a pass. Then, a signal indicating the result of the pass is output from a preset output terminal (step S3-YES).
On the other hand, when all the word lines WL are selected and the common verify determination signal line VERIFYPASS is at the “L” level in the state of “L” level, the control circuit 20 advances the process to step S4 (step S3- NO).

Step S4: (Determination of the number of applied stresses)
Next, the control circuit 20 adds 1 to the number of applied stresses stored in the internal register, and writes it as the new number of applied times in the register.
After writing the number of times of application to the register, the control circuit 20 determines whether or not the number of times of application applied to the word line WL matches a preset number of times.
At this time, if the number of times the stress is applied matches the limit number, the control circuit 20 determines that the limit number of times cannot be erased, ends the erase verify process with the nonvolatile semiconductor memory device as a failure, and sets a preset output terminal. To output a result signal indicating failure (step S4-YES).
On the other hand, the control circuit 20 returns the process to step S1 when the number of times of stress application does not coincide with the limit number of times, that is, when the number of application times is equal to or less than the limit number (step S4-NO).

FIG. 14 is common to the change in potential for each number of times of stress application (Erase Cycle) from the connection point N1 (0) of the latch LT of the page buffer PB0 to the connection point N1 (32767) of the latch LT of the page buffer PB32767. This shows a change in the potential of the verify determination signal line VERIFYPASS.
As described above, the control circuit 20 applies an erasing stress, and from the connection point N1 (0) of the latch LT of the page buffer PB0 as shown in the table of FIG. 14A, the control circuit 20 sets the latch LT of the page buffer PB32767. When all of the nodes up to the connection point N1 (32767) are “H” and “0” data is deleted, it is determined as a pass.
FIG. 14A shows a change in potential at each stress application number (Erase Cycle) from the connection point N1 (0) of the latch LT of the page buffer PB0 to the connection point N1 (32767) of the latch LT of the page buffer PB32767. And a change in potential of the common verify determination signal line VERIFYPASS.

When pseudo data is not written to the connection point N1 of the latch LT in the page buffer PB corresponding to the column cell to be replaced in this embodiment, as shown in FIG. 14B, the connection in which the bit line is an open bit line Since the point N1 [3] changes to the “L” level, the potential of the common verify determination signal line VERIFYPASS becomes the “L” level even when n times is set as the preset limit number. For this reason, the redundant column cell at the replacement destination is a pass, and there is no problem in terms of product. However, since the column cell to be replaced has an influence on the determination of erase verification, even if it is a pass, it is determined as fail. .
On the other hand, as shown in FIG. 14A, when “0” data is erased except for the column cell to be replaced by writing pseudo data from the surplus block 22 to the connection point N1 [3], the page buffer PB [ All the connection points N1 [32767: 0] of the latch LT at 32767: 0] are at the “H” level, and are determined to be paths.

As described above, in the nonvolatile semiconductor memory device of this embodiment, in the erase verify process, the latch LT of the page buffer PB corresponding to the replaced column cell replaced in the block BLCk (first memory cell block). On the other hand, pseudo data (normal data) is written in which “0” data stored in the surplus block 22 (second memory cell block) is erased.
Therefore, according to the nonvolatile semiconductor memory device of the present embodiment, the common verify determination signal is used even when the defect is an open bit line BL in the determination of the erase verify batch determination circuit 25 formed in the OR configuration. The potential of the line VERIFYPASS is not changed to the “L” level, and the pass is not determined as fail.

The embodiment of the present invention has been described in detail with reference to the drawings. However, the specific configuration is not limited to this embodiment, and includes design and the like within a scope not departing from the gist of the present invention.
For example, in the description of the above embodiment, the number of word lines in the surplus block 22 has been described as being the same as the number of word lines in the block BLCk, but is not limited to this example. In the erase verify operation, if the NAND cell string corresponding to the bit line to be replaced forms a current path to the ground, the number of word lines need not be the same. However, when the number of word lines is the same, the block BLCk can be used as it is in the layout design of the surplus block 22, so that the number of layout design steps can be reduced.

  Further, although the redundant block 22 is arranged between the block BLCk and the page buffer group 13, it may be arranged between the blocks BLCk. This arrangement is determined depending on whether layout design is easy. However, in the erase verify operation, the reason why the surplus block 22 writes the pass data to each latch LT of the page buffer group 13 is due to the disconnection of the bit line. It is preferable to be arranged closest to the page buffer group 13 so that writing is possible.

Further, for example, the row decoder 14 or the control circuit 20 may include a storage unit that stores information indicating whether or not to perform the selection operation of the surplus block 22 (second memory cell block).
That is, when the storage unit indicates the selection of the surplus block 22, the selection operation of the surplus block 22 is performed, and when the storage unit does not indicate the selection of the surplus block 22, the selection operation of the surplus block 22 is performed. Good. For example, when the nonvolatile semiconductor memory device of the present invention is a perfect non-defective product that does not have a defective bit line after product manufacture, there is no bit line to be replaced in the surplus block 22. Therefore, it is not necessary to perform the data erasing operation of the nonvolatile memory cell MC in the surplus block 22. Therefore, with the configuration including the storage unit, in the case of a perfect product, information that does not indicate selection of the surplus block 22 is written in the storage unit, and the row decoder 14 or the control circuit 20 does not select the surplus block 22. Make the configuration. As a result, it is not necessary to write data to the surplus block 22 after product manufacture, and the number of inspection steps for inspecting whether or not desired data has been written can be reduced. In addition, in the normal operation mode, an operation for selecting or deselecting the surplus block 22 is not necessary, and power associated with the selection or nonselection operation in the verify process can be reduced.

Further, in the description of the above embodiment, the redundant block 22 has a plurality of word lines, all the nonvolatile memory cells MC in the NAND cell string corresponding to the replacement bit line hold “1” data, and the replacement bit line All the nonvolatile memory cells MC in the NAND cell string corresponding to the other bit lines are configured to hold “0” data. Here, the plurality of word lines are divided into two sets, for example, a first set and a second set. Among these, the word lines connected to one or more nonvolatile memory cells MC in the NAND cell string corresponding to the bit line to be replaced are defined as a first set. Further, the word lines connected to the remaining nonvolatile memory cells MC in the NAND cell string corresponding to the bit line to be replaced are set as the second set. Then, in the NAND cell string corresponding to the bit line to be replaced, “1” data is stored in the nonvolatile memory cells MC connected to the first set of word lines among the nonvolatile memory cells MC (set as on cells). Further, in the NAND cell string corresponding to the bit line other than the bit line to be replaced, “0” data is stored in the nonvolatile memory cell MC connected to the first set of word lines among the nonvolatile memory cells MC (off cell). And). The nonvolatile memory cells MC connected to the second set store arbitrary “0” or “1” data regardless of whether they are in the NAND cell string corresponding to the bit line to be replaced.
Such data is written in advance in the write operation as the test operation mode. Further, for example, the row decoder 14 supplies 0V to the first set of word lines in the erase verify operation as the normal operation mode, and the second set. The pass voltage Vpass is supplied to the word line. Even in such a configuration, the NAND cell string corresponding to the bit line to be replaced forms a current path to the ground, and the NAND corresponding to bit lines other than the bit line to be replaced, as in the erase verify operation in the above embodiment. The cell string does not form a current path to ground. Therefore, as in the erase verify operation in the above embodiment, even if the bit line to be replaced is an open bit line, the potential of the common verify determination signal line VERIFYPASS is not changed to the “L” level, and the pass is determined as fail. Never do.

  DESCRIPTION OF SYMBOLS 11 ... Memory cell array, 12 ... Redundant column cell array, 13 ... Page buffer group, 14 ... Row decoder, 14a ... Block decoder, 14b ... Page decoder, 15 ... Column decoder, 16 ... Voltage generation circuit, 17 ... Input / output circuit, 18 ... Command register, 19 ... Address register, 20 ... Control circuit, 21 ... Transfer transistor group, 22 ... Excess block, 25 ... Batch determination circuit, 26 ... Charge circuit, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 51, 52, 53, 54, MTS, MTG, MTi, MTN, MT0 ... transistor, 50 ... AND circuit, BL, BL0, BL1, BL7, BLn, BLR0 , BLRx ... bit line, BLCk ... block, SOURCE ... common source line, DINBUS ... Data write line, DOUTBUS, DOUTBUS0 ... data read line, IV1, IV2 ... inverter, LT ... latch, MC, MC0, MCi ... nonvolatile memory cell, N1, N2, SO ... connection point, NA ... NAND cell string, PB, PB0, PB1, PB7, PBx8, PB32767 ... page buffer, PBT, PBT0, PBT1, PBT2, PBT63 ... transfer circuit, SUNIT, SUNIT0, SUNIT1, SUNIT2, SUNIT63 ... subunit, CUNIT ... column units, SG1, SG2 ... Selection transistor, WL, WL0, WLi, Word, EWL0... Word line, VERIFYPASS ... common verify determination signal line, SSLk, SGLk, ESSL, ESGL ... selection gate signal, iSSL, iSGL, iESSL IESGL ... internal selection gate signal, PGi, EPGi, EPG0 ... internal word signal, BLKSEL, BLKSELk ... block selection signal, Vpgm ... program voltage, Vpass ... pass voltage, VH ... high voltage, VL ... low-voltage, VCC ... supply voltage

Claims (8)

A first memory cell block in which each of a plurality of bit lines and a plurality of word lines intersects, and a non-volatile memory cell is disposed at the intersecting portion;
A defective replacement circuit comprising a redundant bit line replacing a defective bit line in the first memory cell block;
A page buffer including a latch that is provided for each bit line and stores data to be written to or read from the memory cell selected by the word line;
In a verify process, a batch determination circuit that collectively reads data read from the bit line and written to the latch of the page buffer in units of a plurality of bit lines;
A memory cell block in which each of the plurality of bit lines and at least one word line intersect each other, and a nonvolatile memory cell is disposed at the intersecting portion, and the defect is replaced with the redundant bit line A second memory cell block different from the first memory cell block for storing pseudo data written in the verify process in the latch in the page buffer corresponding to the bit line;
A non-volatile semiconductor memory device comprising:   2. The nonvolatile semiconductor memory device according to claim 1, wherein the verify process is an erase verify process.   3. The nonvolatile semiconductor according to claim 1, wherein the second memory cell block is disposed between the first memory cell block and the page buffer. 4. Storage device.   4. The nonvolatile memory according to claim 1, wherein the number of word lines in the second memory cell block is the same as the number of word lines in the first memory cell block. 5. Semiconductor memory device. In the verify verification, the latch of the page buffer includes pass data indicating successful verification of the memory cell in the first memory cell block and pass data by the defective bit line in the first memory cell block. A circuit for latching complementary fail data,
In the second memory cell block, as the pseudo data,
A memory cell corresponding to the defective bit line stores the pass data;
5. The nonvolatile semiconductor memory device according to claim 1, wherein a memory cell corresponding to a bit line other than the defective bit line stores the fail data. 6. A row decoder for selecting a first memory cell block and selecting any of the plurality of word lines;
The row decoder, when the verify process is an erase verify process,
A second memory cell block is selected, the at least one word line is activated, a memory cell corresponding to the defective bit line in the second memory cell block is turned on, and a bit other than the defective bit line 6. The nonvolatile semiconductor memory device according to claim 1, wherein the memory cell corresponding to the line is an off cell. The at least one or more word lines are two or more word lines composed of a first set and a second set,
In the second memory cell block, as the pseudo data,
In the memory cell corresponding to the defective bit line,
Memory cells connected to the first set of word lines store the pass data;
Memory cells connected to the second set of word lines store the pass data or the fail data,
In a memory cell corresponding to a bit line other than the defective bit line,
Memory cells connected to the first set of word lines store the fail data;
Memory cells connected to the second set of word lines store the pass data or the fail data,
The row decoder, when the verify process is an erase verify process,
Select a second memory cell block;
Of the memory cells connected to the word line belonging to the first set, memory cells corresponding to bit lines other than the defective bit line are turned off cells, and memory cells corresponding to the defective bit lines are turned on cells. Supply a voltage that
7. The nonvolatile semiconductor memory device according to claim 6, wherein a voltage at which a memory cell connected to the word line is turned on is supplied to the word line belonging to the second set.   The row decoder includes a storage unit that indicates whether or not to select the second memory cell block, and the row decoder causes the storage unit to select the second memory cell block. 8. The nonvolatile semiconductor memory device according to claim 6, wherein the second memory cell block is selected when shown.

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