JP2012114412A - Storage device and method of manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a highly reliable storage device and a method of manufacturing the same.SOLUTION: A storage device 1 comprises a nanomaterial aggregate layer 23 where multiple micro-conductors are aggregated via gaps 32, and insulation materials 25 arranged in the gaps 32. The micro-conductors are carbon nano-tubes 31, and the extending direction of carbon nano-tubes 31 is closer to a direction parallel with the lower surface of the nanomaterial aggregate layer 23 than a direction perpendicular thereto. Furthermore, a lower electrode layer 22 in contact with the lower surface of the nanomaterial aggregate layer 23, and an upper electrode layer 24 in contact with the upper surface of the nanomaterial aggregate layer 23 are provided. There is no micro-conductor in contact with both the lower electrode layer 22 and the upper electrode layer 24.

Description

  Embodiments described herein relate generally to a storage device and a method for manufacturing the same.

  In recent years, when a voltage is applied to a specific metal oxide material, a phenomenon has been discovered in which the material has two states, a low resistance state and a high resistance state, depending on the resistivity before the voltage is applied and the magnitude of the applied voltage. Therefore, a new nonvolatile memory device using the phenomenon has attracted attention. This nonvolatile storage device is referred to as ReRAM (resistance random access memory). Regarding the real device structure of ReRAM, a three-dimensional cross-point structure in which memory cells are arranged at the intersections of WL (word lines) and BL (bit lines) has been proposed from the viewpoint of high integration. In addition, when commercializing ReRAM, improvement in reliability is required.

JP 2008-41954 A

  An object of an embodiment of the present invention is to provide a storage device with high reliability and a manufacturing method thereof.

  The storage device according to the embodiment includes a nanomaterial assembly layer in which a plurality of minute conductors are assembled via a gap, and an insulating material disposed in the gap.

1 is a perspective view illustrating a storage device according to a first embodiment. 1 is a schematic cross-sectional view illustrating a pillar of a storage device according to a first embodiment. It is a flowchart figure which illustrates the formation method of the pillar in 1st Embodiment. FIGS. 7A and 7B are process cross-sectional views illustrating the method for manufacturing the memory device according to the first embodiment. FIGS. FIGS. 7A and 7B are process cross-sectional views illustrating the method for manufacturing the memory device according to the first embodiment. FIGS. It is typical sectional drawing which illustrates the pillar of the memory | storage device which concerns on a comparative example. It is a graph which illustrates the switching characteristic of the memory | storage device based on an Example, taking the number of pulses applied to a pillar on a horizontal axis, and taking the electric current amount which flows into a pillar on a vertical axis | shaft. It is a graph which illustrates the influence which an insulating material exerts on the adhesion strength of a nanomaterial assembly layer by taking the presence or absence of an insulating material on the horizontal axis and taking the adhesion strength on the vertical axis. It is a flowchart figure which illustrates the formation method of the pillar in 2nd Embodiment. It is a flowchart figure which illustrates the formation method of the pillar in 3rd Embodiment. It is a flowchart figure which illustrates the formation method of the pillar in 4th Embodiment. FIG. 9 is a schematic cross-sectional view illustrating a pillar of a storage device according to a fourth embodiment. It is a flowchart figure which illustrates the formation method of the pillar in 5th Embodiment. FIG. 11 is a process cross-sectional view illustrating a method for manufacturing a memory device according to a sixth embodiment. FIG. 11 is a process cross-sectional view illustrating a method for manufacturing a memory device according to a sixth embodiment. FIG. 10 is a process diagram illustrating a method for manufacturing a memory device according to a sixth embodiment, where (a) is a top process diagram and (b) is a sectional process diagram. 6 is a cross-sectional process diagram illustrating a method for manufacturing a storage device according to a comparative example; FIG. FIG. 11 is a cross-sectional process diagram illustrating a method for manufacturing a memory device according to a sixth embodiment. It is a top surface schematic diagram which illustrates the modification of the memory | storage device which concerns on 6th Embodiment. It is a flowchart figure which illustrates the formation method of the pillar in 7th Embodiment. FIG. 10 is a schematic cross-sectional view illustrating a pillar of a storage device according to a seventh embodiment.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
First, the first embodiment will be described.
FIG. 1 is a perspective view illustrating a storage device according to this embodiment.
FIG. 2 is a schematic cross-sectional view illustrating a pillar of the storage device according to this embodiment.
The storage device according to the present embodiment is a non-volatile storage device, and more specifically, a ReRAM using a minute conductor.

  As shown in FIG. 1, in the storage device 1 according to the present embodiment, a silicon substrate 11 is provided, and a drive circuit (not shown) of the storage device 1 is provided on the upper layer portion and the upper surface of the silicon substrate 11. Is formed. An interlayer insulating film 12 made of, for example, silicon oxide is provided on the silicon substrate 11 so as to embed a drive circuit, and a memory cell portion 13 is provided on the interlayer insulating film 12.

  In the memory cell portion 13, a word line wiring layer 14 including a plurality of word lines WL extending in one direction (hereinafter referred to as “word line direction”) parallel to the upper surface of the silicon substrate 11, and an upper surface of the silicon substrate 11. A bit line wiring layer 15 including a plurality of bit lines BL extending in a parallel direction and intersecting the word line direction, for example, a direction orthogonal to the word line direction (hereinafter referred to as “bit line direction”). Are alternately stacked. The word lines WL, the bit lines BL, and the word line WL and the bit line BL are not in contact with each other.

  A pillar 16 extending in a direction perpendicular to the upper surface of the silicon substrate 11 (hereinafter referred to as “vertical direction”) is provided at the closest point between each word line WL and each bit line BL. The pillar 16 is formed between the word line WL and the bit line BL. One pillar 16 forms one memory cell. That is, the nonvolatile memory device 1 is a cross-point type device in which a memory cell is arranged at each closest point between the word line WL and the bit line BL. The word lines WL, the bit lines BL, and the pillars 16 are filled with an interlayer insulating film (not shown).

Hereinafter, the configuration of the pillar 16 will be described with reference to FIG.
As shown in FIG. 2, in each pillar 16, a silicon diode layer 21, a lower electrode layer 22, a nanomaterial assembly layer 23, and an upper electrode layer 24 are stacked in this order from the bottom to the top. Further, as will be described later, an insulating material 25 is embedded in the nanomaterial assembly layer 23. The silicon diode layer 21 is in contact with, for example, the word line WL (see FIG. 1), and the upper electrode layer 24 is in contact with, for example, the bit line BL (see FIG. 1). The lower electrode layer 22 is in contact with the lower surface of the nanomaterial assembly layer 23, and the upper electrode layer 24 is in contact with the upper surface of the nanomaterial assembly layer 23. A barrier metal layer may be formed between the word line WL and the silicon diode layer 21 for the purpose of preventing diffusion and improving adhesion. Further, a side wall (not shown) made of, for example, silicon nitride is provided on the side surface of the pillar 16.

The silicon diode layer 21 is made of, for example, polysilicon, and in order from the word line WL side, an n type layer having a conductivity type of n ⁺ , an i type layer made of an intrinsic semiconductor, and a p type layer having a conductivity type of p ^{+ type} are stacked. Has been. Accordingly, the silicon diode layer 21 functions as a selection element layer that allows current to flow only when a potential higher than that of the word line WL is supplied to the bit line BL and does not flow current in the reverse direction.

  The lower electrode layer 22 is formed of a conductive material such as tungsten (W), titanium nitride (TiN), tungsten nitride (WN), tantalum nitride (TaN), or titanium silicide (TiSi).

  The nanomaterial assembly layer 23 is a layer in which carbon nanotubes (CNT) 31 as minute conductors are loosely assembled through a gap 32. Each CNT 31 has a cylindrical shape, and its length is, for example, about 500 nm. The direction in which most CNTs 31 extend is closer to the direction parallel to the lower surface than the direction (vertical direction) perpendicular to the lower surface of the nanomaterial assembly layer 23. Further, there is no CNT 31 in contact with both the lower electrode layer 22 and the upper electrode layer 24. The aspect ratio of the nanomaterial assembly layer 23 is 1 or less. That is, the thickness of the nanomaterial assembly layer 23 is less than the width.

  An insulating material 25 is disposed in the gap 32. The insulating material 25 is preferably a material that has a relatively small molecular weight, is hydrophobic, is resistant to ammonia, can ensure adhesion by a condensation reaction, and the like, and does not damage the CNTs during filling, for example, SOD (spin on dielectric) including silicon (Si), oxygen (O), carbon (C) and hydrogen (H), for example, MSQ (methylsilsesquioxane) It can be. The gap 32 is filled with such an insulating material 25 substantially without a gap.

  The upper electrode layer 24 is formed of the same conductive material as that of the lower electrode layer 22. A part of the CNT 31 constituting the nanomaterial assembly layer 23 is embedded under the upper electrode layer 24. The lower surface of the upper electrode layer 24 is in contact with the insulating material 25.

  In each pillar 16, the silicon diode layer 21 functions as a selection element layer that switches whether a current is passed through the pillar 16. In addition, the nanomaterial assembly layer 23 switches between a “low resistance state” and a “high resistance state” depending on an applied voltage or current, thereby functioning as a storage layer that stores binary data. By providing the selection element layer and the storage layer, each pillar 16 functions as a memory cell. In the nanomaterial assembly layer 23, it is preferable that the CNT 31 in contact with both the lower electrode layer 22 and the upper electrode layer 24 does not exist. Thereby, the resistance value of the nanomaterial assembly layer 23 in the “high resistance state” is increased, and a sufficient operation margin of the memory cell can be ensured.

Next, a method for manufacturing the nonvolatile memory device according to this embodiment will be described.
FIG. 3 is a flowchart illustrating an example of a pillar forming method in the method for manufacturing a storage device according to this embodiment.
4A and 4B and FIGS. 5A and 5B are process cross-sectional views illustrating the method for manufacturing the memory device according to this embodiment.

  First, as shown in FIG. 1, a drive circuit for driving the memory cell unit 13 is formed on the upper surface of the silicon substrate 11. Next, an interlayer insulating film 12 is formed on the silicon substrate 11. Next, a contact (not shown) reaching the drive circuit is formed in the interlayer insulating film 12. Next, tungsten is buried in the upper layer portion of the interlayer insulating film 12 by, for example, a damascene method, and a plurality of word lines WL are formed in parallel to each other so as to extend in the word line direction. A word line wiring layer 14 is formed by these word lines WL.

Hereinafter, a method for forming the pillar 16 will be described with reference to FIGS.
First, as shown in step S1 of FIGS. 2 and 3, amorphous silicon is deposited on the word line wiring layer 14 by, eg, CVD (chemical vapor deposition) to form a silicon diode layer 21. To do. At this time, each impurity is introduced while depositing amorphous silicon to continuously form an n-type layer, an i-type layer, and a p-type layer. If necessary, a barrier metal layer (not shown) made of, for example, titanium nitride (TiN) may be formed between the word line wiring layer 14 and the silicon diode layer 21.

  Next, as shown in step S2 of FIGS. 2 and 3, a conductive material such as tungsten or titanium nitride is deposited on the silicon diode layer 21 by, for example, PVD (physical vapor deposition). Then, the lower electrode layer 22 is formed.

  Next, a structure (hereinafter simply referred to as “substrate”) in which the above-described layers are formed on the silicon substrate 11 is loaded into a coating apparatus (not shown). Then, as shown in step S3 of FIG. 3, pre-baking (pre-application heat treatment) is performed using a hot plate. At this time, for example, the atmosphere is a nitrogen atmosphere, the heating temperature is 200 to 300 ° C., and the heating time is 5 minutes. Thereafter, the substrate temperature is lowered to room temperature.

Next, as shown in step S4 of FIG. 3 and FIG. 4A, a dispersion liquid in which CNTs 31 are dispersed is applied onto the substrate by a spin coating method. That is, for example, about 1 cm ³ of a dispersion liquid is dropped on the substrate and spread while the substrate is rotated at a rotational speed of about 1000 to 2000 revolutions per minute. Thereafter, the dispersion is dried. This application and drying are repeated as many times as necessary. Thereby, the nanomaterial assembly layer 23 is formed. In the nanomaterial assembly layer 23, a plurality of CNTs 31 are aggregated, and a gap 32 is formed between the CNTs 31. In the process of drying the dispersion and reducing the thickness, the direction in which the CNT 31 extends approaches the horizontal direction, that is, the direction parallel to the plane formed by the word line direction and the bit line direction. Moreover, since the application and drying of the dispersion are repeated a plurality of times, there is no CNT 31 penetrating the entire nanomaterial assembly layer 23 in the thickness direction.

  Next, as shown in step S5 of FIG. 3, post-baking (post-application heat treatment) is performed by a hot plate of a coating apparatus. At this time, for example, the atmosphere is a nitrogen atmosphere, the heating temperature is 200 to 300 ° C., and the heating time is 5 minutes. Thereafter, the substrate temperature is lowered to room temperature.

Next, as shown in step S6 of FIG. 3 and FIG. 4B, a solution containing the insulating material 25 as a solute, for example, an MSQ solution, is applied onto the substrate by spin coating. The molecular weight of MSQ contained in this MSQ solution is about 2000. Specifically, for example, an insulating material solution of about 1 cm ³ is dropped on the substrate and spread while the substrate is rotated at a rotational speed of about 1000 to 2000 revolutions per minute. The solution is then dried. As a result, the insulating material 25 is deposited in layers and a deposited layer is formed. At this time, the thickness of the deposited layer of the insulating material 25 after drying does not exceed the thickness of the nanomaterial assembly layer 23. That is, the insulating material 25 is filled in the gap 32 only at the lower part of the nanomaterial assembly layer 23. On the other hand, in the upper part of the nanomaterial assembly layer 23, the CNTs 31 are exposed such that the insulating material 25 is not embedded in the gaps 32. As a result, a part of the CNT 31 protrudes from the upper surface of the deposited layer made of the insulating material 25.

  Next, as shown in step S7 of FIG. 3, post baking (post-application heat treatment) is performed using a hot plate of a coating apparatus. At this time, for example, the atmosphere is an air atmosphere, and the heating temperature is 100 to 200 ° C. Thereafter, the substrate temperature is lowered to room temperature, and the substrate is taken out from the coating apparatus.

  Next, as shown in step S8 of FIG. 3, the substrate is placed in a vertical furnace and annealed (heat treatment). This annealing process is a heat treatment at a higher temperature for a longer time than the post-bake process shown in steps S5 and S7 of FIG. For example, in the annealing process shown in step S8, the atmosphere is a nitrogen atmosphere, the heating temperature is 500 to 600 ° C., and the heating time is 1 hour. Thereby, a cross-linking reaction occurs between the CNTs 31, and the CNTs 31 are loosely bonded. Further, in the insulating material 25, an OH group dehydration condensation reaction occurs between MSQ molecules, and a crosslinking reaction occurs. Thereafter, the substrate is cooled to room temperature and removed from the vertical furnace.

  Next, as shown in step S9 of FIG. 3 and FIG. 5 (a), the substrate is inserted into, for example, a PVD apparatus, and a conductive material such as tungsten or the like is formed from above the nanomaterial assembly layer 23 by the PVD method. Titanium nitride is deposited. At this time, the conductive material enters the gap 32 and is deposited on the deposition layer made of the insulating material 25 to cover the exposed portion of the CNT 31. Thereby, the upper electrode layer 24 is formed, and the CNT 31 is embedded in the lower part thereof. In this manner, the portion of the CNT 31 embedded with the insulating material 25 constitutes the nanomaterial assembly layer 23, and the portion embedded with the conductive material becomes a part of the upper electrode layer 24.

  Next, as shown in step S <b> 10 of FIG. 3, a hard mask (not shown) made of, for example, silicon oxide is formed on the upper electrode layer 24. Next, a resist film (not shown) is formed on the hard mask, and is patterned by a lithography method to remain in a region where the pillar 16 is to be formed. Next, anisotropic etching such as RIE (reactive ion etching) is performed using the patterned resist film as a mask to pattern the hard mask.

  Next, as shown in step S11 of FIG. 3 and FIG. 5B, anisotropic etching such as RIE is performed using the patterned hard mask as a mask. Thereby, the upper electrode layer 24, the nanomaterial assembly layer 23, the lower electrode layer 22, and the silicon diode layer 21 are selectively removed, and the pillar 16 is formed.

  Next, as shown in step S12 of FIG. 3, wet cleaning is performed using, for example, a hydrofluoric acid chemical solution, for example, DHF (diluted hydrofluoric acid) or BHF (buffered hydrofluoric acid). The by-product (not shown) attached on the side surface of the pillar 16 is removed.

Next, as shown in step S <b> 13 of FIG. 3, for example, silicon nitride is deposited by CVD using ammonia gas (NH ₃ ) as a source gas, and sidewalls (not shown) are formed on the side surfaces of the pillars 16. ). Next, an insulating material such as silicon oxide is deposited to fill the spaces between the pillars 16 and form an interlayer insulating film (not shown). Next, CMP (chemical mechanical polishing) is performed using the upper electrode layer 24 as a stopper to flatten the upper surface of the interlayer insulating film.

  Next, as shown in FIG. 1, a plurality of bit lines BL are formed above the pillars 16 and the interlayer insulating film. Thereby, the bit line wiring layer 15 is formed. Next, by the same method as described above, the silicon diode layer 21, the lower electrode layer 22, the nanomaterial assembly layer 23, and the upper electrode layer 24 are stacked in this order, and patterned to form the pillar 16, washed, and sidewalls Formed and embedded with an interlayer insulating film. In this way, the pillar 16 is formed on the bit line BL. When the pillar 16 is formed, the stacking order of the n-type layer, the i-type layer, and the p-type layer in the silicon diode layer 21 is reversed with respect to the pillar 16 formed on the word line WL. Thereafter, the word line wiring layer 14, the plurality of pillars 16, the bit line wiring layer 15, and the plurality of pillars 16 are repeatedly formed by the same method. Thereby, the storage device 1 according to the present embodiment is manufactured.

Next, the effect of this embodiment will be described.
According to the present embodiment, the insulating material 25 is disposed in the gap 32 of the nanomaterial assembly layer 23. Thereby, the mechanical strength of the nanomaterial assembly layer 23 is improved. As a result, it is possible to prevent the pillar 16 from collapsing at the portion of the nanomaterial assembly layer 23 or breaking the nanomaterial assembly layer 23 as a fracture surface. As a result, the reliability of the storage device 1 can be improved.

  Moreover, in this embodiment, in the process shown in step S6 of FIG. 3 and FIG. 4B, the insulating material 25 is filled in the gap 32 formed in the lower part of the nanomaterial assembly layer 23, and the insulating material 25 is used. A deposited layer is formed. Thereby, in the process shown in step S9 of FIG. 3 and FIG. 5A, when the conductive material is deposited to form the upper electrode layer 24, the conductive material enters the lower part of the nanomaterial assembly layer 23. Can be regulated. As a result, since the lower surface of the upper electrode layer 24 is defined by the upper surface of the deposited layer of the insulating material 25, the lower surface of the upper electrode layer 24 becomes flat. Thereby, the thickness of the nanomaterial assembly layer 23 becomes uniform, and the characteristics as the memory layer become uniform. As a result, the reliability of the storage device 1 is improved.

  Further, since the mechanical strength of the nanomaterial assembly layer 23 is improved due to the presence of the insulating material 25, in the process shown in step S11 of FIG. 3 and FIG. 5B, when the pillar 16 is formed by performing RIE, The collapse of the pillar 16 can be prevented. Furthermore, since the insulating material 25 is embedded, the upper surface of the lower electrode layer 22 is not etched through the gap 32 when performing RIE. For this reason, the shape stability of the lower electrode layer 22 is improved. Furthermore, the presence of the insulating material 25 can prevent the material of the side wall from entering the inside from the side surface of the nanomaterial assembly layer 23 when forming the side wall in the process shown in Step S <b> 13 of FIG. 3. For the above reasons, the reliability of the storage device 1 can be improved.

  Furthermore, in this embodiment, the insulating material 25 is deposited by a coating method. Thereby, the embedding property of the insulating material 25 is improved, and it is possible to reliably reach the lower part of the nanomaterial assembly layer 23. In addition, since the coating method has high controllability of the film thickness, the insulating material 25 can be embedded only under the nanomaterial assembly layer 23. Furthermore, according to the coating method, the CNT 31 is not damaged.

  On the other hand, if the insulating material 25 is deposited by the PVD method, the PVD method has a low embedding property, so that it is difficult to reliably reach the insulating material 25 to the lower part of the nanomaterial assembly layer 23. Also, it is difficult to control the thickness of the insulating material 25 deposited. Also, if the insulating material 25 is deposited by the CVD (chemical vapor deposition) method, the embedding property is good, but the insulating material 25 adheres uniformly to the surface of the CNT 31 and the nanomaterial. It becomes difficult to deposit only in the lower part of the aggregate layer 23. Further, the CNT 31 is oxidized, nitrided, or damaged by plasma depending on the atmosphere during the CVD film formation.

  Furthermore, in the present embodiment, by making the insulating material 25 a material having a relatively small molecular weight, high embedding can be realized, and the insulating material 25 can reliably reach the lower part of the nanomaterial assembly layer 23. be able to. Moreover, the adhesiveness between the insulating material 25 and the CNT 31 can be ensured by using the insulating material 25 as a material that causes a crosslinking reaction by a condensation reaction or the like. Furthermore, the insulating material 25 is made of a material that undergoes a crosslinking reaction by heat treatment in an inert atmosphere, so that the CNT is not damaged with the heat treatment. Furthermore, when the insulating material 25 is made of a hydrophobic material, it is possible to prevent the insulating material 25 from being discharged by the cleaning liquid when the pillar 16 is wet cleaned in the process shown in Step S12 of FIG. Furthermore, when the insulating material 25 is made of a material resistant to ammonia, the insulating material 25 is damaged when CVD is performed using ammonia gas as a source gas in the side wall forming process shown in step S13 of FIG. You can prevent it. Examples of the insulating material that satisfies the above conditions include an insulating material (SiOCH) containing silicon (Si), oxygen (O), carbon (C), and hydrogen (H), for example, MSQ.

  Furthermore, in this embodiment, the CNT dispersion liquid is applied and dried in the process shown in step S4 of FIG. 3, and the insulating material solution is applied and dried in the process shown in step S6, and then annealed as shown in step S8. Processing is performed to simultaneously perform crosslinking between the CNTs 31 and crosslinking between the molecules of the insulating material 25. Thereby, the frequency | count of a heating process can be reduced and the manufacturing cost of the memory | storage device 1 can be reduced.

Next, a comparative example of this embodiment will be described.
FIG. 6 is a schematic cross-sectional view illustrating a pillar of the storage device according to this comparative example.
As shown in FIG. 6, in the memory device according to this comparative example, the insulating material 25 (see FIG. 2) is not embedded in the nanomaterial assembly layer 23. Such a storage device can be manufactured by omitting the steps shown in steps S6 and S7 of FIG. 3 in the manufacturing method described in the first embodiment.

  In this comparative example, since the insulating material 25 (see FIG. 2) is not disposed in the gap 32 of the nanomaterial assembly layer 23, the mechanical strength of the nanomaterial assembly layer 23 is low. Further, when the upper electrode layer 24 is formed, since the conductive material enters deeply into the gap 32 of the nanomaterial assembly layer 23, the flatness of the lower surface of the upper electrode layer 24 is lowered. Accordingly, the flatness of the upper surface of the upper electrode layer 24 is also lowered. This makes the memory cell characteristics non-uniform. Further, when the conductive material passes through the gap 32 and reaches the lower electrode layer 22, the nanomaterial assembly layer 23 may be short-circuited.

  Furthermore, in this comparative example, since the insulating material 25 is not embedded in the gap 32, ions for etching pass through the gap 32 of the nanomaterial assembly layer 23 in the RIE process for forming the pillar 16. Passing through and reaching the lower electrode layer 22, the lower electrode layer 22 is etched unevenly. As a result, the shape stability of the lower electrode layer 22 decreases. Furthermore, when the pillar 16 is wet-cleaned, the pillar 16 breaks at the nanomaterial assembly layer 23 portion and is easily collapsed. Furthermore, when the side wall is formed, the material of the side wall enters the nanomaterial assembly layer 23. For these reasons, the storage device according to this comparative example has low reliability.

Next, a test example of this embodiment will be described.
FIG. 7 is a graph illustrating the switching characteristics of the memory device according to the embodiment, where the horizontal axis represents the number of pulses applied to the pillar and the vertical axis represents the amount of current flowing through the pillar.
FIG. 8 is a graph illustrating the influence of the insulating material on the adhesion strength of the nanomaterial assembly layer, where the horizontal axis represents the presence or absence of an insulating material and the vertical axis represents the adhesion strength.

  In this test example, the storage device according to the example was manufactured by the method described in the first embodiment. Further, the storage device according to the comparative example was manufactured by the method described in the comparative example. As described above, the insulating material 25 (see FIG. 2) is provided in the memory device according to the example, and the insulating material 25 is not provided in the memory device according to the comparative example.

  In the memory device according to the example, a pulse voltage was applied to the pillar. Thereby, as shown in FIG. 7, the set operation and the reset operation were repeatedly executed in the nanomaterial assembly layer 23, and the “high resistance state” and the “low resistance state” could be repeatedly expressed. As described above, in the memory device according to this example, it was confirmed that the pillar 16 functions as a memory cell.

  Moreover, the adhesion strength of the nanomaterial assembly layer 23 was measured for the storage devices according to the examples and the comparative examples. Specifically, a scratch test was performed on the nanomaterial assembly layer 23. As a result, as shown in FIG. 8, the adhesion strength of the nanomaterial assembly layer 23 in the storage device according to the example was 1.5 times the adhesion strength of the nanomaterial assembly layer 23 in the storage device according to the comparative example. . Thereby, the effect of the insulating material 25 was confirmed.

Next, a second embodiment will be described.
FIG. 9 is a flowchart illustrating the pillar forming method in the method for manufacturing the memory device according to this embodiment.
As shown in FIG. 9, the manufacturing method of the memory device according to this embodiment is a nanomaterial assembly shown in step S5 as compared to the manufacturing method of the memory device according to the first embodiment (see FIG. 3). The difference is that an annealing step shown in step S21 is provided between the layer post-baking step and the insulating material application / drying step shown in step S6.

  That is, in this embodiment, after the post-baking process shown in step S5 of FIG. 9 is completed, the substrate is cooled to room temperature and taken out from the coating apparatus. Next, as shown in step S21 of FIG. 9, the substrate is placed in a vertical furnace, and the substrate is annealed. The annealing process shown in step S21 is similar to the annealing process shown in step S8. For example, in the annealing process shown in step S21, the atmosphere is a nitrogen atmosphere, the heating temperature is 500 to 600 ° C., and the heating time is 1 hour. Thereby, a cross-linking reaction occurs between the CNTs 31, and the CNTs 31 are loosely bonded. Thereafter, when the substrate is cooled to room temperature, the substrate is removed from the vertical furnace. Next, the substrate is loaded again into the coating apparatus. Thereafter, steps after step S6 are performed. The manufacturing method other than the above in this embodiment is the same as that in the first embodiment.

  According to the present embodiment, after the post-baking process shown in step S5 of FIG. 9, the annealing process shown in step S21 is performed to cause a cross-linking reaction between the CNTs 31, and then, as shown in step S6, the insulating material Is applied. Thereby, since the insulating material 25 does not exist between CNT31 in the case of the crosslinking reaction of CNT31, CNT31 can be combined more reliably. The effects of the present embodiment other than those described above are the same as those of the first embodiment described above.

Next, a third embodiment will be described.
FIG. 10 is a flowchart illustrating the pillar forming method in the method for manufacturing the memory device according to this embodiment.
As shown in FIG. 10, the manufacturing method of the memory device according to the present embodiment is different from the method of manufacturing the memory device according to the first embodiment (see FIG. 3). The plasma processing step shown in step S22 is different from the upper electrode layer forming step shown in step S9.

  That is, in this embodiment, after the annealing process shown in step S8 of FIG. 10 is completed, the substrate is cooled to room temperature and taken out from the coating apparatus. Next, as shown in step S22 of FIG. 10, the substrate is loaded into the plasma processing apparatus. Then, plasma having a higher etching rate with respect to the insulating material 25 than that with respect to the CNT 31, for example, a rare gas plasma, is generated and brought into contact with the upper surface of the substrate, that is, the upper surface of the nanomaterial assembly layer 23. Thereby, the insulating material 25 adhering to the surface of the portion protruding from the upper surface of the deposited layer made of the insulating material 25 in the CNT 31 is removed. Thereafter, the substrate is taken out of the plasma processing apparatus and loaded into the PVD apparatus. Thereafter, the processes after Step S9 are performed. The manufacturing method other than the above in this embodiment is the same as that in the first embodiment.

  According to the present embodiment, in the process shown in FIG. 10 up to step S8, after filling the gap 32 with the insulating material 25, as shown in step S22, it is unnecessary to attach to the CNT 31 using the rare gas plasma. The insulating material 25 is removed, and then the upper electrode layer 24 is formed as shown in step S9. Thereby, CNT31 and the upper electrode layer 24 can be connected more reliably. The effects of the present embodiment other than those described above are the same as those of the first embodiment described above.

Next, a fourth embodiment will be described.
FIG. 11 is a flowchart illustrating an example of a pillar formation method in the method for manufacturing a storage device according to this embodiment.
FIG. 12 is a schematic cross-sectional view illustrating a pillar of the storage device according to this embodiment.

  As shown in FIG. 11, the manufacturing method of the memory device according to the present embodiment is different from the manufacturing method of the memory device according to the first embodiment (see FIG. 3). The difference is that the ashing process shown in step S23 is provided between the upper electrode layer forming process shown in step S9. Thus, as shown in FIG. 12, in the memory device according to the present embodiment, the upper surface of the CNT 31 and the upper surface of the insulating material 25 are substantially in the same plane, and the CNT 31 is not embedded in the upper electrode layer 24.

That is, in this embodiment, after the annealing process shown in step S8 of FIG. 11 is completed, the substrate is cooled to room temperature and taken out from the coating apparatus. Next, as shown in step S23 of FIG. 11, the substrate is loaded into the plasma processing apparatus. Then, plasma having a higher etching rate for the CNT 31 than that for the insulating material 25, for example, a mixed plasma of nitrogen and hydrogen (N ₂ / H ₂ ), a plasma of ammonia (NH ₃ ), or oxygen (O ₂ ). Plasma is generated and brought into contact with the substrate. Thereby, as shown in FIG. 12, the part which protruded from the upper surface of the deposition layer which consists of the insulating material 25 in CNT31 is ashed and removed. As a result, the upper surface of the CNT 31 and the upper surface of the insulating material 25 become substantially flush with each other, and the upper surface of the deposited layer made of the insulating material 25 becomes flat. Thereafter, the substrate is taken out from the plasma processing apparatus, and is again loaded into the coating apparatus, and the processes after step S9 are performed. The manufacturing method other than the above in this embodiment is the same as that in the first embodiment.

  According to the present embodiment, in the process shown in FIG. 11 up to step S8, after the gap 32 is filled with the insulating material 25, as shown in step S23, the plasma treatment is performed so that the insulating material 25 in the CNT 31 The portion protruding from the deposited layer is removed, and then the upper electrode layer 24 is formed as shown in step S9. Thereby, the lower surface of the upper electrode layer 24 can be further flattened. The effects of the present embodiment other than those described above are the same as those of the first embodiment described above.

Next, a fifth embodiment will be described.
FIG. 13 is a flowchart illustrating the pillar forming method in the method for manufacturing the memory device according to this embodiment.

  As shown in FIG. 13, the method for manufacturing the memory device according to the present embodiment is different from the method for manufacturing the memory device according to the first embodiment (see FIG. 3). The difference is that the CMP process shown in step S24 is provided between the upper electrode layer forming process shown in step S9. In the memory device according to the present embodiment, the upper surface of the CNT 31 and the upper surface of the insulating material 25 are substantially flush with the upper electrode, as in the memory device according to the fourth embodiment (see FIG. 12). The layer 24 is not embedded with CNTs 31.

  That is, in this embodiment, after the annealing process shown in step S8 of FIG. 13 is completed and the substrate is cooled to room temperature, the substrate is taken out from the coating apparatus. Next, as shown in step S24 of FIG. 13, the substrate is loaded into a CMP apparatus, and the upper surface of the substrate is subjected to CMP. Thereby, as shown in FIG. 12, the part protruded from the upper surface of the deposition layer which consists of the insulating material 25 in CNT31 is removed. Thereafter, the substrate is taken out from the CMP apparatus and loaded into the PVD apparatus, and the processes after step S9 are performed. The manufacturing method other than the above in this embodiment is the same as that in the first embodiment. The effect of this embodiment is the same as that of the above-described fourth embodiment.

Next, a sixth embodiment will be described.
14 and 15 are process cross-sectional views illustrating the method for manufacturing the memory device according to the sixth embodiment.

  In the sixth embodiment, the state shown in FIG. 5A is prepared in advance through the same manufacturing process as in FIGS. 4A to 5A. The state shown in FIG. 14A is the same as the state shown in FIG.

  For example, the substrate described above is inserted into a PVD apparatus, and a conductive material, for example, tungsten or titanium nitride is deposited from above the nanomaterial assembly layer 23 by the PVD method. At this time, the conductive material enters the gap 32 and is deposited on the deposition layer made of the insulating material 25 to cover the exposed portion of the CNT 31. Thereby, the upper electrode layer 24 is formed, and the CNT 31 is embedded in the lower part thereof.

  Here, when the layer 50 in which the insulating material 25 is filled in the gap 32 of the nanomaterial assembly layer 23 is the structure 50, the structure 50 is formed on the lower electrode layer 22 at this stage. An upper electrode layer 24 is formed thereon. In addition, a layer including the lower electrode layer 22, the structure 50, and the upper electrode layer is a stacked body 51.

  Subsequently, after the stacked body 51 is formed, a hard mask (not shown) made of, for example, silicon oxide is formed on the upper electrode layer 24. Next, a resist film (not shown) is formed on the hard mask and patterned by a lithography method to remain in a region where the pillar 16 is to be formed (not shown). Next, anisotropic etching such as RIE is performed using the patterned resist film as a mask to pattern the hard mask (not shown).

Next, as shown in FIG. 14B, anisotropic etching such as RIE is performed using the patterned hard mask as a mask. Thereby, the upper electrode layer 24, the nanomaterial assembly layer 23, the lower electrode layer 22, and the silicon diode layer 21 are selectively removed, and the pillar 16 is formed. In this way, the stacked body 51 is selectively etched, and the side surface 50w of the structure 50 is exposed. The gas for etching the stacked body 51 is, for example, a mixed gas of oxygen (O ₂ ) and fluorocarbon (CF _x ) gas.

  Next, as shown in FIG. 15A, the side surface 50w of the structure 50 is selected from the group of hydrogen (H) ions, oxygen (O) ions, hydrogen (H) radicals, and oxygen (O) radicals. The active gas 52 containing at least one of the above is exposed. Thereby, the nanomaterial assembly layer 23 is selectively etched from the side surface 50w of the structure 50. Alternatively, defects occur in the nanomaterial assembly layer 23 itself. This state is shown in FIG.

  As shown in FIG. 15B, a part of the side surface of the nanomaterial assembly layer 23 is removed and recedes from the side surface 50 w of the structure 50 toward the center of the pillar 16. An insulating material from which the nanomaterial assembly layer 23 is removed, that is, an insulating layer 55 is formed in a portion where the nanomaterial assembly layer 23 has receded.

  The thickness of the insulating layer 55 in the direction perpendicular to the direction from the lower electrode layer 22 toward the upper electrode layer 24 is adjusted by the etching time for etching a part of the nanomaterial assembly layer 23. That is, the longer the etching time is, the thicker the insulating layer 55 is. As a gas for etching a part of the nanomaterial assembly layer 23, it is desirable to select a hydrogen (H) radical or an oxygen (O) radical that can etch the nanomaterial assembly layer 23 more isotropically.

  As described above, in the sixth embodiment, after the stacked body 51 is selectively etched to expose the side surface 50w of the structure 50, a part of the nanomaterial assembly layer 23 is selectively etched from the side surface 50w. To do. The gas species for selectively etching the stacked body 51 is different from the gas species for selectively etching the nanomaterial assembly layer 23.

  FIGS. 16A and 16B are process diagrams illustrating a method for manufacturing a memory device according to the sixth embodiment. FIG. 16A is a top process diagram, and FIG. 16B is a cross-sectional process diagram.

After the nanomaterial assembly layer 23 is etched, a protective layer 56 is formed on the side surface of the pillar 16. The material of the protective layer 56 is, for example, silicon nitride (Si ₃ N ₄ ). Formation of the protective layer 56 makes it difficult for moisture and the like to enter the pillar 16 from outside the pillar 16.
As described above, the storage device 2 according to the sixth embodiment includes the nanomaterial assembly layer 23 in which a plurality of minute conductors are aggregated via the gap 32, and the insulating material 25 disposed in the gap 32. . Furthermore, the memory device 2 includes a lower electrode layer 22 in contact with the lower surface of the nanomaterial assembly layer 23, an upper electrode layer 24 in contact with the upper surface of the nanomaterial assembly layer 23, and an insulating layer that covers the side surfaces of the nanomaterial assembly layer 23. 55.

  When viewed from the direction perpendicular to the upper surface of the nanomaterial assembly layer 23, the side surface 23 w of the nanomaterial assembly layer 23 is the center of the nanomaterial assembly layer 23 rather than the side surface 22 w of the lower electrode layer 22 or the side surface 24 w of the upper electrode layer 24. Located on the side. In other words, the region where the nanomaterial assembly layer 23 exists is inside the region where the insulating material 25 exists.

  For example, the area of the region where the nanomaterial assembly layer 23 exists is 90% or less with respect to the area of the region where the insulating material 25 exists. Each of the plurality of microconductors is a carbon nanotube. The insulating material 25 contains at least silicon, oxygen, carbon and hydrogen, and is hydrophobic.

  In the storage device 2, the width of the nanomaterial assembly layer 23 in each pillar 16 is narrower than that in the storage device 1. Here, the “width” is a width in a direction substantially parallel to the upper surface of the nanomaterial assembly layer 23.

  As a result, the storage device 2 has a lower operating current than the storage device 1. For example, when the area of the region where the nanomaterial aggregate layer 23 exists is 50% of the area of the region where the insulating material 25 exists, the nanomaterial aggregate layer 23 corresponds to the area of the region where the insulating material 25 exists. When the current path that conducts between the upper electrode layer 24 and the lower electrode layer 22 is halved compared to when the area of the region where the current exists is 100%, the operating current is approximately halved. Become. Further, the “low resistance state” and the “high resistance state” can be obtained at a lower voltage than the storage device 1. In other words, these effects enable low power consumption operation.

  The periphery of the nanomaterial assembly layer 23 is covered with an insulating layer 55. In other words, the memory device 2 has a structure in which the nanomaterial assembly layer 23 is disposed in the cylindrical insulating layer 55. That is, the nanomaterial assembly layer 23 is supported by the insulating layer 55 provided on the outer periphery thereof. Thereby, the mechanical strength of the nanomaterial assembly layer 23 can be maintained at the same level as that of the storage device 1. The insulating material 25 is an SOG (Spin On Glass) layer formed by spin coating. Therefore, the adhesion between the insulating material 25 (insulating layer 55), the lower electrode layer 22, and the upper electrode layer 24 is improved. Thereby, it is suppressed that the pillar 16 collapses in the part of the nanomaterial assembly layer 23 or the pillar 16 breaks with the nanomaterial assembly layer 23 as a fracture surface.

The insulating layer 55 is a layer obtained by removing the CNTs 31 from the insulating material 25. Therefore, the insulating layer 55 has a large number of holes on the order of several nanometers. That is, in the storage device 2, the parasitic capacitance around the nanomaterial assembly layer 23 is lower than that of the storage device 1.
The process of selectively etching the stacked body 51 to expose the side surface 50w of the structure 50 and the process of selectively etching a part of the nanomaterial assembly layer 23 from the side surface 50w are performed in the same etching apparatus. This can be done simply by switching the gas type. Therefore, in the sixth embodiment, the manufacturing cost is not increased.

In addition, when the process proceeds without removing a part of the nanomaterial assembly layer 23, for example, the following problems occur.
FIG. 17 is a cross-sectional process diagram illustrating a method for manufacturing the memory device according to the comparative example.
As shown in FIG. 17A, it is assumed that after the pillar 16 is formed, the residue 60 adheres to the side wall of the structure 50. When such a residue 60 has conductivity, as shown in FIG.
The lower electrode layer 22 and the upper electrode layer 24 are always connected via the CNT 31 and the residue 60.

FIG. 18 is a cross-sectional process diagram illustrating the method for manufacturing the memory device according to the sixth embodiment.
In contrast, the sixth embodiment has the following advantages. For example, even if the residue 60 adheres to the side wall of the structure 50 after the pillar 16 is formed, the insulating layer 55 is already formed between the nanomaterial assembly layer 23 and the residue 60. Therefore, there is no short circuit between the lower electrode layer 22 and the upper electrode layer 24 via the CNT 31 and the residue 60.

FIG. 19 is a top schematic view illustrating a modification of the storage device according to the sixth embodiment.
After part of the nanomaterial assembly layer 23 is removed, the form shown in FIG. 19 is not limited to the form shown in FIG. For example, when viewed from the direction perpendicular to the top surface of the nanomaterial assembly layer 23, the nanomaterial assembly layer 23 does not have to be rectangular, and may have a structure in which the corners are curved.

  In the embodiment, a plurality of pillars 16 may be stacked. Thereby, a storage device with higher recording density is formed.

Next, a seventh embodiment will be described.
FIG. 20 is a flowchart illustrating the pillar forming method in the method for manufacturing the memory device according to the seventh embodiment.
FIG. 21 is a schematic cross-sectional view illustrating a pillar of the memory device according to the seventh embodiment.

As shown in FIG. 20, steps S1 to S11 of the method for manufacturing the storage device according to the present embodiment are the same as the method for manufacturing the storage device according to the fifth embodiment (see FIG. 13).
In this embodiment, after performing anisotropic etching according to step S11, as shown in FIG. 15A, the side surface of the nanomaterial assembly layer 23 is etched (step S30). Thereafter, wet cleaning (step S12) is performed to form a side wall (protective layer 56) (step S13).

  In the memory device according to the present embodiment, as in the memory device according to the fifth embodiment described above, the upper surface of the CNT 31 and the upper surface of the insulating material 25 are substantially in the same plane. Not embedded.

  Thereby, as shown in FIG. 21, the structure which removed the part which protruded from the upper surface of the deposition layer which consists of the insulating material 25 in CNT31 is obtained.

  As mentioned above, although several embodiment of this invention was described, these embodiment is shown as an example and is not intending limiting the range of invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the scope of the invention described in the claims and the equivalents thereof.

  For example, the insulating material 25 may be densely embedded so that voids are not substantially formed in the gaps 32, or has a porous structure in which voids having a size similar to or smaller than that of the CNTs 31 are formed. May be. When it is a porous structure, the void may be formed in the whole nanomaterial assembly layer 23, may be formed only in the lower part, and may be formed only in the center part of the thickness direction.

  Moreover, in each above-mentioned embodiment, the example in which CNT31 which contact | connected both the lower electrode layer 22 and the upper electrode layer 24 does not exist in the nanomaterial assembly layer 23 was shown. However, if there are only a few, there may be CNTs 31 that penetrate the nanomaterial assembly layer 23 in the thickness direction and are in contact with both the lower electrode layer 22 and the upper electrode layer 24. Even in this case, a difference can be made between the resistance value when the nanomaterial assembly layer 23 is in the “low resistance state” and the resistance value when the nanomaterial assembly layer 23 is in the “high resistance state”. 23 can function as a storage layer.

  Furthermore, the above-described embodiments can be implemented in combination with each other. For example, the annealing process for the CNT 31 and the annealing process for the insulating material 25 are performed in different steps as in the second embodiment, and the rare gas plasma process is performed as in the third embodiment. And the insulating material 25 attached to the CNTs 31 may be removed.

  According to the embodiment described above, a highly reliable storage device and a method for manufacturing the same can be realized.

1, 2: Memory device, 11: Silicon substrate, 12: Interlayer insulating film, 13: Memory cell part, 14: Word line wiring layer, 15: Bit line wiring layer, 16: Pillar, 21: Silicon diode layer, 22: Lower electrode layer, 23: Nanomaterial assembly layer, 24: Upper electrode layer, 25: Insulating material, 31: Carbon nanotube (CNT), 32: Gap, 50: Structure, 50w: Side surface, 51: Laminate, 52: Active gas, 55: insulating layer, 56: protective layer, 60: residue, BL: bit line, WL: word line

Claims (29)

A nanomaterial assembly layer in which a plurality of microconductors are aggregated via a gap;
An insulating material disposed in the gap;
A storage device. The microconductor is a carbon nanotube;
The storage device according to claim 1, wherein a direction in which the carbon nanotube extends is closer to a direction parallel to the lower surface than a direction perpendicular to the lower surface of the nanomaterial assembly layer.   The storage device according to claim 1, wherein the insulating material is filled in the gap by a coating method. A lower electrode layer in contact with the lower surface of the nanomaterial assembly layer;
An upper electrode layer in contact with the upper surface of the nanomaterial assembly layer;
Further comprising
The storage device according to claim 1, wherein there is no microconductor in contact with both the lower electrode layer and the upper electrode layer.   The storage device according to claim 1, wherein the insulating material contains at least silicon, oxygen, carbon, and hydrogen and is hydrophobic.   The storage device according to claim 1, wherein the insulating material is methylsilsesquioxane. A word line wiring layer including a plurality of word lines extending in a first direction;
A bit line wiring layer including a plurality of bit lines extending in a second direction intersecting the first direction;
Further comprising
The word line wiring layers and the bit line wiring layers are alternately stacked,
The storage device according to claim 1, wherein the nanomaterial assembly layer is a part of a pillar disposed between each of the word lines and each of the bit lines. A nanomaterial assembly layer in which a plurality of microconductors are aggregated via a gap;
An insulating material disposed in the gap;
A lower electrode layer in contact with the lower surface of the nanomaterial assembly layer;
An upper electrode layer in contact with the upper surface of the nanomaterial assembly layer;
An insulating layer covering a side surface of the nanomaterial assembly layer;
With
Seen from the direction perpendicular to the upper surface of the nanomaterial assembly layer,
The storage device, wherein the side surface of the nanomaterial assembly layer is located closer to the center of the nanomaterial assembly layer than the side surface of the lower electrode or the side surface of the upper electrode.   The storage device according to claim 8, wherein each of the plurality of microconductors is a carbon nanotube.   The memory device according to claim 8, wherein the insulating layer contains at least silicon, oxygen, carbon, and hydrogen and is hydrophobic.   The storage device according to claim 9 or 10, wherein a direction in which the carbon nanotube extends is closer to a direction parallel to the lower surface than a direction perpendicular to the lower surface of the nanomaterial assembly layer.   The storage device according to claim 8, wherein the insulating material is filled in the gap by a coating method. A lower electrode layer in contact with the lower surface of the nanomaterial assembly layer;
An upper electrode layer in contact with the upper surface of the nanomaterial assembly layer;
Further comprising
The memory device according to any one of claims 8 to 12, wherein there is no microconductor in contact with both the lower electrode layer and the upper electrode layer.   The storage device according to claim 8, wherein the insulating material is methylsilsesquioxane. A word line wiring layer including a plurality of word lines extending in a first direction;
A bit line wiring layer including a plurality of bit lines extending in a second direction intersecting the first direction;
Further comprising
The word line wiring layers and the bit line wiring layers are alternately stacked,
The storage device according to claim 8, wherein the nanomaterial assembly layer is a part of a pillar disposed between each word line and each bit line. Forming a nanomaterial assembly layer in which a plurality of microconductors are aggregated through a gap;
Filling the gap with an insulating material;
A method for manufacturing a storage device comprising:   The method for manufacturing a memory device according to claim 16, wherein the step of filling the insulating material includes a step of applying the insulating material.   The method for manufacturing a memory device according to claim 16, further comprising a step of heating the nanomaterial assembly layer and the filled insulating material. Heating the nanomaterial assembly layer;
Heating the filled insulating material;
Further comprising
The method of manufacturing a memory device according to claim 16, wherein the step of heating the nanomaterial assembly layer is performed before the step of filling the insulating material. Contacting the top surface of the nanomaterial assembly layer with a plasma having a higher etching rate for the insulating material than the etching rate for the microconductor;
Depositing a conductive material on the deposited layer made of the insulating material to form an upper electrode layer;
The method for manufacturing a storage device according to any one of claims 16 to 19, further comprising: Contacting the top surface of the nanomaterial assembly layer with a plasma having a higher etching rate for the microconductor than for the insulating material;
Depositing a conductive material on the deposited layer made of the insulating material to form an upper electrode layer;
The method for manufacturing a storage device according to any one of claims 16 to 19, further comprising: Polishing the top surface of the nanomaterial assembly layer to remove a portion protruding from the top surface of the deposited layer made of the insulating material in the microconductor; and
Depositing a conductive material on the deposited layer to form an upper electrode layer;
The method for manufacturing a storage device according to any one of claims 16 to 19, further comprising:   The method for manufacturing a memory device according to any one of claims 16 to 22, wherein the minute conductor is a carbon nanotube. Forming a word line wiring layer including a plurality of word lines extending in a first direction;
Forming a bit line wiring layer including a plurality of bit lines extending in a second direction intersecting the first direction;
Selectively removing the nanomaterial assembly layer filled with the insulating material to form pillars;
Further comprising
Alternately performing the step of forming the word line wiring layer and the step of forming the bit line wiring layer;
The step of forming the nanomaterial assembly layer, the step of filling the insulating material, and the step of forming the pillar are performed between the step of forming the word line wiring layer and the step of forming the bit line wiring layer. The method for manufacturing a storage device according to any one of claims 16 to 23.   A part of the nanomaterial assembly layer is selectively etched from a side surface of a structure in which the insulation material is filled in the gap and then the insulation material is filled in the gap of the nanomaterial assembly layer. 16. A method for manufacturing a storage device according to 16.   The storage device according to any one of claims 16 to 25, wherein the insulating material contains at least silicon, oxygen, carbon, and hydrogen.   A part of the nanomaterial assembly layer is selectively etched from the side surface of the structure using a gas containing at least one selected from the group consisting of hydrogen ions, oxygen ions, hydrogen radicals, and oxygen radicals. Item 27. A method for manufacturing a storage device according to Item 25 or 26.   After forming the structure on the lower electrode layer, forming the upper electrode layer on the structure, and forming the laminate including the lower electrode layer, the structure, and the upper electrode layer, 28. The stack according to claim 25, wherein the stacked body is selectively etched to expose the side surface of the structure, and a part of the nanomaterial assembly layer is selectively etched from the side surface. Method for manufacturing the storage device.   29. The method for manufacturing a storage device according to claim 28, wherein a gas species for selectively etching the stacked body and a gas species for selectively etching a part of the nanomaterial assembly layer are different.

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