JP2012114021A - Circuit pattern evaluation method, and system for the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve throughput without deterioration of evaluation performance of a scanning charged-particle microscope.SOLUTION: A method of evaluating shapes of circuit patterns formed on a semiconductor wafer using a scanning charged-particle microscope, includes: acquiring an image including a plurality of evaluation patterns by performing image capturing on a semiconductor wafer which is formed such that the plurality of evaluation patterns are contained within one field of view of the scanning charged-particle microscope using the scanning charged-particle microscope; adjusting image quality of the image by controlling the scanning charged-particle microscope using a pattern different from the plurality of evaluation patterns contained within the field of view of the scanning charged-particle microscope in the acquired image containing the plurality of evaluation patterns; sequentially acquiring images of the plurality of evaluation patterns within the field of view containing the plurality of evaluation patterns due to image shift by controlling the scanning charged-particle microscope for which the image quality is adjusted; and evaluating the shapes of the plurality of circuit patterns using the images of the plurality of evaluation patterns which are sequentially acquired due to the image shift.

Description

  The present invention relates to a layout design of a semiconductor device circuit pattern, and a circuit pattern evaluation method and system for imaging and evaluating the circuit pattern created on a sample such as a semiconductor wafer with a scanning charged particle microscope.

  As a method for forming a circuit pattern on a semiconductor wafer, a coating material called a resist is applied on the semiconductor wafer, and an exposure mask (reticle) for the circuit pattern is overlaid on the resist, and then visible light, ultraviolet light, or an electron beam is applied thereon. A circuit pattern is formed on a semiconductor wafer by irradiating the resist, exposing the resist to light (exposure) and developing, and etching the semiconductor wafer using the resist circuit pattern as a mask. Etc. are adopted.

  In recent years, in order to meet the needs for higher speed and higher integration of semiconductor devices, optical resolution exposure (Optical Proximity Correction: OPC) and super-resolution exposure represented by exposure light source / mask simultaneous optimization (Source Mask Optimization: SMO) With the introduction of technology, mask patterns are becoming more complex. In particular, in SMO, optimization by a computer is essential, and this is called computer lithography (Computational Lithography).

  In designing and manufacturing a semiconductor device, it is necessary to evaluate the circuit pattern shape and feed back the evaluation result to the design or manufacturing process. For pattern evaluation, a critical dimension scanning electron microscope (CD-SEM), which is one of scanning charged particle microscopes, is widely used.

The CD-SEM is a device that acquires an SEM image of an evaluation pattern and measures the pattern in the sub-nanometer order. As a pattern shape evaluation method using an SEM image, (1) a method of measuring dimensions such as a so-called CD value, such as a line pattern width and a contact hole diameter, (2) for example, Patent Document 1 (Japanese Patent No. 4158384) There are a method for calculating an image feature amount having a high correlation with the disclosed pattern shape, and (3) a method for detecting a two-dimensional contour line of a pattern disclosed in, for example, Patent Document 2 (Japanese Patent No. 4154374). .
In order to perform such evaluation with high accuracy, it is necessary to acquire a high-magnification and high-definition SEM image using a CD-SEM. That is, it is required to align the field of view with an arbitrary evaluation pattern on the wafer at a magnification of several hundred thousand times and adjust the focus position of the converged electron beam to be irradiated on the wafer surface. An imaging sequence including these visual field movement and image quality adjustment is specified using a file called an imaging recipe. Once an imaging recipe is created, the CD-SEM can automatically image the same type of wafer without any special operation by the operator. Patent Document 3 (Japanese Patent Laid-Open No. 2007-250528) discloses a method for automatically generating the imaging recipe.

  The following patterns (a) to (d) are mainly given as patterns with high evaluation needs by CD-SEM, and in particular (a) to (c), the number of evaluation patterns may reach several thousand.

(A) A pattern of a dangerous spot that is likely to cause a device failure called a hot spot output by an exposure / development simulation mounted on an EDA (Electronic Design Automation) tool or the like.
(B) A test pattern or actual mass production pattern for determining the conditions of the exposure / etching apparatus.
(C) In computer lithography or the like, a test pattern or an actual mass production pattern for calibrating an expected shape by simulation and an actual pattern shape.
(D) A pattern that makes it easy to detect process variations for process monitoring during device mass production.

Japanese Patent No. 4158384 Japanese Patent No. 4154374 JP 2007-250528 A JP 2000-348658 A JP 2002-328015 A

  As described above, miniaturization and high density of circuit patterns are progressing in response to needs for higher speed and higher integration of semiconductor devices. The complication of the mask pattern has made it difficult to predict the simulation of the pattern shape to be transferred. In particular, the number of evaluation patterns during device development has been dramatically increased. Furthermore, the trend toward short-term production of consumer equipment has increased the tendency for low-volume production of various types of semiconductor devices, and there is a need for efficient production start-up. SUMMARY OF THE INVENTION An object of the present invention is to meet the above-mentioned demands, and to provide a circuit pattern evaluation method based on the characteristics of a scanning charged particle microscope capable of increasing the throughput of the scanning charged particle microscope without degrading the evaluation performance and its To provide a system.

In order to achieve the above object, the present invention provides a circuit pattern evaluation method and system based on the characteristics of a scanning charged particle microscope having the following characteristics.

  (1) A method for acquiring captured images of a plurality of circuit patterns formed on a semiconductor wafer using a scanning charged particle microscope and evaluating the shape of the circuit pattern from the captured images, the scanning charged particles An evaluation pattern group determination step for determining a plurality of circuit patterns to be imaged as an evaluation pattern using a microscope, an image shift movable range input step for inputting a movable range in an image shift in the scanning charged particle microscope, and the evaluation pattern A distance between at least two of the plurality of circuit patterns to be imaged as the evaluation pattern determined in the determination step is included in the image shift movable range input in the image shift movable range input step. A plurality of circuits to be imaged as the determined evaluation pattern A layout determining step for determining a layout of the turn, and a layout so that the distance among the plurality of circuit patterns to be imaged as the evaluation pattern for which the layout is determined in the layout determining step is included in the image shift movable range An imaging recipe generating step for registering an imaging sequence for performing visual field movement between the at least two or more evaluation patterns determined by image shift in an imaging recipe, and the imaging sequence registered in the imaging recipe in the imaging recipe generating step Imaging a plurality of circuit patterns to be imaged as the evaluation pattern determined in the evaluation pattern group determining step, and imaging as the evaluation pattern using an image captured in the imaging step Multiple circuit patterns A circuit pattern evaluation method characterized by a step of evaluating the shape.

  It supplements about this method. First, the image shift means that the charged particle beam irradiated by the charged particle optical system is deflected without moving the stage, and the imaging position is changed by changing the irradiation position of the charged particle beam to the sample. is there. As another means for changing the imaging position, there is a stage shift for moving a stage on which a sample such as a semiconductor wafer is mounted. Although the stage shift generally has a wider movable range than the image shift, the positioning accuracy of the imaging position is It has the property of being low. Therefore, after the stage shift, addressing for detecting a movement error is performed, and the movement to the evaluation pattern is performed by image shift so as to cancel the movement error. Also, image quality adjustment processing such as autofocus is often performed after stage shifting. That is, the stage shift including processing such as addressing requires much processing time for the image shift.

  Focusing on this point, the present invention inputs an image shift movable range and optimizes the layout of the circuit pattern so that many evaluation patterns are included in the image shift movable range. The number of times of visual field movement between evaluation patterns by image shift during imaging is increased, and high throughput of the scanning charged particle microscope is realized.

  Although the visual field is moved by the image shift between the evaluation patterns existing in the image shift movable range, the stage shift is once performed when the visual field is moved to the evaluation pattern outside the image shift movable range. An evaluation pattern group in which a visual field is moved by image shift without inserting a stage shift in a series of imaging sequences is called an image shift group (IS group). That is, movement between evaluation patterns belonging to different IS groups is accompanied by a stage shift.

  (2) The circuit pattern imaging / evaluation method is characterized in that the layout of the item (1) is a test pattern created for pattern shape evaluation. Further, the circuit pattern evaluation method is characterized in that the plurality of evaluation patterns are arranged in a lattice pattern on the semiconductor wafer.

  The above item (1) is a method applicable to an arbitrary layout, but the test pattern has a higher degree of freedom in changing the layout as compared with a logic pattern or the like, and the effect of the present invention can be particularly expected. In addition, the layout in which the evaluation patterns are arranged in a grid has the advantage that the degree of freedom of layout change is high and the layout change is relatively easy.

  (3) The layout in the layout determining step of item (1) is determined in such a way that the distance between at least two or more evaluation patterns is within the image shift movable range of the scanning charged particle microscope. The circuit pattern evaluation method is characterized in that the distance between the evaluation patterns is determined.

  As described above, the higher the throughput, the more evaluation patterns are included in the IS group. In order to include many evaluation patterns in the IS group, it is effective to reduce the distance between the evaluation patterns and to concentrate the evaluation patterns.

  However, when the distance between the two evaluation patterns is largely shortened, a pattern existing between the two evaluation patterns may interfere. In such a case, the pattern is trimmed within a range centered on the evaluation pattern (a pattern existing between two evaluation patterns is removed) to avoid pattern interference. However, pattern formation may be affected by patterns existing around the pattern due to an optical proximity effect (OPE) in the exposure process. Therefore, it is dangerous to inadvertently remove even a pattern that exists outside the imaging field of the evaluation pattern. Therefore, the range covered by the OPE is input, and the pattern removal range (or the shortened distance between the evaluation patterns) is limited based on the range covered by the OPE.

  (4) The layout determination in the layout determination step of the item (1) includes at least two or more charged particle scanning directions in the image shift movable range when imaging using the scanning charged particle microscope. A circuit pattern evaluation method is characterized in that the evaluation pattern is determined so as to be in the same direction.

  That is, the number of changes in the scanning direction can be reduced as the charged particle scanning direction is the same in the IS group.

  (5) When the evaluation pattern described in item (3) is targeted for a layout in which the evaluation pattern is arranged in a grid pattern, the layout determination in the layout determination step of item (1) is performed by determining the number of rows and columns of the evaluation pattern. Is determined so as to be close to a multiple of the number of evaluation patterns that can be imaged in the row direction and the column direction by image shift, respectively.

  That is, as an ideal arrangement, if the number of rows and the number of columns of the evaluation pattern is a multiple of the number of evaluation patterns that can be obtained by image shift and the intervals between the lattices are equal, the number of evaluation patterns included in all IS groups is Become the maximum. On the other hand, if it is not a multiple, the number of evaluation patterns included in some IS groups decreases, and the number of stage shifts relative to the number of evaluation patterns increases relatively. Therefore, as described above, the layout is determined so as to be as close to a multiple as possible to achieve high throughput.

  (6) The layout determination in the layout determination step of item (1) is based on the evaluation pattern sampling method so that the number of evaluation patterns after sampling existing in the image shift movable range is increased. A characteristic circuit pattern evaluation method is provided.

  When the number of evaluation patterns is large, the number of evaluation patterns actually captured using a scanning charged particle microscope may be reduced by sampling. In addition, various evaluation patterns may be created and sampled depending on the application. If known or previously which evaluation patterns are sampled, it is possible to optimize the layout to evaluate pattern after sampling distributed densely. However, even in the same layout, the sampling method (sampling plan) may be different depending on the purpose and the difference in allowable evaluation time. In order to always achieve good throughput against such sampling plan differences, the number of evaluation patterns after sampling included in the IS group for the sampling plan variations based on the assumed sampling plan variations Determine the layout so that there is as little as possible.

  (7) A method of acquiring captured images of a plurality of circuit patterns formed on a semiconductor wafer using a scanning charged particle microscope, and evaluating the shape of the circuit pattern from the captured images, the scanning charged particles An image shift movable range input step for inputting a movable range in image shift in a microscope, and a plurality of circuit patterns to be imaged as evaluation patterns using the scanning charged particle microscope, at least two of the plurality of circuit patterns An evaluation pattern group determining step for determining the distance between the circuit patterns to be within the input image shift movable range, and the at least two existing image shift movable ranges input in the image shift movable range input step. Imaging sequence that moves between two or more circuit patterns by image shift An imaging recipe generation step for registering the image in the imaging recipe, an evaluation pattern imaging step for imaging the evaluation pattern determined in the evaluation pattern group determination step based on the imaging recipe registered in the imaging recipe generation step, and the evaluation pattern imaging step And a step of evaluating the evaluation pattern count using an image of the evaluation pattern obtained by imaging in (1).

  It supplements about this method. In order to achieve high throughput, it is necessary to include many evaluation patterns within the image shift movable range. Therefore, in determining the evaluation pattern, it is determined so that many IS groups including many evaluation patterns can be set. As described in the background art, conventionally, the determination of the evaluation pattern is (a) a dangerous spot called a hot spot where a device failure is likely to occur, or (b) a pattern suitable for determining the conditions of the exposure / etching apparatus. (B) Judgment criteria such as whether the pattern is suitable for calibration between the predicted shape by simulation and the actual pattern shape, (d) whether the pattern is easy to detect process variations, It is determined in consideration of variations and in-plane distribution. For this reason, the determination of the evaluation pattern is a multi-objective optimization problem that is determined in consideration of not only the criterion for determining whether the evaluation pattern is included in the image shift movable range in the present invention but also the conventional criterion. And

  (8) A method for acquiring captured images of a plurality of circuit patterns formed on a semiconductor wafer using a scanning charged particle microscope, and evaluating the shape of the circuit pattern from the captured images, the scanning charged particles An image shift movable range input step for inputting a movable range by image shift in a microscope, and a range in which a plurality of circuit patterns to be imaged as evaluation patterns using the scanning charged particle microscope can be moved from the evaluation pattern by image shift. An evaluation pattern group determining step for determining that there is a pattern in which addressing or image quality adjustment is possible, and moving from the evaluation pattern by image shift before imaging the evaluation pattern determined in the evaluation pattern group determining step Addressing or image quality adjustment that exists within the range An imaging recipe generation step of registering an imaging sequence for imaging an active pattern and performing addressing or image quality adjustment in an imaging recipe, an evaluation pattern group imaging step of imaging the evaluation pattern group based on the imaging recipe, and the evaluation pattern group And a step of evaluating the shape of the evaluation pattern using an image of the evaluation pattern obtained by imaging in the imaging step.

  It supplements about this method. Appropriate addressing and image quality adjustment (e.g., autofocus, autostigma, autobrightness / contrast adjustment, etc.) before imaging the evaluation pattern in order to achieve a significantly higher throughput of the scanning charged particle microscope without degrading the evaluation performance It is necessary to do part or all of the details (described later). Therefore, the evaluation pattern is selected based on the evaluation performance of the scanning charged particle microscope as to whether or not there is a pattern capable of appropriate addressing and image quality adjustment within the range that can be moved by image shift from the evaluation pattern. To do. In addition, the present invention is a multi-objective optimization problem that is determined in consideration of not only the above-mentioned criteria but also the conventional criteria as in the item (7).

  (9) A method for acquiring captured images of a plurality of circuit patterns formed on a semiconductor wafer using a scanning charged particle microscope, and evaluating the shape of the circuit pattern from the captured images, the scanning charged particles An image shift movable range input step for inputting a movable range in image shift in a microscope, and a plurality of circuit patterns to be imaged as evaluation patterns using the scanning charged particle microscope are addressed from the evaluation pattern within the image shift movable range. Alternatively, it is determined that there is a pattern whose image quality can be adjusted, and / or the distance between at least two evaluation patterns is determined to be within the movable range of the image shift input in the image shift movable range input step. An evaluation pattern group determination step to be performed, and the evaluation pattern group determination step A layout determining step for determining a layout of a circuit pattern so that a distance between at least two or more evaluation patterns included in the evaluation pattern determined in step is within the input image shift movable range; and the evaluation pattern group Before imaging the evaluation pattern determined in the determination step, an imaging sequence for performing addressing or image quality adjustment by imaging an addressable or image quality adjustable pattern existing within the image shift movable range from the evaluation pattern is registered in the imaging recipe. And / or an imaging recipe generation step for registering an imaging sequence for performing movement between at least two or more evaluation patterns existing in the image shift movable range by image shift in an imaging recipe, and the evaluation pattern based on the imaging recipe Imaging a group A circuit pattern evaluation method comprising: a valence pattern group imaging step; and a step of evaluating a shape of the evaluation pattern using an image of the evaluation pattern obtained by imaging in the evaluation pattern group imaging step .

  That is, the layout design or the evaluation pattern determination described in the items (1), (7), and (8) is not performed independently, but the entire optimization is performed in consideration of the throughput, evaluation performance, layout change, and the like. It is characterized by being made.

  As described in the items (1) to (9), the major feature of the present invention is that the specification and / or characteristics of the evaluation apparatus (scanning charged particle microscope) are taken into consideration in the layout design and determination of the evaluation pattern. . Evaluation requirements (defect detection accuracy / pattern shape measurement accuracy, throughput, inspection pattern measurement requirements for evaluation pattern coordinates, etc.) required in device development / manufacturing have become stricter as circuit patterns become finer and more dense. ing. In order to satisfy the above evaluation requirements, improvements on the evaluation device side have been promoted. However, when considering the overall optimization of the design-manufacturing-evaluation flow, the specifications on the evaluation device side are determined in layout design and evaluation pattern determination. Considering, it is possible to realize a significant performance improvement of the evaluation apparatus.

  Of course, especially regarding layout determination, it is necessary to satisfy the original specifications typified by device performance, and it is sometimes difficult to strongly reflect the specifications on the evaluation apparatus side when considering the trouble of changing the layout. However, as the number of evaluation patterns increases, the evaluation time in the design-manufacturing-evaluation flow cannot be ignored, and optimization considering the overall balance is important. In particular, the test pattern has a high degree of freedom in layout change, and even if the layout is changed slightly, a large effect may be obtained, and the present invention exhibits a great effect.

  By actively considering the characteristics of the scanning charged particle microscope when determining the layout and evaluation pattern of the circuit pattern, a significant improvement in throughput and highly reliable evaluation can be realized. This realizes a short TAT (Turn Around Time: period from input to completion) of the entire device development including the pattern verification time using a scanning charged particle microscope.

It is a figure which shows the flow of the whole process in one embodiment of this invention. It is a figure which shows the structure of the SEM apparatus for implement | achieving one embodiment of this invention. It is a figure which shows the method of imaging the signal amount of the electron discharge | released from on a semiconductor wafer. (A) is a figure which shows the imaging sequence in the SEM apparatus for imaging an evaluation pattern, (b) is a figure which shows the EP imaging range in the case of imaging the pattern formed in the wafer with SEM. (A) When the line width of the line pattern is a side long type, (b) When the distance between two line patterns as the side long type, (c) As the side long type, between the line pattern width and the line pattern (D) is the diameter of the contact hole as the side long type, (e) is the short axis length and long axis length of the isolated pattern as the side long type, and (f) is the side long type. In the case of a gap between two line patterns, (g) is the shape of the corner portion of the pattern as a side long type, (h) is an enlarged view of the pattern corner portion, and the design layout data and the contour line of the SEM image It is a figure which shows a gap vector. (A) is a figure which shows the imaging sequence in the SEM apparatus for imaging one evaluation pattern by image shift, (b) is a figure which shows the imaging sequence in the SEM apparatus for imaging four evaluation patterns by image shift. is there. (A) is a figure which shows the layout of the pattern on the wafer which shows the state by which eight EP is arrange | positioned in the position where the distance between adjacent EP is larger than an image shift movable range, (b) is between adjacent EP. The figure which shows the layout of the pattern on the wafer which shows the state which has arrange | positioned eight EP in the position where distance is smaller than an image shift movable range, (c) images all eight EP in the pattern layout shown to (a). 4 is a bar graph showing the time required for imaging and the time required for imaging all eight EPs in the pattern layout shown in FIG. (A) is the figure which shows the layout of the pattern on the wafer which shows the state where the distance between EP is large and only 1 EP is included in the image shift range, (b) includes 4 EPs in the image shift range The figure which shows the layout of the pattern on the wafer which shows the state which is displayed, (c) is the figure which shows the layout of the pattern on the wafer which shows the state where nine EP is included in the image shift range, (d) is the figure of (a) The figure which shows the layout of the pattern on the wafer which expanded and showed the area | region 800, (e) of the pattern on the wafer which expanded and showed the state which trimmed the pattern in the range which OPE in the area | region 800 of (a) FIG. 6F is a diagram showing a layout, and FIG. 5F is an enlarged view of a pattern on a wafer showing a state in which EP1 and EP2 are brought close to each other by a space between the range covered by OPE in the region 800 of FIG. It is a diagram showing a layout. (A) is a layout diagram of a pattern on a wafer showing a state in which the electron beam scanning directions of four EPs existing in each image shift movable range are different, and (b) is present in each image shift movable range. The layout diagram of the pattern on the wafer showing the state where the electron beam scanning directions of the four EPs are aligned, (c) is the layout diagram of the pattern in EP1, and (d) is the electron beam scanning direction for the pattern in EP1. (E) is a layout diagram of a pattern in EP2, and (f) is a diagram showing a scanning direction of an electron beam with respect to the pattern in EP2. (A) is a layout diagram of a pattern on a wafer showing a state in which 35 EPs are arranged on a matrix of 5 rows and 7 columns, and (b) is an image shift movable range with respect to the EP arrangement of (a). The layout diagram of the pattern on the wafer shown, (c) is a layout diagram of the pattern on the wafer showing a state in which 35 EPs are arranged on a matrix of 6 rows and 6 columns, and (d) is an EP layout of (c). It is the layout figure of the pattern on the wafer which showed the image shift movable range with respect to arrangement | positioning. (A) is a figure which shows the variation of the relationship between the line width of pattern A, and the magnitude | size of OPC, (b) is a figure which shows the variation of the relationship between the line width of pattern B, and the magnitude | size of OPC, (c) is pattern C FIG. 6D is a diagram showing variations in the relationship between the line width of the pattern and the size of the OPC, and FIG. 6D is a diagram showing variations in the relationship between the line width of the pattern D and the size of the OPC. (A) is a layout diagram of a pattern on a wafer showing an image shift movable range when all EPs are to be imaged, and (b) is a sample of every pattern type by sampling every other line width and OPC size. FIG. 6 is a layout diagram of a pattern on a wafer showing an image shift movable range when an image of EP is taken. (A) is a layout diagram of a pattern on a wafer showing an image shift movable range when all EPs are to be imaged, and (b) is a sample of every pattern type by sampling every other line width and OPC size. It is a layout diagram of the pattern on the wafer showing the image shift movable range when the layout of the EP is changed so as to image the EP. (A) is a pattern on the wafer showing a state in which only one EP is included in the image shift range when five EPs are selected in a state where two types of EPs are distributed in the plane of the wafer. FIG. 6B is a layout diagram showing a state in which five image shift movable ranges are set such that 15 EPs are included in five image shift movable ranges in a state where the types of EP are biased. (C) shows a state in which five image shift movable ranges are set so that 15 EPs are included in the five image shift movable ranges so that there is no bias in the type of EP. It is a layout figure of the pattern on the wafer shown. (A) is a diagram showing EP decision variations, and a layout diagram of patterns on a wafer when an addressing pattern exists but no autostigma adjustment pattern exists, and (b) shows EP decision variations. In the figure, it is a layout diagram of a pattern on a wafer when an addressing pattern and an autostigma adjustment pattern exist. (A) is a figure which shows the structure of the apparatus system for implement | achieving one embodiment of this invention, (b) integrated 1606, 1608, 1609, 1610, 1612-1615 in (a) into one apparatus. It is a figure which shows the structure of an apparatus system. It is a figure which shows GUI of one embodiment of this invention. (A) is a figure which shows the display variation of GUI display windows 1707-1710 shown in FIG. 17, Comprising: The figure which shows the state which added the display of the pattern for addressing and image quality adjustment, (b) is a mouse | mouth etc. The figure which shows the state which adds a pattern manually with (c) The figure which shows the state which uses the pattern added manually with the mouse etc. as a pattern for autostigma, (d) displays the several pattern added manually (E) is a diagram showing a state in which the EP is divided into a plurality of segmentation regions, (f) is a diagram showing an example in which the segmentation region is changed with respect to the display of (e), and (g) is a diagram showing It is a figure which shows the example displayed shortening the distance between the segmentations displayed by (e).

  The present invention provides a method for evaluating a pattern on a sample such as a semiconductor wafer at high speed using a scanning charged particle microscope without degrading the evaluation performance. Hereinafter, an embodiment according to the present invention will be described by taking a scanning electron microscope (SEM) which is one of scanning charged particle microscopes as an example. However, the present invention is not limited to this, and scanning is performed. The present invention can also be applied to a scanning charged particle microscope such as a scanning ion microscope (SIM) or a scanning transmission electron microscope (STEM). Further, as a variation of the SEM, in addition to the CD-SEM described above, it can be applied to a defect review SEM (Defect Review Scanning Electron Microscope: DR-SEM) or the like.

  Further, in the following description, a test pattern is described as an example of a circuit pattern layout, but the present invention can be applied to an arbitrary circuit pattern such as a logic or a memory. Further, the present invention is not limited to a semiconductor device, and can be applied to high-speed imaging of a sample having many evaluation points.

1. Overview
FIG. 1 shows a flow of the entire processing relating to an embodiment of the present invention. In this embodiment, circuit pattern layout data input on a sample to be evaluated (S101), circuit pattern (evaluation pattern) coordinate input (S102) to be imaged using an evaluation apparatus (SEM), evaluation request input (Defect detection accuracy / pattern shape measurement accuracy, throughput, request for inspection / measurement of imaging conditions, etc.) (S103), evaluation device specification input (image shift movable range, settable imaging conditions, each imaging condition and detection accuracy / (Relationship between measurement accuracy, relationship between imaging sequence and throughput, etc.) (S104), allowable layout change specification input (allowable change range regarding pattern placement / size / shape, etc., range covered by optical proximity effect (OPE), etc. ) (S105), the layout, imaging points, and imaging sequence are optimized (S106). Power (S107), the coordinate determination of evaluation pattern (S108), the determination of the imaging conditions, the imaging sequence (S109).

  Here, the imaging conditions are the electron microscope acceleration voltage (Vacc) and probe current (Ip) in the imaging of the evaluation pattern or the addressing / image quality adjustment pattern, the scanning direction and scanning range of the electron beam (imaging field of view. of view: called FOV), the number of added frames, the scanning direction of the irradiation electron beam in the FOV, and the like. In addition, the inspection / measurement performance (defect detection accuracy / pattern measurement accuracy, throughput, etc.) when imaging is performed with the layout / evaluation pattern / imaging condition / imaging sequence determined in S107 to S109 is predicted and output (S110). This is displayed on the GUI together with the optimization result and presented to the user (S111). Based on the predicted inspection / measurement performance displayed on the GUI, the user changes the optimization engine rule change in S106, the evaluation request input in S103, and the allowable layout change specification input in S105 as necessary. The optimization can be performed again in S106.

  A major feature of the present embodiment is that the specification of the evaluation apparatus (SEM) is taken into consideration in layout design and evaluation pattern determination. Evaluation requirements (defect detection accuracy / pattern shape measurement accuracy, throughput, inspection pattern measurement requirements for evaluation pattern coordinates, etc.) required in device development / manufacturing have become stricter as circuit patterns become finer and more dense. ing. In order to satisfy the above evaluation requirements, improvements on the evaluation device side have been promoted. However, when considering the overall optimization of the design-manufacturing-evaluation flow, the specifications on the evaluation device side are determined in layout design and evaluation pattern determination. Considering, it is possible to realize a significant performance improvement of the evaluation apparatus.

  Of course, especially regarding layout determination, it is necessary to satisfy the original specifications typified by device performance, and it is sometimes difficult to strongly reflect the specifications on the evaluation apparatus side when considering the trouble of changing the layout. However, as the number of evaluation patterns increases, the evaluation time in the design-manufacturing-evaluation flow cannot be ignored, and optimization considering the overall balance is important. In particular, the test pattern has a high degree of freedom in layout change, and even if the layout is changed slightly, a large effect may be obtained, and the present invention exhibits a great effect.

2. SEM
2.1 SEM components
FIG. 2 shows a block diagram of a configuration outline of an SEM that acquires a secondary electron image (Secondary Electron: SE image) or a reflected electron image (Backscattered Electron: BSE image) of a sample. Further, the SE image and the BSE image are collectively referred to as an SEM image. Also, the image acquired here is a top-down image obtained by irradiating the measurement object with an electron beam from the vertical direction, or a part of a tilt image obtained by irradiating the electron beam from an arbitrary tilted direction. Or include everything.

  The electron optical system 202 includes an electron gun 203 therein and generates an electron beam 204. The electron beam emitted from the electron gun 203 is narrowed down by the condenser lens 205 and then deflected so that the electron beam is focused and irradiated on the semiconductor wafer 201 which is a sample placed on the stage 221. The irradiation position and aperture of the electron beam are controlled by 206 and the objective lens 208.

  Secondary electrons and reflected electrons are emitted from the semiconductor wafer 201 irradiated with the electron beam, and the secondary electrons separated from the orbit of the irradiated electron beam by the ExB deflector 207 are detected by the secondary electron detector 209. .

  On the other hand, the reflected electrons are detected by the reflected electron detectors 210 and 211. The backscattered electron detectors 210 and 211 are installed in different directions. Secondary electrons and backscattered electrons detected by the secondary electron detector 209 and backscattered electron detectors 210 and 211 are converted into digital signals by the A / D converters 212, 213, and 214 and input to the processing / control unit 215. Thus, the image data is stored in the image memory 217, and the CPU 216 performs image processing according to the purpose.

  Although FIG. 2 shows an embodiment in which two detectors of reflected electron images are provided, the detector of reflected electron images can be eliminated, the number can be reduced, or the number can be increased.

  FIG. 3 shows a method of imaging the signal amount of electrons emitted from the semiconductor wafer 307 when the semiconductor wafer 307 is scanned and irradiated with an electron beam. For example, as shown in FIG. 3A, the electron beam is irradiated by scanning in the x and y directions as 301 to 303 or 304 to 306. It is possible to change the scanning direction by changing the deflection direction of the electron beam. The locations on the semiconductor wafer irradiated with the electron beams 301 to 303 scanned in the x direction are denoted by G1 to G3, respectively. Similarly, locations on the semiconductor wafer irradiated with electron beams 304 to 306 scanned in the y direction are denoted by G4 to G6, respectively.

  The signal amounts of electrons emitted in G1 to G6 are the brightness values of the pixels H1 to H6 in the image 309 shown in FIG. 3B, respectively (subscripts 1 to 6 in G and H correspond to each other). Reference numeral 308 denotes a coordinate system indicating the x and y directions on the image (referred to as an Ix-Iy coordinate system).

  The image frame 309 can be obtained by scanning the inside of the visual field with the electron beam in this way. In practice, a high S / N image can be obtained by scanning the field of view several times with an electron beam in the same manner and averaging the obtained image frames. The number of addition frames can be set arbitrarily.

  As a method for obtaining a tilt image obtained by observing the measurement object from an arbitrary tilt angle direction using the apparatus shown in FIG. 2, (1) deflecting the electron beam irradiated from the electron optical system and tilting the irradiation angle of the electron beam. A method of capturing an inclined image (referred to as a beam tilt method; see, for example, Patent Document 4 (Japanese Patent Laid-Open No. 2000-348658)), (2) A method of tilting a stage 121 itself for moving a sample such as a semiconductor wafer (stage tilt) 1, the stage is tilted at a tilt angle 222 with respect to the xyz coordinate system 200), and (3) a system in which the electron optical system itself is mechanically tilted (lens barrel tilt system). And so on).

  A processing / control unit 215 in FIG. 2 is a computer system including a CPU 216 and an image memory 217, and images a region including a circuit pattern to be evaluated based on an imaging recipe as an evaluation pattern. Processing and control such as sending a control signal to the deflection control unit 220 or performing various image processing on a captured image of an arbitrary evaluation pattern on the semiconductor wafer 201 based on a measurement recipe is performed. Details of the imaging recipe and the measurement recipe will be described later.

  The processing / control unit 215 is connected to a processing terminal 218 (including an input / output unit such as a display, a keyboard, and a mouse), and displays a GUI or the like on the GUI (accepts input from the user). Graphic User Interface).

  Reference numeral 221 denotes an XY stage that moves the semiconductor wafer 201 and enables imaging of an arbitrary position of the semiconductor wafer. Changing the imaging position with the XY stage 221 is called stage shift, for example, changing the observation position by deflecting an electron beam with the deflector 206 is called image shift. In general, the stage shift has a wide movable range, but in order to observe a sample at an enlargement magnification of several tens of thousands to several hundred thousand times with an SEM, the positioning accuracy of the imaging position is low. The positioning accuracy is high.

  A recipe generation unit 223 in FIG. 2 is a computer system that includes an imaging recipe creation device 224 and a measurement recipe creation device 225. The recipe generation unit 223 is connected to the processing terminal 226, and includes a GUI on the processing terminal 226 that displays the generated recipe to the user or receives a recipe correction from the user.

  A layout creation / evaluation pattern determination unit 227 in FIG. 2 is a computer system including a layout creation device 228 and an evaluation pattern determination device 229. The layout creation / evaluation pattern determination unit 227 is connected to the processing terminal 230 and includes a GUI that displays the generated layout or the coordinates of the determined evaluation pattern to the user or accepts correction of the layout / evaluation pattern coordinates from the user. .

  The processing / control unit 215, the recipe generation unit 223, and the layout creation / evaluation pattern determination unit 227 described above can transmit and receive information via the network 231. A database server 232 having a storage 233 is connected to the network, and (a) layout data (mask design data (without / with OPC), wafer transfer pattern design data), (b) coordinate values of evaluation pattern groups, ( c) generated imaging / measurement recipe, (d) captured image, (e) evaluation result (pattern measurement value, image feature, pattern outline, etc.), (f) layout / evaluation pattern / imaging / measurement recipe A part or all of the determination rules can be stored and shared by linking with the product type, manufacturing process, date and time, data acquisition device, and the like. The processes performed at 215, 223, 227, and 232 can be divided into a plurality of devices or combined and processed in any combination. The processing terminals 218, 226, and 230 can also be shared.

2.2 Imaging recipe
Details of the imaging recipe and the measurement recipe will be described.
First, an imaging recipe is a file that specifies an imaging sequence and imaging conditions for imaging an imaging area to be evaluated with high accuracy without positional displacement.

  FIG. 4 shows a typical imaging sequence for imaging an evaluation pattern (hereinafter referred to as EP). In FIG. 4B, the position of the EP 416 in the pattern layout 409 on the wafer is indicated by a thick frame, which indicates the EP imaging range (FOV) in the SEM.

  First, in step S401 in FIG. 4A, a semiconductor wafer as a sample is attached on the stage 221 of the SEM apparatus. In step S402, the pattern on the wafer is observed at a low magnification with an optical microscope or the like attached to the SEM, thereby correcting a large origin shift of the wafer and rotation of the wafer (referred to as global alignment).

  In step S403, the stage 221 is moved (stage shifted) so that the vertical incident position of the electron beam becomes a coordinate called a Move coordinate (hereinafter referred to as MP) on the wafer by the control and processing of the processing / control unit 215. By deflecting the electron beam by the deflector 206, the electron beam irradiation position can be moved within a range centered on the MP.

  Depending on the electron optical system, it is also possible to irradiate an electron beam at an angle close to perpendicular to the wafer even at a location away from the MP, and the MP may be defined as the center of the image shift movable range. In FIG. 4B, the image shift movable range when MP is a cross mark 410 and MP is 410 is represented by a dotted frame 411. Incidentally, in this example, the image shift movable range is a square region, but there may be a circular region or the like depending on the electron optical system. Usually, when the electron beam irradiation position is separated from the MP, the electron beam irradiation angle with respect to the wafer is slightly inclined. Therefore, in order to capture the EP from the vertical direction as much as possible, the MP is often set at the center of the EP as shown in FIG.

  In step S <b> 404, the imaging position is moved to an addressing pattern 412 (hereinafter referred to as AP) by image shift, and imaging is performed. Here, the AP will be described. When observing the EP, if the EP is directly observed by the stage shift, there is a risk that the imaging position is greatly displaced due to the positioning accuracy of the stage (the stage is shifted to the MP in the step S403, but actually Is shifted to a position shifted by the stage shift error). Therefore, the image is shifted to an AP to which an imaging position and an imaging position pattern (template) are given in advance for positioning, and imaging is performed. Since the template is registered in the imaging recipe, it is hereinafter referred to as a registered template. The AP is selected from a range (dotted line frame 411) that can be moved by image shift from the EP.

  In addition, since the AP generally has a low-magnification field of view with respect to the EP, there is a low risk that the pattern to be imaged is completely out of the field of view even if there is a slight shift in the imaging position. Therefore, by matching the registered template of the AP registered in advance with the SEM image of the AP actually captured, it is possible to estimate the positional deviation amount of the imaging location in the AP.

  Since the coordinate values of AP and EP are known, the relative displacement amount between AP and EP can be obtained, and the displacement amount at the AP can also be estimated by the above-described matching, so the displacement amount is subtracted from the relative displacement amount. Thus, the relative displacement amount between the AP and the EP in which the displacement amount is canceled can be found. By moving by an image shift with high positioning accuracy by the relative displacement amount, it is possible to image the EP with high coordinate accuracy.

  Therefore, the registered AP is a pattern that exists at a distance that can be moved by image shift from (1) EP (in addition, contamination of contaminants (contamination) and pattern shrinkage due to electron beam irradiation in EP) (2) The AP FOV is larger than the expected error of the stage shift in consideration of the positioning accuracy of the stage, and (3) It is desirable that the pattern shape or lightness pattern in the AP is characteristic and the conditions such as easy matching between the registered template and the SEM image of the actually captured AP are satisfied. Conventionally, an SEM operator has manually performed which location is selected as an AP. However, Patent Document 3 discloses a method for automatically generating an imaging sequence including selection of an AP.

  The template in the AP to be registered in the imaging recipe should be imaged only for registration of the image layout as disclosed in the design layout data, SEM image, or Japanese Patent Laid-Open No. 2002-328015. In order to avoid this, variations such as temporarily registering the design layout data as a template and re-registering the SEM image of the AP obtained at the time of actual imaging as a template are conceivable.

  Next, in step S405, based on the control and processing of the processing / control unit 215, the imaging position is moved to an autofocus pattern 413 (hereinafter referred to as AF) by image shift, and imaging is performed to obtain autofocus adjustment parameters. Then, auto focus adjustment is performed based on the obtained parameters.

  Here, a description of AF will be added. Autofocus is performed to obtain a clear image at the time of imaging. However, if the sample is irradiated with an electron beam for a long time, contamination and pattern shrinkage occur. Therefore, in order to suppress contamination and pattern shrinkage in the EP, a measure is taken in which the coordinates around the EP are once observed as AF, the autofocus parameters are obtained, and then the EP is observed based on the parameters. Therefore, the registered AF is (1) a pattern that exists at a distance that can be moved by image shift from the AP and EP, and the AF FOV does not include the EP FOV. (2) It is easy to apply autofocus. It is desirable to satisfy conditions such as having a pattern shape (easy to detect image blur due to focus shift).

  Next, in step S406, based on the control and processing of the processing / control unit 215, the imaging position is moved to an autostigma pattern 414 (hereinafter referred to as AST) by image shift, and imaging is performed to obtain parameters for autostigma adjustment. Then, auto stigma adjustment is performed based on the obtained parameters. Here, a description of AST will be added. Astigmatism correction is performed so that the cross-sectional shape of the converged electron beam becomes a spot shape in order to acquire an image without distortion at the time of imaging. However, as with AF, if a sample is irradiated with an electron beam for a long time, contamination and pattern shrinkage are performed. Will occur.

  Therefore, a measure is taken in which the coordinates near the EP are once observed as AST, the parameters for correcting astigmatism are obtained, and then the EP is observed based on the parameters. Therefore, the registered AST is (1) a pattern that exists at a distance that can be moved by image shift from the AP and EP, and the FOV of the AST does not include the EP FOV. (2) Astigmatism correction It is desirable to satisfy conditions such as having a pattern shape that is easy to apply (e.g., easy detection of image blur due to astigmatism).

  Next, in step S407, based on the control and processing of the processing / control unit 215, the imaging position is moved to an automatic brightness & contrast pattern 415 (hereinafter referred to as ABCC) by image shift, and imaging is performed. Parameters are obtained, and auto brightness / contrast adjustment is performed based on the obtained parameters.

  Here, a description of ABCC will be added. In order to obtain a clear image having an appropriate brightness value and contrast at the time of imaging, for example, by adjusting a parameter such as a voltage value of a photomultiplier (photomultiplier tube) in the secondary electron detector 209, for example, an image signal Although the highest part and the lowest part are set so as to have a full contrast or a contrast close thereto, as in AF, if a sample is irradiated with an electron beam for a long time, contamination and pattern shrinkage occur.

Therefore, a method is used in which coordinates near the EP are once observed as ABCC, and parameters for brightness / contrast adjustment are obtained, and then the EP is observed based on the parameters.
Therefore, the registered ABCC is a pattern that exists at a distance that can be moved by image shift from (1) AP and EP, and the FOV of ABCC does not include the FOV of EP. (2) Parameters adjusted in ABCC In order to obtain a good brightness / contrast when an EP is imaged using an image, it is desirable that the ABCC satisfy a condition such as a pattern similar to the pattern in the EP.

  Note that, in some cases, imaging of AP, AF, AST, and ABCC in steps S404 to S407 described above may be partially omitted, the order may be changed, or the coordinates of AP, AF, AST, and ABCC may overlap. (For example, auto focus and auto stigma are performed at the same location). Further, in the example of the imaging sequence described above, for example, AF is for EP imaging. However, there is a case where AF for AP is set, and AF for AP is captured before AP imaging to perform autofocus processing.

  Finally, in step S408, the imaging location is moved to EP 416 by image shift and imaging is performed. In the imaging recipe, information such as the coordinates of the imaging pattern (EP, AP, AF, AST, ABCC), the imaging sequence, and imaging conditions are written, and the SEM observes the EP based on the imaging recipe.

2.3 Measurement recipe
Next, the measurement recipe is a file that designates a procedure for performing evaluation such as shape measurement of an imaging target and defect detection from the captured SEM image. As the shape evaluation method, as described in the background art, (1) a method of measuring a dimension such as a line pattern width or a contact hole diameter called a so-called CD value, and (2) a pattern shape disclosed in, for example, Patent Document 1 There are a method for calculating an image feature amount having a high correlation, and (3) a method for detecting a two-dimensional contour line of a pattern disclosed in Patent Document 2, for example.

  Measurement targets include line pattern line width measurement, gap measurement between line patterns, line edge retraction, contact hole diameter measurement, optical proximity correction (OPC) shape measurement, etc. Hereinafter, such measurement variations are referred to as length measurement species.

  FIG. 5 shows an example of the length measurement type. In the figure, reference numerals 501, 504, 508, 512, 515, 519, and 523 denote EP FOVs. 5A shows the measurement of the line width 503 of the line pattern 502, FIG. 5B shows the measurement of the space 507 between the two line patterns 505 to 506, and FIG. 5C shows the line end of the line pattern 509. FIG. 4D shows the measurement of the diameter 514 of the contact hole 513, FIG. 4E shows the measurement of the short axis length 517 / long axis length 518 of the pattern 516, and FIG. ) Is a measurement of the gap 522 between the two line patterns 520-521, and FIG. 5G is an example of the shape measurement of the corner portion 525 of the pattern 524. FIG. 11H is an enlarged view of the corner portion 525, and the gap vector 527 between the design layout data 526 indicated by the dotted line and the pattern outline 524 on the SEM image is measured.

  In order to obtain such a measurement value, it is necessary to perform image processing on the obtained SEM image and detect a boundary position (edge) of the pattern. The image processing algorithm and processing parameters are stored in a measurement recipe, and the SEM evaluates the SEM image based on the measurement recipe.

  In the present embodiment, the terms “imaging recipe” and “measurement recipe” are used as described above. However, the separation of the imaging recipe and the measurement recipe is an example, and the setting items specified in each recipe can be managed in any combination. Therefore, when the imaging recipe and the measurement recipe are not particularly distinguished, the both are simply called a recipe.

2.4 High-speed imaging by image shift
As described above, the stage shift has a characteristic that the imaging position positioning accuracy is low although the movable range is generally wider than the image shift. Therefore, after the stage shift, addressing for detecting a movement error is performed, and the movement to the evaluation pattern is performed by image shift so as to cancel the movement error. Also, image quality adjustment processing such as autofocus is often performed after stage shifting. That is, the stage shift including processing such as addressing requires much processing time for the image shift. Therefore, if as much field of view movement as possible is performed by image shift and the number of stage shifts can be reduced, an improvement in SEM throughput can be expected.

  FIG. 6A shows an imaging sequence for imaging EP 606 (displayed by hatched squares) as in FIG. 4B. After stage shifting to MP602 (displayed with a cross mark), image shift is sequentially performed to AP 604 and AF 605 existing within the image shift movable range 603 (displayed with a dotted frame), addressing and autofocus are performed respectively, and finally EP 606 is imaged. To do.

  In this example, the auto stigma adjustment and the auto brightness / contrast adjustment shown in FIG. 4 are not performed. FIG. 6 shows only the positional relationship between MP, AP, AF, and EP in the xy coordinate system, and the layout (circuit pattern) is not drawn and is not drawn. Assume that there is a pattern as depicted on FIG. 4B 409, and appropriate AP 604 and AF 605 are set based on the pattern shape. In this imaging sequence, one stage shift is performed for one EP.

  Similarly in FIG. 6B, after stage shifting to MP 608, image shift is sequentially performed to AP 611 and AF 612 existing in the image shift movable range 609 (displayed by a dotted frame), and addressing and autofocus are performed, respectively. However, in FIG. 6B, the image shift movable range 609 includes four EPs (EP1 to EP4) indicated by 613 to 616, and the visual field can be moved by image shift in order. . That is, in this imaging sequence, only one stage shift is required for four EPs.

  In addition, the image shift movable range may differ for each imaging pattern (EP, AP, AF, AST, ABCC). That is, as long as the minimum condition is within the movement limit range (for example, 609) of the electron beam irradiation position by the image shift from the MP, the visual field movement / imaging by the image shift is possible, but the image quality and accuracy of various processes using the captured image are possible. In view of the above, it is desirable that the imaging position is close to MP (the electron beam incident angle is close to vertical). In particular, in EP, in order to measure a pattern shape with high accuracy, for example, an allowable value for an incident angle of an electron beam may be stricter than that of AP. Therefore, for example, as shown in FIG. 6B, the image shift movable range for AP is given by a dotted frame 609, but the image shift movable range for EP can be given by a dotted frame 610 narrower than the dotted frame 609. .

  When the image shift movable range with respect to the EP is given by the dotted line frame 610, after the stage shift to the MP608, the two EPs that can be imaged by the image shift are EP2 (614) and EP3 (615), and the remaining EP1 (613) In order to image EP4 (616), it is necessary to perform stage shift again. An evaluation pattern group in which a visual field is moved by image shift without inserting a stage shift in a series of imaging sequences is called an image shift group (IS group). That is, movement between evaluation patterns belonging to different IS groups is accompanied by a stage shift.

  In FIG. 6B, when the image shift movable range for the EP is given by the dotted frame 609, EP1 to EP4 belong to the same IS group, and when the image shift movable range for the EP is given by the dotted frame 610, EP2 and EP3 belong to the same IS group.

  In the following description, it is assumed that there is no difference in the image shift movable range for each imaging pattern. However, as described above, the present invention can be applied even when the image shift movable range is different for each imaging pattern.

3. Change layout
In the present embodiment, an evaluation pattern group determination step (step S102 in FIG. 1) for determining a plurality of circuit patterns (evaluation patterns) to be imaged using an SEM, and an image shift for inputting an image shift movable range in the SEM. Layout determination for determining the layout of the circuit pattern such that the movable range input step (step S104) and the distance between at least two evaluation patterns included in the evaluation pattern group are included in the input image shift movable range. A step (step S106), an imaging recipe generation step for registering in the imaging recipe an imaging sequence for performing visual field movement between at least two or more evaluation patterns existing within the image shift movable range by the image shift, and based on the imaging recipe Imaging the evaluation pattern group It is characterized by.

  That is, in this embodiment, an image shift movable range is input, and a circuit pattern layout is optimized so that many evaluation patterns are included in the image shift movable range. The number of times of visual field movement between evaluation patterns due to image shift during imaging is increased, and high throughput of the SEM is realized.

  Furthermore, one of the layouts targeted by this embodiment is a test pattern created for pattern shape evaluation. Similarly, the plurality of evaluation patterns in the layout that is the subject of the present embodiment is arranged in a lattice pattern on the semiconductor wafer. Of course, the present embodiment is a method applicable to any layout / evaluation pattern, but the test pattern has a higher degree of freedom of layout change than a logic pattern or the like, and the effect of the present invention is particularly expected. it can. In addition, the layout in which the evaluation patterns are arranged in a grid has the advantage that the degree of freedom of layout change is high and the layout change is relatively easy.

  Next, some embodiments regarding the layout determination in the layout determination step will be described.

3.1 Layout change based on distance between EPs
Layout determination in the layout, imaging pattern, imaging sequence optimization (step S106 in FIG. 1) in this embodiment is performed so that the distance between at least two evaluation patterns is within the image shift movable range of the SEM. A distance between the at least two or more evaluation patterns is determined.

  As described above, the higher the throughput, the more evaluation patterns are included in the same IS group. In order to include many evaluation patterns in the same IS group, it is effective to reduce the distance between the evaluation patterns and concentrate the evaluation patterns. FIGS. 7A and 7B both show an imaging sequence for eight EPs (EP1 to EP8).

  In FIG. 7A, eight squares 701 to 708 hatched with diagonal lines indicate the FOVs of EP1 to EP8, respectively. Each FOV includes a pattern as shown in FIGS. 5A to 5G, for example. In this example, the distance between any two adjacent EPs (the range including the FOV of two EPs) is larger than the image shift movable range. That is, for example, the distance 733 in the X direction between EP1 and EP2 is larger than the width 417 in the X direction of the image shift movable range 411 shown in FIG. 4B. Similarly, the distance 734 in the Y direction between EP1 and EP5 is the same. The width 418 in the Y direction of the image shift movable range 411 shown in FIG. For this reason, all movements between arbitrary EPs involve a stage shift, and it is necessary to set MP, AP, and AF for each EP (this example is an example in which AST and ABCC are not set).

  MP, AP, and AF for imaging EP1 to EP8 (701 to 708) are MP1 to MP8 (709 to 716), AP1 to AP8 (717 to 724), and AF1 to AF8 (725 to 732), respectively. The time required to image all eight EPs (EP1 to EP8) can be simply expressed as a bar graph in the upper part of FIG. In the graph, boxes with A to D are drawn, which respectively indicate the time required for A: stage shift, B: addressing, C: autofocus, and D: EP imaging.

  As an example of the imaging sequence of FIG. 7A, first, in order to image EP1 (701), the stage is shifted to MP1 (709), the image is shifted to AP1 (717), addressing is performed, and the image is displayed on AF1 (725). Shift to perform autofocus, and finally image shift to EP1 (701) for imaging. The time required for the main imaging sequence corresponds to 755 in FIG. In order to image the remaining EP2 to EP8 with this as one set, the one set is repeated seven more times. Therefore, the time required to image all of EP1 to EP8 should be expressed by a length eight times the time 755 required for one set as shown in the bar graph labeled “Case (a)” in FIG. Can do.

  FIG. 7B shows an example in which the layout is changed and the distance between EPs is shortened in order to increase the number of movements by image shift. This example is an example of imaging eight EPs (EP1 to EP8) represented by eight squares 735 to 742 hatched with diagonal lines as in FIG. 7A, but between any two adjacent EPs. This is an example in which the distance is smaller than the image shift movable range. That is, for example, the distance 751 in the X direction between EP1 and EP2 is smaller than the width 417 in the X direction of the image shift movable range 411 shown in FIG. 4B. Similarly, the distance 752 in the Y direction between EP1 and EP5 is the same. The width 418 in the Y direction of the image shift movable range 411 shown in FIG. Therefore, for example, EP1 (735), EP2 (736), EP5 (739), and EP6 (740) are included in the dotted line frame 749 indicating the image shift movable range when MP is set to MP1 (743).

  MP1, AP, and AF for imaging EP1, EP2, EP5, and EP6 are MP1 (743), AP1 (745), and AF1 (747), respectively. That is, when MP is set to MP1, the four EPs belong to the same IS group because the field of view can be moved by image shift, and one MP, AP, and AF may be provided for the IS group.

  In the meaning of MP, AP, and AF shared by EPs belonging to the same IS group, they are called shared MP, shared AP, and shared AF. In addition, as a notation method of the figure, the IS group number is represented by a number in a square frame such as 753 and 754 (the IS group number of the EP group surrounded by the image shift movable range 749 is written in the square frame 753. (1: IS group 1 is the IS group number of the EP group surrounded by the image shift movable range 750, and 2: IS group 2 written in the square frame 754).

  Similar to IS group 1, the shared MP, shared AP, and shared AF of IS group 2 are given by 744, 746, and 748, respectively. That is, as shown in the figure, the eight EPs can be divided into two IS groups. The time required to image all the eight EPs (EP1 to EP8) can be simply expressed as a bar graph displaying “case (b)” in the lower part of FIG.

  As an example of the imaging sequence in FIG. 7B, first, EP1 (735), EP2 (736), EP5 (739), and EP6 (740) are stage-shifted to MP1 (743) and AP1 (745). The image is shifted to 1 and then addressed, the image is shifted to AF1 (747) and autofocus is performed, and then the images are sequentially shifted to EP1 (735), EP2 (736), EP5 (739), and EP6 (740). Image each one. The time required for the main imaging sequence corresponds to 756 in FIG. In order to capture the remaining EP3 (737), EP4 (738), EP7 (741), and EP8 (742) as one set, the one set is repeated once more. Therefore, the time required to image all of EP1 to EP8 can be represented by a length twice as long as the time 756 required for one set as shown in the lower graph of FIG.

  7 (a) and 7 (b) show the same number of EP images, but when comparing the upper and lower graphs in FIG. 7 (c), the distance between the EPs is shortened to form an IS group. It can be seen that throughput can be achieved.

  FIG. 8 is a diagram showing a variation of distance reduction between EPs. In FIGS. 8A to 8C, evaluation patterns represented by, for example, EP1 (801) and EP2 (802) are arranged in a grid pattern (EP is indicated by a hatched square). FIGS. 8A to 8C are imaging examples of the same number of EPs, except that the distance between the EPs becomes smaller in the order of (a), (b), and (c) with respect to the layout. In FIG. 8A, the distance between the EPs is large, and only one EP can be included in the image shift movable range 803. As the distance between the EPs is reduced, 2 × 2 = 4 in FIG. 8B and 3 × 3 = 9 EPs in the image shift movable range 803 in FIG. Imaging is possible.

  8B and 8C show only the image shift movable range in one IS group, but the remaining EP is 2 × 2 = 4 as shown in FIG. 8B as described above. In the case of FIG. 8C, the EP can be included in the IS group in units of 3 × 3 = 9. Of course, it is a premise that there is a good addressing or image quality adjustment pattern (not shown) such as AP and AF within the image shift movable range of each IS group.

  In order to achieve much higher throughput, it is necessary to further reduce the distance between the EPs. However, when the distance between the EPs is greatly reduced, the patterns existing between the EPs may interfere with each other. In such a case, the pattern is trimmed in a range centered on the EP (a pattern existing between the EPs is removed) to avoid pattern interference.

  FIGS. 8D and 8E are diagrams illustrating a pattern trimming method using EP1 (801) and EP2 (802) as an example. FIG. 8D is an enlarged view of the area 800 in FIG. 8A, and a layout (circuit pattern) that is omitted and not drawn in FIG. 8A is drawn. As circuit pattern examples, there are five line patterns 804 near EP1 (801) and five line patterns 805 also near EP2. EP1 is imaged by SEM with FOV 801, and the line width 806 of the center line pattern of the five line patterns 804 is measured. The line width 807 is similarly measured for EP2.

  In order to reduce the distance between the EPs, the space between the five line patterns 804 and 805 is reduced as shown in FIGS. 8B and 8C. In addition, the space between the five line patterns 804 and 805 can be reduced. However, when the line patterns 804 and 805 are brought closer to the space 810 or more, the patterns interfere with each other.

  On the other hand, in the case of a test pattern, from the viewpoint that there is no problem in device operation even if the pattern is trimmed, a pattern that is not included in the EP FOVs 801 and 802, which is a pattern evaluation range, is removed (EP FOV801). 802, the pattern is trimmed), and a layout change that brings EP1 and EP2 closer by the space 811 between EP1 and EP2 can be considered.

  However, there is a possibility that the formation of a pattern is affected by a pattern existing around the pattern due to an optical proximity effect (OPE) in the exposure process. Therefore, even if the pattern exists outside the FOV of the EP, it is dangerous to remove it carelessly. Therefore, the range covered by the OPE is input, and the pattern removal range (or the shortened distance between the evaluation patterns) is limited based on the range covered by the OPE.

  In FIG. 8D, the range covered by the OPE with respect to the pattern in the EP1 FOV 801 is indicated by a dotted line frame 808, and the range covered by the OPE with respect to the pattern within the EP2 FOV 802 is indicated by a dotted line frame 809. The result of trimming the pattern at 808 and 809 is shown in FIG. in this case. It is possible to change the layout so that the EP1 and EP2 peripheral patterns are brought closer by the space 812 between the ranges 808 and 809 covered by the OPE. The result of changing the layout from such a viewpoint is shown in FIG. The peripheral patterns EP1 and EP2 are brought closer to the pattern of FIGS. 8D and 8E by a space 812 between the ranges 808 and 809 covered by the OPE.

  FIG. 8F is an example in which the distance between all the EPs is uniformly reduced while maintaining the arrangement on the lattice, but the distance reduction width can be changed depending on the location. Further, the arrangement of EPs does not need to be on the grid both before and after the layout change.

3.2 Layout change based on electron beam scanning direction in EP
The layout, imaging pattern, and imaging sequence optimization (step 106 in FIG. 1) in this embodiment is determined by the scanning direction of the electron beam when imaging using the SEM is within the image shift movable range. At least two or more evaluation patterns are determined so as to be in the same direction. That is, as the scanning direction of the electron beam is the same in the same IS group, the number of times of changing the scanning direction can be reduced, thereby improving the throughput.

  In FIG. 9A, for example, evaluation patterns represented by EP1 to EP8 (901 to 908) are arranged in a grid pattern in a region surrounded by image shift ranges 909 and 910. EP is indicated by a hatched square, and an arrow (“→” or “↑”) indicating an electron beam scanning direction is entered therein.

  An example of EP1 (901) and EP2 (902) in the image shift range 909 will be described with reference to FIGS. 9C to 9F in the electron beam scanning direction. FIG. 9C is an enlarged view of EP1 (901) in FIG. 9A, and a layout (circuit pattern) that is omitted and not drawn in FIG. 9A is drawn. As an example of the circuit pattern, there are three line patterns extending in the Y direction in the EP. When SEM imaging of EP1 is performed with the FOV 901 and the line width 911 of the center line pattern of the three line patterns is measured, the electron beam scanning path is preferably 912 in FIG. The scanning path 912 is a simplified display of the actual scanning path, but indicates that continuous scanning in the X direction is performed discretely in the Y direction (generally called a raster scan). This is because, in order to obtain an accurate line width 911, it is necessary to accurately detect the edge position of the line pattern, and it is necessary to continuously perform scanning in the X direction.

  Such an electron beam scanning direction is called X-direction scanning, and is represented by “→”. Similarly, FIG. 9E is an enlarged view of EP2 (902) in FIG. 9A, and is a measurement of the line width 913 of a line pattern extending in the X direction within the EP. Therefore, the scanning path of the electron beam is given by 914 as shown in FIG. 9 (f), which is called Y-direction scanning and is expressed by “↑”.

  When capturing all the EPs in FIG. 9A, it is necessary to change the scanning direction of the electron beam within the same IS group (EPs having different scanning directions are mixed in the IS group). Therefore, as shown in FIG. 9B, for example, the layout is changed so that the patterns around EP2 (902) and EP5 (905), EP3 (903) and EP8 (908) in FIG. By doing so, it is possible to align the scanning direction in the EP within the IS group.

3.3 Layout change based on the number of EP arrangement matrices
When the evaluation pattern is intended for a layout arranged in a grid pattern, layout determination in the layout / imaging pattern / imaging sequence optimization (step S106 in FIG. 1) in the present invention determines the number of rows and columns of the evaluation pattern. The image shift is determined so as to be close to a multiple of the number of evaluation patterns that can be imaged in the row direction and the column direction, respectively. That is, as an ideal arrangement, if the number of rows and the number of columns of the evaluation pattern is a multiple of the number of evaluation patterns that can be obtained by image shift and the intervals between the lattices are equal, the number of evaluation patterns included in all IS groups is Become the maximum.

  On the other hand, if it is not a multiple, the number of evaluation patterns included in some IS groups decreases, and the number of stage shifts relative to the number of evaluation patterns increases relatively. Therefore, as described above, the layout is determined so as to be as close to a multiple as possible to achieve high throughput.

  FIG. 10 (a) is an example in which 35 (5 rows and 7 columns) EPs are arranged in a grid at the same interval (EPs are indicated by squares hatched with diagonal lines). FIG. 10B shows the result of dividing the EP arrangement of FIG. 10A into IS groups based on the image shift movable range. In FIG. 10B, the image shift movable range is indicated by a dotted frame (for example, 1002), and the IS group number formed by the image shift movable range is numerically entered in the square frame (the place is On the dotted frame of the corresponding image shift movable range, for example, the IS group number formed by the image shift movable range 1002 is written in the square frame 1003 1).

  Therefore, in this example, 35 EPs are divided into 12 IS groups. Among them, the number 1 to 3 and 5 to 7 IS groups belong to 4 EPs, but the number 4, 8 and 9 to 11 IS groups belong to 2 and the number 12 IS groups belong to EP numbers. Is 1. This is because the number of EP rows (5 in this example) and the number of columns (7 in this example) are the number of evaluation patterns that can be imaged in the row and column directions by image shift, respectively (in this example, both in the row and column directions) This is because the number of EPs belonging to the same IS group is reduced for the remaining EPs because it is not a multiple of 2). Even if the number of EPs belonging to a small number, movement to a different IS group is accompanied by a stage shift, so that there is a case where sufficient high throughput cannot be achieved. That is, without considering this problem, there is a risk that the throughput as predicted cannot be obtained even if the distance between the EPs is simply reduced so that the distance between the EPs is within the image shift operation range.

FIG. 10C considers the problem of the number of matrices described above, and the layout is such that the number of rows and columns of EP is as close as possible to the multiple of the number of evaluation patterns that can be imaged in the row and column directions by image shift. This is a modified example. Specifically, the EP group surrounded by the frame 1001 in FIG. 10A is moved to the position surrounded by the frame 1004 in FIG. FIG. 10 (d) shows the result of dividing the EP arrangement of FIG. 10 (c) into IS groups based on the image shift movable range 1002. By this layout change, the number of IS groups becomes nine. The number of EPs belonging to the IS group of ˜8 could be improved to 4 and the number of EPs belonging to the IS group of number 9 could be improved to 3.
3.4 Layout change based on EP sampling method
The layout determination in the layout, imaging pattern, and imaging sequence optimization (step S106 in FIG. 1) in the present embodiment is based on the evaluation pattern sampling method and the number of evaluation patterns after sampling existing within the image shift movable range. It is determined based on the above.

  When the number of evaluation patterns is large, the number of evaluation patterns actually captured using SEM may be reduced by sampling. In addition, various evaluation patterns may be created and sampled depending on the application. If known or previously which evaluation patterns are sampled, it is possible to optimize the layout to evaluate pattern after sampling distributed densely.

  However, even in the same layout, the sampling method (sampling plan) may be different depending on the purpose and the difference in allowable evaluation time. In order to always achieve good throughput against such sampling plan differences, based on the assumed sampling plan variations, the sampling plan variations included in the same IS group for the sampling plan variations The layout is determined so that the number of patterns is not reduced as much as possible.

  FIG. 11 shows an example of evaluation pattern variations. In the same figure, (a) to (d) have four pattern types (patterns A to D) and variations in line width and OPC size for each pattern type. An ID such as A-1-1 is shown immediately below each evaluation pattern, and the ID indicates (pattern type ID)-(line width ID)-(OPC size ID). The larger the line width ID is, the thicker the line width is, and the larger the OPC size ID is, the larger the correction shape by OPC (such as a hammer head or a serif).

  FIG. 12 shows an example in which a plurality of EPs 1211 are arranged at the same interval in a grid pattern, and the ID (A-1-1 etc.) of the evaluation pattern variation described in FIG. Yes. The EP 1211 that is actually imaged (after sampling) is hatched with diagonal lines, and FIG. 12A is an example in which all EPs are imaged (no sampling). Therefore, each image shift movable range (for example, 1201) surrounded by a dotted frame includes four EPs 1211. If there is no problem with the number of matrices described in FIG. 10, the number of IS groups is ¼ of the number of EPs. become.

However, in FIG. 11, all pattern types are imaged, but when every other line width and OPC size are sampled, in the arrangement of EP 1211 in FIG. 12 (b) (EP hatched with hatched EP1212 after sampling). Therefore, a distance between adjacent sampled EPs 1212 (a range including the FOV of two EP1212s) is, for example, a distance 1203, which is larger than an image shift movable range (for example, 1202). Therefore, a plurality of EPs 1212 are not included in the same IS group, and the number of IS groups becomes equal to the number of EPs 1212 after sampling, as shown in FIG.
Consider such an EP arrangement in which the number of EPs included in the same IS group is as large as possible with respect to the sampling related to the line width and the OPC size. FIG. 13 is an example of such an EP arrangement. FIG. 13 is different from the layout shown in FIG. 12 in the variation of the evaluation pattern included and the interval between the EPs, but only the EP arrangement is different.

  FIG. 13A shows an example in which all EPs 1311 are imaged, and the IS group 1301 is ¼ of the total number of EPs 1311 as in FIG. On the other hand, FIG. 13B shows an arrangement of EP1312 when all pattern types are imaged as in FIG. 12B, but every other line width and OPC size are sampled. In this arrangement, the sampled EPs 1312 hatched with diagonal lines do not vary. For example, four EPs 1312 can be included in the same IS group so as to be surrounded by the image shift movable range 1302. That is, the number of IS groups is ¼ of the number of EP1312 after sampling. Incidentally, this arrangement does not depend on the sampling interval related to the line width and the size of the OPC. For example, even if every second or third sampling is performed, the number of IS groups becomes 1/4 of the number of EP1312 after sampling. Therefore, the effect of increasing the throughput can always be expected.

  Such a layout change is possible when there is prior knowledge of sampling plan variations. In the case of this example, the line width and the size of the OPC may be sampled, and the sampling interval may change. However, since there is prior knowledge that the pattern type is not sampled, FIGS. ) Such that four different pattern types (patterns A to D) are densely arranged as shown in FIG. This sampling method is an example, but it is effective to determine the layout based on the evaluation pattern sampling method.

4). Evaluation pattern determination
4.1 Evaluation pattern determination based on the number of EPs included in the IS group
In the present embodiment, an image shift movable range input step (step S104 in FIG. 1) for inputting a movable range in image shift in the SEM, and a plurality of circuit patterns (evaluation patterns) to be imaged using the SEM. An evaluation pattern group determining step (step S106) for determining the distance between at least two or more evaluation patterns to be within the input image shift movable range, and at least two or more existing within the image shift movable range. An imaging recipe generating step of registering an imaging sequence for performing movement between the evaluation patterns by image shift in an imaging recipe, and imaging the evaluation pattern group based on the imaging recipe.

  In order to achieve high throughput, it is necessary to include many evaluation patterns within the image shift movable range. Therefore, in determining the evaluation pattern, it is determined so that many IS groups including many evaluation patterns can be set. As described in the background art, conventionally, the determination of the evaluation pattern is (a) a dangerous spot called a hot spot where a device failure is likely to occur, or (b) a pattern suitable for determining the conditions of the exposure / etching apparatus. (C) Judgment criteria such as whether the pattern is suitable for calibration between the predicted shape by simulation and the actual pattern shape, or (d) the pattern is easy to detect process variations, It is determined in consideration of variations and in-plane distribution. For this reason, the determination of the evaluation pattern is a multi-objective optimization problem that is determined in consideration of not only the criterion for determining whether the evaluation pattern is included in the image shift movable range in the present embodiment but also the conventional criterion. It is characterized by.

  FIG. 14 is a diagram for explaining evaluation pattern (EP) determination variations. The symbols “O” and “X” shown in the figure indicate the positions of EP candidates, and the difference between “O” and “X” indicates the difference in defect type. Examples of the defect type include a type of device failure that is predicted to be highly likely to occur by exposure / development simulation, such as a short circuit between patterns or a narrowing (necking) pattern. Although the distribution of the EP candidates shown in FIGS. 14A to 14C is the same, the selected EPs are different.

  First, the EPs selected in FIG. 14A are five EPs surrounded by dotted line frames 1401 to 1405 indicating the image shift movable range. However, there are no other EPs around each selected EP, and the number of EPs included in each IS group is one. On the other hand, the EPs selected in FIG. 14B are 15 EPs surrounded by dotted line frames 1406 to 1410 indicating the image shift movable range. In this example, since the EP is selected from a place where EP candidates are densely populated, the number of EPs included in each IS group is three.

  That is, as compared with FIG. 14A, the imaging time around the point EP1 is shortened. However, paying attention to the defect type of the selected EP, EPs with “O” symbols (EPs within dotted line frames 1406 to 1408) are placed at the top of the EP candidate distribution (EPs with dotted line frames 1409). , 1410) is biased to the lower part of the distribution of EP candidates, and is not valid when it is desired to sample each defect type from the distribution without a bias in coordinates.

  The selected EPs in FIG. 14C are 10 EPs surrounded by dotted line frames 1411 to 1415 indicating the image shift movable range. In this example, both EPs with “◯” and “x” symbols are selected without bias to the distribution of EP candidates. The number of EPs included in each IS group is 2, which is smaller than 3 in FIG. 14B, but larger than 1 in FIG. Although the evaluation items to be considered and the weight of each item differ depending on the situation, the requirements regarding the defect type, distribution, and throughput of the EP are satisfied by performing EP selection based on various judgment criteria as shown in FIG. be able to.

4.2 Evaluation pattern determination based on presence / absence of addressing / image quality adjustment pattern
In the present embodiment, an image shift movable range input step (step S104 in FIG. 1) for inputting a movable range in image shift in the SEM, and a plurality of circuit patterns (evaluation patterns) to be imaged using the SEM, An evaluation pattern group determination step (step S106) for determining that a pattern capable of addressing or image quality adjustment exists within a range movable by image shift from the evaluation pattern, and image shift from the evaluation pattern before imaging the evaluation pattern An imaging recipe generating step for registering an imaging sequence for performing addressing or image quality adjustment by imaging an addressable or image quality adjustable pattern existing within a movable range by the imaging recipe, and the evaluation pattern group based on the imaging recipe Imaging And features.

  In order to achieve a significantly higher throughput of the SEM without degrading the evaluation performance, one of appropriate addressing and image quality adjustment (autofocus, autostigma, autobrightness / contrast adjustment, etc.) before imaging the evaluation pattern Part or all need to be done. For this reason, the evaluation pattern is selected based on the evaluation performance of the SEM as to whether or not there is a pattern capable of appropriate addressing and image quality adjustment within a range movable by image shift from the evaluation pattern. Further, the present embodiment is characterized by a multi-objective optimization problem that is determined in consideration of not only the above-mentioned determination criteria but also the conventional determination criteria as in the item (7).

  FIG. 15A is a diagram for explaining a determination variation of the evaluation pattern (EP). A hatched pattern 1510 indicates a layout (circuit pattern). Consider sampling only one of the two EP candidates, EP1 (1501) and EP2 (1502). If the influence of the optical proximity effect from the surrounding patterns in each EP candidate and the in-plane distribution of EP coordinates in the wafer / chip / cell are not significant, both images are considered from the viewpoint of evaluation performance. It is effective to select an EP having an appropriate addressing or image quality adjustment pattern within the shift movable range. In the case of FIG. 15A, an appropriate AP1 (in the image shift movable range 1503) is more suitable than an EP2 (1502) in which an appropriate addressing pattern (AP) does not exist in the dotted frame 1505 indicating the image shift movable range. It is reasonable to select EP1 (1501) in which AP1 for EP1 exists.

  Conversely, when there is no appropriate addressing or image quality adjustment pattern around the EP, as an example of layout determination in layout / imaging pattern / imaging sequence optimization (step S106 in FIG. 1) in the present invention, An appropriate addressing or image quality adjustment pattern is added to the layout. In the image shift movable range 1503 of EP1 (1501) in FIG. 15A, there is an appropriate addressing pattern AP1 (1504), but there is an appropriate autostigma adjustment pattern (AST). If not, as shown in FIG. 15B, a new pattern 1506 suitable for the AST is added to the layout, and an area including the pattern 1506 is registered in the imaging recipe as AST1 (AST for EP1 1507). be able to. Such a layout change needs to be performed in consideration of an optical proximity effect to surrounding patterns and an influence on device characteristics.

5. Layout change / Evaluation pattern determination
In this embodiment, an image shift movable range input step (step S101 in FIG. 1) for inputting a movable range by image shift in the SEM, and a plurality of circuit patterns (evaluation) to be imaged using the scanning charged particle microscope Pattern) is determined so that there is a pattern capable of addressing or image quality adjustment within the movable range of the image shift from the evaluation pattern, and / or the distance between at least two or more evaluation patterns is the movable of the input image shift. An evaluation pattern group determining step (step S106) for determining to be within the range, and a distance between at least two or more evaluation patterns included in the evaluation pattern group is within the movable range of the input image shift. Layout determination step (schedule for determining circuit pattern layout) S106) and registering in the imaging recipe an imaging sequence for performing addressing or image quality adjustment by imaging an addressable or image quality adjustable pattern existing within the image shift movable range from the evaluation pattern before imaging the evaluation pattern, and / Or an imaging recipe generating step for registering an imaging sequence for performing movement between at least two or more evaluation patterns existing within an image shift movable range by image shift in an imaging recipe; and the evaluation pattern group based on the imaging recipe It is characterized by imaging.

  That is, various embodiments have been described so far regarding layout design, evaluation pattern determination, imaging condition / imaging sequence determination, but these plural processes are not performed independently, but steps S101 to S101 in FIG. The overall optimization is performed in consideration of various data / specifications / requests written in S105, throughput (imaging sequence), evaluation performance, layout change, and the like. There may be any combination of the plurality of processes related to the layout design, evaluation pattern determination, and imaging sequence determination performed in the optimization.

6). System configuration
An embodiment of the system configuration in the present invention will be described with reference to FIG.
In FIG. 16A, 1601 is a mask pattern design apparatus (including mask pattern layout data (without / with OPC), wafer transfer pattern layout design), 1602 is a mask drawing apparatus, and 1603 is a mask pattern onto the wafer. Exposure / development apparatus, 1604 is a wafer etching apparatus, 1605 and 1607 are SEM apparatuses, 1606 and 1608 are SEM control apparatuses for controlling the SEM apparatus, 1609 is an EDA (Electronic Design Automation) tool server, 1610 is a database server, Reference numeral 1611 denotes a storage for storing a database, 1612 denotes a layout change tool server, 1613 denotes an evaluation pattern determination tool server, 1614 denotes an image processing / imaging / measurement recipe creation calculation device, and 1615 denotes an imaging / measurement recipe server. These can send and receive information via the network 1600.

  A storage 1611 is attached to the database server 1610. (a) Layout data (mask design data (without / with OPC), wafer transfer pattern design data), (b) coordinate values of evaluation pattern group, (c) generation Captured imaging / measurement recipe, (d) captured image, (e) evaluation result (pattern length measurement value, image feature, pattern outline, etc.), (f) layout / evaluation pattern / imaging / measurement recipe determination rule It is possible to store or share a part or all of the data by linking with a product type, a manufacturing process, a date and time, a data acquisition device, or the like.

  In the figure, two SEM devices 1605 and 1607 are connected to the network as an example. However, in this embodiment, an imaging / measurement recipe is stored in the database server 1610 or the imaging in any of a plurality of SEM devices. It can be shared by the measurement recipe server 1615, and the plurality of SEM devices can be operated by one imaging / measurement recipe creation.

  In addition, by sharing a database among a plurality of SEM devices, past optimization and processing, that is, layout design, evaluation pattern determination, imaging sequence determination, or success and failure cause accumulation during actual SEM imaging / measurement can be quickly performed. By referring to this, it is possible to assist in the above-described optimization and processing.

  FIG. 16B shows an example in which 1606, 1608, 1609, 1610, and 1612 to 1615 in FIG. 16A are integrated into one device 1616. As in this example, it is possible to divide or integrate an arbitrary function into an arbitrary plurality of apparatuses.

7). GUI
FIG. 17 shows an example of GUI for setting or displaying input / optimization / output information in the present embodiment. Various information drawn in a window 1701 in FIG. 17 can be displayed on a display or the like in one screen or divided. Further, “**” in FIG. 17 indicates an arbitrary numerical value (or character string) or numerical value range input or output to the system.

  A list of layouts / evaluation patterns (EP) / imaging sequences, etc., input in the window 1702 or optimization candidates can be displayed. In this example, there are two layout / EP candidates with different layouts arranged in the vertical direction and two candidates with different EP selections are displayed in the horizontal report (1703 to 1706) (not shown in this example) It is also possible to display a plurality of imaging sequence candidates).

  The layout / EP positions of the candidates 1703 to 1706 are displayed in 1707 to 1710, and the evaluation performance (throughput, addressing accuracy, etc.) expected when the candidates are selected are displayed in 1711 to 1714, respectively. In layout / EP position display windows 1707 to 1710, layouts (circuit patterns) are hatched patterns, EP is indicated by a thick frame, image shift movable range (in each IS group) is indicated by a dotted line, The number is entered in a circle (the location is near the corresponding EP), and the IS group number is entered in the square (on the dotted frame of the corresponding image shift movable range). However, the image shift movable range of the IS group that has only one EP is omitted and not displayed (1707 and 1708). The user can determine (select) a layout / EP / imaging sequence from a plurality of candidates based on these pieces of information (in this example, the candidate 1705 is checked and selected).

  18A to 18G show display variations of the display windows 1707 to 1710 at the layout / EP position.

  FIG. 18A shows a pattern for addressing and image quality adjustment in addition to the information displayed in the windows 1707 to 1710. Here, the positions of AP 1801 and AF 1802 are displayed.

  Further, as described with reference to FIG. 15B, a pattern can be added. The addition can be performed by automatic layout optimization or manually. 18B and 18D are examples of manual pattern addition. After selecting the shape and size of the pattern to be added on the GUI screen shown in FIG. 18D, the selection pattern in this example is a crosshair. Mark 1805) and an additional position of the selection pattern is designated with a mouse or the like as shown in FIG. 18B (1803 in this example). As shown in FIG. 18C, the added selection pattern can be used as an autostigma pattern 1804, for example.

  FIGS. 18E to 18G show examples of layout changes for shortening the distance between the EPs described with reference to FIG. 8 and pattern arrangement replacement as shown in FIGS. 12A to 13A. The addition can be performed by automatic layout optimization or manually.

  First, after assigning a value to the maximum pattern distance designation box 1720 of the same segment in FIG. 17 and pressing a layout segmentation button 1719, the layout is divided into several segmentation areas indicated by dotted frames in FIG. Can be divided. In this example, the area is divided into a total of nine dotted line frames such as dotted line frames 1806 and 1807 (1806, 1807 and the like are called segmentation areas). This is one of the functions that support the layout change, and the dotted frame area can be used as a unit for moving or exchanging the layout. In other words, changing each pattern has a high degree of freedom and requires labor, so here the layout is changed in a segmentation area divided at a location where the distance between patterns is far (the threshold of the distance between the patterns). The value can be given in box 1720).

  FIG. 18 (e) to FIG. 18 (f) show an example of replacement of the segmentation area. In this example, the positions of the segmentation areas 1806 and 1807 are exchanged using a mouse or the like.

  FIG. 18E to FIG. 18G are examples of shortening the distance between the segmentation regions. In this example, the three segmentation areas existing in the third line of the 3 × 3 segmentation area are selected and moved upward (the spaces in the second and third lines of the segmentation area are 1808). From 1809 to 1809).

  In window 1701 of FIG. 17, as input information for calculating optimization candidates such as layout / EP / imaging sequence, inspection / measurement requests (required throughput, required addressing accuracy, etc.), imaging conditions (image shift movable range, EP / MP allowable distance, EP FOV, AP FOV, etc.) and various requirements / specifications of allowable layout change specifications (optical proximity effect range, layout change allowable items, etc.) from windows 1715, 1716, 1717, respectively. Can be entered. Further, by pressing a layout input button 1718, layout data to be optimized can be read. Regarding the change-permitted items related to the layout in the window 1717, it is possible to specify items that allow change in the pattern arrangement, size, shape, etc. (the pattern arrangement is checked in the figure) It is also possible to specify a range in which the change is allowed by a numerical value (not shown).

  By pressing an EP candidate calculation button 1721, a layout candidate calculation button 1723, and an imaging sequence candidate calculation button 1725, an EP candidate, a layout candidate, and an imaging sequence candidate are calculated based on the above-described input information, respectively. The final candidate selected by the user from the calculated candidates or determined by the user based on each candidate is output as a recipe or layout design data by pressing the determination buttons 1722, 1724, and 1726, respectively.

  In addition, the calculation of the above-described EP candidate, layout candidate, and imaging sequence candidate can be performed independently or overall optimization can be performed. When total optimization is performed, items to be included in optimization are selected in 1728 (in this example, EP and layout are selected as optimization items), and then a total optimization button 1727 is pressed.

  Information of the imaging sequence including EP and IS group can be displayed like windows 1729 and 1730. That is, the window 1729 is a list of EPs in the selected candidate (candidate 1705 in this example), and for each EP, an ID (number written in a circle), coordinates / FOV, electron beam scanning direction, and IS group to which it belongs. ID (number written in a square frame) is displayed. A window 1730 is a list of IS groups in the EP group displayed in the window 1729. For each IS group, an ID (number written in a square), MP, addressing, or coordinates / FOV of an image quality adjustment pattern is displayed. .

  The present embodiment provides a method for realizing a significant increase in throughput of the scanning charged particle microscope without lowering the evaluation performance by the above means. As a result, the entire device development including the pattern verification time using the scanning charged particle microscope can be shortened.

200 ... x-yz coordinate system (coordinate system of electron optical system) 201 ... semiconductor wafer 202 ... electron optical system 203 ... electron gun 204 ... electron beam (primary electron) 205 .... Condenser lens 206 ... Deflector 207 ... ExB deflector 208 ... Objective lens 209 ... Secondary electron detector 210, 211 ... Reflected electron detector 212, 213, 214 ... A / D converter 215 ... Processing / control unit 216 ... CPU 217 ... Image memory 218, 226, 230 ... Processing terminal 219 ... Stage controller 220 ... Deflection control unit 221 ... Stage 222 ... Stage tilt angle 223 ... Recipe generation unit 224 ... Imaging recipe creation device 225 ... Measurement recipe raw Formation device 227 ... Layout creation / evaluation pattern determination unit 228 ... Layout creation device 229 ... Evaluation pattern determination device 232 ... Database server 233 ... Database (storage) 307 ... Sample surface 308 .. Ix-Iy coordinate system (image coordinate system) 309... Image 409... Layout data 410 .. MP 412... AP 413 .. AF 414... AST 415. ABCC 416 ... EP 604, 611 ... AP 605, 612 ... AF 606, 613-616 ... EP 701-708, 735-742 ... EP 709-716, 743, 744 ... MP 717-724, 745, 746 ... AP 725 32, 747, 748 ... AF 801, 802 ... EP 804, 805 ... Line pattern 901-908 ... EP 1504 ... AP 1506 ... Additional pattern 1507 ... AST 1600 ... Network 1601 ... Mask pattern design device 1602 ... Mask drawing device 1603 ... Exposure / development device 1604 ... Etching device 1605, 1607 ... SEM device 1606, 1608 ... SEM control device 1609 .. EDA tool server 1610... Database server 1611... Database 1612... Layout change tool server 1613... Evaluation pattern determination tool server 1614. 1615: Imaging / measurement recipe server 1616: EDA tool, database management, layout change tool, evaluation pattern determination tool, image processing, imaging / measurement recipe creation, imaging / measurement recipe management, SEM control integrated server & calculation Apparatus 1701 ... GUI window 1702 ... Layout / EP / imaging sequence candidate list display window 1703 to 1706 ... Layout / EP / imaging sequence candidate 1707 to 1710 ... Layout / EP / imaging sequence candidate display window 1711 1714 ... Expected performance display window 1715 ... Inspection / measurement request input window 1716 ... Imaging condition input window 1717 ... Allowable layout change specification input window 1718 ... Iout input button 1719 ... Layout segmentation button 1720 ... Maximum pattern distance input box of the same segment 1721 ... EP candidate calculation button 1722 ... EP decision (recipe output) button 1723 ... Layout candidate calculation Button 1724 ... Layout determination (design data output) button 1725 ... Imaging sequence candidate calculation button 1726 ... Imaging sequence determination (recipe output) 1727 ... Overall optimization button 1728 ... Included in overall optimization Item selection check box 1729 ... EP list window 1730 ... IS group list window 1801 ... AP 1802 ... AF 1803 ... Additional pattern 1804 ... AST.

Claims (12)

A method of acquiring captured images of a plurality of circuit patterns formed on a semiconductor wafer using a scanning charged particle microscope and evaluating the shape of the circuit pattern from the captured images,
An evaluation pattern group determination step for determining a plurality of circuit patterns to be imaged as an evaluation pattern using the scanning charged particle microscope;
An image shift movable range input step for inputting a movable range in image shift in the scanning charged particle microscope;
The distance between at least two of the plurality of circuit patterns to be imaged as the evaluation pattern determined in the evaluation pattern group determination step is within the image shift movable range input in the image shift movable range input step. A layout determining step for determining a layout of a plurality of circuit patterns to be imaged as the determined evaluation pattern so as to be included in
The at least two or more evaluations whose layout is determined such that the distance among the plurality of circuit patterns to be imaged as the evaluation pattern whose layout has been determined in the layout determining step is included in the image shift movable range. An imaging recipe generation step of registering an imaging sequence for performing visual field movement between patterns by image shift in an imaging recipe;
Imaging a plurality of circuit patterns to be imaged as the evaluation pattern determined in the evaluation pattern group determination step based on the imaging sequence registered in the imaging recipe in the imaging recipe generation step;
And a step of evaluating the shape of a plurality of circuit patterns to be imaged as the evaluation pattern using an image obtained by imaging in the imaging step. 2. The circuit pattern evaluation method according to claim 1, wherein the plurality of circuit patterns to be imaged as evaluation patterns determined in the evaluation pattern group determination step are test patterns created for pattern shape evaluation. 2. The circuit pattern evaluation method according to claim 1, wherein a plurality of circuit patterns to be imaged as evaluation patterns determined in the evaluation pattern group determination step are arranged in a grid pattern on the semiconductor wafer. In determining the layout in the layout determining step, the distance between the at least two evaluation patterns is set such that the distance between the at least two evaluation patterns is within an image shift movable range of the scanning charged particle microscope. 2. The circuit pattern evaluation method according to claim 1, wherein the circuit pattern evaluation method is determined. The layout determination in the layout determination step is performed such that the scanning direction of the charged particles when imaging using the scanning charged particle microscope is the same direction with respect to at least two or more evaluation patterns existing within the image shift movable range. 2. The circuit pattern evaluation method according to claim 1, wherein the circuit pattern evaluation method is determined as follows. A plurality of evaluation patterns arranged as the evaluation pattern are arranged so that the number of rows and the number of columns of the evaluation patterns arranged in a grid are close to multiples of the number of evaluation patterns that can be imaged in the row direction and the column direction by the image shift, 4. The circuit pattern evaluation method according to claim 3, wherein a layout of the circuit pattern is determined. The layout of a plurality of circuit patterns to be imaged as the evaluation pattern is determined based on a sampling method of the evaluation pattern so that the number of evaluation patterns after sampling existing within the image shift movable range is increased. Item 2. The circuit pattern evaluation method according to Item 1. A method of acquiring captured images of a plurality of circuit patterns formed on a semiconductor wafer using a scanning charged particle microscope and evaluating the shape of the circuit pattern from the captured images,
An image shift movable range input step for inputting a movable range in image shift in the scanning charged particle microscope;
A plurality of circuit patterns to be imaged as evaluation patterns using the scanning charged particle microscope are arranged such that a distance between at least two circuit patterns of the plurality of circuit patterns is within the input image shift movable range. An evaluation pattern group determination step to be determined,
An imaging recipe generating step for registering an imaging sequence for performing movement between the at least two circuit patterns existing in the image shift movable range input in the image shift movable range input step by image shift in an imaging recipe;
An evaluation pattern imaging step of imaging the evaluation pattern determined in the evaluation pattern group determination step based on the imaging recipe registered in the imaging recipe generation step;
And a step of evaluating the shape of the evaluation pattern using an image of the evaluation pattern obtained by imaging in the evaluation pattern imaging step. A method of acquiring captured images of a plurality of circuit patterns formed on a semiconductor wafer using a scanning charged particle microscope and evaluating the shape of the circuit pattern from the captured images,
An image shift movable range input step for inputting a movable range in image shift in the scanning charged particle microscope;
An evaluation pattern for determining a plurality of circuit patterns to be imaged as an evaluation pattern using the scanning charged particle microscope so that a pattern capable of addressing or image quality adjustment exists within a range movable by image shift from the evaluation pattern A group determination step;
Imaging in which addressing or image quality adjustment is performed by imaging an addressable or image quality adjustable pattern existing within a range movable by image shift from the evaluation pattern before imaging the evaluation pattern determined in the evaluation pattern group determining step An imaging recipe generation step for registering a sequence in an imaging recipe;
An evaluation pattern group imaging step of imaging the evaluation pattern group based on the imaging recipe, and a step of evaluating the shape of the evaluation pattern using an image of the evaluation pattern obtained by imaging in the evaluation pattern group imaging step A circuit pattern evaluation method comprising: A method of acquiring captured images of a plurality of circuit patterns formed on a semiconductor wafer using a scanning charged particle microscope and evaluating the shape of the circuit pattern from the captured images,
An image shift movable range input step for inputting a movable range in image shift in the scanning charged particle microscope;
An evaluation pattern group determination step for determining a plurality of circuit patterns to be imaged as an evaluation pattern using the scanning charged particle microscope;
A layout determining step for determining a layout of a circuit pattern such that a pattern capable of addressing or image quality adjustment exists within a range movable by image shift from the evaluation pattern determined in the evaluation pattern group determining step;
Imaging in which addressing or image quality adjustment is performed by imaging an addressable or image quality adjustable pattern existing within a movable range by image shift from the evaluation pattern before imaging the evaluation pattern determined in the evaluation pattern group determining step. An imaging recipe generation step for registering a sequence in an imaging recipe;
An evaluation pattern group imaging step of imaging the evaluation pattern determined in the evaluation pattern group determination step based on the imaging sequence registered in the imaging recipe in the imaging recipe generation step;
And a step of evaluating a shape of the evaluation pattern using an image of the evaluation pattern obtained by imaging in the evaluation pattern group imaging step. A method of acquiring captured images of a plurality of circuit patterns formed on a semiconductor wafer using a scanning charged particle microscope and evaluating the shape of the circuit pattern from the captured images,
An image shift movable range input step for inputting a movable range in image shift in the scanning charged particle microscope;
A plurality of circuit patterns to be imaged as an evaluation pattern using the scanning charged particle microscope is determined so that a pattern capable of addressing or image quality adjustment exists within the movable range of the image shift from the evaluation pattern, and / or at least An evaluation pattern group determination step for determining a distance between two or more evaluation patterns so as to be within the movable range of the image shift input in the image shift movable range input step;
A layout determining step for determining a layout of the circuit pattern so that a distance between at least two evaluation patterns included in the evaluation pattern determined in the evaluation pattern group determining step is within the input image shift movable range; ,
An imaging sequence for performing addressing or image quality adjustment by imaging an addressable or image quality adjustable pattern existing within an image shift movable range from the evaluation pattern before imaging the evaluation pattern determined in the evaluation pattern group determining step. An imaging recipe generating step for registering an imaging sequence for registering an imaging recipe and / or moving between at least two or more evaluation patterns existing within an image shift movable range by an image shift in the imaging recipe;
An evaluation pattern group imaging step of imaging the evaluation pattern group based on the imaging recipe;
And a step of evaluating a shape of the evaluation pattern using an image of the evaluation pattern obtained by imaging in the evaluation pattern group imaging step. An apparatus for acquiring captured images of a plurality of circuit patterns formed on a semiconductor wafer using a scanning charged particle microscope and evaluating the shape of the circuit pattern from the captured images,
Evaluation pattern group determining means for determining a plurality of circuit patterns to be imaged as an evaluation pattern using the scanning charged particle microscope;
Image shift movable range input means for inputting a movable range in image shift in the scanning charged particle microscope;
Layout determining means for determining a layout of a circuit pattern so that a distance between at least two evaluation patterns included in the evaluation pattern group determined by the evaluation pattern group determining means is within the input image shift movable range; ,
An imaging recipe generating means for registering in the imaging recipe an imaging sequence in which movement between at least two or more evaluation patterns existing within the image shift movable range by the layout determining means is performed by image shift;
A circuit pattern evaluation system comprising: an imaging unit that images the evaluation pattern group based on the imaging recipe and acquires an SEM image.

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