JP2012113604A - Computer system, method, and i/o switch - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce congestion in an I/O interface and interconnect in a server by distributing data transmission between the server and an I/O device to multiple I/O interfaces which the server has.SOLUTION: When CPUs 102A-D in a server 100 issue a load instruction or a store instruction for I/O devices 120A-D, a computer system adds a different offset value for each CPU to a destination address of a packet or a transaction occurring due to the load instruction or the store instruction. Also, an I/O switch having a switch exchange part subtracts a different offset value for each I/O interface from a destination address or a destination ID of a packet or a transaction issued by the server.

Description

  The present invention relates to a server or computer system having a plurality of processors and a plurality of I / O interfaces, and more particularly to a technique for distributing a data transfer load of an I / O interface.

  In recent years, a configuration in which an I / O switch is interposed between a server and an I / O (Input / Output) device has been used in order to increase the flexibility of the configuration of a computer system. As a result, the connection between the server and the I / O device can be switched only by changing the setting of the I / O switch, and the configuration can be changed quickly and flexibly. As a result, it is possible to obtain convenience in the operation of the computer system, such as increasing I / O against fluctuations in the load of jobs operating on the computer system, and realizing switching when a failure occurs in an I / O device.

  Normally, a server is an I / O hub (IOH, Input / Output Hub) that provides an I / O interface for connecting a processor (CPU, Central Processing Unit), a main storage (memory), and an I / O device. ).

  Technologies related to the I / O interface are disclosed in Non-Patent Documents 1, 2, 3, and Patent Document 1 including various industry standard technologies. For example, PCI-SIG (Peripheral Component Interconnect-Special Interest Group). An interface defined by an industry standard such as PCI Express is used (Non-Patent Document 1). In recent years, commercially available apparatuses provide one or a plurality of PCI Express IOHs.

  A typical example of the I / O device is, for example, a network interface card (NIC, Network Interface Card) for connecting a server to Ethernet (registered trademark). An I / O device such as a NIC is connected to a server via the I / O interface described above. Currently, 1 Gbit Ethernet and 10 Gbit Ethernet NICs are used as standard, and many servers are connected to the server by PCI Express.

JP 2010-79816 A

PCI Express Base Specification Revision 2.0, PCI-SIG, December 20, 2006. Multi-Root I / O Virtualization and Sharing Specification Revision 1.0, PCI-SIG, May 12, 2008. Multi-Root I / O Virtualization and Sharing Specification Revision 1.0. Single Root I / O Virtualization and Sharing Specification Revision 1.0, PCI-SIG, September 11, 2007.

  Considering the above-mentioned PCI Express, which is now widely used in servers, PCI Express adopts a tree-like topology, so that even if an I / O switch is introduced, the configuration is restricted. Yes, the invention for this has been made.

  For example, sharing a single I / O device from a plurality of servers is impossible with the PCI Express standard disclosed in Non-Patent Document 1. An I / O device connected by PCI Express corresponds to a leaf (terminal) in a tree topology, but only a single route (server) can be reached from the leaf by following the tree. There is a restriction that a plurality of servers (root) cannot be reached from a single I / O device (leaf).

  On the other hand, there is a PCI Express extended standard called MR-IOV (Multi Root I / O Virtualization and Sharing) shown in Non-Patent Document 2, for example. In order to realize this MR-IOV, a new mechanism is required for system software such as an I / O device, an I / O switch, and an operating system operating on a server. As a result, a single device is shared by a plurality of servers, but it is necessary to newly develop a device (MR-IOV device) corresponding to MR-IOV.

  Therefore, in the technology disclosed in Patent Document 1, a device (SR-IOV device) compliant with the PCI Express extended standard called SR-IOV (Single Root I / O Virtualization and Sharing) shown in Non-Patent Document 3 is used. Discloses a technique shared by a plurality of servers. SR-IOV is a technology for sharing a single I / O device among multiple virtual machines running on a single server. Compared with MR-IOV devices, SR-IOV devices are more widely distributed in the market. is doing.

  However, SR-IOV devices cannot be shared from a plurality of servers like MR-IOV devices. Thus, in Patent Document 1, a single SR-IOV device is shared from a plurality of servers by having a mechanism such as address translation in the I / O switch.

  In addition, the use of SMP (Symmetric Multiple Processor) servers has become widespread in order to increase the processing capacity of computer systems. The SMP server has a plurality of CPUs, and a plurality of CPUs share a single main storage space, and operates system software such as an individual operating system on each CPU. Instead, a single operating system is operated and used across a plurality of CPUs constituting the SMP server.

  Since the SMP server has multiple CPUs to improve processing performance, it is necessary to increase the I / O performance to match that, and there are multiple IOHs between the multiple CPUs and multiple IOHs. The bus to be connected is often point-to-point connection by high-speed serial transmission.

  In other words, in an SMP server that has a plurality of CPUs and is provided with a plurality of I / O interfaces from a plurality of IOHs, it is provided from an IOH that is directly connected to the CPU when viewed from a certain CPU. I / O interfaces are classified into two types: I / O interfaces (close I / O interfaces) and I / O interfaces (distant I / O interfaces) provided by IOH connected via other CPUs It will be possible.

  On the SMP server, an operating system, other system software, and a plurality of threads constituting application software operate in a distributed manner on a plurality of CPUs. That is, the near I / O interface and the far I / O interface are different for each thread. Such an event occurs near and far between the memory and the CPU even in NUMA (Non Uniform Memory Architecture), which is one of the methods for configuring the SMP server, but the I / O interface has similar characteristics. Has occurred.

  In the invention of Patent Document 1, a single I / O device is shared by a plurality of servers. However, since each individual server is a root of a tree-like topology, there is only one path between the server and the I / O device. In other words, even if a server has multiple I / O interfaces, only one I / O interface is used when transferring data to or from a specific I / O device. .

  However, since the above-mentioned SMP server has a plurality of I / O interfaces, the operation described in Patent Document 1 cannot make use of the I / O performance of the SMP server. Specifically, when an SMP server and an I / O device are connected via an I / O switch, the SMP server is connected to the I / O switch via a plurality of I / O interfaces. Since the path is determined based on the tree-like topology described above, there is a problem that the same I / O interface is always used when accessing a specific I / O device.

  As a result, congestion of a specific I / O interface is likely to occur. Further, since transfer is performed from a specific I / O interface inside the SMP server, there is a problem that congestion of internal interconnects connecting between CPUs becomes significant. In particular, since the internal interconnect is responsible for various processes such as cache coherence as well as I / O, congestion of the internal interconnect is a factor that significantly reduces the performance of the entire SMP server.

  Therefore, while using an I / O interface with a tree-like topology such as PCI Express, it is an issue to distribute the I / O load to each I / O interface in an SMP server having a plurality of I / O interfaces. It has become.

  An object of the present invention is to provide a computer system, a method, and an I / O switch for solving the problems existing in the I / O interface technology such as the server described above.

  In order to achieve the above object, according to the present invention, a computer system includes a plurality of I / O interfaces, a server having a plurality of processing units sharing a storage space, and an I / O device used by the server. And an I / O interface of the server and an I / O switch for connecting the I / O device. When the processing unit issues a command for the I / O device, the processing unit has an offset value that is different for each processing unit. Is added to the destination data of the data generated based on the command, and the I / O switch has a configuration having an offset subtracting unit that subtracts the corresponding offset value from the destination data issued by the server Provide a system.

  In order to achieve the above object, in the present invention, an I / O interface used by a server having a plurality of processing units sharing a storage space with a plurality of I / O interfaces is connected to the I / O interface. A data transfer method for a computer system having an I / O switch, wherein when a command is issued to an I / O device, a processing unit adds an offset value that differs for each processing unit to destination data of data generated based on the command The I / O switch provides a data transfer method for transferring the data to the I / O device after removing the corresponding offset value from the destination data issued by the server.

  Furthermore, in order to achieve the above object, the present invention is an I / O switch for connecting a plurality of I / O interfaces of a server having a plurality of processing units sharing a storage space and an I / O device. An offset subtracting unit that subtracts a different offset value for each I / O interface from destination data issued by the server, a switch exchanging unit connected to the output of the offset subtracting unit, an offset subtracting unit, and a switch exchanging unit An I / O switch having an I / O controller for controlling the I / O controller is provided.

  That is, in order to solve the above problems, in a preferred aspect of the present invention, a server having a plurality of I / O interfaces and a plurality of CPUs, and at least one or more I / O devices used by the server, A computer system comprising an I / O switch for connecting between a server and an I / O device, wherein a plurality of CPUs of the server share a single main storage space, and a plurality of servers and I / O switches are provided. The server has an address conversion unit, and the address conversion unit has an offset different for each CPU when the CPU issues a load instruction or a store instruction to the I / O device. The value is added to the destination address of a packet or transaction generated due to an instruction such as a load instruction or a store instruction. The I / O switch includes an offset subtracting unit that subtracts an offset value corresponding to each I / O interface from a destination address of a packet or transaction issued by a server, or a destination identifier (Identifier: ID), and an offset. A computer system having an offset information storage unit for storing a value is provided.

  The present invention reduces the congestion of I / O interfaces and internal interconnects used inside the server in a computer system using a server having a plurality of I / O interfaces, and improves the performance of the entire system. Have

It is a block diagram which shows an example of the whole structure of the computer system which concerns on a 1st Example. It is a block diagram which shows an example of a structure of the offset subtraction part in the I / O switch of the computer system concerning a 1st Example. It is a block diagram which shows an example of a structure of the destination port search part in the I / O switch of the computer system concerning a 1st Example. It is a conceptual diagram which shows an example of a structure of the offset information which the I / O controller of the computer system concerning a 1st Example has. It is a conceptual diagram which shows an example of a structure of the destination port table which the I / O controller of the computer system concerning a 1st Example has. It is a memory map which shows an example of the main storage space of the computer system which concerns on a 1st Example. It is a memory map which shows an example of ECAM space among the main memory spaces of the computer system which concerns on a 1st Example. It is a flowchart which shows an example of the initialization sequence of the computer system which concerns on a 1st Example. It is a conceptual diagram which shows an example of the bus tree of the computer system which concerns on a 1st Example. It is a conceptual diagram which shows the path | route by which data is transferred on the computer system which concerns on a 1st Example. It is a conceptual diagram which shows the path | route by which data is transferred on the computer system which concerns on a 1st Example. It is a conceptual diagram which shows the path | route by which data is transferred on the computer system which concerns on a 1st Example. It is a conceptual diagram which shows the path | route by which data is transferred on the computer system which concerns on a 1st Example. It is a memory map which shows an example of the whole main storage space of the computer system concerning a 1st Example. It is a conceptual diagram which shows the path | route by which data is transferred on the computer system which concerns on a 1st Example.

  Hereinafter, an embodiment of the present invention will be described with reference to the accompanying drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiment, and the repetitive description of the same symbols will be omitted. In this specification, a server is a computer that includes a processor (CPU, Central Processing Unit) that is a processing unit, a memory that is a storage unit, and an I / O hub (IOH) that is an interface unit. is there. Further, in this specification, functional blocks that are elements of each system may be expressed as “mechanism”, “means”, or “part”. For example, the address conversion function is referred to as “address conversion mechanism”, “address conversion unit”, or “address conversion means”. As this address translation mechanism, the computer system in this specification includes a first address translation mechanism used by the operating system and a second address translation mechanism used by the hypervisor and other system software. Furthermore, a packet or transaction issued by the CPU or I / O device is called data, and a destination address of the packet or transaction is called a destination address or destination ID.

  FIG. 1 is a diagram illustrating an overall configuration of a computer system according to the first embodiment. The computer system shown in FIG. 1 includes an SMP server 100, an I / O switch 110, I / O devices 120A to 120D, and a management server 130. The I / O switch 110 may be formed in the form of an I / O drawer or may be configured in the form of an integrated circuit (IC).

  Various configurations are conceivable in the SMP server 100. In this embodiment, an SMP server to which an inter-blade SMP, which is a technology for realizing an SMP server in blade servers widely used in recent years, is applied is illustrated. The inter-blade SMP includes blades 101A to 101D of blade servers (numbers # 0 to # 3 are assigned to the respective blades. For example, blade 101A is blade # 0). Is a technique for using a plurality of blades 101A-D as a single SMP server 100. As the internal interconnect 109, for example, QuickPath Interconnect of Hyper and HyperTransport are used.

  All of the blades 101A to 101D have the same internal configuration. Each of the blades 101A to 101D includes CPUs 102A to 102D, memories 103A to 103D, internal interconnects 104A to 104D, and IOH 105A to 105D.

  In general, the same type of interconnect technology is often used for the internal interconnects 104A to 104D that are responsible for connection within the blade and the internal interconnect 109 that connects the blades. Each of the CPUs 102A to 102D of the blades 101A to 101D is composed of at least one CPU. A part of each of the memories 103A to 103D is used as a main storage memory of the SMP server 100.

  The IOHs 105A to 105D provide I / O interfaces 115A to 115D (PCI Express interfaces). Instructions such as load instructions and store instructions issued by the CPUs 102A to 102D to transfer data to and from the I / O devices 120A to 120D are converted into PCI Express packets by the IOH 105A to D, and the I / O interface Output to 115A-D. In addition, the IOHs 105A to 105D directly access the memories 103A to 103D (Direct Memory) in order to realize writing to and reading from the memory indicated by the PCI Express packet transmitted from the I / O devices 120A to 120D. Access: DMA). Since the SMP server 100 shares a single main memory, the memory that can be accessed by the IOHs 105A to 105D is not limited to the memory on the blade in which the IOH exists. For example, the IOH 105A can access the memory 103C existing on another blade. In this case, access is made via the internal interconnects 104A, 109, and 104C.

  In the SMP server 100, a single operating system, hypervisor, or other system software can be operated across the blades 101A to 101D, and an application can be operated thereon. For example, in this embodiment, it is assumed that a single hypervisor is operated on the SMP server 100 and a virtual machine (Virtual Machine: VM) is operated thereon. For this purpose, the hypervisor binary and the VM image binary are arranged on the memories 103A to 103D.

  The I / O switch 110 provides a switch for flexibly switching the connection relationship between the SMP server 100 and the I / O devices 120A to 120D. The I / O switch 110 includes a switch exchanging unit 111 configured with a PCI Express switch, an I / O controller 112, offset subtracting units 113A to 113D, and destination port searching units 114A to 114D.

  The switch exchange unit 111 is a switch having a plurality of ports (hereinafter referred to as server-side ports) for connecting servers. In addition, it has at least one port for connecting devices (hereinafter referred to as a device-side port).

  As such a switch, for example, there is a switch compliant with the MR-IOV standard of Non-Patent Document 2. Further, a switch having a plurality of server-side ports can be used in this embodiment without conforming to the MR-IOV standard.

  The I / O controller 112 is a controller for controlling the components in the I / O switch 110, that is, the switch exchange unit 111, the offset subtraction units 113A to 113D, and the destination port search units 114A to D. Specifically, the I / O controller 112 may use a microcontroller in which a CPU and a memory are integrated on a single chip. On the I / O controller 112, offset information 150 and a destination port table 151, which will be described in detail later, are stored.

  The management server 130 is a server for managing the entire computer system shown in FIG. The management server 130 can be realized using a blade server or the like as hardware. If the load required for management is light, it can be realized using a microcontroller.

  The management server 130 is connected to the SMP server 100 and the I / O controller 112 via the management network 131. The management server communicates with the hypervisor operating on the SMP server 100 and the I / O controller 112 and can specify various parameters to be described later to the hypervisor or the I / O controller 112. Further, the management server 130 can acquire the number of blades, the memory capacity, and the like as the configuration information of the SMP server 100.

  FIG. 14 shows the main storage space of the SMP server 100 of this embodiment. The memories 103A to 103D included in the blades 101A to 101D are mapped to a single main storage space shown in FIG. In addition, a memory mapped input / output (MMIO) space used when the CPUs 102A to 102D access the I / O devices 120A to 120D are also arranged.

  In PCI Express, the I / O devices 120A to 120A-D can throw a packet for requesting memory writing or memory reading to an arbitrary address in the main storage space shown in FIG.

  In PCI Express, an MMR (Memory Mapped Register) included in the I / O devices 120A to 120D can be mapped in the main storage space, which is referred to as an MMIO space. The CPUs 102A to 102D can read from the MMR or write to the MMR by issuing a load instruction or a store instruction to the MMIO space.

  In the PCI Express bus topology, an I / O device is a combination of three numbers (Bus # (bus number, 8 bits), Dev # (device number, 5 bits), Fun # (function number, 3 bits)) (16 bits in total). And specify the route. Note that Dev # and Fun # are used for designation when the I / O device has a plurality of functions. In the present embodiment, the operation in the I / O device has no effect, and thus description of Dev # and Fun # is omitted.

  FIG. 9 shows a bus tree when the present invention is not applied to the computer system shown in FIG. 1 and the computer system is used only in conformity with the PCI Express standard. In FIG. 9, four lines from the SMP server 100 are connected to the I / O switch 110, which corresponds to the I / O interfaces 115A to 115D as physical components shown in FIG. Similarly, the lines connecting the I / O switches to the I / O devices correspond to the I / O interfaces 121A to 121D in FIG. 1, respectively, and the I / O devices correspond to the I / O devices 120A to 120D in FIG. ing.

  In PCI Express, Bus # is assigned in the depth priority direction from the apex (root) of the bus tree. The Bus # is assigned to the I / O interface as shown in FIG. On the way, a plurality of bridges (tree relay points) are connected to a single Bus #, but at the end (leaf), one I / O device per bridge cannot be connected. Therefore, the Bus # of the I / O interface to which the I / O device is directly connected can be regarded as an identifier for identifying the I / O device. For example, the Bus # of the I / O interface 121A is Bus # 3, but Bus # 3 is used as an identifier indicating the I / O device 120A.

  In PCI Express, when a packet is issued from the CPU 102A to D to the I / O devices 120A to 120D, the MMIO that specifies the address of the MMIO space to which the MMR of the I / O devices 120A to 120D is mapped as a destination There are two types of configuration requests: a request, an identifier indicating the I / O devices 120A to 120D, and a configuration request that designates a combination of addresses in a 4 KB space (Configuration space) in the device as a destination.

  The Configuration request expresses the destination by a combination of Bus # (further combining Dev # and Fun # if the I / O device has a plurality of functions) and Configuration space address (12 bits). Routing from the CPUs 102A to 102D to the I / O devices 120A to 120D is performed using Bus # as a clue. Then, after reaching the I / O devices 120A to 120D, a configuration space address in the case of a device having only a single function, Dev #, Fun #, and configuration in the case of a device having a plurality of functions. The location to be finally reached in the I / O device is determined by the combination of the space addresses.

  The routing using the Bus # as a clue can be easily performed in a tree-like topology in which the Bus # is given with depth priority as shown in FIG. In the SMP server 100, looking at the destination Bus #, Bus # 1 to 63 are the I / O interface 115A, Bus # 65 to 127 are the I / O interface 115B, and Bus # 129 to 191 are the I / O interface. In 115C, Bus # 193-255 outputs to the I / O interface 115D. In this way, the range of Bus # under the bridge is recorded in each bridge, and routing can be performed using this as a clue. By performing routing in the I / O switch 110 in the same manner, it is possible to reach the I / O devices 120A to 120D.

  Note that the Configuration request and the MMIO request are both issued as a load instruction to the main storage space or a store instruction when viewed from the CPUs 102A to 102D. Issuing a load instruction or a store instruction to the MMIO space in the main memory space generates an MMIO request. In addition, a special space (PCI Express Enhanced Configuration Mechanism space, ECAM space) for generating a Configuration request is prepared in the main memory space, and a load instruction or a store instruction issuance for this space is issued. Generate a request. It should be noted that none of them is distinguished from access to the memory in the main storage space when viewed from the CPUs 102A to 102D.

  The MMIO request designates a destination by an address of the main storage space (in recent servers, there are many 64 bits. In conventional servers, there are also 32 bits). Similar to the routing using Bus # as a clue, each bridge shown in FIG. 9 records the range of addresses under the bridge, and performs routing using this as a clue. Since the MMIO request and the configuration request are similar as routing operations, the configuration request is an example in the following description.

  FIG. 10 shows a path for accessing the I / O device 120B (Bus # 4) from the SMP server 100 in the bus tree of FIG. This path is unchanged regardless of where the load instruction or the store instruction addressed to Bus # 4 is executed in the CPUs 102A to 102D (blades 101A to D, blade numbers # 0 to # 3).

  The route shown in FIG. 10 is a logical layer called a bus tree. However, when expressed by a physical route, the route is as shown in FIG. In FIG. 11, the path from the CPU 102A (blade 101A, # 0) to the I / O device 102B (Bus # 4) is indicated by a broken line, and the CPU 102C (blade 101C, # 2) to the I / O device 102B (Bus # 4). The route to be accessed is indicated by a solid line. In the bus tree shown in FIG. 9, all pass the same route. However, in the physical route shown in FIG. 10, the CPU to which the load instruction or the store instruction is issued is different, so the route is different until halfway.

  In FIG. 11, the CPU 102C accesses the I / O device 102B via the internal interconnect 109. In addition to access to I / O devices, the internal interconnect 109 has a lot of traffic such as cache coherence, which affects the overall performance of the SMP server 100. Therefore, avoid traffic on the internal interconnect 109 as much as possible. Is desirable. Further, if not only the CPU 102C but also the CPUs 102B and 102D try to access the I / O device 120B at the same time, the internal interconnect 109 is further congested.

  In this computer system, since there is also an I / O interface 115C between the blade 101C and the I / O switch 110, access from the CPU 102C to the I / O device 102B is via the internal interconnect 109 via the I / O interface 115C. Can be avoided.

  However, in order to perform access via the I / O interface 115C in the bus topology shown in FIG. 9, the I / O device 102B must be Bus # 129-191. For example, the I / O device 102B needs to be placed on the Bus # 132. In this case, all accesses from the CPUs 102A to 102D to the I / O device 102B are concentrated on the I / O interface 115C, and even if the congestion caused by the access from the CPU 102C is eliminated, the CPUs 102A, B, D Congestion due to access from the network will occur.

  Therefore, in this embodiment, the offset calculation units 113A to 113D, the destination port search units 114A to 114D, the I / O controller 112, the offset information 150, the destination port table 151, the management server 130, and the SMP server 100 in FIG. A hypervisor loaded on the memories 103A to 103D or other system software, and an EPT (Extended Page Table) or other address translation mechanism are used to provide means for solving the above congestion. .

  Here, a desired offset is set in each of the blades 101A, # 0 to 101D, and # 03 by a normal method using an address translation mechanism such as EPT. This address translation mechanism is configured so that when the CPUs of the blades 101A, # 0 to 101D, and # 03 issue instructions such as a load instruction or a store instruction for the I / O device, the blades 101A, # 0 to 101D, and # 03 A different offset value for each CPU is added to destination data such as a packet generated due to a load instruction or a store instruction, or a destination address of a transaction. This offset value is stored in advance as offset information 150 in the I / O controller 112.

  FIG. 2 is a block diagram showing a detailed configuration of the offset subtraction units 113A to 113D included in the I / O switch 110 of FIG. The offset subtracting units 113A to 113D are components provided in the server side port, and one offset subtracting unit is provided for one server side port. In this embodiment, since the server side ports are the four ports of the I / O interfaces 115A to 115D, there are four offset subtracting units 113A to 113D according to the number.

  The offset subtraction units 113A to 113D are connected to the SMP server 100 via I / O interfaces 115A to 115D, and are connected to the switch exchange unit 111 via I / O interfaces 116A to 116D. Further, offset information 150 included in the I / O controller is received as a signal 118. This offset information 150 is used to rewrite the destination of the packet addressed to the I / O device from the SMP server input from the I / O interfaces 115A to 115D and output it from the I / O interfaces 116A to 116D. .

  The offset subtracting units 113A to 113D pass the I / O device originating server-addressed packet 220 input from the I / O interfaces 116A to 116D and output from the I / O interfaces 115A to 115D.

  On the other hand, the server-originated I / O device-addressed packet 230 input from the I / O interfaces 115A to 115D is the destination of the packet (destination address in the case of a MMIO request packet, destination in the case of a Configuration request packet). (Bus #) is rewritten and output from the I / O interfaces 116A to 116D.

  The server-originated I / O device-addressed packet 230 is analyzed by the packet analysis unit 211. The data payload and the like of the packet 230 are sent as data 233 to the packet allocation unit 212 as they are. The destination information 232 is input to the subtracter 214. Note that the destination information 232 may be a 64-bit address (MMIO request) and an 8-bit Bus # (Configuration request) as described above. The packet analysis unit 211 analyzes whether the packet 230 is an MMIO request or a configuration request, and provides the request type information 231 to the selector 213.

  The selector 213 receives the offset information 150 by the signal 118, and selects an entry corresponding to the server side port number of the I / O interface 115A-D that the offset subtracting unit 113A-D is in charge of from the offset information 150. . Further, based on the request type information 231, if it is an MMIO request, an MMIO address offset is selected and input to the subtracter 234 as an offset value 236.

  The subtractor 234 inputs the result obtained by subtracting the offset value 236 from the destination information 232 as the destination information 234 to the packet assembling unit 212. Expressing the calculation as an expression, (destination information 234) = (destination information 232) − (offset value 236).

  The packet assembling unit 212 assembles the packet 235 from the destination information 234 and the data 233 and outputs the packet 235 to the I / O interfaces 116A to 116D.

  FIG. 3 is a block diagram illustrating a detailed configuration of the destination port search units 114A to 114D included in the I / O switch 110 of FIG. The destination port search units 114A to 114D are components provided in the device side port, and one destination port search unit is provided for one device side port. In this embodiment, since the device side ports are the four ports of the I / O interfaces 121A to 121D, there are four destination port search units 114A to 114D corresponding to the number of the device side ports.

  The destination port searching units 114A to 114D pass through the server-originated I / O device-addressed packet 320 input from the I / O interfaces 117A to 117D and output from the I / O interfaces 121A to 121D.

  On the other hand, the packet addressed to the I / O device originating server input from the I / O interfaces 121A to 121D is based on the destination of the packet (the packet addressed to the I / O device originating server is addressed to the address of the main storage space). The PCI Express switch determines the I / O interfaces 116A to 116D to output the packet. In other words, the server (blade) as the destination is determined based on the destination address of the packet addressed to the I / O device originating server.

  The packet analysis unit 311 extracts the destination address 332 of the packet 330 addressed to the I / O device originating server. The destination address 332 is input to the table reference unit 312. On the other hand, the packet 330 is directly input to the packet assembling unit 313 as a packet 331 without modification.

  The table reference unit 312 refers to the destination port table 151 using the signal 119 and searches for an entry corresponding to the destination address 332 input to the table reference unit 312. That is, an entry satisfying the condition (base address) ≦ (destination address 332) <(base address + size) is searched, and the destination port number corresponding to the entry is output as the destination port number 333.

  When the destination address 332 does not correspond to any entry, the default destination port number is output as the destination port number 333. In this embodiment, the default destination port number is 0 (corresponding to the I / O interface 116A, that is, the blade 110A (# 0)).

  The packet assembling unit 313 assigns the destination port number 333 to the packet 331 and outputs the packet 334 from the interfaces 113A to 113D.

  As the destination port number, when a PCI Express switch compatible with MR-IOV is used, VH (Virtual Hierarchy) defined in the MR-IOV standard can be used. A mechanism for assigning a destination port number (VH) to a packet is also defined in the MR-IOV standard as TLP Prefix.

  In the present embodiment, a PCI Express switch that employs a unique routing mechanism may be used instead of the MR-IOV standard. In that case, the destination port number is given by the protocol determined by the switch.

  FIG. 4 shows an example of the configuration of the offset information 150 of this embodiment stored in the I / O controller 112. As shown in the figure, the offset information 150 includes an MMIO address offset table 410 and an ID offset table 420. Each table includes the same number of entries as the number of server-side ports. That is, in this embodiment, since there are 4 ports, the offset information 150 is composed of a total of 8 entries including 4 entries for MMIO address offset and 4 entries for ID offset.

  The MMIO address offset is a 64-bit entry, and the server-originated I / O device addressed packet (MMIO request) input to the I / O switch 110 from the port (I / O interface 115A to 115D) corresponding to the server-side port number. Indicates the offset amount to be subtracted from the destination address. As hardware, it is implemented as a register or flip-flop.

  The ID offset is an 8-bit entry, and, similar to the MMIO address offset, the packet addressed to the server-originated I / O device input to the I / O switch 110 from the port (I / O interface 115A to 115D) corresponding to the server-side port number The offset amount to be subtracted from the destination Bus # of the (Configuration request) is indicated. The mounting form uses registers and flip-flops in the same manner as the MMIO address offset.

  FIG. 5 shows the configuration of the destination port table 151 of FIG. The destination port table is composed of at least one entry, with (valid bit, base address, size, destination port number) as one entry. Only entries with a valid bit set (valid bit = 1) are used.

  In the case of the SMP server 100 having a 64-bit main storage space, the base address is a 64-bit base address. The size is a size indicating an area starting from the base address. In general, since the size of the area on the main storage space is often expressed by a power of 2, in this embodiment, the size is a 6-bit numerical value representing N of 2 ^ N bytes. In this case, since a size of 2 ^ 0 bytes to 2 ^ 63 bytes can be expressed, the size is sufficient for use in a 64-bit main storage space.

  The destination port number specifies the port number of the server side port to which the packet addressed to the I / O device originating server for the area indicated by the base address and size is to be output. In this embodiment, since the server side port is 4 ports, the destination port number can be expressed by 2 bits.

  FIG. 12 shows an example of a bus tree-like route in the computer system of FIG. In FIG. 12, the path for accessing the I / O device 102B (Bus # 4) from the CPU 102A (blade 101A, # 0) from the CPU 102A (blade 101A, # 0) is indicated by a broken line, and the path for accessing the CPU 102C (blade 101C, # 2) is indicated by the solid line. Show.

  The route from blade # 0 to Bus # 4 indicated by the broken line is the same as in FIG. However, the path from blade # 2 to Bus # 4 indicated by the solid line is different from that in FIG. 11 and passes through Bus # 129 (I / O interface 115C). FIG. 13 shows the paths shown in FIG. 12 on physical components. Looking at this, it is possible to avoid congestion of the internal interface 109 and Bus # 1 (I / O interface 115A), which was a problem in FIG.

  The operation performed in FIG. 12 will be described using the operation of the components of this embodiment shown in FIG. When the CPU 102A of blade # 0 issues a configuration request addressed to Bus # 4, it issues a load instruction and a store instruction for the address of the main storage space corresponding to Bus # 4. Similarly, the CPU 102C of blade # 2 issues a load instruction and a store instruction.

  At this time, in this embodiment, the load instruction and the store instruction of the CPU 102A are issued as they are, but the load instruction and the store instruction of the CPU 102C are configured for the Bus # 4 by performing address conversion using the EPT in the memory 103C. The request is converted into a configuration request for Bus # 132 (Bus # 4 + offset # 128).

  As a result, the packet issued due to the load instruction and the store instruction of the CPU 102C is routed toward the Bus # 132, so that it is routed along the path passing through the Bus # 129. That is, the SMP server 110 and the I / O switch 110 are routed via the I / O interface 115C (Bus # 129), and the internal interconnect 109 and the I / O interface 115A (Bus # 1) are congested. Can be avoided.

  Next, inside the I / O switch 110, the destination of the packet (addressed to Bus # 132 when it reaches the I / O switch 110) that should originally go to Bus # 4 is set to Bus # 4. return. For this purpose, the offset subtraction unit 113C performs processing to return to Bus # 4 (Bus # 132−offset # 128). After that, by routing the packet to the Bus # 2 bridge having Bus # 3 to Bus # 6 under control, the packet can reach the I / O device 120B of Bus # 4. In this way, routing as shown in FIGS. 12 and 13 can be realized.

  In the case of an MMIO request, the same processing can be realized by replacing Bus # with an address. In addition, all of the above-mentioned packets are requests for a server-originated I / O device, but it is necessary to return a reply packet to the request from the I / O device to the server by tracing back the request path. .

  In PCI Express, RID (Requester ID) for identifying the component that issued the request is assigned to each requesting packet. In the bus tree as shown in FIG. 10 and FIG. 12, the request is issued at the top of the bus tree, but as hardware operation, packets are generated by the IOHs 105A to 105D shown in FIG. That is, the RID should have the IOHs 105A-D that generated the requesting packet. When receiving the request, the I / O devices 120A to 120D generate a reply packet for responding to the request, and the reply packet destination uses the RID of the request packet. Therefore, the reply packet for the request can be returned from the I / O device to the server by tracing the request path in reverse.

  In order to perform the operations shown in FIGS. 12 and 13, when the CPUs 102A to 102D issue a load instruction or a store instruction, the destination address of the packet is sent if it is an MMIO request, and the destination bus of the packet is sent if it is a Configuration request It is necessary to shift # by a predetermined offset. The operation for this will be described.

  As described above, the SMP server 100 has the single main storage space shown in FIG. The MMIO request and the Configuration request are generated when the CPUs 102A to 102D issue a load instruction or a store instruction to a space designated as “MMIO space, etc.” in the main storage space of FIG.

  FIG. 6 is a memory map showing the above-mentioned “MMIO space, etc.” in more detail. Among them, there are a blade # 0 MMIO space, a blade # 1 MMIO space, a blade # 2 MMIO space, a blade # 3 MMIO space, and a PCI Express Enhanced Configuration Mechanism space (ECAM space).

  The MMIO request is routed in the form of a bus tree in the same manner as the configuration request. The bridge shown in FIG. 9 knows the Bus # under its control, and the configuration request is routed based on the Bus #. In addition, the bridge also knows the MMIO address under its control, and the configuration request is routed based on the MMIO address.

  Here, the blade # 0 MMIO space in FIG. 6 is an MMIO address space under the IOH 105A, and an MMIO request packet addressed to the blade # 0 MMIO space is output from the I / O interface 115A. Similarly, blade # 1 MMIO space is IOH 105B and I / O interface 115B, blade # 2 MMIO space is IOH 105C and I / O interface 115C, and blade # 3 MMIO space is IOH 105D and I / O interface 115D. , Respectively.

  Here, all the MMRs included in the I / O devices 120A to 120D are mapped to the blade # 0 MMIO space. Therefore, all MMIO requests issued by the CPUs 102A to 102D are addressed to the address of the blade # 0 MMIO space.

  However, as it is, all MMIO requests are concentrated on the I / O interface 115A. Therefore, by performing address conversion, the I / O interfaces 115A to 115D used for the CPUs 102A to 102D are distributed.

  When the CPU 102A issues a load instruction to the blade # 0 MMIO space or a store instruction, an offset +0 is added in the address conversion (that is, the address is not converted). Thereby, the MMIO request derived from the CPU 102A is output from the I / O interface 115A.

  When the CPU 102B issues a load instruction to the blade # 0 MMIO space or a store instruction, an offset + α is added in the address conversion (the offset + α is shown in FIG. 6). Thus, the MMIO request derived from the CPU 102B is for the blade # 1 MMIO space and is output from the I / O interface 115B. However, since the original destination is the address before the offset is added, after the arrival at the I / O switch 110, the offset calculation unit 113B subtracts the offset (subtracts α from the destination address).

  When the CPU 102C issues a load instruction to the blade # 0 MMIO space or a store instruction, an offset + β is added in the address conversion (the offset + β is shown in FIG. 6). As a result, the MMIO request derived from the CPU 102C is for the blade # 2 MMIO space and is output from the I / O interface 115C. However, since the original destination is the address before the offset is added, after the arrival at the I / O switch 110, the offset calculation unit 113C subtracts the offset (subtracts β from the destination address).

  When the CPU 102D issues a load instruction to the blade # 0 MMIO space or a store instruction, an offset + γ is added in the address conversion (the offset + γ is shown in FIG. 6). As a result, the MMIO request derived from the CPU 102D is for the blade # 3 MMIO space and is output from the I / O interface 115D. However, since the original destination is the address before the offset is added, the offset is reduced by the offset calculation unit 113D after arrival at the I / O switch 110 (β is subtracted from the destination address).

  In the operation as described above, load distribution can be realized by distributing MMIO requests to the I / O interfaces 115A to 115D according to the CPUs 102A to 102D that issued the requests. It was.

  Next, the case of a configuration request will be described. As described above, the destination of the Configuration request is specified by a combination of Bus #, Dev #, Fun #, and Configuration space address.

  A packet is generated when the CPU 102A to 102D issues a load instruction or a store instruction to the ECAM space of FIG. The ECAM space is a combination of areas corresponding to the configuration space (12-bit space = 4 KB space) by the number of Bus #, Dev #, and Fun #. That is, a space of 256 MB in total of 4 KB × Fun # number (8 / Dev #) × Dev # number (32 / Bus #) × Bus # number (256 / system).

  FIG. 7 shows details of the ECAM space. For example, the configuration request for the Bus # 3 I / O device 120A is a 1 MB space from the start address y to + 10000H to + 1FFFFH (4 KB × Fun # number × Dev # number = 1 MB). The address in the 1 MB space differs depending on which resource (register) the I / O device 120A has to access.

  The CPU 102C converts the configuration request for the Bus # 4 from the CPU 102C into a Configuration request for the Bus # 132 (Bus # 4 + offset # 128). The CPU 102C loads the Bus # 0 to Bus # 63 space, This can be realized by performing address conversion by adding an offset + 8000000H to the address when a store instruction is issued.

  As described above, using the I / O interfaces 115A to 115D in a distributed manner by adding an offset to the destination address of the MMIO request or adding an offset to the destination Bus # of the Configuration request is performed on the CPUs 102A to D. This shows that it can be realized by address conversion when issuing a load instruction or a store instruction.

  As means for realizing the address translation, various mechanisms included in the CPUs 102A to 102D or system software such as a hypervisor can be used. In general, a CPU provides a PT (Page Table) for performing address conversion from a virtual address to a physical address. This is generally used by an operating system. In order to realize the conversion, it is necessary to modify the operating system.

  As another means, there is a case where an SPT (Shadow Page Table) is prepared in the hypervisor, and the above address conversion is realized in the hypervisor layer without changing the operating system. In addition to the PT, some CPUs may implement the above address conversion using an EPT (Extended Page Table) prepared as a second-stage address conversion mechanism.

  Next, a packet for making a request addressed to the I / O device originating server will be described. All of the above has been described with respect to a request from a server to an I / O device and a reply to the request. In the following, a request directed to an I / O device originating server and a reply to the request will be described.

  The I / O devices 120A to 120D can read and write the entire main storage space of the SMP server 100 shown in FIG. However, if the destination port search units 114A to 114D shown in the present embodiment are not used, the I / O devices 120A to 120D have the blade # 0 memory (memory 103A), the blade # 1 memory (memory 103B), and the blade # 2 memory. (Memory 103C) and blade # 3 memory (memory 103D) are all accessed via IOH 105A and I / O interface 115A. This causes congestion of the I / O interface 115A and the internal interconnect 109.

  Therefore, in this embodiment, the destination port table search units 114A to 114D refer to the server side port number from the destination address of the packet of the request issued by the I / O day bus 120A to D, and output the I / O interface 115A. Select ~ D. As a result, if the destination port table 151 is set appropriately, the requests issued by the I / O devices 120A to 120D can be transmitted to the destination memories 103A to 103D through the shortest path as shown in FIG. Thus, it is possible to reduce the latency of memory access and to reduce congestion of the I / O interfaces 115A to 115D and the internal interconnect 190.

  Next, FIG. 8 shows an initialization sequence necessary for obtaining a desired effect using the computer system based on the present embodiment shown in FIG.

  In step S801, the management server 130 is activated in the computer system shown in FIG. The management server 130 manages the overall operation of the computer system of FIG.

  In step S <b> 802, the management server 130 issues an activation command to the I / O switch 110 via the management network 131 to activate the I / O switch 110. When the I / O switch 110 is activated, the internal switching unit 111 is initially set by the internal I / O controller 112. The I / O controller 112 is initialized so that the offset subtraction unit 113A does not subtract the offset value (all entries in the MMIO address offset table 410 and the ID offset table 420 are set to 0). Similarly, the I / O controller 112 invalidates all valid bits (0) in order to invalidate all entries in the destination port table 151.

  In step S <b> 803, the management server 130 issues a configuration information collection command to the I / O switch 110 via the management network 131 and receives configuration information from the I / O switch 110. When the I / O switch 110 receives the configuration information collection command, the I / O controller 112 accesses the I / O devices 120A to 120D connected to the I / O switch 110 via the I / O interface 180. , Detecting the presence of an I / O device. Then, the fact that the I / O devices 120A to 120D are connected is transmitted to the management server 130 as configuration information.

  In step S804, the management server 130 presents the configuration information obtained from the I / O switch 110 to the administrator of the computer system, and receives an instruction regarding the connection between the I / O device and the SMP server 100. In the following description, it is assumed that the setting for connecting all the I / O devices 120A to 120D to the SMP server 100 is made by the administrator.

  In step S805, an offset value to be set in the offset information 150 (MMIO address offset table 410 and ID offset table 420) is calculated. In the computer system shown in this embodiment, the offset values are as shown in FIGS.

  That is, the server side port number 0 entry (corresponding to the I / O interface 115A and used by the offset subtraction unit 113A) of the MMIO address offset table 410 is 0, and the server side port number 1 entry (corresponding to the I / O interface 115B) Offset subtracting unit 113B) is α, server side port number 2 entry (corresponding to I / O interface 115B, offset subtracting unit 113B is used) β, server side port number 3 entry (corresponding to I / O interface 115C) The offset subtraction unit 113C uses γ.

  Further, the server side port number 0 entry (corresponding to the I / O interface 115A and used by the offset subtracting unit 113A) of the ID offset table 420 is 0, and the server side port number 1 entry (corresponding to the I / O interface 115B is offset. 64 is used for the server side port number 2 (corresponding to the I / O interface 115B, and used by the offset subtractor 113B) is 128, and 3 entries for the server side port number (corresponding to the I / O interface 115C). , Used by the offset subtracting unit 113C) is 256. These offset values need to be set corresponding to the EPTs of the blades # 0 to # 3, as will be described later.

  In step S806, the base address, size, and destination port number to be set in the destination port table 151 are generated. In the computer system shown in this embodiment, the base address and size are as shown in FIG.

  That is, entry 0 in the destination port table 151 has a base address of D0, a size of R0, a destination port number of 0 (a number indicating the I / O interface 115A), and a valid bit of valid (1). For entry No. 1, the base address is D1, the size is R1, the destination port number is 1 (number indicating the I / O interface 115B), and the valid bit is valid (1). For entry No. 2, the base address is D2, the size is R2, the destination port number is 2 (number indicating the I / O interface 115C), and the valid bit is valid (1). For entry 3, the base address is D3, the size is R3, the destination port number is 3 (number indicating the I / O interface 115D), and the valid bit is valid (1). Since entries 4-5 are not used, they are left invalidated in step S802.

  In step S807, the offset value calculated in step S805 is written into the offset information 150 on the I / O controller 112 via the management network 131. Also, the destination port table generated in step S806 is written into the destination port table 151 on the I / O controller 112 via the management network 131.

  In step S808, the management server 130 issues an instruction to activate the SMP server 100 via the management network 131. In this embodiment, since the SMP server 100 is composed of blades 101A to 101D, the blades 101A to 101D are activated.

  In the process of starting up the blades 101A-D, various system software (BIOS, EFI, hypervisor, operating system, etc.) set the IOHs 105A-D and the bus-tree bridge shown in FIG. A bus tree as shown in FIG. 9 is formed.

  In step S809, the management server 130 notifies the hypervisor operating on the SMP server 100 of the offset value used for address conversion via the management network 131. In the case of this embodiment, assuming that EPT is used as the address conversion means, the following offset value is notified to the hypervisor, and the hypervisor sets a value corresponding to the EPT of each blade 101A-D. Enable EPT. As described above, the EPT of each blade 101A-D is used as usual.

  The EPT used by the hypervisor thread operating on the CPU 102A adds the offset value +0 (or does not add the offset value) when an access to the blade # 0 MMIO space (addresses x to (x + s)) in FIG. 6 occurs. EPT is set as follows. Further, when an access to the space for Bus # 0 to 63 in FIG. 7 occurs, the EPT is set so that the offset value +0 is added (or the offset value is not added).

  The EPT used by the thread of the hypervisor operating on the CPU 102B is set so that the offset value + α is added when an access to the blade # 0 MMIO space (address x to (x + s)) in FIG. 6 occurs. Further, when an access to the space for Bus # 0 to 63 in FIG. 7 occurs, the EPT is set so that the offset value + 4000000H is added.

  The EPT used by the thread of the hypervisor operating on the CPU 102C is set so that the offset value + β is added when an access to the blade # 0 MMIO space (address x to (x + s)) in FIG. 6 occurs. Further, when an access to the space for Bus # 0 to 63 in FIG. 7 occurs, the EPT is set so that the offset value + 8000000H is added.

  The EPT used by the hypervisor thread operating on the CPU 102D is set to add an offset value + γ when an access to the blade # 0 MMIO space (addresses x to (x + s)) in FIG. 6 occurs. Further, when an access to the space for Bus # 0 to 63 in FIG. 7 occurs, the EPT is set so that the offset value + C000000H is added.

  According to the present embodiment, the data transfer between the SMP server and the plurality of I / O devices is distributed to the plurality of I / O interfaces of the SMP server, thereby congesting the I / O interface and the server internal interconnect. Can be relaxed.

  Although the present invention has been specifically described above based on the embodiments, it is needless to say that the present invention is not limited to the above-described embodiments and can be variously modified without departing from the gist thereof. The above-described embodiments have been described in detail for better understanding of the present invention, and are not necessarily limited to those having all the configurations described above.

  Furthermore, each of the above-described configurations, functions, processing units, and the like may be realized by hardware by designing a part or all of them with an integrated circuit, or a program that realizes part or all of them. Needless to say, it can be realized by software.

  The present invention has the effect of reducing the congestion of the I / O interface and the internal interconnect used inside the computer in a computer such as an SMP server having a plurality of I / O interfaces, and improving the performance of the entire computer. Have.

100 SMP servers 101A-D Blades 102A-D CPU
103A to D Memory 104A to D, 109 Internal interconnect 105A to D IOH (I / O hub)
110 I / O switch 111 Switch exchange unit 112 I / O controller 113A-D Offset subtraction unit 114A-D Destination port search unit 120A-D I / O device 130 Management server 131 Management network 115A-D, 121A-D I / O Interface 150 Offset information 151 Destination port table.

Claims (15)

A computer system,
A server having a plurality of I / O interfaces and a plurality of processing units sharing a storage space;
An I / O device used by the server;
Comprising the I / O interface of the server and an I / O switch for connecting the I / O device;
The processor is
When the processing unit issues an instruction to the I / O device, the processing unit has an address conversion mechanism that adds a different offset value for each processing unit to destination data of data generated based on the command,
The I / O switch is
An offset subtraction unit that subtracts the corresponding offset value from the destination data issued by the server;
A computer system characterized by that. The computer system according to claim 1,
The I / O switch is
A destination port table for storing a correspondence relationship between a plurality of areas constituting a part of the storage space and the I / O interface;
The destination port table is referred to by the destination data address of the data issued by the I / O device, and the data is transferred to the I / O interface obtained as a reference result.
A computer system characterized by that. The computer system according to claim 1,
The instruction is a load instruction or a store instruction issued by the processing unit to the I / O device.
A computer system characterized by that. The computer system according to claim 1,
The destination data is a destination address of data issued by the server or a destination ID (Identifier).
A computer system characterized by that. The computer system according to claim 1,
The server is an SMP (Symmetric Multiple Processor) server.
A computer system characterized by that. The computer system according to claim 5,
The SMP server includes a plurality of blades, and each of the blades includes the processing unit, the I / O interface, a storage unit, and an internal interconnect, and the plurality of processing units and the plurality of the storage units include the internal unit. By connecting to each other through an interconnect, a single main storage space is formed as the storage space.
A computer system characterized by that. A data transfer method for a computer system comprising an I / O device used by a server having a plurality of processing units sharing a storage space with a plurality of I / O interfaces, and an I / O switch for connecting the I / O interface. And
The processor is
When issuing an instruction to the I / O device, a different offset value is given for each processing unit to destination data of data generated based on the instruction,
The I / O switch is
Transferring the data to the I / O device after removing the corresponding offset value from the destination data issued by the server;
A data transfer method characterized by the above. The data transfer method according to claim 7, comprising:
The I / O switch is
Storing a correspondence relationship between a plurality of areas constituting a part of the storage space and the I / O interface;
The correspondence relationship stored is referred to by destination data of data issued by the I / O device, and the data is transferred to the I / O interface obtained as a reference result.
A data transfer method characterized by the above. The data transfer method according to claim 7, comprising:
The processor is
As the instruction, a load instruction or a store instruction is issued to the I / O device.
A data transfer method characterized by the above. The data transfer method according to claim 7, comprising:
The destination data is a destination address or a destination ID of the data issued by the processing unit.
A data transfer method characterized by the above. An I / O switch for connecting a plurality of I / O interfaces of a server including a plurality of processing units sharing a storage space and an I / O device,
An offset subtraction unit that subtracts a different offset value for each I / O interface from destination data of data issued by the server;
A switch exchange unit connected to the output of the offset subtraction unit;
An I / O controller for controlling the offset subtraction unit and the switch exchange unit;
I / O switch characterized by that. The I / O switch according to claim 11, wherein
The I / O controller
An offset information storage unit for storing the offset value;
I / O switch characterized by that. The I / O switch according to claim 11, wherein
A destination search unit for searching for an I / O interface to be a destination among a plurality of the I / O interfaces of the server to be a destination according to destination data of data issued by the I / O device;
The data is transferred to the I / O interface obtained as a search result via the switch exchange unit.
I / O switch characterized by that. The I / O switch according to claim 13, wherein
The I / O controller
A destination port table that stores information indicating an area of the storage space of the server and a correspondence relationship with the I / O interface;
The destination port search unit
The I / O interface is searched with reference to the destination port table.
I / O switch characterized by that. The I / O switch according to claim 11, wherein
The destination data is a destination address of the data issued by the server or a destination ID (Identifier).
I / O switch characterized by that.

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