JP2012113508A - Floating point arithmetic circuit, computer with floating point arithmetic circuit, and arithmetic control method and arithmetic control program for the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To quicken arithmetic processing, and to shorten an arithmetic execution time by achieving a parallel arithmetic operation with mutual single accuracy/mutual double accuracy by an extension accuracy arithmetic circuit and a single/double accuracy arithmetic circuit.SOLUTION: A floating point arithmetic circuit having a plurality of arithmetic circuits each of which performs a floating point arithmetic operation to a numerical value with first bit width and a numerical value with second bit width which is shorter than the first bit width includes; a halt determination part for determining that a first arithmetic circuit which performs an arithmetic operation to the numerical value with the first bit width halts on the basis of an arithmetic instruction; and an arithmetic control part for, when it is determined that the first arithmetic circuit halts by the halt determination part, controls the first arithmetic circuit to perform the arithmetic operation to the numerical value with the second bit width, and controls the first arithmetic circuit and a second arithmetic circuit which performs an arithmetic operation to the numerical value with the second bit width to execute the arithmetic operation to the numerical value with the second bit width in parallel.

Description

  The present invention relates to an arithmetic technique for performing high-speed floating point arithmetic such as supercomputer vector arithmetic.

  Currently, a supercomputer needs to perform floating point arithmetic on three types of data: single precision, double precision, and extended precision. In particular, in vector operations and the like, since one operation process includes many repetitions of floating point operations, shortening of each floating point operation contributes to speeding up of the operation processing. In addition, simplifying the circuit configuration contributes to speeding up of the arithmetic processing. For example, in Patent Document 1, operation data having a 128-bit extended precision data width is divided into an upper part and a lower part having a 64-bit width, and one execution of an extended precision data width is performed twice in a 64-bit width arithmetic circuit. Find the result. Thereby, the calculation of the extended precision data width can be executed by a small amount of hardware. In Patent Document 2, an arithmetic unit having a 16-byte width (= 128-bit width) is divided into two 8-byte widths (= 64-bit width). Then, two divided 8-byte arithmetic units can simultaneously execute arithmetic data of 8-byte width (= 64-bit width) and 4-byte width ((= 32-bit width)).

Japanese Patent Laid-Open No. 06-149544 JP 09-091118 A

  However, even when performing floating-point arithmetic on three types of data of single precision, double precision, and extended precision, it is desirable to execute the computations simultaneously in parallel in order to speed up the computation processing and shorten the computation execution time. In addition, there is a need to provide hardware that can efficiently use limited hardware resources, speed up the computation processing, and shorten the computation execution time, thereby improving operational efficiency and reducing the power consumption of the computer system. Yes.

  On the other hand, the above-mentioned Patent Document 1 only executes an operation with an extended precision (128 bits = 16 bytes) using a double precision (64 bits = 8 bytes) arithmetic circuit, and all the operations are performed sequentially. Can only be executed. On the other hand, the above-mentioned patent document 2 can simultaneously execute single precision (4 bytes = 32 bits) and double precision (8 bytes = 64 bits) using an arithmetic unit with extended precision (16 bytes = 128 bits). is there. However, single-precision / double-precision parallel operations cannot be performed.

  The objective of this invention is providing the technique which solves the above-mentioned subject.

In order to achieve the above object, an apparatus according to the present invention provides:
A floating-point arithmetic circuit having a plurality of arithmetic circuits each performing a floating-point arithmetic on a numerical value of a first bit width and a numerical value of a second bit width shorter than the first bit width,
Pause determining means for determining whether the first arithmetic circuit for performing the calculation of the first bit width is paused based on an arithmetic instruction;
When the pause determination means determines that the first arithmetic circuit is paused, the first arithmetic circuit is controlled to perform a calculation of the numerical value of the second bit width, and the calculation of the numerical value of the second bit width is Arithmetic control means for executing in parallel by the first arithmetic circuit and a second arithmetic circuit for calculating a numerical value of the second bit width;
It is characterized by providing.

In order to achieve the above object, an apparatus according to the present invention provides:
A floating-point arithmetic circuit that performs floating-point arithmetic on an extended bit-width number,
An operation determination means for determining whether an operation instruction to the floating-point arithmetic circuit is an operation on an extended bit width value;
If the operation determining means determines that the operation is an operation on an extended bit width value, the floating point operation is performed on the extended bit width value, and the operation determining means is an extended bit width value. If it is determined that the operation is not for the operation, operation execution means for performing a floating point operation of a numerical value having a bit width shorter than the expanded bit width,
It is characterized by providing.

In order to achieve the above object, an apparatus according to the present invention provides:
A floating-point arithmetic circuit that performs floating-point arithmetic on an extended bit-width number,
An operation instruction register for storing an input operation instruction;
Generates an in-execution flag that detects whether or not to stop the floating-point operation with the extended bit width by the floating-point operation circuit based on the value of the output signal of the operation instruction register and generates an in-operation flag Circuit,
An execution flag storage register for storing the operation execution flag generated by the operation execution flag generation circuit;
A first register group for storing the sign, exponent, and mantissa of the input operation data having an extended bit width and the sign, exponent, and mantissa of the operation data;
A second register group for storing the sign, exponent, and mantissa of the input unexpanded bit-width operand data, and the sign, exponent, and mantissa of the operation data;
The first register group is selected when the operation in progress flag indicates that the floating point operation with an extended bit width is performed by the floating point operation circuit, and the operation execution flag is in the floating point operation circuit. A sign, exponent and mantissa selection circuit for selecting the second register group when indicating that the floating-point operation with the extended bit width by
A code generation circuit for generating a code of a calculation result based on a calculation instruction, a sign of operation data, and a sign of calculation data;
An exponent generation circuit that adjusts the exponent of the operand data and the exponent of the operand data based on the arithmetic instruction, the sign of the operand data, and the sign of the operand data;
In accordance with the adjustment of the exponent of the operand data and the exponent of the calculation data in the exponent generation circuit, the mantissa calculation that generates the mantissa of the calculation result by aligning the mantissa of the operand data with the mantissa of the calculation data Circuit,
A matching circuit for matching the exponent and mantissa of the operation result;
A calculation result storage register for storing a sign of the calculation result and an exponent and mantissa of the calculation result matched by the matching circuit;
The in-execution flag stored in the in-execution flag storage register and the sign, exponent, and mantissa of the operation result stored in the operation result storage register are output as a floating-point operation result.

In order to achieve the above object, an apparatus according to the present invention provides:
A computer having a floating-point arithmetic circuit having a plurality of arithmetic circuits that perform floating-point arithmetic on numerical values having different bit widths,
The first arithmetic circuit is
An operation determination means for determining whether an operation instruction to the first operation circuit is an operation on a numerical value of a first bit width or an operation on a numerical value of a second bit width shorter than the first bit width;
When the operation determining means determines that the operation is for the numerical value of the first bit width, a floating point operation of the numerical value of the first bit width is executed, and the operation determining means is for the numerical value of the second bit width. And a calculation execution means for executing a floating point calculation of the numerical value of the second bit width when it is determined as a calculation,
A second arithmetic circuit for performing a floating point arithmetic operation on the numerical value of the second bit width,
When the operation instruction to the floating point arithmetic circuit indicates that the operation on the numerical value of the first bit width is suspended, the floating point arithmetic operation of the numerical value of the second bit width is performed with the first arithmetic circuit and the second arithmetic circuit. It is characterized by being executed in parallel by an arithmetic circuit.

In order to achieve the above object, the method according to the present invention comprises:
An arithmetic control method for a computer having a floating point arithmetic circuit having a plurality of arithmetic circuits each performing a floating point arithmetic on numerical values having different bit widths,
A reading step of reading the arithmetic program from the storage means;
A determination step of analyzing an instruction of the arithmetic program and determining whether a numerical value to be calculated in the floating-point arithmetic circuit is a first bit width or a second bit width shorter than the first bit width;
When the numerical value to be calculated in the floating-point arithmetic circuit is the first bit width, the first arithmetic circuit for performing the operation of the first bit width is provided with the arithmetic instruction of the first bit width and the numerical value to be calculated. A first calculation step of obtaining a calculation result of the first bit width from the first calculation circuit;
When the numerical value to be calculated in the floating-point arithmetic circuit is the second bit width, the first arithmetic circuit that performs the operation of the first bit width and the second arithmetic circuit that performs the operation of the second bit width are connected in parallel. A second operation step of providing an operation instruction of the second bit width and a numerical value to be operated, and obtaining an operation result of the second bit width in parallel from the first operation circuit and the second operation circuit;
It is characterized by including.

In order to achieve the above object, a program according to the present invention provides:
An arithmetic control program for a computer comprising a floating point arithmetic circuit having a plurality of arithmetic circuits that respectively perform floating point arithmetic on numerical values of different bit widths,
A reading step of reading the arithmetic program from the storage means;
A determination step of analyzing an instruction of the arithmetic program and determining whether a numerical value to be calculated in the floating-point arithmetic circuit is a first bit width or a second bit width shorter than the first bit width;
When the numerical value to be calculated in the floating-point arithmetic circuit is the first bit width, the first arithmetic circuit for performing the operation of the first bit width is provided with the arithmetic instruction of the first bit width and the numerical value to be calculated. A first calculation step of obtaining a calculation result of the first bit width from the first calculation circuit;
When the numerical value to be calculated in the floating-point arithmetic circuit is the second bit width, the first arithmetic circuit that performs the operation of the first bit width and the second arithmetic circuit that performs the operation of the second bit width are connected in parallel. A second operation step of providing an operation instruction of the second bit width and a numerical value to be operated, and obtaining an operation result of the second bit width in parallel from the first operation circuit and the second operation circuit; Is executed by a computer.

  According to the present invention, single-precision / double-precision parallel computation is realized by the extended precision computation circuit and the single / double precision computation circuit, so that the computation processing can be speeded up and the computation execution time can be shortened.

It is a block diagram which shows the structure of the floating point arithmetic circuit of 1st Embodiment of this invention. It is a block diagram which shows the structure of the computer containing the floating point arithmetic circuit which concerns on 2nd Embodiment of this invention. It is a flowchart which shows the arithmetic processing procedure of the computer containing the floating point arithmetic circuit which concerns on 2nd Embodiment of this invention. It is a block diagram which shows the structure of the floating point addition / subtraction circuit contained in the floating point arithmetic circuit which concerns on 2nd Embodiment of this invention. It is a block diagram which shows the structure of the extended precision data width arithmetic circuit contained in the floating point addition / subtraction circuit which concerns on 2nd Embodiment of this invention. It is a block diagram which shows the structure of the single precision and double precision data width arithmetic circuit contained in the floating point addition / subtraction circuit which concerns on 2nd Embodiment of this invention. It is a figure which shows an example of the scientific calculation data format which concerns on 2nd Embodiment of this invention. It is a figure which shows the logic of the arithmetic instruction generation which concerns on 2nd Embodiment of this invention. It is a figure which shows the logic of the code data selection which concerns on 2nd Embodiment of this invention. It is a figure which shows the logic of the exponent data selection which concerns on 2nd Embodiment of this invention. It is a figure which shows the logic of the mantissa data selection which concerns on 2nd Embodiment of this invention. It is a figure which shows the logic of the exponent magnitude comparison signal generation which concerns on 2nd Embodiment of this invention. It is a figure which shows the logic of the reference | standard index selection which concerns on 2nd Embodiment of this invention. It is a block diagram which shows the structure of the mantissa selection circuit which concerns on 2nd Embodiment of this invention. It is a figure which shows the logic of addition mantissa data selection which concerns on 2nd Embodiment of this invention. It is a figure which shows the logic of the addition mantissa and inversion data selection which concern on 2nd Embodiment of this invention. It is a figure which shows the logic of the addition mantissa data selection which concerns on 2nd Embodiment of this invention. It is a figure which shows the logic of the intermediate code generation which concerns on 2nd Embodiment of this invention. It is a figure which shows the logic of the code generation which concerns on 2nd Embodiment of this invention. It is a figure which shows the example of a data value of each register at the time of extended precision addition in the extended precision data width arithmetic circuit which concerns on 2nd Embodiment of this invention. It is a figure which shows the example of a data value of each signal line at the time of extended precision addition in the extended precision data width arithmetic circuit which concerns on 2nd Embodiment of this invention. It is a figure which shows the data value example of each register at the time of double precision addition in the extended precision data width arithmetic circuit which concerns on 2nd Embodiment of this invention. It is a figure which shows the data value example of each signal line at the time of double precision addition in the extended precision data width arithmetic circuit which concerns on 2nd Embodiment of this invention.

  Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the drawings. However, the components described in the following embodiments are merely examples, and are not intended to limit the technical scope of the present invention only to them.

[First Embodiment]
A floating point arithmetic circuit 100 according to a first embodiment of the present invention will be described with reference to FIG. In FIG. 1, the floating point arithmetic circuit 100 includes a first arithmetic circuit 101, a second arithmetic circuit 102, a pause determination unit 103, and an arithmetic control unit 104. The first arithmetic circuit 101 is a circuit that performs arithmetic operation so that either a numerical value of the first bit width or a numerical value of the second bit width shorter than the first bit width can be selected. The second arithmetic circuit 102 is a circuit that calculates the second bit width. The pause determination unit 103 analyzes the calculation instruction and determines that the calculation instruction pauses the calculation of the numerical value of the first bit width by the first calculation circuit 101. When the determination from the pause determination unit 103 indicates that the calculation of the first bit width value is stopped, the calculation control unit 104 inputs the second bit width value to the first calculation circuit 101 and first The arithmetic circuit 101 performs arithmetic operation on the numerical value of the second bit width.

  According to the present embodiment, when the calculation of the numerical value of the first bit width by the first arithmetic circuit 101 is suspended, the arithmetic operation of the numerical value of the second bit width shorter than the first bit width is performed with the first arithmetic circuit 101. Two arithmetic circuits 102 can execute in parallel. Therefore, the computation processing time is increased and the computation execution time is shortened.

[Second Embodiment]
The second embodiment shows the circuit configuration of the floating point arithmetic circuit of the present embodiment, and the configuration of a scientific arithmetic circuit and a computer using this floating point arithmetic circuit. In the present embodiment, for example, in the vector calculation of the supercomputer, the calculation processing speed is increased to shorten the operation execution time, thereby making it possible to improve the efficiency of business and reduce the power consumption of the computer system.

<Configuration of Computer Using Floating Point Arithmetic Circuit of Second Embodiment>
FIG. 2A shows a floating point arithmetic circuit 41 according to the second embodiment, a scientific arithmetic circuit 40 using the floating point arithmetic circuit 41 according to the second embodiment, and a computer 200 using the floating point arithmetic circuit 41 according to the second embodiment. It is a block diagram which shows the structure of these.

(Schematic configuration of computer)
2A, the computer 200 includes a scientific arithmetic circuit 40, a main storage device 43, an input / output control device 44, and an external storage device 45. The main storage device 43 stores a scientific computation program and three types of scientific computation data and scientific computation instructions of single precision 601 / double precision 602 / extended precision 603 shown by the standard exponent data system in FIG. The main storage device 43 is also used as a temporary storage of calculation results. The scientific operation circuit 40 reads a scientific operation program from the main storage device 43, analyzes the instruction, executes the instruction, and outputs the execution result to the main storage device 43. The input / output control device 44 controls the input / output of the scientific operation result to the external storage device 45 according to the instruction analyzed by the scientific operation circuit 40. The external storage device 45 stores the data sent from the input / output control device 44 in accordance with the command and sends the stored data to the input / output control device 44. Here, the signal line L110 is a signal line for an input / output signal between the scientific arithmetic circuit 40 and the main memory 43. A signal line L111 is an input / output signal between the scientific arithmetic circuit 40 and the input / output control device 44, and L112 is an input / output signal between the input / output control device 44 and the external storage device 45.

(Structure of scientific operation circuit)
In FIG. 2A, the scientific arithmetic circuit 40 includes a floating point arithmetic circuit 41 and an instruction issue control circuit 42. The instruction issuance control circuit 42 analyzes the scientific operation data and the scientific operation instruction read from the main storage device 43. Then, a calculation instruction indicating the calculation accuracy and calculation type, operation data, and calculation data are issued to the floating point calculation circuit 41, and the calculation result by the floating point calculation circuit 41 is received to receive the main storage device 43 or the external storage device. 45. For example, when the operation repeats the same operation as a vector operation, it is repeated by the scientific operation circuit 40. Here, signal lines L100 to L106 are signal lines for input signals from the instruction issuance control circuit 42 to the floating point arithmetic circuit 41, and signal lines L400 and L401 are output signals from the floating point arithmetic circuit 41 to the instruction issuance control circuit 42. Signal line. The signal line L100 is a calculation instruction. Among the signal lines L101 to L106, the signal lines L101 to L103 are numerical signs, exponents, and mantissas that are input when single / double precision or extended precision operations are executed in sequence. The signal lines L104 to L106 are represented by the sign, exponent, and mantissa of single / double precision numerical values input in parallel with the signal lines L101 to L103 when executing single / double precision operations in parallel (in parallel). is there. The calculation result from the single precision / double precision data width calculation circuit is output to L400, and the calculation result from the extended precision data width calculation circuit is output to the signal line L401. In this embodiment, when the operation instruction of the signal line L100 is an instruction to pause the extended precision data width operation circuit, two single / double precision operation results are output in parallel from both the signal lines L400 and L401. Is done.

(Operation procedure of instruction issue control circuit)
FIG. 2B is a flowchart showing the operation procedure of the instruction issue control circuit 42. The operation of the instruction issue control circuit 42 may be configured in any manner such as hardware, software, firmware, and microprogram. Therefore, the flowchart of FIG. 2B not only shows the flow of the program but also includes hardware processing. Actually, the operation data and the operation data are sequentially output from the instruction issuance control circuit 42 to the signal lines L101 to L106 and held in the respective registers. However, since this is complicated, detailed description thereof is omitted. It is. In this example, the data width of the arithmetic instruction on the signal line L100 is 2 bits, and the extended precision arithmetic pause instruction and the single / double precision arithmetic instruction are issued separately. However, if the data width of the signal line L100 is 3 bits or more, an extended precision arithmetic pause instruction and a single / double precision arithmetic instruction can be combined and output to the signal line L100 simultaneously.

  First, in step S201, an arithmetic program is read from the main storage device 43. Next, in step S203, the instruction of the arithmetic program is analyzed. In step S205, a determination is made as to whether the analysis result is a single / double precision calculation or an extended precision calculation.

  If the determination result is single / double precision calculation, the extended precision arithmetic circuit is determined to pause and the process proceeds to step S207. In step S207, a command indicating extended accuracy calculation suspension is provided to the signal line L100. In step S209, a single / double precision operation command is issued to the signal line L100, and single / double precision data is provided to the signal lines L104 to L106 in parallel with the signal lines L101 to L103. In step S211, two single / double precision calculation results are acquired from the signal lines L400 and L401. In step S213, it is determined whether or not the calculation is repeated. If it is repeated, the process returns to step S209 to repeat steps S209 to S213. If not repeated, the process proceeds to step S221.

  On the other hand, if the determination result in step S205 is an extended precision calculation, in step S215, an extended precision calculation command is issued to the signal line L100, and extended precision data is output to the signal lines L101 to L103. In step S217, one extended precision calculation result is acquired from the signal line L401. In step S219, it is determined whether or not the calculation is repeated. If it is repeated, the process returns to step S215, and steps S215 to S219 are repeated. If not repeated, the process proceeds to step S221.

  In step S221, the calculation result is stored in the main storage device 43. Alternatively, it may be stored in the external storage device 45 via the input / output control device 44. In step S223, it is determined whether or not the operation program is ended. If not, the process returns to step S203 to process the next instruction. If the arithmetic program is finished, the process is finished. Then, a series of flows starting from reading out the next arithmetic program from the main memory 43 continues.

  Note that the procedure of FIG. 2B is an example, and the present invention is not limited to this.

(Configuration of floating point arithmetic circuit)
2A, the floating point arithmetic circuit 41 includes a floating point addition / subtraction circuit 46, a floating point multiplication circuit 47, a floating point division circuit 48, and a floating point arithmetic result selection circuit 49. The floating point addition / subtraction circuit 46 executes an addition / subtraction instruction among the instructions output from the instruction issue control circuit 42 to the floating point arithmetic circuit 41. The floating point multiplication circuit 47 executes a multiplication instruction among the instructions output from the instruction issue control circuit 42 to the floating point arithmetic circuit 41. The floating point division circuit 48 executes a division instruction among the instructions output from the instruction issue control circuit 42 to the floating point arithmetic circuit 41. The floating point arithmetic result selection circuit 49 selects the arithmetic result from each arithmetic circuit and outputs it to the instruction issue control circuit 42. Here, the signal lines L300 to L305 and L310 represent signal lines connecting the respective circuits. The signal lines L300, L302, and L304 are signal lines that output the calculation results of the single / double precision arithmetic circuit, and the signal lines L301, L303, and L305 are signals that output the arithmetic results of the extended precision arithmetic circuit. The signal line L310 is a signal line that outputs whether or not the extended precision arithmetic circuit obtained by analyzing the arithmetic instruction of the signal line L100 is suspended. In this example, “1 (high)” is output to the signal line L310 when the extended precision arithmetic circuit is paused, and “0 (low)” is output to the signal line L310 when the extended precision arithmetic circuit is operated. Is done. The calculation result is selected by the floating-point calculation result selection circuit 49 and output to the signal lines L400 and L401. In the floating-point arithmetic result selection circuit 49, when the extended precision arithmetic circuit is paused and the signal line L310 is "1", the single and double precision arithmetic operations from the signal lines L300, L302, and L304 are applied to the signal line L400. The result is output. At the same time, the single / double precision calculation results from the signal lines L301, L303, and L305 are output in parallel to the signal line L401. On the other hand, when the signal line L310 on which the extended precision arithmetic circuit performs the operation is “0”, the extended precision calculation results from the signal lines L301, L303, and L305 are output to the signal line L401.

(Configuration of floating point addition / subtraction circuit)
FIG. 3 is a block diagram showing a configuration of the floating point addition / subtraction circuit 46 included in the floating point arithmetic circuit 41 according to the second embodiment. In the present embodiment, the configuration and operation of the floating point addition / subtraction circuit 46 will be described below as a representative. However, the floating-point multiplication circuit 47 and the floating-point division circuit 48 also include two arithmetic circuits for single-precision / double-precision data width and extended-precision data width. And, it is the same that the arithmetic circuit for the extended precision data width performs the calculation of the single precision / double precision data width in parallel during the suspension of the extended precision calculation, and the feature of the configuration is not changed only by the type of the calculation. . Therefore, in this specification, the floating point addition / subtraction circuit 46 and the like are also collectively referred to as a floating point arithmetic circuit.

  The floating point addition / subtraction circuit 46 of FIG. 3 includes a single precision / double precision data width arithmetic circuit 11 and an extended precision data width arithmetic circuit 12. As shown in FIG. 2A, in the floating point addition / subtraction circuit 46, when the single precision / double precision data width arithmetic circuit 11 and the extended precision data width arithmetic circuit 12 perform addition / subtraction, respectively, "00" is applied to the signal line L100. Each operation command that is not “or“ 11 ”is input. In this example, “00” and “11” of the operation instructions are instructions indicating the suspension of the extended precision data width operation circuit 12. In that case, the respective operation data and operation data are input using the signal lines L101 to L103. The calculation results of the single precision / double precision data width arithmetic circuit 11 and the extended precision data width arithmetic circuit 12 are output from the signal line L300 or L301, respectively. The signal line L310 outputs “0 (low)” indicating that “00” or “11” has not been input to the signal line L100.

  On the other hand, when the extended precision data width arithmetic circuit 12 pauses the extended precision calculation, “00” or “11” (an instruction indicating the pause of the extended precision data width arithmetic circuit 12) is input to the signal line L100. In that case, the single-precision / double-precision data width arithmetic circuit 11 is inputted with single-precision / double-precision operand data and calculation data using the signal lines L101 to L103. At the same time, single-precision / double-precision operand data and computation data are input to the extended precision data width computation circuit 12 using the signal lines L104 to L106. The calculation results of single precision / double precision data of the single precision / double precision data width arithmetic circuit 11 and the extended precision data width arithmetic circuit 12 are output in parallel from the signal lines L300 and L301. The signal line L310 outputs “1 (high)” indicating that “00” or “11” is input to the signal line L100. “1 (High)” of the signal line L310 is connected to the single-precision / double-precision data width arithmetic circuit 11 and the extended precision data width arithmetic circuit in the signal lines L400 and L401 with respect to the floating-point arithmetic result selection circuit 49 in FIG. 2A. 12 outputs the operation result calculated in parallel with 12.

(Configuration of extended precision data width arithmetic circuit)
FIG. 4 is a block diagram showing a configuration of the extended precision data width arithmetic circuit 12 included in the floating point addition / subtraction circuit 46 according to the second embodiment. The extended precision data width arithmetic circuit 12 calculates the extended precision arithmetic data in the format indicated by 603 in FIG. 6, but may also execute single precision / double precision arithmetic data in the format indicated by 601 and 602 in FIG. Is possible. Therefore, each register and each circuit of the extended precision data width arithmetic circuit 12 of FIG. 4 are configured to be able to execute the arithmetic of the extended precision arithmetic data and the arithmetic of the single precision / double precision arithmetic data, and details thereof are omitted. To do. In the following description, the function and operation order of each circuit are considered. In addition, since the operation in the subtraction of the extended precision data width arithmetic circuit 12 is substantially the same if the addition and the sign are changed, the following description will be focused on the addition. That is, the wording “addition” used in the following means “addition / subtraction” particularly in FIGS. Therefore, in this specification, the extended precision data width arithmetic circuit 12 having a characteristic configuration is also collectively referred to as a floating point arithmetic circuit.

(A: Input data register and output data register)
The extended precision data width arithmetic circuit 12 includes a register group that holds signals input from the instruction issue control circuit 42 through the signal lines L100 to L106. The register 1 is an arithmetic instruction register that holds an arithmetic instruction from the signal line L100. The registers 2 to 13 are registers that hold operation data and operation data from the signal lines L101 to L106. Among these, the registers 2, 4, 6, 8, 10, and 12 connected to the signal lines L101 to L103 hold the extended width data when the extended precision data width arithmetic circuit 12 adds the extended precision width. A first register group. The first register group further includes registers 2, 6, and 10 for holding the sign, exponent, and mantissa of the added data, and registers 4, 8, and 12 for holding the sign, exponent, and mantissa of the added data. On the other hand, the registers 3, 5, 7, 9, 11, and 13 connected to the signal lines L104 to L106 are single precision / double when the extended precision data width arithmetic circuit 12 performs addition of single precision / double precision width. It is a second register group that holds precision width data. The second register group further includes registers 3, 7, and 11 for holding the sign, exponent, and mantissa of the added data, and registers 5, 9, and 13 for holding the sign, exponent, and mantissa of the added data.

  On the other hand, the extended precision data width arithmetic circuit 12 includes registers 14 and 15 that hold signals output from the signal lines L301 and L310 to the floating-point arithmetic result selection circuit 49. The register 14 is an operation result storage register that holds the sign, exponent, and mantissa of the operation result. The register 15 is a calculation execution flag storage register that holds a calculation execution flag generated by the calculation execution flag generation circuit 16 from a calculation instruction input from the signal line L100 and held in the register 1. FIG. 7 shows a logic 700 based on the operation instruction including the logic that receives the operation instruction from the register 1 of the signal line L200 and outputs the operation execution flag of the signal line L257 in the operation execution flag generation circuit 16. . An operation execution flag 702 is generated based on the operation instruction 701 in FIG. As shown in FIG. 7, when the operation instruction is “00” or “11”, “1” is output to the operation execution flag, indicating that the extended accuracy data width calculation circuit 12 pauses the extended accuracy operation. Therefore, the register 15 functions as an operation execution flag storage register.

(B: Single / double precision / extended precision input selection circuit)
The calculation execution flag of the signal line L257 output from the calculation execution flag generation circuit 16 is input to the calculation sign selection circuit 17, the calculation exponent selection circuit 18, and the calculation mantissa selection circuit 19. The arithmetic code selection circuit 17, the arithmetic exponent selection circuit 18, and the arithmetic mantissa selection circuit 19 select the sign, exponent, and mantissa input according to the calculation execution flag of the signal line L257 and transmit them to the arithmetic circuit group.

  The operation code selection circuit 17 receives the added data code and the added data code output from the registers 2 to 5 to the signal lines L240 to L243, respectively. The operation code selection circuit 17 selects the input code and outputs it to the signal lines L253 and L254 according to the logic 800 shown in FIG. 8 based on the operation execution flag of the signal line L257. When the calculation execution flag is “0”, as shown by 801, the extended precision added data code and the added data code output from the registers 2 and 4 to the signal lines L240 and L241, respectively, are selected. Output to the signal lines L253 and L254. On the other hand, when the calculation execution flag is “1”, as indicated by 802, single-precision / double-precision added data code and added data code output from the registers 3 and 5 to the signal lines L242 and L243, respectively, Is output to the signal lines L253 and L254.

  The added exponent data and the added exponent data output from the registers 6 to 9 to the signal lines L244 to L247, respectively, are input to the arithmetic exponent selection circuit 18. The calculation index selection circuit 18 selects the input index data and outputs it to the signal lines L255 and L256 according to the logic 900 shown in FIG. 9 by the calculation execution flag of the signal line L257. When the calculation execution flag is “0”, as shown by 901, the extended precision added index data and the added index data output from the registers 6 and 8 to the signal lines L244 and L245, respectively, are selected, Output to the signal lines L255 and L256. On the other hand, when the operation execution flag is “1”, as indicated by 902, single-precision / double-precision added exponent data and added exponent data output from the registers 7 and 9 to the signal lines L 246 and L 247, respectively, Is output to the signal lines L255 and L256.

  The arithmetic mantissa selection circuit 19 receives the added mantissa data and the added mantissa data output from the registers 10 to 13 to the signal lines L248 to L251, respectively. The arithmetic mantissa selection circuit 19 selects the input mantissa data and outputs the selected mantissa data to the signal lines L258 and L259 in accordance with the logic 1000 shown in FIG. 10 based on the operation executing flag of the signal line L257. When the operation execution flag is “0”, as shown by 1001, the extended precision added mantissa data and the added mantissa data output from the registers 10 and 12 to the signal lines L248 and L249, respectively, are selected. Output to the signal lines L258 and L259. On the other hand, when the calculation execution flag is “1”, as indicated by 1002, single-precision / double-precision added mantissa data and added mantissa data output from the registers 11 and 13 to the signal lines L250 and L251, respectively, Is output to the signal lines L258 and L259.

(C: Operation instruction analysis circuit)
The operation instruction held in the register 1 is input to the operation instruction analysis circuit 20 through the signal line L200. The arithmetic instruction analysis circuit 20 outputs the arithmetic instruction analysis result to the signal line L207 based on the arithmetic instruction of the signal line L200, the added data code of the signal line L253, and the added data code of the signal line L254 according to the logic 700 of FIG. Output from. As shown in FIG. 7, “0” in the operation instruction analysis result is addition and “1” is subtraction, and is used for control of the mantissa selection circuit 25.

(D: exponent selection circuit and exponent adjustment circuit)
The exponent magnitude comparison circuit 21 compares the magnitude of the added exponent data output from the arithmetic exponent selection circuit 18 to the signal lines L255 and L256 and the added exponent data. FIG. 11 is a diagram showing a logic 1100 between the exponent data in the exponent magnitude comparison circuit 21 and the value output to the signal line L211. If the added index data output to the signal line L255 is larger than the added index data output to the signal line L256, “1” is output to the signal line L211. If the added index data output to the signal line L255 is not larger than the added index data output to the signal line L256, “0” is output to the signal line L211. The value of the signal line L211 is used for selection of the reference exponent selection circuit 22, intermediate code generation of the intermediate code generation circuit 24, and control of the mantissa selection circuit 25.

  The reference exponent selection circuit 22 determines which digit alignment of the added mantissa data and the added mantissa data is performed. FIG. 12 is a diagram showing the logic 1200 of exponent data output to the signal line L209 corresponding to the value output to the signal line L211 in the reference exponent selection circuit 22. When the output value of the signal line L211 from the exponent magnitude comparison circuit 21 is “0”, the added exponent data is output to the signal line L209 based on the added exponent data. When the output value of the signal line L211 from the exponent magnitude comparison circuit 21 is "1", the addition exponent data is used as a reference and the addition exponent data is output to the signal line L209.

  The shift amount calculation circuit 23 calculates a difference between the larger exponent selected by the arithmetic exponent selection circuit 18 and the smaller exponent not selected, obtains a right shift amount for right-shifting the small mantissa data and performing signal alignment. The data is sent to the digit alignment right shift circuit 27 through the line L210.

(E: Mantissa calculation circuit)
The mantissa selection circuit 25 receives the added mantissa and the addition mantissa selected by the arithmetic mantissa selection circuit 19 and output to the signal lines L258 and L259, and the added mantissa and the addition mantissa are input to the signal lines L212 and L213. Select which to output to. The mantissa selection circuit 25 selects the magnitude comparison result between the added index and the added index output from the exponent magnitude comparison circuit 21 to the signal line L211 and the calculation instruction analysis output from the calculation instruction analysis circuit 20 to the signal line L207. Based on the results. In other words, the smaller exponent is output as a mantissa requiring digit alignment, and the other is output as a mantissa requiring no digit alignment.

  FIG. 13 is a diagram showing an internal configuration of the mantissa selection circuit 25. The mantissa selection circuit 25 includes a mantissa A selection circuit 50, a mantissa B selection circuit 51, and a mantissa B inversion selection circuit 52.

  The mantissa A selection circuit 50 selects a mantissa having a small exponent from the mantissa to be added and the mantissa to be added, based on the result of comparison between the exponent to be added and the addition exponent of the signal line L211. . FIG. 14 is a diagram illustrating the logic 1400 of the mantissa A selection circuit 50. The mantissa B selection circuit 51 and the mantissa B inversion selection circuit 52 determine the mantissa output to the signal line L213, the result of comparing the added exponent of the signal line L211 with the addition exponent, the result of the operation instruction analysis of the signal line L207, Based on, a mantissa having a large exponent is selected from the added mantissa and the added mantissa. FIG. 15 is a diagram illustrating the logic 1500 of the mantissa B selection circuit 51. The selected mantissa is output as it is to the signal line L280 output from the mantissa B selection circuit 51, and data obtained by inverting the selected mantissa is output to the signal line L281. The mantissa B inversion selection circuit 52 selects the mantissa of the signal line L280 and the inversion mantissa of the signal line L281 output from the mantissa B selection circuit 51 based on the operation instruction analysis result of the signal line L211 and outputs the selected mantissa to the signal line L213. To do. FIG. 16 is a diagram showing the logic 1600 of the mantissa B inversion selection circuit 52. When the operation instruction analysis result is “0” (addition), the mantissa that is not inverted of the signal line L280 is output to the signal line L213, and when the operation instruction analysis result is “1” (subtraction), the mantissa is inverted of the signal line L280. Is output to the signal line L213.

  The digit alignment right shift circuit 27 shifts the mantissa with a small exponent input from the signal line L212 to the right by the difference between the large and small exponents output from the shift amount calculation circuit 23 to the signal line L210, and calculates the addition / subtraction circuit 29. Perform mantissa digit alignment. The addition / subtraction circuit 29 outputs the addition / subtraction result obtained by adding the mantissa data of the signal line L215 aligned by the digit alignment right shift circuit 27 and the mantissa data of the signal line L213 not requiring alignment to the signal line L216. At the same time, a case where a large added mantissa is subtracted from a small added mantissa with the same numerical value is detected, and the result is output to the signal line L220. When a large addition mantissa is subtracted from a small added mantissa with the same exponent, “1” is output.

The 0-digit number check circuit 28 detects the presence or absence of “0” data in the higher rank of the calculation result output from the adder / subtracter circuit 29 to the signal line L216 and outputs it to the signal line L217. The normalized left shift circuit 31 shifts the numerical value output from the signal number L217 by the 0-digit number check circuit 28 to the left, normalizes the mantissa of the operation result, and outputs the result to the signal line L218 as the mantissa of the operation result. The mantissa of the normalized calculation result of the signal line L218 is sent to the register 14 and held.
The normalized left shift circuit 31 and the 0-digit number check circuit 28 function as a matching circuit that matches the mantissa of the operation result with the exponent.

(F: exponent generation circuit)
The exponent generation / subtraction circuit 30 inputs the large exponent output from the reference exponent selection circuit 22 to the signal line L209. Then, the numerical value of the signal line L217 is subtracted from the exponent of the signal line L209 as the calculation result is shifted to the left by the normalized left shift circuit 31 by the numerical value output by the zero digit number check circuit 28 to the signal line L217. Then, it is output to the signal line L219 as an exponent of the calculation result. The generated code of the signal line L219 is sent to the register 14 and held.

(G: code generation circuit)
The added data code and the added data code output from the operational code selection circuit 17 to the signal lines L253 and L254 are input to the intermediate code generation circuit 24. Based on the value of the signal line L211 from the exponent magnitude comparison circuit 21, the intermediate code generation circuit 24 selects either the added data code or the added data code input from the signal lines L253 and L254, and outputs the signal Output to line L208. FIG. 17 is a diagram illustrating the logic 1700 of the intermediate code generation circuit 24. The intermediate code generation circuit 24 selects and outputs a large data code. That is, when the value of the signal line L211 is “0” (additional exponent data is equal to or greater than the added exponent data), the addition data code is output to the signal line L208. On the other hand, when the value of the signal line L211 is “1” (addition index data is smaller than the addition index data), the addition data code is output to the signal line L208.

  The code generation circuit 26 inputs the intermediate code of the signal line L208 output from the intermediate code generation circuit 24. Then, the intermediate code is adjusted based on the result of detecting the case where a large addition mantissa is subtracted from a small added mantissa with the same numerical value in the addition / subtraction circuit 29 and outputting it to the signal line L220. FIG. 18 is a diagram illustrating the logic 1800 of the code generation circuit 26. When the sign inversion signal of the signal line L220 is “1”, the intermediate code is inverted to become a generated code. The code generation circuit 26 outputs the generated generated code to the signal line L214 as a calculation result code. The generated code of the signal line L214 is sent to the register 14 and held.

  With the configuration of the extended precision data width arithmetic circuit 12 in FIG. 4, the extended precision data width arithmetic circuit 12 can execute single / double precision arithmetic while the extended precision arithmetic is paused. In other words, if the arithmetic instruction input from the signal line L100 is an extended precision calculation, numerical data having the extended precision data width input from the signal lines L101 to L103 is calculated. Then, the extended precision calculation result is held in the register 14 and “0” indicating the extended precision calculation is held in the register 15 and is output from the signal lines L301 and L310. On the other hand, if the operation instruction input from the signal line L100 is not an extended precision operation, numerical data having other / double precision data widths input from the signal lines L104 to L106 is calculated. The register 14 holds the single / double precision calculation result, the register 15 holds “1” indicating the single / double precision calculation, and outputs the result from the signal lines L301 and L310.

(Configuration of single precision / double precision data width arithmetic circuit 11)
FIG. 5 is a block diagram showing a configuration of the single precision / double precision data width arithmetic circuit 11 included in the floating point addition / subtraction circuit 46 according to the second embodiment. The single-precision / double-precision data width arithmetic circuit 11 shown in FIG. 5 differs from the configuration of the extended precision data width arithmetic circuit 12 shown in FIG. Since the functions of the elements are the same, a detailed description is omitted. The data width of each register, the circuit related to the exponent operation and the circuit related to the mantissa operation is only adapted to the format of the single precision / double precision operation data shown in FIG.

  The register 70 in FIG. 5 corresponds to the register 1 in FIG. The registers 71 to 76 in FIG. 5 correspond to the registers 2, 4, 6, 8, 10, and 12 in FIG. The operation instruction analysis circuit 77 in FIG. 5 corresponds to the operation instruction analysis circuit 20 in FIG. The exponent magnitude comparison circuit 81 in FIG. 5 corresponds to the exponent magnitude comparison circuit 21 in FIG. The reference index selection circuit 79 in FIG. 5 corresponds to the reference index selection circuit 22 in FIG. The shift amount calculation circuit 80 in FIG. 5 corresponds to the shift amount calculation circuit 23 in FIG. The mantissa selection circuit 82 in FIG. 5 corresponds to the mantissa selection circuit 25 in FIG. 4. The digit alignment right shift circuit 84 in FIG. 5 corresponds to the digit alignment right shift circuit 27 in FIG. The addition / subtraction circuit 86 in FIG. 5 corresponds to the addition / subtraction circuit 29 in FIG. 4. The zero-digit number check circuit 85 in FIG. 5 corresponds to the zero-digit number check circuit 28 in FIG. The normalized left shift circuit 88 in FIG. 5 corresponds to the normalized left shift circuit 31 in FIG. The exponent generation / subtraction circuit 87 in FIG. 5 corresponds to the exponent generation / subtraction circuit 30 in FIG. 4. The intermediate code generation circuit 78 in FIG. 5 corresponds to the intermediate code generation circuit 24 in FIG. The code generation circuit 83 in FIG. 5 corresponds to the code generation circuit 26 in FIG. The register 89 in FIG. 5 corresponds to the register 14 in FIG.

  The single-precision / double-precision data width arithmetic circuit 11 includes a register group that holds input data of the signal lines L104 to L106 of the extended precision data width arithmetic circuit 12, an arithmetic code selection circuit 17 that selects the input data, and an arithmetic exponent selection circuit 18. The arithmetic mantissa selection circuit 19 is not provided. Further, it does not have a calculation execution flag generation circuit 16 that generates a calculation execution flag that is a selection signal, and a register 15 that holds the calculation execution flag.

  With the configuration including the extended precision data width arithmetic circuit 12 of FIG. 4 and the single precision / double precision data width arithmetic circuit 11 of FIG. 5, the floating point addition / subtraction circuit 46 of FIG. 3 operates as follows. In the case of the extended precision calculation, the extended precision calculation result is output from the signal line L301 of the extended precision data width calculation circuit 12. On the other hand, in the case of single / double precision computation, one single / double precision computation result is output from the signal line L300 of the single / double precision data width computation circuit 11. In parallel, another single / double precision calculation result is output from the signal line L301 of the extended precision data width arithmetic circuit 12. Whether it is an extended precision calculation or a single / double precision calculation is indicated by a signal on the signal line L310.

  With the configuration including the floating point addition / subtraction circuit 46 of FIG. 3, the scientific operation circuit 40 of FIG. 2A operates as follows. Whether it is an extended precision calculation or a single / double precision calculation is indicated by a signal on the signal line L310. In the case of the extended precision calculation, the extended precision calculation result output from the signal line L301 of the extended precision data width calculation circuit 12 is selected by the floating point calculation result selection circuit 49, and is sent to the instruction issue control circuit 42 by the signal line L401. Returned. On the other hand, in the case of single / double precision computation, one single / double precision computation result output from the signal line L300 of the single / double precision data width computation circuit 11 is returned to the instruction issue control circuit 42 by the signal line L400. Further, in parallel, another single / double precision operation result output from the signal line L301 of the extended precision data width arithmetic circuit 12 is returned to the instruction issue control circuit 42 via the signal line L401.

<Operation Procedure of Floating Point Arithmetic Circuit Having Extended Precision Data Width Arithmetic Circuit of Second Embodiment>
Hereinafter, as a specific operation of the floating point arithmetic circuit according to the second embodiment, a processing example of the floating point addition / subtraction circuit 46 will be described. In the present embodiment, on the condition that the extended precision data width arithmetic circuit 12 is inactive, the instruction issue control circuit 42 sends a single precision / double precision arithmetic instruction and a single precision / double precision instruction to the extended precision data width arithmetic circuit 12. 32-bit or 64-bit data is transferred. As a result, the single-precision / double-precision calculation result can be obtained in the extended precision data width calculation circuit 12. Since the operation of the single precision / double precision data width arithmetic circuit 11 and the single precision / double precision arithmetic of the extended precision data width arithmetic circuit 12 are similar, the extended precision arithmetic of the extended precision data width arithmetic circuit 12 and the single precision / The double precision calculation will be described.

(Operation procedure of extended precision data width arithmetic circuit 12 at the time of extended precision calculation)
In the following, an operation of calculating the extended precision data width, “1000000000000000000000000000 × 16 ² ” (data to be added) + “7FFFFFFFFFFFFFFFFFFFFFFFFFFF × 16 ⁴ ” (addition data), will be described. The floating point arithmetic data to be handled is the so-called standard exponent data format, extended exponent data format, and IEEE exponent data format. The standard exponent data format shown in FIG. Hex notation and mantissa data 112 bits in 28-digit hexadecimal notation).

  19 and 20 are diagrams showing each register value 1900 and each signal line value 2000 in the description of the operation.

  As the addition instruction for the signal line L100 from the instruction issuance control circuit 42, the numerical value “01” of the addition instruction is stored in the register 1. Further, the sign value “0” (positive sign) of the added data is stored in the register 2 and the code value “0” (positive sign) of the added data is stored in the register 4 based on the added data and the added data having the extended precision data width. ) Is stored. In addition, an exponent value “02” of the added data is stored in the register 6, and an exponent value “04” of the added data is stored in the register 8. Further, the added mantissa data value “1000000000000000000000000000” is stored in the register 10, and the added mantissa data value “7FFFFFFFFFFFFFFFFFFFFFFFFFFF” is stored in the register 12.

  Since the operation execution flag generation circuit 16 is the addition instruction of the extended precision data width of the signal line L200 from the operation instruction generation logic 700 of FIG. 0 "is output to the signal line L257. On condition that the signal line L257 is “0”, the operation code selection circuit 17 selects the added code data of the extended precision data width of the signal lines L240 and L242 from the code data selection logic 800 of FIG. "0" (plus sign) is output to both L and L254. The arithmetic exponent selection circuit 18 selects exponential data with the extended precision data width of the signal lines L244 and L245 from the exponent data selection logic 900 of FIG. 9, and outputs “02” and signal line L256 “04” to the signal line L255. To do. The arithmetic mantissa selection circuit 19 selects the mantissa data of the extended precision data width of the signal lines L248 and L249 from the mantissa data selection logic 1000 of FIG. Then, “1000000000000000000000000000” is output to the signal line L258, and “7FFFFFFFFFFFFFFFFFFFFFFFFFFFF” is output to the signal line L259.

  The arithmetic instruction analyzing circuit 20 includes a numerical value “01” (addition instruction) of the arithmetic instruction of the signal line L200, a numerical value “0” (positive sign) of the signal line L253, and a numerical value “0” (positive sign) of the signal line L254. 7 is analyzed from the operation instruction generation logic 700 of FIG. 7, and a numerical value “0” (addition instruction) is output to the signal line L207.

  The exponent magnitude comparison circuit 21 compares the numerical value “02” of the added exponent data of the signal line L255 with the numeric value “04” of the added exponent data of the signal line L256. As a comparison result, the exponent magnitude comparison logic 1100 in FIG. 11 determines that the exponent data of the signal line L256 is large, and outputs a numerical value “0” to the signal line L211 as an exponent magnitude comparison result signal. The reference exponent selection circuit 22 selects the numeric value “04” of the signal line L256, which is large added exponent data, from the reference exponent selection logic 1200 of FIG. 12 based on the condition of the numeric value “0” of the exponent magnitude comparison result of the signal line L211. To the signal line L209. The shift amount calculation circuit 23 obtains the difference between the exponent value “02” of the added data of the signal line L255 and the exponent value “04” of the added data of the signal line L256, and the right shift amount for digit alignment The numerical value “2” is output to the signal line L210.

  Since the exponent magnitude comparison result signal of the signal line L211 is “0” and the exponent of the addition data is large, the mantissa selection circuit 25 has the mantissa of the addition data and the mantissa of the addition data from the addition mantissa data selection result logic 1400 of FIG. It is judged that the replacement with is unnecessary. Therefore, the added mantissa data of the signal line L258 is selected, and the added mantissa data “1000000000000000000000000000” is output to the signal line L212. On the other hand, the numerical value of the added mantissa data of the signal line L259, “7FFFFFFFFFFFFFFFFFFFFFFFFFFF”, is output to the signal line L280 from the selection logic 1500 of the added mantissa data and the addition inverted mantissa data in FIG. Further, the complement of the signal line L259, “1000000000000000000000000000”, is output to the signal line L281. Then, on the condition of “0 (addition)” of the operation instruction analysis result signal of the signal line L207, the added mantissa data selection logic 1600 of FIG. Select and output as selection signal. The digit alignment right shift circuit 27 shifts right by two digits based on the value “2” of the right shift amount signal of the signal line L210, and therefore outputs “0010000000000000000000000000” as the mantissa value of the added data to the signal line L215. To do. The addition / subtraction circuit 29 adds the numerical value “0010000000000000000000000000” of the signal line L215 and the numerical value “7FFFFFFFFFFFFFFFFFFFFFFFFFFF” of the signal line L213. Then, the numerical value of the addition result, “800FFFFFFFFFFFFFFFFFFFFFFFFF” is output to the signal line L216.

  The zero digit number check circuit 28 checks whether or not there is a numerical value “0” in the upper digit starting with “8” of the numerical value “800FFFFFFFFFFFFFFFFFFFFFFFFF” of the addition result signal of the signal line L216. When it is confirmed that the beginning of the numerical value of the signal line L216 is “8” and the numerical value of “1” exists in the leading data, the numerical value “0” of the 0-digit number check signal is output to the signal line L217. Since “0” of the signal line L217 does not need a left shift for normalization, the normalized left shift circuit 31 does not perform a left shift for normalization, and as a result, the numerical value “800FFFFFFFFFFFFFFFFFFFFFFFFF” is changed to the signal line L218. Output to.

  The exponent generation / subtraction circuit 30 subtracts the numeric value “0” of the zero-digit number check signal of the signal line L217 from the numeric value “04” of the reference exponent selection result of the signal line L209, and the exponent data numeric value “04” to the signal line L219. "Is output.

  The intermediate code generation circuit 24 calculates the value “0” of the exponent magnitude comparison result signal of the signal line L211 and the condition “0” of the added code data of the signal line L253 and the added code data of the signal line L254 of FIG. From the intermediate code generation logic 1700, the numerical value “0” (positive code) of the sign of the large exponent of the signal line L254 is output to the signal line L208. Then, the sign generation circuit 26 outputs “0” to the signal line L220 because it does not subtract the large added mantissa data from the small added mantissa data from the numerical value of the added mantissa and the added mantissa for performing the operation. Based on the condition “0” of the signal line L220, the code generation logic 1700 in FIG. 18 outputs a numerical value “0” (plus sign) to the signal line L214 without inverting the sign.

  The register 14 stores the code value “0” (plus sign) of the signal line L214 generated by the code generation circuit 26. Also, the exponent data “04” of the signal line L219 obtained by the exponent generation / subtraction circuit 30 and the mantissa data “800FFFFFFFFFFFFFFFFFFFFFFFFF” output by the normalized left shift circuit 31 to the signal line L218 are stored. And it outputs by the signal line L301 as a calculation result. Further, the register 15 stores an output “0” to the signal line L257 of the calculation execution flag generation circuit 16 and outputs it by a signal L310.

Thus, the addition of “1000000000000000000000000000 × 16 ² ” + “7FFFFFFFFFFFFFFFFFFFFFFFFFFF × 16 ⁴ ” is completed, and the floating-point addition / subtraction circuit 46 of FIG. 2A outputs the floating-point addition / subtraction result through the signal line L301. The floating point calculation result selection circuit 49 outputs the addition result of the extended precision of the signal line L301 to the instruction issue control circuit 42 through the signal line L401, and one calculation of the extended precision is completed.

The solution of this addition is “800FFFFFFFFFFFFFFFFFFFFFFFFF × 16 ⁴ ”. Thus, the numerical value of the exponent of the signal line L219 is “04”, and the numerical value of the mantissa is “800FFFFFFFFFFFFFFFFFFFFFFFFF” in the signal line L218.

  Similarly, the floating point multiplication circuit 47 of the floating point arithmetic circuit 41 shown in FIG. 2 outputs the extended precision arithmetic result to the signal line L303, and the floating point division circuit 48 outputs the extended precision arithmetic result to the signal line L305. These extended precision arithmetic results are returned from the floating-point arithmetic result selection circuit 49 to the instruction issuance control circuit 42, and one arithmetic operation with the extended precision of addition / subtraction, multiplication and division is completed.

(Operation procedure of single / double precision calculation of extended precision data width arithmetic circuit 12)
Hereinafter, the operation of double-precision data width calculation, “10000000000000000xxxxxxxxxxxx × 16 ² ” (added data) “added data” + “7FFFFFFFFFFFFFxxxxxxxxxxxx × 16 ⁴ ” (added data) will be described. The floating-point arithmetic data to be handled is the so-called standard exponent data format, extended exponent data format, and IEEE exponent data format. The standard data format shown in FIG. 6 (code data 1 bit, exponent data 7 bits, 2 digits 16 This is described using a hexadecimal notation and a mantissa data of 56 bits (hexadecimal notation of 14 digits).

  FIG. 21 and FIG. 22 are diagrams showing each register value 2100 and each signal line value 2200 in the description of the operation.

  First, a numerical value “00” or “11” is stored in the register 1 as an operation instruction for the signal line L100 from the instruction issuance control circuit 42. The signal line L200 from the register 1 is input to the operation execution flag generation circuit 16, and the operation execution flag is output as "1" to the signal line L257 in accordance with the logic 700 of FIG. Double precision data input from the signal lines L104 to L106 is selected as an operation code, an operation index, and an operation mantissa when the operation execution flag is “1”. Further, “1” of the operation execution flag is stored in the register 15 and output from the signal line L310, and is used for selection of the operation result in the floating-point operation result selection circuit 49 shown in FIG. 2A.

  Next, as the addition instruction for the signal line L100 from the instruction issuance control circuit 42, the numerical value “01” of the addition instruction is stored in the register 1. In addition, based on the added data and the added data having the double precision data width described above, the sign value “0” (plus sign) of the added data is stored in the register 2, and the sign value “0” (plus sign) of the added data is stored in the register 4. ) Is stored. Further, the added mantissa data value “10000000000000xxxxxxxxxxxx” is stored in the register 10, and the added mantissa data value “7FFFFFFFFFFFFFxxxxxxxxxxxx” is stored in the register 12, respectively.

  The arithmetic instruction analysis circuit 20, similarly to the arithmetic operation with extended precision, calculates the numerical value “01” (addition instruction) of the arithmetic instruction of the signal line L 200, the numerical value “0” (positive sign) of the signal line L 253, and the signal line L 254. 7 is analyzed from the calculation instruction generation logic 700 of FIG. 7 and a numerical value “0” (addition instruction) is output to the signal line L207.

  Exponential processing is the same as that for extended precision calculation. The exponent magnitude comparison circuit 21 compares the numerical value “02” of the added exponent data of the signal line L255 with the numeric value “04” of the added exponent data of the signal line L256. As a comparison result, the exponent magnitude comparison logic 1100 in FIG. 11 determines that the exponent data of the signal line L256 is large, and outputs a numerical value “0” to the signal line L211 as an exponent magnitude comparison result signal. The reference exponent selection circuit 22 selects the numeric value “04” of the signal line L256, which is large added exponent data, from the reference exponent selection logic 1200 of FIG. 12 based on the condition of the numeric value “0” of the exponent magnitude comparison result of the signal line L211. To the signal line L209. The shift amount calculation circuit 23 obtains the difference between the exponent value “02” of the added data of the signal line L255 and the exponent value “04” of the added data of the signal line L256, and the right shift amount for digit alignment The numerical value “2” is output to the signal line L210.

  Since the exponent magnitude comparison result signal of the signal line L211 is “0” and the exponent of the addition data is large, the mantissa selection circuit 25 has the mantissa of the addition data and the mantissa of the addition data from the addition mantissa data selection result logic 1400 of FIG. It is judged that the replacement with is unnecessary. Accordingly, the added mantissa data of the signal line L258 is selected, and the added mantissa data “10000000000000xxxxxxxxxxxx” is output to the signal line L212.

  On the other hand, from the selection logic 1500 of the added mantissa data and the added inverted mantissa data in FIG. 15, the numerical value of the added mantissa data of the signal line L259, “7FFFFFFFFFFFFFxxxxxxxxxxxx” is output to the signal line L280. Further, the complement of the signal line L259, “10000000000000xxxxxxxxxxxx” is output to the signal line L281. Then, on the condition of “0 (addition)” of the operation instruction analysis result signal of the signal line L207, the addition mantissa data selection logic 1600 of FIG. Select and output as selection signal. Since the digit alignment right shift circuit 27 shifts right by two digits based on the value “2” of the right shift amount signal of the signal line L210, “00100000000000xxxxxxxxxxxx” is output to the signal line L215 as the mantissa value of the added data. To do. The addition / subtraction circuit 29 adds the numerical value “00100000000000000xxxxxxxxxxxx” of the signal line L215 and the numerical value “7FFFFFFFFFFFFFxxxxxxxxxxxx” of the signal line L213. The numerical value of the addition result, “800FFFFFFFFFFFxxxxxxxxxxxx” is output to the signal line L216.

  The check of the 0 digit number check circuit 28 is different between the case of the extended precision and the case of the double precision. The 0-digit number check circuit 28 checks whether or not the numerical value “0” exists in the upper digit starting with “8” of the numerical value “800FFFFFFFFFFFxxxxxxxxxxxx” of the addition result signal of the signal line L216. When it is confirmed that the beginning of the numerical value of the signal line L216 is “8” and the numerical value of “1” exists in the leading data, the numerical value “0” of the 0-digit number check signal is output to the signal line L217. Since “0” of the signal line L217 does not require a left shift for normalization, the normalized left shift circuit 31 does not perform a left shift for normalization. As a result, the numerical value “800FFFFFFFFFFFxxxxxxxxxxxx” is represented by the signal line L218. Output to.

  The exponent generation / subtraction circuit 30 subtracts the numeric value “0” of the zero-digit number check signal of the signal line L217 from the numeric value “04” of the reference exponent selection result of the signal line L209, and the exponent data numeric value “04” to the signal line L219. "Is output.

  The intermediate code generation circuit 24 calculates the value “0” of the exponent magnitude comparison result signal of the signal line L211 and the condition “0” of the added code data of the signal line L253 and the added code data of the signal line L254 of FIG. From the intermediate code generation logic 1700, the numerical value “0” (positive code) of the sign of the large exponent of the signal line L254 is output to the signal line L208. Then, the sign generation circuit 26 outputs “0” to the signal line L220 because it does not subtract the large added mantissa data from the small added mantissa data from the numerical value of the added mantissa and the added mantissa for performing the operation. Based on the condition “0” of the signal line L220, the code generation logic 1700 in FIG. 18 outputs a numerical value “0” (plus sign) to the signal line L214 without inverting the sign.

The register 14 stores the code value “0” (plus sign) of the signal line L214 generated by the code generation circuit 26. Further, the exponent data “04” of the signal line L219 obtained by the exponent generation / subtraction circuit 30 and the mantissa data “800FFFFFFFFFFFxxxxxxxxxxxx” output from the normalized left shift circuit 31 to the signal line L218 are stored. And it outputs by the signal line L301 as a calculation result. Further, the register 15 stores an output “0” to the signal line L257 of the calculation execution flag generation circuit 16 and outputs it by a signal L310.

This completes the addition of the double precision “0010000000000000xxxxxxxxxxxx × 16 ² ” + “7FFFFFFFFFFFFFxxxxxxxxxxxx × 16 ⁴ ”, and outputs the floating point addition / subtraction result from the floating point addition / subtraction circuit 46 of FIG. 2A via the signal line L301.

  Similarly, the floating point multiplication circuit 47 of the floating point arithmetic circuit 41 shown in FIG. 2 outputs two double-precision arithmetic results in parallel with the signal lines L302 and L303, and the floating point division circuit 48 in parallel with the signal lines L304 and L305. Outputs two double-precision arithmetic results. These two precision results are returned from the floating-point computation result selection circuit 49 to the instruction issuance control circuit 42 in parallel by signal lines L400 and L401, and are added twice in double precision of addition / subtraction, multiplication and division, respectively. The computation is complete.

  The operation procedure at the time of extended precision calculation or double precision calculation of the extended precision data width arithmetic circuit 12 has been described above. The operation procedure of the single-precision / double-precision data width calculation circuit 11 is similar to the operation procedure at the time of double-precision calculation of the extended-precision data width calculation circuit 12 when the extended-precision calculation is stopped and no calculation data is selected.

  According to this embodiment, an arithmetic circuit with a 128-bit extended precision data width can execute a 32-bit single-precision data width and a 64-bit double-precision data width. Accordingly, the calculation time can be reduced to ½ by performing the calculation in parallel with the two arithmetic circuits of the existing single-precision / double-precision data width arithmetic circuit and the extended precision arithmetic circuit. The reason is that a circuit for detecting that the extended arithmetic circuit is executing or not in use is provided. In addition, when an arithmetic circuit with an extended data width is not used, a circuit is provided that can execute single-precision double precision and arithmetic data with an extended precision data width by allocating them to the extended arithmetic circuit. The present embodiment exhibits a more remarkable effect especially in a large number of repetitive operations in a vector operation in a supercomputer or the like.

[Other Embodiments]
As mentioned above, although embodiment of this invention was explained in full detail, the system or apparatus which combined the separate characteristic contained in each embodiment how was included in the category of this invention.

  Further, the present invention may be applied to a system composed of a plurality of devices, or may be applied to a single device. Furthermore, the present invention can also be applied to a case where an arithmetic control program that realizes the functions of the embodiment is supplied directly or remotely to a system or apparatus. Therefore, in order to realize the functions of the present invention on a computer, an arithmetic control program installed in the computer, a storage medium storing the arithmetic control program, and a WWW server that downloads the arithmetic control program are also included in the scope of the present invention. included.

[Other expressions of embodiment]
A part or all of the above-described embodiment can be described as in the following supplementary notes, but is not limited thereto.
(Appendix 1)
A floating-point arithmetic circuit having a plurality of arithmetic circuits each performing a floating-point arithmetic on a numerical value of a first bit width and a numerical value of a second bit width shorter than the first bit width,
Pause determining means for determining whether the first arithmetic circuit for performing the calculation of the first bit width is paused based on an arithmetic instruction;
When the pause determination means determines that the first arithmetic circuit is paused, the first arithmetic circuit is controlled to perform a calculation of the numerical value of the second bit width, and the calculation of the numerical value of the second bit width is Arithmetic control means for executing in parallel by the first arithmetic circuit and a second arithmetic circuit for calculating a numerical value of the second bit width;
A floating-point arithmetic circuit comprising:
(Appendix 2)
The supplementary note 1 includes input means for selectively inputting the numerical value of the first bit width and the numerical value of the second bit width to the first arithmetic circuit according to the determination result of the pause determination means. The floating-point arithmetic circuit described.
(Appendix 3)
An output for selecting and outputting the calculation result obtained by the first calculation circuit calculating the numerical value of the second bit width and the calculation result of the second calculation circuit calculating the numerical value of the second bit width in the calculation control means. The floating point arithmetic circuit according to appendix 1 or 2, further comprising: means.
(Appendix 4)
The first arithmetic circuit includes:
An operation determination means for determining whether an operation instruction to the first operation circuit is an operation on the numerical value of the first bit width;
When the operation determining means determines that the operation is for the numerical value of the first bit width, a floating point operation is performed on the numerical value of the first bit width, and the operation determining means is If it is determined that the operation is not a numerical value, an arithmetic execution means for performing a floating point operation on the numerical value of the second bit width;
The floating-point arithmetic circuit according to any one of appendices 1 to 3, wherein the floating-point arithmetic circuit includes:
(Appendix 5)
The calculation determination means includes
An operation instruction register for storing operation instructions; and
A calculation execution flag generating means for detecting whether to pause the first calculation circuit based on a value of an output signal of the calculation instruction register and generating a calculation execution flag;
An in-execution flag storage register for storing the in-operation flag indicating whether or not to pause the first arithmetic circuit generated by the in-operation flag generation unit;
The calculation execution means includes
When the operation execution flag indicates that the operation is being executed, the sign, exponent, and mantissa included in the numerical value of the first bit width are selected and transmitted to a circuit group that realizes a floating-point operation, and the operation is performed. A selection means for selecting a sign, an exponent, and a mantissa included in the numerical value of the second bit width and transmitting them to a circuit group for realizing a floating-point operation when the execution flag indicates that the operation is not being executed;
5. The floating point arithmetic circuit according to any one of appendices 1 to 4, further comprising: an arithmetic result storage register that stores a floating point arithmetic result obtained from a circuit group that realizes the floating point arithmetic.
(Appendix 6)
A floating-point arithmetic circuit that performs floating-point arithmetic on an extended bit-width number,
An operation determination means for determining whether an operation instruction to the floating-point arithmetic circuit is an operation on an extended bit width value;
If the operation determining means determines that the operation is an operation on an extended bit width value, the floating point operation is performed on the extended bit width value, and the operation determining means is an extended bit width value. If it is determined that the operation is not for the operation, operation execution means for performing a floating point operation of a numerical value having a bit width shorter than the expanded bit width,
A floating-point arithmetic circuit comprising:
(Appendix 7)
The calculation determination means includes
An operation instruction register for storing an input operation instruction;
A calculation execution flag generating means for detecting whether to pause the floating-point calculation circuit based on the value of the output signal of the calculation instruction register and generating a calculation execution flag;
An execution flag storage register that stores the calculation execution flag generated by the calculation execution flag generation unit;
The calculation execution means includes
When the operation execution flag indicates that the operation is being executed, the sign, exponent, and mantissa included in the extended bit-width value are selected and transmitted to a circuit group that realizes a floating-point operation, and When the operation execution flag indicates that the operation is not being executed, the sign, exponent, and mantissa included in the numerical value having a bit width shorter than the extended bit width are selected and transmitted to the circuit group that realizes the floating-point operation. A selection means;
A calculation result storage register for storing a floating point calculation result from a circuit group for realizing the floating point calculation;
The floating point arithmetic circuit according to appendix 6, characterized by comprising:
(Appendix 8)
When the operation performed by the floating point arithmetic circuit is addition or subtraction,
The calculation execution means includes
A reference index selection circuit that selects an index suitable for the data width of the index based on the calculation execution flag;
A shift amount calculation circuit for determining an exponent difference based on the calculation execution flag and determining a digit-aligned right shift amount; and
A first register storing a mantissa of first data;
A second register storing a mantissa of second data;
Of the mantissa of the first data and the mantissa of the second data, the one with the smaller exponent is output as a mantissa requiring digit alignment based on the in-operation flag, and the other is output as a mantissa requiring no digit alignment. A mantissa selection circuit;
The mantissa requiring digit alignment output from the mantissa selection circuit is shifted to the right by a shift amount corresponding to the difference between the mantissa of the first data and the exponent during execution of the second data, Digit shift right shift circuit that outputs the result
Addition / subtraction circuit for performing addition / subtraction between the result of shifting the mantissa requiring digit alignment output from the digit alignment right shift circuit and the mantissa not requiring digit alignment output from the mantissa selection circuit, and outputting the addition / subtraction result When,
A normalized left shift circuit that normalizes the addition / subtraction result output from the addition / subtraction circuit;
The floating point arithmetic circuit according to appendix 7, characterized by comprising:
(Appendix 9)
A floating-point arithmetic circuit that performs floating-point arithmetic on an extended bit-width number,
An operation instruction register for storing an input operation instruction;
Generates an in-execution flag that detects whether or not to stop the floating-point operation with the extended bit width by the floating-point operation circuit based on the value of the output signal of the operation instruction register and generates an in-operation flag Circuit,
An execution flag storage register for storing the operation execution flag generated by the operation execution flag generation circuit;
A first register group for storing the sign, exponent, and mantissa of the input operation data having an extended bit width and the sign, exponent, and mantissa of the operation data;
A second register group for storing the sign, exponent, and mantissa of the input unexpanded bit-width operand data, and the sign, exponent, and mantissa of the operation data;
The first register group is selected when the operation in progress flag indicates that the floating point operation with an extended bit width is performed by the floating point operation circuit, and the operation execution flag is in the floating point operation circuit. A sign, exponent and mantissa selection circuit for selecting the second register group when indicating that the floating-point operation with the extended bit width by
A code generation circuit for generating a code of a calculation result based on a calculation instruction, a sign of operation data, and a sign of calculation data;
An exponent generation circuit that adjusts the exponent of the operand data and the exponent of the operand data based on the arithmetic instruction, the sign of the operand data, and the sign of the operand data;
In accordance with the adjustment of the exponent of the operand data and the exponent of the calculation data in the exponent generation circuit, the mantissa calculation that generates the mantissa of the calculation result by aligning the mantissa of the operand data with the mantissa of the calculation data Circuit,
A matching circuit for matching the exponent and mantissa of the operation result;
A calculation result storage register for storing a sign of the calculation result and an exponent and mantissa of the calculation result matched by the matching circuit;
The floating flag stored in the in-execution flag storage register and the sign, exponent, and mantissa of the operation result stored in the operation result storage register are output as a floating-point operation result. Decimal point arithmetic circuit.
(Appendix 10)
A computer having a floating-point arithmetic circuit having a plurality of arithmetic circuits that perform floating-point arithmetic on numerical values having different bit widths,
The first arithmetic circuit is
An operation determination means for determining whether an operation instruction to the first operation circuit is an operation on a numerical value of a first bit width or an operation on a numerical value of a second bit width shorter than the first bit width;
When the operation determining means determines that the operation is for the numerical value of the first bit width, a floating point operation of the numerical value of the first bit width is executed, and the operation determining means is for the numerical value of the second bit width. And a calculation execution means for executing a floating point calculation of the numerical value of the second bit width when it is determined as a calculation,
A second arithmetic circuit for performing a floating point arithmetic operation on the numerical value of the second bit width,
When the operation instruction to the floating point arithmetic circuit indicates that the operation on the numerical value of the first bit width is suspended, the floating point arithmetic operation of the numerical value of the second bit width is performed with the first arithmetic circuit and the second arithmetic circuit. A computer that is executed in parallel by an arithmetic circuit.
(Appendix 11)
Input means for selectively inputting the numerical value of the first bit width and the numerical value of the second bit width to the first arithmetic circuit according to a determination result of the pause determination means;
An output for selecting and outputting the calculation result obtained by the first calculation circuit calculating the numerical value of the second bit width and the calculation result of the second calculation circuit calculating the numerical value of the second bit width in the calculation control means. The computer according to appendix 10, characterized by comprising: means.
(Appendix 12)
The computer issues, to the first arithmetic circuit, at least an arithmetic instruction indicating that the arithmetic operation is performed on the second bit width value when the arithmetic operation on the first bit width value is suspended. 12. The computer according to appendix 10 or 11, further comprising instruction issue control means for providing a numerical value with a 2-bit width to the first arithmetic circuit and the second arithmetic circuit.
(Appendix 13)
Connected to the instruction issue control means and provides the instruction issue control means with the arithmetic instruction and the numerical value of the first bit width and the numerical value of the second bit width to be calculated in the floating point arithmetic circuit. Main storage means for temporarily storing the operation result calculated in the floating-point arithmetic circuit;
And an external storage means connected to the instruction issue control means via an input / output control means for controlling the input / output of data, and for storing a calculation result calculated in the floating point arithmetic circuit. The computer of any one of thru | or 12.
(Appendix 14)
An arithmetic control method for a computer having a floating point arithmetic circuit having a plurality of arithmetic circuits each performing a floating point arithmetic on numerical values having different bit widths,
A reading step of reading the arithmetic program from the storage means;
A determination step of analyzing an instruction of the arithmetic program and determining whether a numerical value to be calculated in the floating-point arithmetic circuit is a first bit width or a second bit width shorter than the first bit width;
When the numerical value to be calculated in the floating-point arithmetic circuit is the first bit width, the first arithmetic circuit for performing the operation of the first bit width is provided with the arithmetic instruction of the first bit width and the numerical value to be calculated. A first calculation step of obtaining a calculation result of the first bit width from the first calculation circuit;
When the numerical value to be calculated in the floating-point arithmetic circuit is the second bit width, the first arithmetic circuit that performs the operation of the first bit width and the second arithmetic circuit that performs the operation of the second bit width are connected in parallel. A second operation step of providing an operation instruction of the second bit width and a numerical value to be operated, and obtaining an operation result of the second bit width in parallel from the first operation circuit and the second operation circuit;
An arithmetic control method comprising:
(Appendix 15)
An arithmetic control program for a computer comprising a floating point arithmetic circuit having a plurality of arithmetic circuits that respectively perform floating point arithmetic on numerical values of different bit widths,
A reading step of reading the arithmetic program from the storage means;
A determination step of analyzing an instruction of the arithmetic program and determining whether a numerical value to be calculated in the floating-point arithmetic circuit is a first bit width or a second bit width shorter than the first bit width;
When the numerical value to be calculated in the floating-point arithmetic circuit is the first bit width, the first arithmetic circuit for performing the operation of the first bit width is provided with the arithmetic instruction of the first bit width and the numerical value to be calculated. A first calculation step of obtaining a calculation result of the first bit width from the first calculation circuit;
When the numerical value to be calculated in the floating-point arithmetic circuit is the second bit width, the first arithmetic circuit that performs the operation of the first bit width and the second arithmetic circuit that performs the operation of the second bit width are connected in parallel. A second operation step of providing an operation instruction of the second bit width and a numerical value to be operated, and obtaining an operation result of the second bit width in parallel from the first operation circuit and the second operation circuit; An arithmetic control program for causing a computer to execute.

Claims (10)

A floating-point arithmetic circuit having a plurality of arithmetic circuits each performing a floating-point arithmetic on a numerical value of a first bit width and a numerical value of a second bit width shorter than the first bit width,
Pause determining means for determining whether the first arithmetic circuit for performing the calculation of the first bit width is paused based on an arithmetic instruction;
When the pause determination means determines that the first arithmetic circuit is paused, the first arithmetic circuit is controlled to perform a calculation of the numerical value of the second bit width, and the calculation of the numerical value of the second bit width is Arithmetic control means for executing in parallel by the first arithmetic circuit and a second arithmetic circuit for calculating a numerical value of the second bit width;
A floating-point arithmetic circuit comprising: The first arithmetic circuit includes:
An operation determination means for determining whether an operation instruction to the first operation circuit is an operation on the numerical value of the first bit width;
When the operation determining means determines that the operation is for the numerical value of the first bit width, a floating point operation is performed on the numerical value of the first bit width, and the operation determining means is If it is determined that the operation is not a numerical value, an arithmetic execution means for performing a floating point operation on the numerical value of the second bit width;
The floating point arithmetic circuit according to claim 1, further comprising: The calculation determination means includes
An operation instruction register for storing operation instructions; and
A calculation execution flag generating means for detecting whether to pause the first calculation circuit based on a value of an output signal of the calculation instruction register and generating a calculation execution flag;
An in-execution flag storage register for storing the in-operation flag indicating whether or not to pause the first arithmetic circuit generated by the in-operation flag generation unit;
The calculation execution means includes
When the operation execution flag indicates that the operation is being executed, the sign, exponent, and mantissa included in the numerical value of the first bit width are selected and transmitted to a circuit group that realizes a floating-point operation, and the operation is performed. A selection means for selecting a sign, an exponent, and a mantissa included in the numerical value of the second bit width and transmitting them to a circuit group for realizing a floating-point operation when the execution flag indicates that the operation is not being executed;
The floating point arithmetic circuit according to claim 1, further comprising: an arithmetic result storage register that stores a floating point arithmetic result obtained from a circuit group that realizes the floating point arithmetic. A floating-point arithmetic circuit that performs floating-point arithmetic on an extended bit-width number,
An operation determination means for determining whether an operation instruction to the floating-point arithmetic circuit is an operation on an extended bit width value;
If the operation determining means determines that the operation is an operation on an extended bit width value, the floating point operation is performed on the extended bit width value, and the operation determining means is an extended bit width value. If it is determined that the operation is not for the operation, operation execution means for performing a floating point operation of a numerical value having a bit width shorter than the expanded bit width,
A floating-point arithmetic circuit comprising: The calculation determination means includes
An operation instruction register for storing an input operation instruction;
A calculation execution flag generating means for detecting whether to pause the floating-point calculation circuit based on the value of the output signal of the calculation instruction register and generating a calculation execution flag;
An execution flag storage register that stores the calculation execution flag generated by the calculation execution flag generation unit;
The calculation execution means includes
When the operation execution flag indicates that the operation is being executed, the sign, exponent, and mantissa included in the extended bit-width value are selected and transmitted to a circuit group that realizes a floating-point operation, and When the operation execution flag indicates that the operation is not being executed, the sign, exponent, and mantissa included in the numerical value having a bit width shorter than the extended bit width are selected and transmitted to the circuit group that realizes the floating-point operation. A selection means;
A calculation result storage register for storing a floating point calculation result from a circuit group for realizing the floating point calculation;
5. The floating point arithmetic circuit according to claim 4, further comprising: When the operation performed by the floating point arithmetic circuit is addition or subtraction,
The calculation execution means includes
A reference index selection circuit that selects an index suitable for the data width of the index based on the calculation execution flag;
A shift amount calculation circuit for determining an exponent difference based on the calculation execution flag and determining a digit-aligned right shift amount; and
A first register storing a mantissa of first data;
A second register storing a mantissa of second data;
Of the mantissa of the first data and the mantissa of the second data, the one with the smaller exponent is output as a mantissa requiring digit alignment based on the in-operation flag, and the other is output as a mantissa requiring no digit alignment. A mantissa selection circuit;
The mantissa requiring digit alignment output from the mantissa selection circuit is shifted to the right by a shift amount corresponding to the difference between the mantissa of the first data and the exponent during execution of the second data, Digit shift right shift circuit that outputs the result
Addition / subtraction circuit for performing addition / subtraction between the result of shifting the mantissa requiring digit alignment output from the digit alignment right shift circuit and the mantissa not requiring digit alignment output from the mantissa selection circuit, and outputting the addition / subtraction result When,
A normalized left shift circuit that normalizes the addition / subtraction result output from the addition / subtraction circuit;
The floating point arithmetic circuit according to claim 5, further comprising: A floating-point arithmetic circuit that performs floating-point arithmetic on an extended bit-width number,
An operation instruction register for storing an input operation instruction;
Generates an in-execution flag that detects whether or not to stop the floating-point operation with the extended bit width by the floating-point operation circuit based on the value of the output signal of the operation instruction register and generates an in-operation flag Circuit,
An execution flag storage register for storing the operation execution flag generated by the operation execution flag generation circuit;
A first register group for storing the sign, exponent, and mantissa of the input operation data having an extended bit width and the sign, exponent, and mantissa of the operation data;
A second register group for storing the sign, exponent, and mantissa of the input unexpanded bit-width operand data, and the sign, exponent, and mantissa of the operation data;
The first register group is selected when the operation in progress flag indicates that the floating point operation with an extended bit width is performed by the floating point operation circuit, and the operation execution flag is in the floating point operation circuit. A sign, exponent and mantissa selection circuit for selecting the second register group when indicating that the floating-point operation with the extended bit width by
A code generation circuit for generating a code of a calculation result based on a calculation instruction, a sign of operation data, and a sign of calculation data;
An exponent generation circuit that adjusts the exponent of the operand data and the exponent of the operand data based on the arithmetic instruction, the sign of the operand data, and the sign of the operand data;
In accordance with the adjustment of the exponent of the operand data and the exponent of the calculation data in the exponent generation circuit, the mantissa calculation that generates the mantissa of the calculation result by aligning the mantissa of the operand data with the mantissa of the calculation data Circuit,
A matching circuit for matching the exponent and mantissa of the operation result;
A calculation result storage register for storing a sign of the calculation result and an exponent and mantissa of the calculation result matched by the matching circuit;
The floating flag stored in the in-execution flag storage register and the sign, exponent, and mantissa of the operation result stored in the operation result storage register are output as a floating-point operation result. Decimal point arithmetic circuit. A computer having a floating-point arithmetic circuit having a plurality of arithmetic circuits that perform floating-point arithmetic on numerical values having different bit widths,
The first arithmetic circuit is
An operation determination means for determining whether an operation instruction to the first operation circuit is an operation on a numerical value of a first bit width or an operation on a numerical value of a second bit width shorter than the first bit width;
When the operation determining means determines that the operation is for the numerical value of the first bit width, a floating point operation of the numerical value of the first bit width is executed, and the operation determining means is for the numerical value of the second bit width. And a calculation execution means for executing a floating point calculation of the numerical value of the second bit width when it is determined as a calculation,
A second arithmetic circuit for performing a floating point arithmetic operation on the numerical value of the second bit width,
When the operation instruction to the floating point arithmetic circuit indicates that the operation on the numerical value of the first bit width is suspended, the floating point arithmetic operation of the numerical value of the second bit width is performed with the first arithmetic circuit and the second arithmetic circuit. A computer that is executed in parallel by an arithmetic circuit. An arithmetic control method for a computer having a floating point arithmetic circuit having a plurality of arithmetic circuits each performing a floating point arithmetic on numerical values having different bit widths,
A reading step of reading the arithmetic program from the storage means;
A determination step of analyzing an instruction of the arithmetic program and determining whether a numerical value to be calculated in the floating-point arithmetic circuit is a first bit width or a second bit width shorter than the first bit width;
When the numerical value to be calculated in the floating-point arithmetic circuit is the first bit width, the first arithmetic circuit for performing the operation of the first bit width is provided with the arithmetic instruction of the first bit width and the numerical value to be calculated. A first calculation step of obtaining a calculation result of the first bit width from the first calculation circuit;
When the numerical value to be calculated in the floating-point arithmetic circuit is the second bit width, the first arithmetic circuit that performs the operation of the first bit width and the second arithmetic circuit that performs the operation of the second bit width are connected in parallel. A second operation step of providing an operation instruction of the second bit width and a numerical value to be operated, and obtaining an operation result of the second bit width in parallel from the first operation circuit and the second operation circuit;
An arithmetic control method comprising: An arithmetic control program for a computer comprising a floating point arithmetic circuit having a plurality of arithmetic circuits that respectively perform floating point arithmetic on numerical values of different bit widths,
A reading step of reading the arithmetic program from the storage means;
A determination step of analyzing an instruction of the arithmetic program and determining whether a numerical value to be calculated in the floating-point arithmetic circuit is a first bit width or a second bit width shorter than the first bit width;
When the numerical value to be calculated in the floating-point arithmetic circuit is the first bit width, the first arithmetic circuit for performing the operation of the first bit width is provided with the arithmetic instruction of the first bit width and the numerical value to be calculated. A first calculation step of obtaining a calculation result of the first bit width from the first calculation circuit;
When the numerical value to be calculated in the floating-point arithmetic circuit is the second bit width, the first arithmetic circuit that performs the operation of the first bit width and the second arithmetic circuit that performs the operation of the second bit width are connected in parallel. A second operation step of providing an operation instruction of the second bit width and a numerical value to be operated, and obtaining an operation result of the second bit width in parallel from the first operation circuit and the second operation circuit; An arithmetic control program for causing a computer to execute.

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