JP2012109713A - Bias circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a bias circuit that protects a receiving transistor against damage from excessive input in a simple configuration and shortens time for recovery to a steady state operation after the resolution of the excessive input.SOLUTION: The bias circuit for use with a receiving amplifier is so constructed that a resistor is connected in series between a drain electrode of a field effect transistor and a drain bias terminal, at least two resistors are connected in series between the drain electrode and a gate bias terminal, and a junction connecting two of the two or more series-connected resistors is connected to a gate electrode.

Description

  The present invention relates to a bias circuit for a high-frequency semiconductor device, and more particularly to prevention of destruction at the time of excessive input of a receiving amplifier and improvement of an electric characteristic return speed after cancellation of excessive input.

  Conventionally, a variable bias circuit is provided in a unit amplifier of an FET amplifier, and the variable bias circuit includes a bias resistor that determines a gate side bias potential of the unit amplifier and a control transistor that controls a bias amount in combination with the bias resistor. When the microwave signal input level of the FET amplifier exceeds the rated level of the FET, the voltage drop of the gate current detection resistor connected to the gate side bias circuit of the FET at the final stage of the FET amplifier is detected, and the output is accordingly generated. The control signal is input to the control transistor, and the drain current is narrowed by changing the gate side bias potential of the FET, or the drain current of the FET is directly reduced to protect against over-input (for example, Patent Documents) 1).

JP-A 64-22102

  However, the variable bias circuit having such a configuration is complicated and has a problem of high cost.

  The present invention has been made in order to solve the above-described problems, and has a simple configuration for preventing the receiving transistor from being destroyed by over-input, and after the over-input has been eliminated, the operation returns to the steady operation. An object is to obtain a bias circuit whose time is shortened.

  The bias circuit according to the present invention is a bias circuit used in a receiving amplifier, wherein a resistor is connected in series between a drain electrode and a drain bias terminal of a field effect transistor, and the drain electrode and the gate bias terminal are connected. At least two or more resistors are connected in series to each other, and a connection point where two of the two or more resistors connected in series are connected to the gate electrode.

  In the bias circuit according to the present invention, the gate voltage increases as the drain voltage increases immediately after the over-input is eliminated, and the drain current increases, so that the over-input is eliminated and then returns to the steady state. There is an effect that the time until the time can be shortened.

1 is a circuit diagram of a receiving amplifier according to a first embodiment of the present invention. It is a circuit diagram of the receiving amplifier which concerns on Embodiment 2 of this invention. It is a circuit arrangement | positioning figure of the receiving amplifier which concerns on Embodiment 3 of this invention. It is a circuit diagram of the receiving amplifier which concerns on Embodiment 3 of this invention. It is a circuit diagram of a conventional receiving amplifier. 6 is a circuit in which a resistor is added to the conventional receiving amplifier shown in FIG. It is a calculation result expressing the amount of decrease in drain current due to excessive input as voltage VG_offset.

Hereinafter, preferred embodiments of a bias circuit of the present invention will be described with reference to the drawings.
Embodiment 1 FIG.
1 is a circuit diagram of a receiving amplifier according to Embodiment 1 of the present invention.
In the receiving amplifier according to the first embodiment of the present invention, the bias circuit controls the gate side bias of the receiving transistor 2. The reception transistor 2 has a gate electrode connected to the reception signal input terminal 1, a drain electrode connected to the reception signal output terminal 7, and a source electrode grounded. In the receiving transistor 2, the matching circuit 3a is connected to the gate electrode, and the junction circuit 3b is also connected to the drain electrode.

  The bias circuit of the receiving amplifier according to the first embodiment of the present invention includes a bias line also used as a matching circuit 3a, one end of which is connected to the gate electrode of the receiving transistor 2, and one end of the drain electrode of the receiving transistor 2. A bias line that is also used as a matching circuit 3b connected to the same, a high-frequency short-circuit capacitor 4a connected to the other end of the grounded matching circuit 3a, and a high-frequency short-circuit capacitor connected to the other end of the grounded matching circuit 3a 4b, a resistor 8 having one end connected to the drain voltage application terminal 6 as a drain bias terminal and the other end connected to the other end of the matching circuit 3b, and one end connected to the other end of the matching circuit 3b. One end is connected to the resistor 9 having the other end connected to the connection point 12 and the gate voltage application terminal 5 serving as a gate bias terminal, and the other end is connected to the connection point 1. It comprises a resistor 10, which is connected to.

The resistance values R ₈ , R ₉ and R ₁₀ of the resistors ₈ , ₉ and ₁₀ are set in advance so that an appropriate bias is applied to the receiving transistor 2. That is, the operating drain current of the receiving transistor 2 is I _d , the operating drain voltage is V _d , the operating gate voltage is V _g , the voltage input to the gate voltage application terminal 5 is V _gg , and the voltage input to the drain voltage application terminal 6 When V _dd is V _dd , the relations of the expressions (1) and (2) are established, and the resistance value is determined using this relational expression.

V _d = V _dd −R ₈ × I _d (1)
(V _d −V _g ) :( V _g −V _gg ) = R ₉ : R ₁₀ (2)

Next, the operation of the bias circuit according to the first embodiment of the present invention will be described.
The drain current I _d of the receiving transistor 2 is increased at the time of excessive input. Since the drain voltage V _d applied to the receiving transistor 2 according this case equation (1) decreases, the receiving transistor 2 can be prevented from being destroyed.
By the way, it is known that immediately after the over-input is eliminated, the drain current _Id is reduced from that in the steady state due to the influence of heat generated by the over-input and the charging effect caused by the high electric field generated inside the transistor at the time of the over-input. It has been. As a result, there is a problem that the gain of the receiving amplifier is lowered.

However, the drain voltage _Vd increases when the drain current _Id is small immediately after the over-input is eliminated. Since the gate voltage V _g applied to the receiving transistor 2 is a voltage obtained by dividing the drain voltage V _d and the gate voltage applied voltage V _gg by the resistance value R ₉ and the resistance value R ₁₀ , the gate voltage V _g increases when the drain voltage V _d increases. The voltage _Vg also increases.
When the gate voltage _Vg is increased, the drain current _Id is increased. Therefore, compared with the conventional bias circuit, it is possible to shorten the time from the cancellation of the excessive input to the return to the steady state. it can.

Embodiment 2. FIG.
FIG. 2 is a circuit diagram of a receiving amplifier according to Embodiment 2 of the present invention.
The receiving amplifier according to the second embodiment of the present invention is different in that a resistor 11 is connected in series to the source electrode of the receiving transistor 2 of the receiving amplifier according to the first embodiment of the present invention. Since they are the same, the same parts are denoted by reference numerals and description thereof is omitted.
The configuration of the bias circuit for controlling the gate side bias is the same as the configuration of the bias circuit described in the first embodiment, and the operation is also the same. Thus, the higher the gate voltage V _g with that drain voltage V _d immediately after the excessive input is eliminated is increased, by the drain current I _d increases, returning from excessive input is solved in a steady state Can be shortened.

In a depletion type field effect transistor, two types of voltage sources are usually required, ie, a negative voltage for the gate electrode and a positive voltage for the drain electrode, but a self-bias circuit in which a resistor 11 is connected in series to the source electrode. By adopting the configuration, the voltage V _gg input to the gate voltage application terminal 5 can be set to zero or a positive voltage to operate with a single power source.

Embodiment 3 FIG.
FIG. 3 is a circuit layout diagram of a receiving amplifier according to Embodiment 3 of the present invention.
The receiving amplifier according to the third embodiment of the present invention is obtained by configuring the receiving amplifier according to the first embodiment of the present invention in a monolithic integrated circuit, and the same reference numerals are given to the components.
The resistance value of the resistor 8 is about the same as the output impedance of the receiving transistor 2 made of a field effect transistor, and need not be so large. Also, a relatively high resistance value is required to set the drain voltage with high accuracy. As such a resistance requiring a relatively low resistance and an absolute accuracy of the resistance value, an implantation resistance that constitutes the resistance by injecting impurity ion atoms into the substrate by an ion implantation technique is suitable.

On the other hand, the absolute values of the resistance values of the resistors 9 and 10 may not be accurate if only the ratio is accurate when the gate voltage of the receiving transistor 2 is set. Moreover, in order to reduce the power consumed by the resistors 9, 10, it is desirable that the resistance is as high as possible. As described above, epi resistance using the two-dimensional electron gas in the substrate as it is as a resistor is suitable when high resistance is desired to be realized in a small size although absolute accuracy is not required.
In this way, a circuit can be configured in a small size while satisfying a necessary function by properly using an injection resistor and an epi resistor according to the application.

Embodiment 4 FIG.
In the fourth embodiment of the present invention, the calculation result of the drain current immediately after elimination of the excessive input of the receiving amplifier according to the first embodiment of the present invention will be described.
FIG. 4 shows a circuit diagram of a receiving amplifier according to Embodiment 3 of the present invention, and FIG. 5 is a circuit diagram of a conventional receiving amplifier in which the drain current immediately after elimination of excessive input is calculated for comparison. is there. FIG. 6 shows a circuit in which a resistor 8 is added to the conventional receiving amplifier shown in FIG.

In the following calculation, a DC equivalent circuit is used for simplicity.
The decrease in the drain current caused by the excessive input is expressed as a change in the pin-off voltage by the voltage VG_offset of the voltage source DCVS connected in series with the gate electrode. By increasing the voltage VG_offset, it is possible to increase the decrease in drain current due to excessive input.
In FIG. 7, the amount of decrease in drain current due to excessive input is expressed as a voltage VG_offset as a calculation result.
In a conventional receiving amplifier or a circuit in which a resistor 8 is added to the conventional receiving amplifier, when the voltage VG_offset is −1V, the drain current of 50 mA is greatly reduced to 4 mA or less in a steady state.
On the other hand, in the receiving amplifier according to the first embodiment of the present invention, when the voltage VG_offset is −1V, the drain current is flowing at 42 mA or more, and the time until the return to the steady state after the excessive input is eliminated is shortened. It is recognized that it can.

  DESCRIPTION OF SYMBOLS 1 Reception signal input terminal, 2 Reception transistor, 3a, 3b Matching circuit, 4a, 4b High frequency short circuit capacitor, 5 Gate voltage application terminal, 6 Drain voltage application terminal, 7 Reception signal output terminal, 8, 9, 10, 11 Resistance , 12 connection point.

Claims (3)

A bias circuit used in a receiving amplifier,
A resistor is connected in series between the drain electrode and the drain bias terminal of the field effect transistor,
At least two resistors are connected in series between the drain electrode and the gate bias terminal,
A bias circuit, wherein a connection point to which two of the two or more resistors connected in series are connected is connected to the gate electrode.   2. The bias circuit according to claim 1, wherein a self-bias resistor is connected to a source electrode of the field effect transistor.   3. The bias circuit according to claim 1, wherein the low-resistance resistor is an injection resistor, and the high-resistance resistor is an epi resistor.

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