JP2012095104A - Pattern insertion circuit for oor testing and pattern insertion method for oor testing - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a pattern insertion circuit for OOR testing for causing disturbance of LM, for confirming that a reception side correctly detects and releases OOR.SOLUTION: The pattern insertion circuit for OOR testing includes: a code inversion part 32 which, with OTU3 frame data DT-DTbeing inputted, inverts one bit (a) among the LM arranged at bottom two bits (aa) being the representation of MFAS in binary format, to (r); an alarm pattern generating part 33 which replaces the other bit (a) of the LM with the data (b) of code (0) or code (1) so that repetition of identical code is four times or less, and (r) from the code inversion part 32 is arranged at one bit, for generating a pattern (br) for OOR testing of 2 bit; and an alarm pattern insertion part 34 which replaces an LM of arbitrary lane with the pattern for ORR testing that is generated by the alarm pattern generating part 33.

Description

  The present invention relates to an OOR test pattern insertion circuit and an OOR test pattern insertion method in OTU3 (Optical-channel Transport Unit 3).

  ITU-T Recommendation G. 709 describes a method of transmitting OTU3 frame data using LLD (Logical Lane Distribution) (see, for example, Non-Patent Document 1). When transmitting OTU3 frame data using LLD, the signal sequence of OTU3 is distributed to four lanes in LLD. In addition, ITU-T Recommendation G. In 798, various alarms are defined for identifying a failure location when there is a failure when transmitting OTU frame data using LLD, one of which is OOR (Out of Recovery). (For example, see Non-Patent Document 2).

  FIG. 7 shows an example of lane allocation of OTU3 frame data using LLD. The frames are distributed to each lane while rotating so that MFAS (Multi Frame Alignment Signal) is inserted into all lanes. In the MFAS, an LM (Lane Marker) is inserted to distinguish lanes.

FIG. 8 shows the position of the LM in the OTU3 frame. The MFAS takes a value from 0 to 255 in decimal number display, a value from 0x00 to 0xFF in hexadecimal number display, and a value from 0000000 to 11111111 in binary display. The MFAS is incremented by 1 for each frame. The least significant 2 bits “a ₁ a ₀ ” of the MFAS “a ₇ a ₆ a ₅ a ₄ a ₃ a ₂ a ₁ a ₀ ” become the LM.

  The LM of each of the four lanes has a different value. On the receiving side, when the OTU3 frame data is normally received, the LM of a certain value embedded in the OTU3 frame data is received for each lane. If there is an abnormality in the OTU3 frame data due to signal interruption or skew fluctuation between lanes, the LM having the same value cannot be received, and an alarm is detected as OOR. The detection condition for detecting the OOR is reception of LM having a value different from that in the normal state for five consecutive frames. The cancellation condition for canceling the OOR is reception of an LM having a constant value for five consecutive frames. As a transmitting side function of the measuring instrument, a function that causes a disturbance of the LM value is required in order to confirm that the receiving side can correctly detect and cancel the OOR.

ITU-T G. 709 ITU-T G. 798

  Since the method of transmitting OTU3 frame data using LLD is a new technology, the OOR insertion function is also a new technology.

In order to confirm that the receiving side can correctly detect and cancel the OOR, the LM is changed on the transmitting side and embedded in the OTU3 frame. In that case, the following conditions must be satisfied.
The first condition is that only LM, that is, only the lower 2 bits of MFAS are changed.
The second condition is that the LM received at normal time is not included within the number of detection conditions (5 frames).
The third condition is that the same LM does not continue for the cancellation condition number (5 frames) or more.
The fourth condition is that the lane number and the LM do not always match. That is, the LM of the 0th lane is not necessarily 0. For example, there is a possibility that the LM of the 0th lane is 1 and the LM of 0 is assigned to other lanes.

  In order to confirm that the receiving side can correctly detect and cancel the OOR, as a method of generating an LM that satisfies the above four conditions on the transmitting side, a method of changing to a fixed value outside the range can be considered. However, since LM uses the lower 2 bits of MFAS, values other than the 4 values of 0 to 3 cannot be used. For this reason, since there are four lanes, there is a problem that it cannot be changed to a fixed value outside the range.

  A method of incrementing or decrementing the value is conceivable. However, since LM cannot use a value other than the four values of 0 to 3, it becomes a normal LM within 5 frames. Therefore, the second condition for generating an LM that can confirm that the receiving side can correctly detect and cancel the OOR cannot be satisfied, and there is a problem that the receiving side cannot correctly detect the OOR.

  Accordingly, the present invention provides an OOR test pattern insertion circuit, an OTU3 frame data transmission device, an OOR test system, and an OOR test pattern insertion method that cause LM disturbance to confirm that the receiving side can correctly detect and cancel OOR. An object is to provide an OTU3 frame data transmission method and an OOR test method.

  The OOR test pattern insertion circuit of the present invention receives OTU3 frame data of an arbitrary lane out of OTU3 frame data having a multi-lane structure, and expresses MFAS included in the input OTU3 frame data in a binary format. A sign inversion unit (32) for inverting one of the LMs arranged in the two least significant bits, and the other bit of the LM so that the continuation of the same sign is 4 times or less. An alarm pattern generation unit (33) that generates data of a 2-bit OOR test by replacing the data of the code “0” or the data of the code “1” and arranging the code from the code inversion unit in the one bit And an alarm pattern for replacing the LM of the arbitrary lane with the OOR test pattern generated by the alarm pattern generation unit. Comprising down insertion portion (34), the.

  Since the sign inversion unit and the alarm pattern generation unit are provided, an OOR test pattern that satisfies the above four conditions for generating an LM that can confirm that the receiving side can correctly detect and cancel the OOR is generated. Can do. Since the alarm pattern insertion unit is provided, the OOR test pattern can be inserted into the OTU3 frame data. Therefore, it is possible to provide an OOR test pattern insertion circuit that causes LM disturbance in order to confirm that the receiving side can correctly detect and cancel OOR.

In the OOR test pattern insertion circuit of the present invention, the alarm pattern generation unit replaces the other bit of the LM with one of the lower second bit, the lower third bit, or the lower fourth bit of the MFAS. The other bit of the LM may be replaced with data of code “0” or data of code “1” so that the continuation of the same code is 4 times or less.
According to the present invention, the alarm pattern generation unit can generate an OOR test pattern that satisfies the above four conditions for generating an LM that can confirm that the receiving side can correctly detect and cancel the OOR.

The OOR test pattern insertion circuit of the present invention further includes a bit generation unit (35) that outputs data of code “0” or data of code “1” so that the continuation of the same code is 4 times or less, The alarm pattern generation unit replaces the other bit of the LM with the output data from the bit generation unit, so that the other bit of the LM has a code “0” so that the continuation of the same code is 4 times or less. Or data with the code “1” may be substituted.
According to the present invention, the alarm pattern generation unit can generate an OOR test pattern that satisfies the above four conditions for generating an LM that can confirm that the receiving side can correctly detect and cancel the OOR.

  The OTU3 frame data transmitting apparatus according to the present invention includes an OTU3 frame data generation circuit (11) for generating the OTU3 frame data, and the OTU3 frame data from the OTU3 frame data generation circuit in four lanes from the 0th lane to the 3rd lane. A distribution circuit (12) for distributing to lanes, and OTU3 frame data of an arbitrary lane among the OTU3 frame data distributed by the distribution circuit are input, and the LM included in the input OTU3 frame data is The OOR test pattern insertion circuit (13) of the present invention to be replaced with the OOR test pattern, and the OTU3 frame data in which the LM is replaced with the OOR test pattern by the OOR test pattern insertion circuit to the transmission line A transmission circuit (14) for transmission; That.

  Since the OTU3 frame data generation circuit, the distribution circuit, and the transmission circuit are provided, the OTU3 frame data can be transmitted. Here, since the OOR test pattern insertion circuit of the present invention is provided, the OOR test pattern can be inserted into the OTU3 frame data. Therefore, it is possible to provide an OTU3 frame data transmitting apparatus that causes LM disturbance in order to confirm that the receiving side can correctly detect and cancel OOR.

  The OOR test system of the present invention receives the OTU3 frame data transmission apparatus (101) of the present invention and the OTU3 frame data transmitted via the transmission path, and the lane of the OTU3 frame data obtained by the reception When the bit strings arranged at the LM positions are the same continuously for 5 or more times, the synchronization state is established, and the bit strings arranged at the LM positions and the synchronized bit strings are consecutive for 5 or more times. A measurement target (102) that receives OTU3 frame data that outputs an OOR alarm if the synchronization state is different.

  In order to provide the OTU3 frame data transmitting apparatus of the present invention and the measurement target for receiving OTU3 frame data, the OTU3 frame data into which the OOR test pattern is inserted is transmitted, and the receiving side as the measurement target detects the OOR. And it can be confirmed that the release can be performed correctly. Therefore, it is possible to provide an OOR test system that causes LM disturbance in order to confirm that the receiving side can correctly detect and cancel the OOR.

  The OOR test pattern insertion method of the present invention is arranged in the two least significant bits when the MFAS included in the OTU3 frame data of an arbitrary lane among the OTU3 frame data having a multi-lane structure is expressed in binary format. One bit of the LM is inverted and arranged in the one bit, and the other bit of the LM is set to the data of the code “0” or the code “ 1 ”to replace the data of“ 1 ”, an alarm pattern generation procedure (S302) for generating a 2-bit OOR test pattern, and the LM of the arbitrary lane to the OOR test pattern generated by the alarm pattern generation procedure And an alarm pattern insertion procedure (S303).

  Since it has an alarm pattern generation procedure and an alarm pattern insertion procedure, it generates an OOR test pattern that satisfies the above four conditions for generating an LM that can confirm that the receiving side can correctly detect and cancel OOR. Can be inserted into the OTU3 frame data. Accordingly, it is possible to provide an OOR test pattern insertion method that causes LM disturbance in order to confirm that the receiving side can correctly detect and cancel OOR.

In the OOR test pattern insertion method of the present invention, in the alarm pattern generation procedure, the other bit of the LM is replaced with any one of the lower second bit, the lower third bit or the lower fourth bit of the MFAS. The other bit of the LM may be replaced with data of code “0” or data of code “1” so that the continuation of the same code is 4 times or less.
According to the present invention, in the alarm pattern generation procedure, it is possible to generate an OOR test pattern that satisfies the above four conditions for generating an LM that can confirm that the receiving side can correctly detect and cancel the OOR.

In the OOR test pattern insertion method of the present invention, in the alarm pattern generation procedure, the data of the code “0” or the data of the code “1” is generated so that the continuation of the same code is 4 times or less, and the LM By replacing the other bit with the generated data, the other bit of the LM can be replaced with the data of the code “0” or the data of the code “1” so that the continuation of the same code is 4 times or less. Good.
According to the present invention, in the alarm pattern generation procedure, it is possible to generate an OOR test pattern that satisfies the above four conditions for generating an LM that can confirm that the receiving side can correctly detect and cancel the OOR.

  The OTU3 frame data transmission method of the present invention includes an OOR test pattern insertion method of the present invention, an OTU3 frame data generation procedure (S101) for generating the OTU3 frame data before the alarm pattern generation procedure, and the alarm pattern. After the insertion procedure, there is a transmission procedure (S104) in which the LM transmits the OTU3 frame data replaced by the OOR test pattern to the transmission line by the alarm pattern insertion procedure.

  Since it has an OTU3 frame data generation procedure and a transmission procedure, OTU3 frame data can be transmitted. Here, since the OOR test pattern insertion method of the present invention is provided, the OOR test pattern can be inserted into the OTU3 frame data. Therefore, it is possible to provide an OTU3 frame data transmission method that causes LM disturbance in order to confirm that the receiving side can correctly detect and cancel OOR.

  The OOR test method of the present invention includes an OTU3 frame data transmission method of the present invention, a reception procedure (S201) for receiving the OTU3 frame data transmitted by the OTU3 frame data transmission method, and the above-described reception procedure. When the bit string arranged at the LM position for each lane of the OTU3 frame data is the same for five or more consecutive times, the synchronization state is established, and the bit string synchronized with the bit string arranged at the LM position is 5 In the case where it is different continuously more than once, an OOR determination procedure (S202) for outputting an OOR alarm when the synchronization state is lost is sequentially provided.

  Since it has the OTU3 frame data transmission method, reception procedure, and OOR determination procedure of the present invention, it is possible to transmit the OTU3 frame data with the OOR test pattern inserted, and the receiving side can correctly detect and cancel the OOR. Can be confirmed. Therefore, it is possible to provide an OOR test method that causes LM disturbance in order to confirm that the receiving side can correctly detect and cancel the OOR.

  The above inventions can be combined as much as possible.

  According to the present invention, an OOR test pattern insertion circuit, an OTU3 frame data transmission device, an OOR test system, and an OOR test pattern insertion method that cause LM disturbance in order to confirm that the receiving side can correctly detect and cancel OOR. , An OTU3 frame data transmission method and an OOR test method can be provided.

An example of the OOR test system which concerns on Embodiment 1 is shown. An example of the OOR test method which concerns on Embodiment 1 is shown. 1 shows a first form of an OOR test pattern insertion circuit; Specific examples of MFAS and OOR test patterns are shown. An example of the OOR determination circuit 25-0 is shown. The 2nd form of the pattern insertion circuit for an OOR test is shown. An example of lane allocation of OTU3 frame data using LLD is shown. The position of the LM in the OTU3 frame is shown.

  Embodiments of the present invention will be described with reference to the accompanying drawings. The embodiments described below are examples of the present invention, and the present invention is not limited to the following embodiments. In the present specification and drawings, the same reference numerals denote the same components.

(Embodiment 1)
FIG. 1 shows an example of an OOR test system according to this embodiment. The OOR test system according to the present embodiment includes an OTU3 frame data transmission device 101 and a measurement target 102 that receives OTU3 frame data. The measurement target 102 that receives the OTU3 frame data is an apparatus or device that receives the OTU3 frame data.

  The OTU3 frame data transmission apparatus 101 includes an OTU3 frame data generation circuit 11, a distribution circuit 12, an OOR test pattern insertion circuit 13, and a transmission circuit 14. A measurement target 102 that receives OTU3 frame data includes a reception circuit 21, a frame detection circuit 22, an aggregation circuit 23, an OTU3 frame data analysis circuit 24, and an OOR determination circuit 25.

  FIG. 2 shows an example of the OOR test method according to this embodiment. The OOR test method according to this embodiment includes an OTU3 frame data transmission method S100, a reception procedure S201, and an OOR determination procedure S202 in this order. The OTU3 frame data transmission method S100 includes an OTU3 frame data generation procedure S101, an OOR test pattern insertion method S300 according to the present embodiment, and a transmission procedure S104 in this order. The OOR test pattern insertion method S300 includes an alarm pattern generation procedure S302 and an alarm pattern insertion procedure S303 in order.

  In the OTU3 frame data generation procedure S101, the OTU3 frame data generation circuit 11 generates OTU3 frame data DT. For example, data is input, the data is divided into frames having a predetermined length, and MFAS is attached to each frame. At this time, MFAS is incremented by one. As a result, the OTU3 frame data generation circuit 11 generates OTU3 frame data DT.

The distribution circuit 12 distributes the OTU3 frame data DT from the OTU3 frame data generation circuit 11 to four lanes from the 0th lane to the 3rd lane. For example, the distribution circuit 12 divides the OTU3 frame data DT into OTU3 frame data DT _{0 to} DT ₃ for each frame. The distribution circuit 12 distributes the OTU3 frame data DT ₀ to the 0th lane, distributes the OTU3 frame data DT ₁ to the first lane, distributes the OTU3 frame data DT ₂ to the second lane, and supplies the OTU3 frame data DT. ₃ is distributed to the third lane.

In the alarm pattern generation procedure S302, the OOR test pattern insertion circuit 13 generates an OOR test pattern using the LMs of the OTU3 frame data DT _{0 to} DT ₃ . For example, the OOR test pattern insertion circuit 13 includes OOR test pattern insertion circuits 13-0 to 13-3 for each lane. The OOR test pattern insertion circuits 13-0 to 13-3 generate OOR test patterns using the LMs of the OTU3 frame data DT _{0 to} DT ₃ , respectively.

For example, OOR test pattern insertion circuit 13-0 is inverted to one bit of the LM arranged on two least significant bits of the time representing the MFAS included in OTU3 frame data DT ₀ in binary format The data of the code “0” or the data of the code “1” is arranged so that the other bits of the LM arranged in the lower 2 bits of the MFAS are not more than 4 times in the same code. To generate a 2-bit OOR test pattern. For example, the data of the code “0” is replaced with the data of the code “0”, the data of the code “0” is replaced with the data of the code “0”, and the data of the code “0” is next. This means that when the data is replaced and the next is replaced with the data of the code “0”, the next is the data of the code “1”.

  FIG. 3 shows a first form of the OOR test pattern insertion circuit 13-0. The OOR test pattern insertion circuit 13-0 shown in FIG. 3 includes an MFAS extraction unit 31, a sign inversion unit 32, an alarm pattern generation unit 33, an alarm pattern insertion unit 34, a delay circuit 37, and an alarm insertion timing signal. And a generation unit 38.

The MFAS extraction unit 31, a frame head signal and OTU3 frame data DT ₀ is input. Then, MFAS extraction unit 31, according to the frame start signal, extracts the MFAS from OTU3 frame data DT _0. Then, 8 bits “a ₇ a ₆ a ₅ a ₄ a ₃ a ₂ a ₁ a ₀ ” representing the MFAS in a binary format are acquired, and the least significant two bits “a ₁ a ₀ ” are converted into a sign inversion unit. 32.

The sign inverting unit 32 inverts one of the two bits “a ₁ a ₀ ”. For example, when one bit is the 0th bit a ₀ and the other bit is the first bit a ₁ , the bit a ₀ is inverted and the inverted bit r ₀ is output to the alarm pattern generation unit 33. For example, if the sign of bit a ₀ is “1”, the sign of bit r ₀ is “0”, and if the sign of bit a ₀ is “0”, the sign of bit r ₀ is “1”. It becomes.

  FIG. 4 shows specific examples of MFAS and OOR test patterns. LM “0” is allocated to the 0th lane, LM “1” is allocated to the 1st lane, LM “2” is allocated to the 2nd lane, and LM “3” is allocated to the 3rd lane. Note that, as described in the fourth condition for generating the LM that can confirm that the receiving side can correctly detect and cancel the OOR, this is an example, and the LM “0” is allocated to the 0th lane. However, the LM of the 0th lane may be “1”, “2”, or “3”.

The MFAS of the 0th lane is “0”, “4”, “8”,. When these MFASs are expressed in binary format, they are “00000000”, “00000100”, “00001000”,... “11111100”. As described above, when the MFAS is expressed in the binary format, the least significant two bits are all “00” and LM “0” is allocated. In this case, the bit a ₀ is “0”, and the bit r ₀ obtained by inverting the bit a ₀ is “1”.

The alarm pattern generation unit 33 replaces the other bit a ₁ of the LM with the bit b ₁ and arranges the bit r ₀ at the position of the bit a ₀ to generate a 2-bit OOR test pattern. Here, the replacement from the bit a ₁ to the bit b ₁ is replaced with the data of the code “0” or the data of the code “1” so that the continuation of the same code is 4 times or less. As a result, an OOR test pattern “b ₁ r ₀ ” is generated.

For example, the lower second bit a ₂ of the MFAS of the 0th lane shown in FIG. 4 is a sequence of the same sign as “0”, “1”, “0”, “1”,. Is less than once. For this reason, by replacing the bit a ₁ with the lower second bit a ₂ of the MFAS, the other bit a ₁ of the LM is replaced with the data of the code “0” or the code “ 1 ”can be substituted. As a result, “01”, “11”, “01”, “11”,... “11”, that is, the OOR test pattern “b ₁ r ₀ ” that repeats the values “1” and “3”. Can be generated.

In this way, using the fact that the LM is 0 to 3 and the MFAS is 0 to 255 and incrementing by 1 every OTU3 frame, the value r obtained by inverting the lower 0th bit a ₀ of the LM in a certain lane r _The OOR test pattern “b ₁ r ₀ ” is generated by combining ₀ and the value b ₁ of the lower second bit a ₂ of MFAS.

In the alarm pattern insertion procedure S303 shown in FIG. 2, the OTU3 frame data DT ₀ and the OOR test pattern “b ₁ r ₀ ” are input to the alarm pattern insertion unit 34. At this time, the delay circuit 37 adjusts the input timing of the OTU3 frame data DT ₀ and the OOR test pattern “b ₁ r ₀ ”. Further, the alarm insertion timing signal generation unit 38 outputs a timing signal indicating the position of the LM to be replaced with the alarm pattern of the OTU3 frame data DT ₀ to the alarm pattern insertion unit 34 in accordance with the alarm insertion instruction. Then, the alarm pattern insertion unit 34 replaces the LM “a ₁ a ₀ ” of the OTU3 frame data DT ₀ with the OOR test pattern “b ₁ r ₀ ” according to the timing signal from the alarm insertion timing signal generation unit 38. OTU3 and outputs the frame data DA _0.

Since the MFAS of the OTU3 frame data DA ₀ is “a ₇ a ₆ a ₅ a ₄ a ₃ a ₂ b ₁ r ₀ ”, only the LM, that is, only the lower 2 bits of the MFAS are changed. For this reason, the first condition for generating an LM that can confirm that the receiving side can correctly detect and cancel the OOR is satisfied. In the MFAS shown in FIG. 4, the OOR test pattern “b ₁ r ₀ ” of the 0th lane is a repetition of the value “1” and the value “3”, and the LM “0” received in the normal state is Since it is not included, the second condition for generating an LM that can confirm that the receiving side can correctly detect and cancel the OOR is satisfied. Further, since the same LM does not continue, the third condition for generating an LM that can confirm that the receiving side can correctly detect and cancel the OOR is satisfied. Furthermore, when LM “1” is assigned to the 0th lane, the OOR test pattern repeats values “0” and “2” that are different from the normal LM “1”. Similarly, when LM “2” is allocated, the pattern becomes an OOR test pattern that repeats a value “1” and a value “3” different from the normal LM “2”, and LM “3” is allocated to the 0th lane. In the same way, since the pattern for OOR test repeats “0” and “2” different from the normal LM “3”, it is possible to confirm that the receiving side can correctly detect and cancel the OOR. The fourth condition for generating a correct LM is satisfied.

Therefore, the OOR test pattern insertion circuit 13 according to the present embodiment and the OOR test pattern insertion method S300 according to the present embodiment generate an LM that can confirm that the receiving side can correctly detect and cancel the OOR. it is possible to output a satisfying OTU3 frame data DA ₀ of the fourth from the first condition.

Each of the OOR test pattern insertion circuits 13-1, 13-2 and 13-3 shown in FIG. 1 repeats two values different from the LM at the normal time in the same manner as the OOR test pattern insertion circuit 13-0. OTU3 frame data DA ₁ , DA ₂ and DA ₃ into which an OOR test pattern is inserted can be output.

Therefore, the OOR test pattern insertion circuit 13 according to the present embodiment and the OOR test pattern insertion method S300 according to the present embodiment generate an LM that can confirm that the receiving side can correctly detect and cancel the OOR. OTU3 frame data DA _{0 to} DA ₃ satisfying the fourth condition can be output from the first condition.

In the transmission procedure S <b> 104, OTU3 frame data DA _{0 to} DA ₃ in which LM is replaced with the OOR test pattern by the OOR test pattern insertion circuit 13 is input to the transmission circuit 14. Then, the transmission circuit 14 transmits the OTU3 frame data DA _{0 to} DA ₃ to the transmission path.

In the reception procedure S201, the OTU3 frame data output from the OTU3 frame data transmission apparatus 101 is received. For example, the receiving circuit 21 receives OTU3 frame data and outputs OTU3 frame data DR _{0 to} DR ₃ to each lane from the 0th lane to the 3rd lane. The frame detection circuit 22 detects the head of the frame of the OTU3 frame data DR _{0 to} DR ₃ from the reception circuit 21 and performs frame processing such as deskew between frames. At this time, the frame detection circuits 22-0 to 22-3 included in each lane perform frame processing for each lane. The aggregation circuit 23 aggregates the OTU3 frame data DD _{0 to} DD ₃ from the frame detection circuit 22 and constructs OTU3 frame data DD. The OTU3 frame data analysis circuit 24 analyzes the OTU3 frame data DD from the aggregation circuit 23.

In OOR determining step S202, OOR determination circuit 25 performs the detection and cancellation of OOR the OTU3 frame data _DR 0 _{~DR 3} received by the receiving procedure S201. For example, the OOR determination circuit 25 includes an OOR determination circuit 25-0 that detects and releases an OOR of the OTU3 frame data DD ₀ , an OOR determination circuit 25-1 that detects and releases an OOR of the OTU3 frame data DD ₁ , It includes a OOR decision circuit 25-2 for detecting and cancellation of OOR the OTU3 frame data DD _2, the OOR decision circuit 25-3 for detecting and cancellation of OOR the OTU3 frame data DD _3, the.

FIG. 5 shows an example of the OOR determination circuit 25-0. The OOR determination circuit 25-0 includes an MFAS extraction unit 51 and a continuity detection unit 52. From frame detection circuit 22-0 to MFAS extractor 51, a frame head signal and OTU3 frame data DD ₀ is input. MFAS extraction unit 51 extracts a bit string which is disposed in LM position from the OTU3 frame data DD _0. The continuity detecting unit 52 is in a synchronized state when the bit string arranged at the LM position from the MFAS extracting unit 51 is the same for five times or more, and is synchronized with the bit string arranged at the LM position. If the bit string is different five or more times continuously, the synchronization state is lost and an OOR alarm is output.

For example, in a state where a bit string of “00”, which is a normal LM, is continuous five times or more, a synchronization state is established. Thereafter, the synchronization state is maintained even if the bit string becomes “01”. Then, “01” is followed by “11”, “01”, “11”, “01”, and the number of detection conditions (5 frames) is reached. Then, the synchronization state is lost and an OOR alarm is output. In the present embodiment, the bit string arranged at the position of the LM of DD _{0 in} the 0th lane is a repetition of the value “1” and the value “3” when the OOR test pattern is inserted, and is received in the normal state. The LM “0” that was being used is not included. For this reason, when the number of detection conditions is 5 frames, the OOR determination circuit 25-0 outputs an OOR alarm if the transmitting side inserts an OOR test pattern five or more times.

  Similarly to the OOR determination circuit 25-0, when the OOR determination circuits 25-1 to 25-3 are inserted OOR test patterns five or more times on the transmission side, the OOR determination circuits 25-1 to 25-3 become OOR Output an alarm.

As described above, the OOR test pattern insertion circuit 13 and the OOR test pattern insertion method S300 are based on the first condition for generating an LM that can confirm that the receiving side can correctly detect and cancel the OOR. OTU3 frame data DA _{0 to} DA ₃ satisfying the fourth condition can be output. Therefore, the OTU3 frame data transmission apparatus 101 and the OTU3 frame data transmission method S100 use the OTU3 frame data DT _{0 to} DT to generate an OOR test pattern that causes LM disturbance in order to confirm that the reception side can correctly detect and cancel the OOR. _The OTU3 frame data DA _{0 to} DA ₃ inserted in ₃ can be transmitted.

The OOR test system according to the present embodiment includes an OTU3 frame data transmission apparatus 101, and the OOR test method according to the present embodiment includes an OTU3 frame data transmission method S100. Therefore, in the OOR test system and the OOR test method according to the present embodiment, the OOR test pattern that causes the LM disturbance in order to confirm that the receiving side can correctly detect and cancel the OOR is used as the OTU3 frame data DT _{0 to} DT _3. The OTU3 frame data DA _{0 to} DA ₃ inserted in can be transmitted and received to confirm that the OOR can be detected and canceled correctly.

Incidentally, one of the bit the alarm pattern generation unit 33 inverts the 0th lane in alarm pattern generation step S302 may be the lower first bit a ₁ in the MFAS. In this case, the other bit is the lower 0th bit a _{0 of} MFAS. For example, the bit “r ₁ ” is generated by inverting the bit a ₁ . Also, the bit a ₀ is replaced with the bit b ₀ so that the continuation of the same sign is 4 times or less. As a result, a 2-bit OOR test pattern “r ₁ b ₀ ” is generated. In the case of the MFAS shown in FIG. 4, the OOR test pattern “r ₁ b ₀ ” is a repetition of “2” and “3”. As described above, even if the OOR test pattern is “r ₁ b ₀ ”, the fourth condition to the fourth condition for generating the LM that can confirm that the receiving side can correctly detect and cancel the OOR can be obtained. Satisfy the condition of Similarly, for the OOR test patterns from the first lane to the third lane, the fourth condition to the fourth condition for generating an LM that can be confirmed that the receiving side can correctly detect and cancel the OOR are changed. Fulfill.

  In the present embodiment, the OOR test pattern insertion circuits 13-0, 13-1, 13-2, and 13-3 are provided in all the lanes. However, the present invention is not limited to this. For example, one OOR test pattern insertion circuit common to each lane may be provided, and the OOR test pattern insertion circuit may be inserted into any lane. Since the OOR test pattern insertion circuit according to the present embodiment generates an OOR test pattern using the input MFAS, an appropriate OOR test pattern can be generated even if it is inserted into any lane.

Moreover, although this embodiment demonstrated the case where the number of detection conditions and the number of cancellation conditions were 5 frames, it is not limited to this. For example, the number of detection conditions and the number of cancellation conditions may be 4 frames or less. In this embodiment, by replacing the bit a ₁ with the lower second bit a ₂ of the MFAS, an OOR test pattern that repeats a value “1” and a value “3” different from the normal LM “0” is generated. can do. For this reason, even if the number of detection conditions and the number of cancellation conditions are two frames, it can be confirmed that the receiving side can correctly detect and cancel the OOR. Therefore, even when the number of detection conditions and the number of cancellation conditions are set to 4 or less, it can be confirmed that the receiving side can correctly detect and cancel the OOR.

(Embodiment 2)
OOR test system according to the present embodiment, the alarm pattern generation unit 33 shown in FIG. 3, the other bit _{a 1} in the LM, by replacing the lower third bits _{a 3} of MFAS, LM of the other bits a ₁ is replaced with data of code “0” or data of code “1” so that the continuation of the same code is 2 times or less.

For example, the lower third bits of the MFAS of the 0th lane shown in FIG. 4 are “0”, “0”, “1”, “1”, “0”, “0”, “1”, “1”, ... As in “1”, the same symbol continues twice or less. Therefore, by replacing the bit a ₁ with the lower third bit a ₃ of the MFAS, the other bit a ₁ of the LM is replaced with the data of the code “0” or the code “ 1 ”can be substituted.

In this case, the OOR test pattern “b ₁ r ₀ ” for the 0th lane is “01”, “01”, “11”, “11”, “01”, “01”, “11”, “11”. ..,... Repeated as “11”, “1”, “1”, “3”, “3”. For this reason, the same LM is not more than 2 times and does not continue 3 times or more. As described above, since the LM “0” received in the normal state is not included, the second condition for generating the LM that can be confirmed that the receiving side can correctly detect and cancel the OOR is satisfied. Further, since the same LM does not continue three or more times, the third condition for generating an LM that can be confirmed that the receiving side can correctly detect and cancel the OOR is satisfied. Furthermore, when LM “1”, LM “2”, or LM “3” is assigned to the 0th lane, similarly, the binary value is different from the normal LM, and the same value is within two times. And do not continue more than 3 times. Therefore, the fourth condition for generating an LM that can confirm that the receiving side can correctly detect and cancel the OOR is satisfied.

Similarly to the OOR test pattern insertion circuit 13-0, the OOR test pattern insertion circuits 13-1, 13-2 and 13-3 each have a binary value different from the normal LM, and the same value is 2 The OTU3 frame data DA ₁ , DA _2, and DA ₃ into which the OOR test pattern that is not continuous three times or more is inserted can be output.

Therefore, the OOR test pattern insertion circuit 13 according to the present embodiment and the OOR test pattern insertion method S300 according to the present embodiment generate an LM that can confirm that the receiving side can correctly detect and cancel the OOR. OTU3 frame data DA _{0 to} DA ₃ satisfying the fourth condition can be output from the first condition.

Incidentally, one of the bit the alarm pattern generation unit 33 inverts the alarm pattern generation step S302 may be the lower first bit a ₁ in the MFAS. In this case, the other bit is the lower 0th bit a _{0 of} MFAS. For example, the bit “r ₁ ” is generated by inverting the bit a ₁ . Also, the bit a ₀ is replaced with the bit b ₀ so that the continuation of the same sign is 4 times or less. As a result, a 2-bit OOR test pattern “r ₁ b ₀ ” is generated. In the case of the MFAS shown in FIG. 4, in the case of the 0th lane, the OOR test pattern “r ₁ b ₀ ” repeats “2”, “2”, “3”, and “3”. Thus, even if the OOR test pattern is “r ₁ b ₀ ”, it is confirmed that the receiving side can correctly detect and cancel the OOR as in the case of the OOR test pattern “b ₁ r ₀ ”. The first condition to the fourth condition for generating a possible LM are satisfied. Similarly, for the OOR test patterns from the first lane to the third lane, the fourth condition to the fourth condition for generating an LM that can be confirmed that the receiving side can correctly detect and cancel the OOR are changed. Fulfill.

Therefore, when the OOR test pattern insertion circuit 13 according to the present embodiment and the OOR test pattern insertion method S300 according to the present embodiment are used, the receiving side can correctly detect and cancel the OOR as in the first embodiment. In order to confirm this, it is possible to output OTU3 frame data DA _{0 to} DA _{3 in} which OOR test patterns that cause LM disturbance are inserted into OTU3 frame data DT _{0 to} DT ₃ .

(Embodiment 3)
OOR test system according to the present embodiment, the alarm pattern generation unit 33 shown in FIG. 3, the other bit _{a 1} in the LM, by replacing the lower fourth bit _{a 4} of MFAS, LM of the other bits a ₁ is replaced with data of code “0” or data of code “1” so that the continuation of the same code is 4 times or less.

For example, the lower fourth bits of the MFAS of the 0th lane shown in FIG. 4 are “0”, “0”, “0”, “0”, “1”, “1”, “1”, “1”, As in “0”,..., “1”, the same symbol continues four times or less. For this reason, by replacing the bit a ₁ with the lower 4th bit of the MFAS, the other bit a ₁ of the LM is the data of the code “0” or the code “1” so that the continuation of the same code is 4 times or less. Can be replaced with

In this case, the OOR test pattern “b ₁ r ₀ ” for the 0th lane is “01”, “01”, “01”, “01”, “11”, “11”, “11”, “11”. , “01”, “01”, “01”, “01”, “11”,... “11”, “1”, “1”, “1”, “1”, “3” , “3”, “3”, “3” are repeated. For this reason, the same LM is 4 times or less and does not continue 5 times or more. As described above, since the LM “0” received in the normal state is not included, the second condition for generating the LM that can be confirmed that the receiving side can correctly detect and cancel the OOR is satisfied. Further, since the same LM does not continue five times or more, the third condition for generating an LM that can be confirmed that the receiving side can correctly detect and cancel the OOR is satisfied. Furthermore, when LM “1”, LM “2”, or LM “3” is assigned to the 0th lane, similarly, the binary value is different from the normal LM, and the same value is within 4 times. And do not continue for more than 5 times. Therefore, the fourth condition for generating an LM that can confirm that the receiving side can correctly detect and cancel the OOR is satisfied.

Similarly to the OOR test pattern insertion circuit 13-0, the OOR test pattern insertion circuits 13-1, 13-2, and 13-3 each have a binary value different from the normal LM, and the same value is 4. The OTU3 frame data DA ₁ , DA _2, and DA ₃ into which the OOR test pattern that is not continuous five times or more is inserted can be output.

Therefore, the OOR test pattern insertion circuit 13 according to the present embodiment and the OOR test pattern insertion method S300 according to the present embodiment generate an LM that can confirm that the receiving side can correctly detect and cancel the OOR. OTU3 frame data DA _{0 to} DA ₃ satisfying the fourth condition can be output from the first condition.

Incidentally, one of the bit the alarm pattern generation unit 33 inverts the alarm pattern generation step S302 may be the lower first bit a ₁ in the MFAS. In this case, the other bit is the lower 0th bit a _{0 of} MFAS. For example, the bit “r ₁ ” is generated by inverting the bit a ₁ . Also, the bit a ₀ is replaced with the bit b ₀ so that the continuation of the same sign is 4 times or less. As a result, a 2-bit OOR test pattern “r ₁ b ₀ ” is generated. For the MFAS shown in FIG. 4, in the case of the 0th lane, the OOR test pattern “r ₁ b ₀ ” is “2”, “2”, “2”, “2”, “3”, “3”, “3” and “3” are repeated. Thus, even if the OOR test pattern is “r ₁ b ₀ ”, it is confirmed that the receiving side can correctly detect and cancel the OOR as in the case of the OOR test pattern “b ₁ r ₀ ”. The first condition to the fourth condition for generating a possible LM are satisfied. Similarly, for the OOR test patterns from the first lane to the third lane, the fourth condition to the fourth condition for generating an LM that can be confirmed that the receiving side can correctly detect and cancel the OOR are changed. Fulfill.

Therefore, when the OOR test pattern insertion circuit 13 according to the present embodiment and the OOR test pattern insertion method S300 according to the present embodiment are used, the receiving side can correctly detect and cancel the OOR as in the first embodiment. It is possible to output OTU3 frame data DA _{0 to} DA _{3 in} which an OOR test pattern for generating an LM that can be confirmed is inserted into OTU3 frame data DT _{0 to} DT ₃ .

(Embodiment 4)
The OOR test system according to the present embodiment includes a second form of an OOR test pattern insertion circuit 13-0 instead of the first form of the OOR test pattern insertion circuit 13-0 shown in FIG. Then, in the alarm pattern generation procedure S302 shown in FIG. 2, the second form of the OOR test pattern insertion circuit 13-0 generates an OOR test pattern using the LM of the OTU3 frame data DT _{0 to} DT ₃ . FIG. 6 shows a second form of the OOR test pattern insertion circuit.

  The OOR test pattern insertion circuit 13-0 shown in FIG. 6 includes an MFAS extraction unit 31, a sign inversion unit 32, an alarm pattern generation unit 36, an alarm pattern insertion unit 34, a bit generation unit 35, and a delay circuit 37. And an alarm insertion timing signal generation unit 38. The MFAS extraction unit 31, the sign inversion unit 32, the alarm pattern generation unit 36, the alarm pattern insertion unit 34, the delay circuit 37, and the alarm insertion timing signal generation unit 38 are as described in the first embodiment.

The MFAS expressed in binary format is “a ₇ a ₆ a ₅ a ₄ a ₃ a ₂ a ₁ a ₀ ”, one bit of LM is the lower 0th bit a ₀ of MFAS, and the other bit of LM is MFAS for a lower first bit a _1, sign inversion unit 32 inverts the bits a _0, to output a bit r ₀ obtained by inverting the alarm pattern generation unit 36.

The bit generation unit 35 outputs the bit b ₁ such that the continuation of the same code is 4 times or less. For example, the bit generation unit 35 outputs a bit string such that “0”, “1”, “0”, “1”,. .

The alarm pattern generation unit 36 replaces the other bit a ₁ of the LM with the bit b ₁ and arranges the bit r ₀ at the position of the bit a ₀ to generate a 2-bit OOR test pattern “b ₁ r ₀ ”. To do.

For example, the bit b ₁ is a bit string such that “0”, “1”, “0”, “1”,. Therefore, by replacing the bit a ₁ with the bit b ₁ , the other bit a ₁ of the LM is replaced with the data of the code “0” or the data of the code “1” so that the continuation of the same code is less than once. Can be replaced.

In the alarm pattern insertion procedure S303 shown in FIG. 2, the alarm pattern insertion unit 34 generates the LM “a ₁ a ₀ ” of the OTU3 frame data DT _{0 in} the alarm pattern generation procedure S302 “b ₁ r ₀ ”. Replace with. As a result, the OTU3 frame data DA ₀ is output from the alarm pattern insertion unit 34.

Since the MFAS of the OTU3 frame data DA ₀ is “a ₇ a ₆ a ₅ a ₄ a ₃ a ₂ b ₁ r ₀ ”, only the LM, that is, only the lower 2 bits of the MFAS are changed. For this reason, the first condition for generating an LM that can confirm that the receiving side can correctly detect and cancel the OOR is satisfied. In the MFAS shown in FIG. 4, the OOR test pattern “b ₁ r ₀ ” of the 0th lane is a repetition of the value “1” and the value “3”, and the LM “0” received in the normal state is Since it is not included, the second condition for generating an LM that can confirm that the receiving side can correctly detect and cancel the OOR is satisfied. Further, since the same LM does not continue, the third condition for generating an LM that can confirm that the receiving side can correctly detect and cancel the OOR is satisfied. Further, when LM “1”, LM “2”, or LM “3” is allocated to the 0th lane, similarly, two values different from the normal LM are repeated. Therefore, the fourth condition for generating an LM that can confirm that the receiving side can correctly detect and cancel the OOR is satisfied.

The OOR test pattern insertion circuits 13-1, 13-2, and 13-3 are similar to the OOR test pattern insertion circuit 13-0, and repeat OOR test patterns that are different from the normal LM. OTU3 frame data DA ₁ , DA _2, and DA ₃ into which is inserted can be output.

Therefore, the OOR test pattern insertion circuit 13 according to the present embodiment and the OOR test pattern insertion method S300 according to the present embodiment generate an LM that can confirm that the receiving side can correctly detect and cancel the OOR. OTU3 frame data DA _{0 to} DA ₃ satisfying the fourth condition can be output from the first condition.

Incidentally, one of the bit the alarm pattern generation unit 33 inverts the alarm pattern generation step S302 may be the lower first bit a ₁ in the MFAS. In this case, the other bit is the lower 0th bit a _{0 of} MFAS. For example, the bit “r ₁ ” is generated by inverting the bit a ₁ . Also, the bit a ₀ is replaced with the bit b ₀ so that the continuation of the same sign is 4 times or less. As a result, a 2-bit OOR test pattern “r ₁ b ₀ ” is generated. In the case of the MFAS shown in FIG. 4, in the case of the 0th lane, the OOR test pattern “r ₁ b ₀ ” repeats “2” and “3”. Thus, even if the OOR test pattern is “r ₁ b ₀ ”, it is confirmed that the receiving side can correctly detect and cancel the OOR as in the case of the OOR test pattern “b ₁ r ₀ ”. The first condition to the fourth condition for generating a possible LM are satisfied. Similarly, for the OOR test patterns from the first lane to the third lane, the fourth condition to the fourth condition for generating an LM that can be confirmed that the receiving side can correctly detect and cancel the OOR are changed. Fulfill.

  Further, the bit generation unit 35 is configured such that “0”, “0”, “1”, “1”, “0”, “0”, “1”, “1”,. A bit string in which the same code continues twice or less may be output. In addition, the bit generation unit 35 selects “0”, “0”, “0”, “1”, “1”, “1”, “0”, “0”, “0”,. In this way, a bit string in which the continuation of the same code is 3 times or less may be output. In addition, the bit generation unit 35 selects “0”, “0”, “0”, “0”, “1”, “1”, “1”, “1”, “0”,. In this way, a bit string in which the continuation of the same code is 4 times or less may be output. Also in these cases, as described in the second and third embodiments, the first condition to the fourth condition for generating an LM that can confirm that the receiving side can correctly detect and cancel the OOR is satisfied. be able to.

Therefore, when the OOR test pattern insertion circuit 13 according to the present embodiment and the OOR test pattern insertion method S300 according to the present embodiment are used, the receiving side can correctly detect and cancel the OOR as in the first embodiment. In order to confirm this, it is possible to output OTU3 frame data DA _{0 to} DA _{3 in} which OOR test patterns that cause LM disturbance are inserted into OTU3 frame data DT _{0 to} DT ₃ .

  The present invention can be applied to the information communication industry.

11: OTU3 frame data generation circuit 12: distribution circuit 13, 13-0, 13-1, 13-2, 13-3: OOR test pattern insertion circuit 14: transmission circuit 21: reception circuit 22: frame detection circuit 23: Aggregation circuit 24: OTU3 frame data analysis circuit 25, 25-0, 25-1, 25-2, 25-3: OOR determination circuit 31: MFAS extraction unit 32: sign inversion unit 33, 36: alarm pattern generation unit 34: Alarm pattern insertion unit 35: Bit generation unit 37: Delay circuit 38: Alarm insertion timing signal generation unit 51: MFAS extraction unit 52: Continuity detection unit 101: OTU3 frame data transmitter 102: Measurement target for receiving OTU3 frame data

Claims (10)

An OTU3 frame data of an arbitrary lane among OTU3 (Optical-channel Transport Unit 3) frame data having a multi-lane structure is input, and an MFAS (Multi Frame Alignment Signal) included in the input OTU3 frame data is in a binary format. A sign inversion unit (32) that inverts one bit of the LM (Lane Marker) arranged in the lowest two bits represented by
The other bit of the LM is replaced with the data of the code “0” or the data of the code “1” so that the continuation of the same code is 4 times or less, and the code from the code inversion unit is arranged in the one bit Then, an alarm pattern generation unit (33) that generates a 2-bit OOR (Out of Recovery) test pattern;
An alarm pattern insertion unit (34) for replacing the LM of the arbitrary lane with the OOR test pattern generated by the alarm pattern generation unit;
An OOR test pattern insertion circuit comprising:   The alarm pattern generation unit replaces the other bit of the LM with one of the lower second bit, the lower third bit, or the lower fourth bit of the MFAS, so that the other bit of the LM has the same sign. 2. The OOR test pattern insertion circuit according to claim 1, wherein the data is replaced with data of a code “0” or data of a code “1” so that the continuity is 4 times or less. A bit generation unit (35) for outputting data of code “0” or data of code “1” so that the same code continues four times or less;
The alarm pattern generation unit replaces the other bit of the LM with the output data from the bit generation unit, so that the other bit of the LM has a code “0” so that the continuation of the same code is 4 times or less. The OOR test pattern insertion circuit according to claim 1, wherein the OOR test pattern insertion circuit is replaced with data “1” or data “1”. An OTU3 frame data generation circuit (11) for generating the OTU3 frame data;
A distribution circuit (12) for distributing the OTU3 frame data from the OTU3 frame data generation circuit to four lanes from the 0th lane to the 3rd lane;
2. The OTU3 frame data of an arbitrary lane among the OTU3 frame data distributed by the distribution circuit is input, and the LM included in the input OTU3 frame data is replaced with the OOR test pattern. To OOR test pattern insertion circuit (13) according to any one of 1 to 3,
A transmission circuit (14) for transmitting the OTU3 frame data in which the LM is replaced with the OOR test pattern by the OOR test pattern insertion circuit to a transmission line;
An OTU3 frame data transmitter. An OTU3 frame data transmission device (101) according to claim 4,
When the OTU3 frame data transmitted via the transmission path is received, and the bit string arranged at the LM position for each lane of the OTU3 frame data obtained by the reception is the same continuously for five times or more Is in a synchronized state, and if the bit string arranged at the position of the LM and the synchronized bit string are different five or more times continuously, the synchronization state is lost and the OTU3 frame data that outputs an OOR alarm is received. A measurement object (102);
OOR test system. Inverts one bit of the LM arranged in the two least significant bits when the MFAS included in the OTU3 frame data of an arbitrary lane among the OTU3 frame data having a multi-lane structure is expressed in binary format And the other bit of the LM is replaced with the data of the code “0” or the data of the code “1” so that the continuation of the same code is 4 times or less. An alarm pattern generation procedure (S302) for generating an OOR test pattern;
An alarm pattern insertion procedure (S303) for replacing the LM of the arbitrary lane with the OOR test pattern generated by the alarm pattern generation procedure;
The pattern insertion method for OOR test which has these in order.   In the alarm pattern generation procedure, the other bit of the LM is replaced with one of the lower second bit, the lower third bit, or the lower fourth bit of the MFAS, so that the other bit of the LM has the same sign. The OOR test pattern insertion method according to claim 6, wherein the data is replaced with data of code “0” or data of code “1” so that the continuation is 4 times or less.   In the alarm pattern generation procedure, the data of the code “0” or the data of the code “1” is generated so that the continuation of the same code is 4 times or less, and the other bit of the LM is replaced with the generated data. 7. The OOR test according to claim 6, wherein the other bit of the LM is replaced with data of a code “0” or data of a code “1” so that the continuation of the same code is 4 times or less. Pattern insertion method. The OOR test pattern insertion method according to any one of claims 6 to 8,
Before the alarm pattern generation procedure, an OTU3 frame data generation procedure (S101) for generating the OTU3 frame data;
After the alarm pattern insertion procedure, a transmission procedure (S104) for transmitting the OTU3 frame data in which the LM is replaced with the OOR test pattern by the alarm pattern insertion procedure to a transmission line;
A method for transmitting OTU3 frame data. The OTU3 frame data transmission method according to claim 9,
A reception procedure (S201) for receiving the OTU3 frame data transmitted by the OTU3 frame data transmission method;
When the bit string arranged at the LM position for each lane of the OTU3 frame data obtained by the reception procedure is the same for five or more consecutive times, a synchronization state is established, and the bit string arranged at the LM position An OOR determination procedure (S202) in which the synchronization state is lost and an OOR alarm is output when the synchronized bit string is continuously different five times or more;
The OOR test method which has in order.

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