JP2012095035A - Image processing device and method of controlling the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a technique capable of displaying an interlaced video faithfully to an original image and reducing interlace interference such as line flickers and plane flickers and the like, in a flat panel display.SOLUTION: An image processing device has: frame generation means generating an odd frame by inserting a blank line between lines in an odd field of an inputted interlaced video signal, and generating an even frame by inserting a blank line between lines in an even field; intermediate image generation means generating an intermediate image having a brightness lower than a half of the original brightness, based on any one or both of the odd frame image and the even frame image; and output means outputting the odd frame and the even frame alternately while interposing a frame of the intermediate image between those at a frame frequency twice as much as a field frequency of the interlaced video signal.

Description

  The present invention relates to a technique for displaying an interlaced video on a flat panel display.

A CRT has been used for many years as a moving image display device typified by a television receiver. In recent years, a flat panel display (FPD) such as a liquid crystal display (LCD) is becoming mainstream. When the frame rate of the moving image is 60 Hz or 50 Hz, the liquid crystal display continues to emit light for 1/60 second or 1/50 second. Therefore, the liquid crystal display is called a “hold type” display.
When interlaced video is input to such a hold-type display, the interlaced video is generally converted into progressive video (hereinafter referred to as IP conversion) and displayed.

In addition, field emission type display devices (Field Emission Display (FED), Surface-conduction Electron-emitter Display (SED), etc.) have been developed as devices having light emission characteristics similar to those of CRTs. This type of display device is called an “impulse type” display because it emits light for an instant within one frame display period (1 / 60th or 1 / 50th of a second).
The impulse display can in principle display an interlaced display. However, when interlaced display is performed with an FPD that is a pixel-isolated display device in which each pixel emits light alone, there is a problem that line flicker, which is a kind of interlace interference, appears strongly.

  8A to 8D are diagrams for explaining the occurrence of line flicker in interlaced display. 8A and 8B show an example in which a white rectangular image is displayed on a flat panel display (FPD), and FIGS. 8C and 8D show an example in which the same image is displayed on a CRT. In the figure, reference numeral 121 denotes a white display portion line in the odd field of the FPD, and 122 denotes a white display portion line in the FPD even field. Reference numeral 123 denotes a white display portion in the odd field of the CRT, and 124 denotes a line of the white display portion in the even field of the CRT. 125 is an even field line in the odd field of the FPD, and 126 is an even field line in the odd field of the CRT.

In the CRT, the lines of the white image portion are spread and displayed as shown by 123 and 124 due to the diffusion of the electron beam, so the line 126 which is a non-light emitting line is not completely black but becomes brightly bright. As a result, since the luminance change between fields in the lines 126 and 124 at the same position becomes small, the line flicker is not so conspicuous.
On the other hand, in the FPD, since light emission is controlled in units of pixels, white image portions are clearly displayed as 121 and 122, and the non-light emitting lines 125 are also clearly black lines. Therefore, the luminance change between fields becomes remarkable, and a strong line flicker appears. Due to this line flicker, a disturbing feeling that a horizontal striped pattern appears in a white rectangle (striped pattern interference) or the upper and lower ends of the rectangle appear to flicker.

  Therefore, in an impulse display, although interlaced display is possible, it is common to perform IP conversion in order to avoid deterioration in image quality due to line flicker.

  There is no standard algorithm for IP conversion, and various methods are adopted by TV and monitor manufacturers. For example, there are intra-field interpolation that generates interpolated pixels from the upper and lower lines, inter-field interpolation that generates interpolated pixels from the preceding and following fields, and a method that adaptively combines intra-field interpolation and inter-field interpolation by motion estimation. As described above, since IP conversion involves interpolation processing and estimation processing, there is no perfect conversion method that can cope with any video, and image disturbance due to a conversion error occurs more or less. The generated image disturbance differs depending on the IP conversion algorithm (that is, depending on the type of monitor and manufacturer).

  In broadcasting stations and content production companies, video quality is checked using a standard display called a master monitor. In the conventional CRT master monitor, the interlaced video can be displayed and confirmed as it is, but in the LCD master monitor, the interlaced video is displayed after being converted into the progressive video by the IP conversion circuit. Then, when an image disturbance is found on the LCD master monitor, it is determined whether it is a problem originally included in the input video signal (original image) or whether the image quality is deteriorated due to a mistake in the IP conversion processing in the master monitor. There is a possibility that it will not connect, and there is a problem.

  Recently, an LCD master monitor having a progressive display mode and an interlaced display mode has appeared. However, since the LCD is a pixel-isolated display device, interlaced display on the LCD master monitor is very difficult to see because the line flicker appears strongly like the above-described FED and SED. For this reason, the interlaced display mode is not a regular mode, and is often used only for checking whether there is an IP conversion error. Therefore, the conventional LCD master monitor requires time and effort to switch the display mode, and there is a problem in using the master monitor that constantly monitors the quality of the original image.

  Several methods for reducing line flicker in interlaced display have been proposed. The method disclosed in Patent Document 1 selectively applies a line flicker prevention filter when a non-interlaced video signal is displayed by an interlace method. The method disclosed in Patent Document 2 applies a low-pass filter in the vertical direction when a character is determined in order to prevent line flicker. The method disclosed in Patent Document 3 is to reduce the vertical resolution when motion is recognized in order to prevent line flicker.

  However, these conventional examples use character discrimination, motion recognition, or the like to prevent line flicker, so that the manner of interference may vary depending on the image. For this reason, as in the case of an IP conversion error, it is impossible to distinguish whether the display image disturbance is a problem included in the original image or a problem caused by image processing on the monitor. Therefore, these methods are not suitable for a display such as a master monitor that requires a display faithful to the original image.

JP-A-6-46299 JP-A-9-252430 JP-A-6-276415

  An object of the present invention is to provide a technique capable of faithfully displaying an interlaced video on an original image on a flat panel display and reducing interlace interference such as line flicker and surface flicker.

  In the first aspect of the present invention, an odd frame is generated by inserting a blank line, which is a line not including image information, between lines of odd fields of an input interlaced video signal, and between lines of even fields. Frame generation means for generating an even frame by inserting a blank line, and an intermediate image darker than ½ of the original luminance based on the image of either the odd frame or the even frame, or both images Intermediate image generating means for generating image data, and output means for alternately outputting odd frames and even frames at a frame frequency twice the field frequency of the interlaced video signal, with the frames of the intermediate image being sandwiched therebetween. An image processing apparatus is provided.

  According to a second aspect of the present invention, there is provided a control method for an image processing apparatus, wherein an odd frame is inserted by inserting a blank line, which is a line not including image information, between lines in an odd field of an input interlaced video signal. Generating an even frame by inserting a blank line between the lines of the even field, and generating an original luminance based on the image of the odd frame and / or the even frame. Generating an intermediate image darker than ½, and alternately outputting odd frames and even frames at a frame frequency twice the field frequency of the interlaced video signal, with the intermediate image frames in between And a method for controlling the image processing apparatus.

  According to the present invention, on a flat panel display, an interlaced video can be displayed faithfully to the original image, and interlace interference such as line flicker and surface flicker can be reduced.

Functional block diagram of the image processing apparatus of the first embodiment The figure which shows the transition of the process image by the image processing apparatus of 1st Embodiment. The figure explaining the change of the display brightness of each line Functional block diagram of the image processing apparatus of the second embodiment The figure which shows the transition of the process image by the image processing apparatus of 2nd Embodiment. Functional block diagram of an intermediate image creation circuit of the image processing apparatus of the third embodiment The figure which shows the transition of the process image by the image processing apparatus of 3rd Embodiment. Diagram explaining the occurrence of line flicker in interlaced display

  Preferred embodiments of an image processing apparatus and a control method thereof according to the present invention will be described below with reference to the accompanying drawings. The image processing apparatus of the present invention is an apparatus that performs image processing on an input interlaced video signal and outputs the processed image signal to a panel module of a flat panel display (FPD). The present invention can be applied to an image processing circuit built in a display device such as a TV receiver or a monitor, or can be applied to a display device such as a video device (tuner, video camera, video recorder, etc.) or a personal computer. On the other hand, the present invention can be applied to an apparatus that outputs an image signal. Note that although FPD includes LCD, FED, SED, organic EL display, plasma display, etc., the present invention can be preferably applied to any FPD.

(First embodiment)
FIG. 1A is a block diagram schematically illustrating a functional configuration of the image processing apparatus according to the first embodiment of the present invention. The image processing apparatus includes an image quality adjustment circuit 111, a frame frequency conversion circuit 11, a frame memory 12, an intermediate image creation circuit 13, a delay circuit 14, a subtraction circuit 15, and a selector 16. FIG. 1B shows details of the intermediate image creation circuit 13, and the intermediate image creation circuit 13 of the present embodiment includes a minimum value filter 17 and a multiplier 18.

  The operation of each block will be described with reference to FIG. FIG. 2 shows an example of an image in which a white rectangular object is moving from left to right in a black background. Here, a description will be given by taking a 1080i60 (interlace with a resolution of 1920 × 1080, a field frequency of 60 Hz (frame frequency of 30 Hz)) as an example. However, the present invention is not limited to this, and can be applied to any format of interlaced video such as 480i60, 480i50, 720i60, 720i50, 1080i60, and 1080i50.

  As an input image, an odd field F1, an even field F2, an odd field F3,. Each field is input to the frame frequency conversion circuit 11 after the image quality adjustment circuit 111 has adjusted the contrast, gradation (gamma), color, and the like.

  The frame frequency conversion circuit 11 converts the first frames F11, F21, F31,... And the second frames F12, F22, F32 from the fields F1, F2, F3,. This circuit generates and outputs at a frame frequency of 120 Hz.

  The operation of the frame frequency conversion circuit 11 as the frame generation means will be described in detail by taking as an example the case where the even field F2 is input. When the frame frequency conversion circuit 11 receives the even field F2, the frame frequency conversion circuit 11 adds (inserts) a blank line between the lines of the even field F2, thereby generating the first frame F21. A blank line refers to an empty line that does not include image information, and is also called a dummy line. As the blank line, it is preferable to use a black line having a pixel value of 0. However, the same effect can be obtained even with a sufficiently dark line (for example, a line having a luminance of about 1/100 of the maximum luminance). Further, the frame frequency conversion circuit 11 reads the data of the first frame F11 created from the odd field F1 in the process of the previous step from the frame memory 12, and the logical sum (OR) of the two first frames F11 and F21. And the second frame F22 is generated. Then, the first frame F21 is output to the delay circuit 14, and the second frame F22 is output to the intermediate image creation circuit 13. At this time, the frame frequency is increased to 120 Hz by outputting the first frame F21 and the second frame F22 twice each. (In FIG. 2, it is described that the first and second frames are output alternately, but this is for convenience of illustration and explanation. In fact, the first and second frames are the same. Note that the first frame F21 is stored in the frame memory 12, which is an image buffer, for processing in the next step.

  Similar processing is performed when an odd field is input. That is, when the odd field F3 is input, the first frame F31 by blank line insertion and the second frame F32 by the logical sum of the first frames F21 and F31 are generated, and the delay circuit 14 and the intermediate image are respectively generated. It is output to the creation circuit 13.

  The first frames (F11, F31) generated by inserting blank lines in the odd fields (F1, F3) are also referred to as “odd frames” hereinafter. In addition, the first frame (F21) generated by inserting a blank line in the even field (F2) is hereinafter also referred to as “even frame”. In this case, the second frame can be called a logical sum image of an odd frame and an even frame that are temporally continuous.

  The intermediate image creating circuit 13 is an intermediate image generating means for generating an intermediate image for reducing line flicker based on the second frame (that is, images of both odd and even frames). The intermediate image creation circuit 13 of this embodiment includes a minimum value filter 17 and a multiplier 18 as shown in FIG. 1B. The minimum value filter 17 is a filter that outputs the minimum pixel value from the target pixel and neighboring pixels. For example, a filter having a tap size of 3 × 3 or 5 × 5 can be preferably used. The multiplier 18 is a circuit that uniformly reduces the brightness of the intermediate image by multiplying all the pixels of the image output from the minimum value filter 17 by a gain.

  FIG. 2 shows an intermediate image F14 obtained by applying a 5 × 5 minimum value filter to the second frames F12, F22, and F32 (F13, F23, and F33) and multiplying by a gain of 0.33. , F24 and F34 are shown. It can be seen that due to the effect of the minimum value filter, only the image portion common to the odd field and the even field remains in the intermediate image. Further, by applying the gain, the luminance of the intermediate image is reduced to about ３ compared to the original image. The value of the gain is not limited to 0.33, but is set to a value that is at least smaller than 0.5 (that is, the intermediate image is darker than ½ of the original luminance). This is because if the gain is 0.5 or more, the intermediate image is too conspicuous, and the interlaced display may not be visible, or another disturbing feeling may occur. On the other hand, the gain value is preferably set to 0.2 or more. This is because if the gain is less than 0.2, the intermediate image is too dark and the effect of improving the line flicker is not sufficient.

  When the input image is a color image, the processing of the intermediate image creation circuit 13 may be performed on the RGB signal or the luminance signal (Y signal). For example, the method of separately generating an intermediate image of each color by passing each RGB signal through a minimum value filter and a gain has the advantage that it can be realized with a simple circuit, although the color balance may slightly change. is there. In addition, if a luminance signal can be obtained separately from the color signal, the RGB signal can be obtained from the converted luminance signal and color signal after applying a minimum value filter and gain to the luminance signal. This method has the advantage that the color balance is maintained. Furthermore, a minimum value filter is applied to a representative value obtained from the RGB value of each pixel (for example, a minimum value, an average value, a value obtained using a predetermined calculation formula), and a pixel having the smallest representative value is employed. This method is also preferable because the color balance is maintained.

  The intermediate image F14 (F24, F34) generated as described above is output to the selector 16 and the subtraction circuit 15.

  The first frame F11 (F21, F31) whose timing is adjusted by the delay circuit 14 is input to the subtraction circuit (subtraction means) 15 in synchronization with the corresponding intermediate image F14 (F24, F34). Then, the subtracting circuit 15 outputs a synthesized frame generated by subtracting the corresponding intermediate image F14 (F24, F34) from the first frame F11 (F21, F31) to the selector 16. Hereinafter, the composite frame generated from the odd frames (F11, F31) is referred to as an odd frame whose luminance is adjusted, or simply an odd frame. Also, the composite frame generated from the even frame (F21) is called an even frame whose luminance is adjusted, or simply an even frame.

The selector 16 is output means for alternately switching output images in accordance with frame timings input from a timing generation circuit (not shown). As shown in FIG. 2, first, an odd frame whose luminance has been adjusted by the subtracting circuit 15 is output as the main frame M1, and then the intermediate image F14 generated by the intermediate image creating circuit 13 is output as the subframe S1. After that, the even frame whose luminance is adjusted as the main frame M2, the intermediate image F24 as the subframe S2, the odd frame whose luminance is adjusted as the main frame M3, the intermediate image F34 as the subframe S3, and so on are output. The

  In the interlace display in the conventional FPD, frames having the same luminance as the original field (for example, frames F11, F21, and F31 in FIG. 2) are output at a frame frequency of 60 Hz. On the other hand, in the pseudo interlaced display according to the present embodiment, the odd-numbered frames (M1, M3) and the even-numbered frames (M1, M3) and the even-numbered frames (S1, S2, S3) having slightly lower brightness than the original field with the low-luminance subframes (S1, S2, S3) sandwiched therebetween. M2) are displayed alternately. Therefore, the luminance change between frames on the same line is greatly reduced as compared with the conventional method. Therefore, the occurrence of stripe pattern interference due to line flicker, which has been a problem in the conventional pixel-isolated FPD, is suppressed.

  Further, the repetition period of the odd frames and the even frames, that is, the pseudo field frequency is 60 Hz which is the same as that of the input image, but the frame frequency of the output image itself is increased to 120 Hz which is doubled. Therefore, when this output image is displayed on the hold type display, there is an effect that motion blur (afterimage feeling), which is a problem peculiar to the hold type, can be reduced. In addition, when this output image is displayed on an impulse display, there is an effect that it is possible to reduce surface flicker (a phenomenon in which bright portions in the screen appear to flicker), which is a problem peculiar to the impulse display.

  FIG. 3 is a diagram for explaining a change in display luminance of each line. 3A and 3B show a case where the original image is displayed as it is with 60 Hz interlace, and FIGS. 3C to 3F show examples of pseudo-interlace display of the present embodiment.

In FIG. 3A and FIG. 3B, 31 is the luminance of the odd line shining in the odd field F1 of the original image, 32 is the luminance of the even line not shining in the odd field F1 of the original image, and 33 is the even field F2 of the original image. It is the brightness of even lines that are shining. Note that the luminance of a line that is not illuminated is called black luminance, and a certain level of luminance is generated due to light leakage in the LCD or seeding in the PDP.
3C to 3F, 34 is the luminance of the even lines that are not illuminated in the main frame M1, 35 is the luminance of the odd lines that are illuminated in the subframe S1, 36 is the luminance of the even lines that are illuminated in the subframe S1, 37 Is the luminance of the even lines shining in the main frame M2.

  As can be seen from FIGS. 3A and 3B, in the conventional method, the luminances 32 and 33 of the same line greatly change between fields. The brighter the part of the image, the greater the difference in brightness. As a result, line flicker with a period of 30 Hz is generated, and horizontal stripe pattern interference appears.

  On the other hand, in the method of the present embodiment, as shown in FIGS. 3C to 3F, the luminance of the same line changes stepwise as 34, 36, and 37. If the luminance is distributed so that the sum of the luminances 36 and 37 is equal to the luminance 33 of the original image, and the luminance 36: luminance 37 = 1: 2, the luminance 36 is one third of the luminance 33. The brightness 37 is 2/3 of the brightness 33. Due to the limitations of the eye's reaction speed, for a frame frequency of 120 Hz, two consecutive frames of the image are completely synthesized in the eye. Therefore, the luminance difference of the line between frames in this case is the difference between the average value of the luminance 34 and the luminance 36 and the average value of the luminance 36 and the luminance 37, which is one third of the conventional method. This suppresses the occurrence of striped pattern interference due to line flicker.

In the method of the present embodiment, the luminance of the main frames M1 and M2 corresponding to the fields F1 and F2 of the original image is sufficiently larger than the luminance of the subframes S1 and S2 (twice in this embodiment). Therefore, a display image close to CRT interlace is obtained. In addition, since processing that varies in accuracy depending on the image, such as interpolation processing and estimation processing, is not performed at all, display that is faithful to the original image is possible. Therefore, the method of this embodiment can be preferably applied to a display device that requires high reliability such as a master monitor.

(Second Embodiment)
The above configuration example shows one embodiment, and there are various embodiments that share the same principle and object of the present invention. Some of them will be described.

  FIG. 4A is a block diagram schematically illustrating a functional configuration of the image processing apparatus according to the second embodiment of the present invention. Although the functions of the frame frequency conversion circuit 51 and the intermediate image creation circuit 52 are different from those of the first embodiment, the functions of the other blocks are the same as those of the first embodiment. FIG. 4B shows details of the intermediate image creation circuit 52. The intermediate image creation circuit 52 of this embodiment includes a Gaussian filter 53 that performs a process of blurring an image instead of the minimum value filter.

The operation of each block will be described with reference to FIG. The input image is the same as that in the first embodiment (FIG. 2).
As an input image, an odd field F1a, an even field F2a, an odd field F3a,. Each field is input to the frame frequency conversion circuit 51 after the image quality adjustment circuit 111 has adjusted the contrast, gradation (gamma), color, and the like.

  The frame frequency conversion circuit 51 generates an odd frame by adding (inserting) a blank line between the lines of the odd field F1a, and sends it to the delay circuit 14 and the intermediate image creation circuit 52 twice at a frame frequency of 120 Hz. Output. In FIG. 5, F11a indicates an odd frame output to the delay circuit 14, and F12a indicates an odd frame output to the intermediate image creation circuit 52.

  The intermediate image creation circuit 52 passes the odd-numbered frame F12a through the Gaussian filter 53, thereby obtaining an image F13a with smoothed pixel values. Here, a known soft filter of 5 × 5 size, in which coefficients are set according to a Gaussian distribution so that the sum of the coefficients becomes 1, is used. In this embodiment, a Gaussian filter is used, but the same effect can be obtained by using another soft filter (smoothing filter) such as a low-pass filter or an average value filter. Next, the multiplier 18 multiplies all pixels of the image F13a by a gain (for example, 0.33), thereby creating an intermediate image F14a. The intermediate image F14a is output to the subtraction circuit 15 and the selector 16.

  The odd frame 11a, the timing of which is adjusted by the delay circuit 14, is input to the subtraction circuit 15 in synchronization with the corresponding intermediate image F14a. Then, the subtracting circuit 15 outputs a combined frame whose luminance is adjusted by subtracting the intermediate image F14a from the odd frame 11a to the selector 16.

  The same process as described above is performed for the even field F2a. In other words, even-numbered frames F21a and F22a are generated by blank line insertion, smoothed (F23a) by the intermediate image creation circuit 52, and then gained to generate an intermediate image F24a. Then, the intermediate image F24a is subtracted from the even frame F21a to obtain a composite frame in which the luminance is adjusted. The same applies to the next odd field F3a. Odd frames F31a and F32a are generated by blank line insertion, smoothed (F33a) by the intermediate image creation circuit 52, and then gained to generate an intermediate image F34a. . Then, the intermediate image F34a is subtracted from the odd-numbered frame F31a to obtain a composite frame whose luminance is adjusted.

  The selector 16 switches the output image according to the frame timing. As shown in FIG. 5, first, an odd-numbered frame whose luminance is adjusted is output as the main frame M1a, and then the intermediate image F14a is output as the subframe S1a. After that, the even frame with the luminance adjusted as the main frame M2a, the intermediate image F24a as the subframe S2a, the odd frame with the luminance adjusted as the main frame M3a, the intermediate image F34a as the subframe S3a, and so on are output. The

  According to the method described above, as in the first embodiment, it is possible to suppress the occurrence of striped pattern interference due to line flicker and to display the original image close to the CRT interlace and faithful to the original image. In addition, in the method according to the present embodiment, the disturbing feeling that the upper and lower ends of a bright object appear to flicker is also reduced. Further, in the first embodiment, it is necessary to take a logical sum of two temporally continuous frames, whereas in the second embodiment, since there is no such processing, the frame memory 12 has a small capacity band. There is also an advantage that a narrow one is sufficient.

(Third embodiment)
Next, as a third embodiment, a configuration in which a Gaussian filter is further applied to the minimum value filter image created in the first embodiment will be described.

  FIG. 6 is a block diagram of an intermediate image creation circuit in the image processing apparatus according to the third embodiment of the present invention. In the third embodiment, a configuration in which a Gaussian filter is applied to a minimum value filter image created in the same manner as in the first embodiment is used. 6 is the same as that of the first embodiment, and the Gaussian filter 53 is the same as that of the second embodiment. Further, since the configuration other than the intermediate image creation circuit is the same as that of the first embodiment, description will be made below using the reference numerals in FIG. 1A.

  FIG. 7 is an example of a processed image in the image processing apparatus according to the third embodiment. Similar to the first embodiment, the frame frequency conversion circuit 11 generates the first frame F11b and the second frame F12b from the input odd field F1b, and sends the first frame F11b to the delay circuit 14 and the second frame F11b. The frame F12b is output to the intermediate image creation circuit at 120 Hz.

  In the intermediate image creation circuit, the 5 × 5 minimum value filter 17 is applied to the second frame F12b (F13b), and then smoothed by the Gaussian filter 53 (F14b), and then gain (for example, 0. 33) to generate an intermediate image F15b. The subsequent processing is the same as in the first embodiment. The image obtained by subtracting the intermediate image F15b from the first frame F11b is the main frame M1b, the intermediate image F15b is the subframe S1b, and the output image with a frame frequency of 120 Hz is the selector 16. Is output from. Although intermediate processing is omitted, as shown in FIG. 7, the main frame M2b and the subframe S2b are similarly generated from the even field F2b.

  According to the method of the present embodiment described above, as in the first embodiment, it is possible to suppress the occurrence of striped pattern interference due to line flicker and to display an original image close to the interlace of the CRT and faithful to the original image. In addition, as in the second embodiment, the disturbing feeling that the upper end and the lower end of a bright object flicker can be reduced. In addition, according to the method of the present embodiment, the image area in the sub-frame S1b is smaller than the image area in the main frame M1b, so that better image quality than in the second embodiment can be obtained. Further, since the sub-frame S1b is blurred by the Gaussian filter, a slight shadow that appears when displaying a moving object is less noticeable than in the first embodiment.

(Other embodiments)
In the above embodiment, an image obtained by subtracting the luminance of the intermediate image from the odd and even frames is used as the main frame. However, the odd and even frames whose luminance is not adjusted may be used as they are as the main frame. In this case, the display is slightly brighter than the original image, but the objectives of reducing line flicker and displaying faithful to the original image can be achieved.
Since the sensitivity brightness of the human eye varies depending on the frame frequency, even if the exact same image is displayed at 60 Hz and 120 Hz, the 60 Hz display image looks about 1.08 times brighter than the 120 Hz display image. Therefore, it is preferable to perform correction so that the total luminance of the main frame and the subframe is 1.08 times the luminance of the original image. This enables interlaced display that looks as bright as the original image.

  11, 51: Frame frequency conversion circuit, 13, 52: Intermediate image creation circuit, 15: Subtraction circuit, 16: Selector, 18: Multiplier

Claims (6)

An odd frame is generated by inserting a blank line, which is a line not including image information, between the lines of the odd field of the input interlaced video signal, and an even number by inserting a blank line between the lines of the even field. Frame generating means for generating a frame;
Intermediate image generating means for generating an intermediate image that is darker than half of the original luminance, based on the image of either the odd frame or the even frame, or both images;
Output means for alternately outputting odd-numbered frames and even-numbered frames at a frame frequency twice the field frequency of the interlaced video signal, with the frame of the intermediate image sandwiched therebetween;
An image processing apparatus comprising: Subtracting means for subtracting the intermediate image from the odd and even frames generated by the frame generating means;
The image processing apparatus according to claim 1, wherein the output unit outputs an odd frame and an even frame obtained by subtracting the intermediate image by the subtracting unit.   The intermediate image generating means generates the intermediate image by applying a minimum value filter to a logical sum image of odd-numbered frames and even-numbered frames that are temporally continuous, and lowering the luminance from 1/2. The image processing apparatus according to claim 1, wherein the image processing apparatus is an image processing apparatus.   3. The intermediate image generation unit according to claim 1 or 2, wherein the intermediate image generation unit generates the intermediate image by applying a smoothing filter to an odd frame or an even frame and lowering the luminance below 1/2. The image processing apparatus described.   The intermediate image generating means applies a smoothing filter after applying a minimum value filter to a logical sum image of odd-numbered frames and even-numbered frames that are temporally continuous, and lowers the luminance by less than 1/2. The image processing apparatus according to claim 1, wherein an intermediate image is generated. A control method for an image processing apparatus, comprising:
An odd frame is generated by inserting a blank line, which is a line not including image information, between the lines of the odd field of the input interlaced video signal, and an even number by inserting a blank line between the lines of the even field. Generating a frame;
Generating an intermediate image that is darker than ½ of the original luminance based on the image of either the odd frame or the even frame, or both images; and
Alternately outputting odd frames and even frames at a frame frequency twice the field frequency of the interlaced video signal, with the intermediate image frame in between,
A control method for an image processing apparatus, comprising:

Images