JP2012094208A - Magnetic random access memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a spin injection type magnetic random access memory which is composed of a memory cell comprising a magnetic resistance element whose one end is connected to a bit line and a selection transistor whose one end is connected to the other end of the magnetic resistance element, whose gate is connected to a reading word line and whose other end is grounded, and is a magnetic random access memory capable securing both a writing margin and a reading margin by securing a writing current value equal to the conventional one.SOLUTION: The magnetic resistance element is configured to connect a plurality of separate magnetic resistance elements in series, an N channel transistor and a P channel transistor are respectively connected to both ends of the separate magnetic resistance element through a drain, a writing word line is connected to a gate of the N channel transistor and ground voltage is connected to a source, and an inverse writing word line is connected to a gate of the P channel transistor and power-supply voltage is connected to a source.

Description

  The present invention relates to a spin injection magnetic random access memory.

A spin injection magnetic random access memory (hereinafter referred to as MRAM) is a memory element using a magnetoresistive element exhibiting a magnetoresistive effect such as a TMR (Tunnel MagnetoResistance) effect. Data writing and erasing of this element are performed by injecting electron spin.
Specifically, the magnetoresistive element has a magnetic tunnel junction (MTJ) in which a tunnel barrier layer is sandwiched between two ferromagnetic layers, and is also referred to as an MTJ element. The two ferromagnetic layers are composed of a pinned layer whose magnetization direction is fixed and a free layer whose magnetization direction can be reversed (Patent Document 1).

  It is known that the MTJ resistance value when the magnetization directions of the pinned layer and the free layer are “antiparallel” is larger than the resistance value when they are “parallel” due to the magnetoresistance effect. . The MRAM uses such an MTJ element as a memory cell, and stores data in a nonvolatile manner by utilizing the change in resistance value. Data is read by passing a current through the MTJ and detecting the magnitude of the resistance value. Data is written to the memory cell by reversing the magnetization direction of the free layer.

  As a method for writing data to the MRAM, a “spin injection method” that can suppress an increase in write current accompanying miniaturization is being implemented. According to the spin injection method, a spin-polarized current is injected into the ferromagnetic conductor, and the magnetization is reversed by the direct interaction between the spin of the conduction electron carrying the current and the magnetic moment of the body (hereinafter referred to as spin injection magnetization). Invert).

  FIG. 5 shows a cycle of spin injection magnetization reversal. In FIG. 5, the MTJ element 60 includes a free layer 61 and a pinned layer 63 that are magnetic layers, and a tunnel barrier layer 62 that is a nonmagnetic layer sandwiched between the free layer 61 and the pinned layer 63. Here, the pinned layer 63 whose magnetic direction is fixed is formed so as to be thicker than the free layer 61, and plays a role as a mechanism (spin filter) for creating a spin-polarized current. The state in which the magnetization directions of the free layer 61 and the pinned layer 63 are parallel is associated with data “0”, and the state in which they are antiparallel is associated with data “1”.

  In FIG. 5, the write current IW is injected perpendicular to the film surface. Electrons having a spin flow in a direction opposite to the current IW. Specifically, the write current IW flows from the pinned layer 63 to the free layer 61 at the time of transition from data “0” to data “1”. In this case, electrons having the same spin state as the pinned layer 63 as a spin filter move from the free layer 61 to the pinned layer 63. Then, the magnetization (indicated by an arrow) of the free layer 61 is reversed by the spin transfer effect (transfer of spin angular momentum). On the other hand, at the transition from data “1” to data “0”, the write current IW flows from the free layer 61 to the pinned layer 63. In this case, electrons having the same spin state as the pinned layer 63 as a spin filter move from the pinned layer 63 to the free layer 61. As a result, the magnetization of the free layer 61 is reversed due to the spin transfer effect.

Thus, in spin injection magnetization reversal, data is written by the movement of spin electrons. The direction of magnetization of the free layer 61 can be defined by the direction of the spin-polarized current injected perpendicular to the film surface. Here, it is known that the threshold for writing (magnetization reversal) depends on the current density. Therefore, as the memory cell size is reduced, the write current required for magnetization reversal decreases. Since the write current decreases with the miniaturization of the memory cell, the spin injection magnetization reversal is important for realizing a large capacity of the MRAM.

  An example of such a spin injection MRAM memory cell is shown in FIG. In the figure, the cell is composed of an MTJ element 71 and a selection transistor 72. The free layer of the MTJ element 71 is connected to the bit line (BL), and the pinned layer is connected to one end of the selection transistor 72. The gate of the selection transistor 72 is connected to the word line (WL), and the other end (source) is connected to the source line (SL). FIGS. 6A and 6B show circuits when N-channel transistors and P-channel transistors are used as selection transistors, respectively. FIGS. 6C and 6D show a state where “0” and “1” are written in the circuit of FIG. 6A by the input of each terminal and the direction of current flow (arrows in the figure).

  As shown in FIG. 6C, when “0” is written, the source line, the word line, and the bit line of the selection transistor are connected to the ground VSS, the power supply voltage VDD, and the power supply voltage VDD, respectively. At this time, the MTJ element 71 and the selection transistor 72 are grounded, and a power supply voltage can be applied to the MTJ element in the high resistance state, so that a sufficient current can flow. As shown in FIG. 6D, when “1” is written, the source line, the word line, and the bit line of the selection transistor are connected to the power supply voltage VDD, the power supply voltage VDD, and the ground VSS, respectively. At this time, the voltage between the MTJ element 71 and the selection transistor 72 is a voltage that is lowered by the threshold voltage Vth of the selection transistor 72 with respect to the power supply voltage.

  FIG. 7 shows a partial explanatory diagram of an example of an MRAM using such an MTJ element memory cell. When reading data from the memory cell 75, the source line and the word line of the selection transistor 72 are connected to the ground VSS and the selection signal (power supply voltage VDD), respectively. The bit line is connected to one input of the sense amplifier 73. The reference signal output from the reference cell (Ref.) 74 is input to the other input of the sense amplifier 73. The input from the bit line is compared with the reference signal, and “0” and “1” are compared. The data of the memory cell 75 is read out. That is, the magnitudes of the currents in the reference cell 74 and the memory cell 75 are compared by the sense amplifier and reading is performed. Here, it is the resistance value of the MTJ element 71 that determines the magnitude of the current.

  However, when the resistance value of the MTJ element is smaller than the on-resistance and wiring resistance of the select transistor 72, the difference in resistance value between the MTJ element 71 of the reference cell 74 and the memory cell 75 is caused by variations in MOS on-resistance and wiring resistance. It will be buried in the variation and correct reading will not be possible. Therefore, when reading data from the memory cell 75, the resistance value of the MTJ element 71 is preferably larger than the on-resistance and wiring resistance of the selection transistor 72. However, when writing data, it is necessary to pass a sufficient amount of current, so a smaller resistance value is preferable.

  That is, the above problem is that the conventional spin injection MRAM has the same current path at the time of writing and at the time of reading, and therefore there is a trade-off relationship between the writing margin and the reading margin. In order to ensure a large write current during writing, the resistance value of the MTJ is designed to be relatively small. In this case, since the contribution of the on-resistance and wiring resistance of the transistor to the resistance value of the MTJ detected at the time of reading increases, the variation in the resistance value of the MTJ is not significant. That is, the quality of the read signal is deteriorated and accurate reading becomes difficult. In order to avoid this, it is necessary to design the resistance value of the MTJ to be relatively large. In this case, it becomes difficult to supply a sufficient write current that exceeds the threshold for writing.

  As described above, the conventional method has a problem in that it is difficult to secure both the write margin and the read margin.

  On the other hand, a semiconductor device is disclosed in which magnetic tunnel junction elements that take the same resistance state when a write current is applied are arranged in series on both sides of a source / drain of a selection transistor (Patent Document 3). However, in such a circuit in which the selection transistor and the two magnetic tunnel junction elements are arranged in series, the current path is the same at the time of writing and at the time of reading, so a larger write current is required than before. There was a problem.

WO2008 / 018266 JP 2008-198311 A JP 2009-094226 A

  It is an object of the present invention to provide a magnetic random access memory that can secure a write current value equivalent to that of the prior art and can secure both a write margin and a read margin.

The present invention has been made in view of the problems, and the invention of claim 1
The magnetoresistive element has one end connected to the bit line, and one end connected to the other end of the magnetoresistive element, the gate connected to the read word line, and the other end connected to the ground. A spin injection magnetic random access memory comprising memory cells,
The magnetoresistive element is formed by connecting a plurality of individual magnetoresistive elements in series, and N-channel transistors and P-channel transistors are connected to both ends of the individual magnetoresistive elements by drains,
A write word line is connected to the gate of the N-channel transistor, and a ground voltage is connected to the source.
The magnetic random access memory is characterized in that an inversion write word line is connected to the gate of a P-channel transistor and a power supply voltage is connected to the source.

  Since the present invention is configured as described above, it is possible to provide a magnetic random access memory that can secure a write current value equivalent to the conventional one and secure both a write margin and a read margin.

It is explanatory drawing which showed the example of embodiment of the memory cell concerning this invention. It is the partial explanatory view showing the magnetic random access memory of the example of the embodiment of the present invention. It is another partial explanatory view showing a memory cell of an example of an embodiment of the present invention. FIG. 5 is another partial explanatory view showing a memory cell according to an embodiment of the present invention. It is explanatory drawing which shows the cycle of spin injection magnetization reversal. It is explanatory drawing which shows an example of the memory cell of the conventional MRAM of a spin injection system. Partial explanatory drawing of an example of MRAM using the memory cell by the conventional MTJ element

  Hereinafter, modes for carrying out the present invention will be described.

  The magnetic random access memory of the present invention has a magnetoresistive element having one end connected to the bit line, one end connected to the other end of the magnetoresistive element, a gate connected to the read word line, and the other end connected to the ground. It is assumed that the magnetic random access memory is based on a spin injection method and includes a memory cell composed of the selected transistor. The magnetoresistive element is formed by connecting a plurality of individual magnetoresistive elements in series, and N-channel transistors and P-channel transistors are connected to both ends of the individual magnetoresistive elements by drains. A write word line is connected to the gate of the N channel transistor, a ground voltage is connected to the source, an inverted write word line is connected to the gate of the P channel transistor, and a power supply voltage is connected to the source. To do.

  FIG. 1 is an explanatory diagram showing an embodiment of a memory cell according to the present invention. In FIG. 1, a memory cell 5 according to the spin injection magnetic random access memory of this example has a magnetoresistive element having one end connected to a bit line and one end connected to the other end of the magnetoresistive element, and a gate read out. The selection transistor 2 is connected to the main word line and the other end is connected to the ground. The magnetoresistive elements are formed by connecting individual magnetoresistive elements (MTJ elements 11 and 12) in series, and N-channel transistors N1 and N2 are connected to both ends of the individual magnetoresistive elements (MTJ elements 11 and 12), respectively. , N3 and P-channel transistors P1, P2, and P3 are paired (N1-P1, N2-P2, and N3-P3, respectively) and connected at the drain. Write word lines WWLT0, WWLT1, and WWLT2 are connected to the gates of the N-channel transistors N1, N2, and N3, and a ground voltage is connected to the sources. Inverted write word lines WWLB0, WWLB1, and WWLB2 are connected to the gates of the P-channel transistors P1, P2, and P3, and a power supply voltage is connected to the sources. The free layer of each magnetoresistive element (MTJ element 11, 12) is connected to the bit line side or the side close to the bit line, and the pinned layer is connected to the selection transistor 2 side or the side close to the selection transistor 2 side.

  FIG. 2 is a partial explanatory view showing a magnetic random access memory according to an embodiment of the present invention, and shows a read state of a cell. The bit line BL of each memory cell is connected to one input of the sense amplifier 3 and the other input is connected to the output of the reference cell 4. Since the selection transistor 2 is input to the sense amplifier through the magnetoresistive elements (MTJ elements 11 and 12) whose drains are connected in series, the read signal VDD is input to the read word line. The resistance value of the magnetoresistive element can be made larger than the wiring resistance, and the read margin can be improved.

  FIG. 3 is a partial explanatory view showing a memory cell according to an embodiment of the present invention, and shows a written state of the cell. FIG. 3 shows a case where “0” is written.

FIG. 3A shows a state in which the MTJ element 11 is written. WWLT1 and WWLB0 are selected as the write word lines. That is, the N-channel transistor N2 and the P-channel transistor P1 connected to both terminals of the MTJ element 11 are turned on, and all other transistors are turned off. As a result, the MTJ element 1
Current flows from the bit line side of 1 (the free layer side of the MTJ element 11), and "0" is written. FIG. 3B shows a writing state of the MTJ element 12. WWLT2 and WWLB1 are selected as the write word lines. That is, the N-channel transistor N3 and the P-channel transistor P2 connected to both terminals of the MTJ element 12 are turned on, and all other transistors are turned off. As a result, a current flows from the side of the MTJ element 12 facing the bit line (from the free layer side of the MTJ element 12 to the pinned layer side), and “0” is written.

  FIG. 4 is a partial explanatory view showing a memory cell according to an embodiment of the present invention, and shows a written state of the cell. FIG. 4 shows a case where “1” is written.

  FIG. 4A shows a state in which the MTJ element 11 is written. WWLT0 and WWLB1 are selected as the write word lines. That is, the N-channel transistor N1 and the P-channel transistor P2 connected to both terminals of the MTJ element 11 are turned on, and all other transistors are turned off. As a result, current flows from the MTJ element 11 to the bit line side (from the pinned layer to the free layer side of the MTJ element 11), and “1” is written. FIG. 4B shows a state in which the MTJ element 12 is written. WWLT1 and WWLB2 are selected as the write word lines. That is, the N-channel transistor N2 and the P-channel transistor P3 connected to both terminals of the MTJ element 12 are turned on, and all other transistors are turned off. As a result, a current flows in the direction of the MTJ element 12 toward the bit line (from the pinned layer to the free layer side of the MTJ element 12), and “1” is written.

  In this example, the number of magnetoresistive elements is two. However, it is obvious that writing and reading can be performed in the same manner with a larger number of elements. Further, the individual magnetoresistive elements do not have to have the same value.

  As described above, in the magnetic random access memory of the present application, when writing data, a current is passed through each individual magnetoresistive element connected in series and when reading data, Current can flow through a path in which magnetoresistive elements are connected in series. That is, by separating the current path at the time of writing and the current path at the time of reading so that each magnetoresistive element can be written independently, a write current value equivalent to the conventional one can be secured, and the write margin and the read margin can be reduced. The magnetic random access memory can secure both.

11, 12, 71 ... MTJ elements 2, 72 ... select transistors 3, 73 ... sense amplifiers 4, 74 ... reference cells 5, 75 ... memory cells 60 ... MTJ elements 61 .... Free layer 62 ... Tunnel barrier layer 63 ... Pin layers N1, N2, N3 ... N channel transistors P1, P2, P3 ... P channel transistors

Claims (1)

The magnetoresistive element has one end connected to the bit line, and one end connected to the other end of the magnetoresistive element, the gate connected to the read word line, and the other end connected to the ground. A spin-injection magnetic random access memory comprising memory cells, wherein a magnetoresistive element is formed by connecting a plurality of individual magnetoresistive elements in series, and an N-channel transistor and a P The channel transistor is connected at the drain,
A write word line is connected to the gate of the N-channel transistor, and a ground voltage is connected to the source.
A magnetic random access memory comprising a P channel transistor having a gate connected to an inverted write word line and a source connected to a power supply voltage.

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