JP2012093945A - Node controller, output order determination method of requests and inter-node communication system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the entire processing performance of plural requests when accessing other nodes by inter-node communication.SOLUTION: A node controller is connected to plural nodes and includes: a priority calculation circuit for accepting plural requests to a processor belonging to any of plural nodes from plural processors within its own node and calculating a priority according to a node of request destination of the request for each of the plural requests; a determination circuit for determining the request to be output among the accepted plural requests based on the calculated priority; and a selecting circuit for selecting the determined request and outputting it to the node of request destination.

Description

  The present invention relates to a node controller, a request output order determination method, and an inter-node communication system, and in particular, a node controller for arbitrating a request transmission order when accessing another node by inter-node communication, and a request output. The present invention relates to an order determination method and an inter-node communication system.

  A large-scale computer system has a plurality of processors in order to execute a plurality of processes in parallel. A plurality of processors are managed as one node. Furthermore, a plurality of such nodes are provided, the nodes are connected, and predetermined processing is realized by processing of each node and inter-node communication. In such a large-scale computer system, data communication frequently occurs between nodes. For example, in order to complete the processing in a certain processor, the processing may be performed on another processor and the result may be required. At that time, the requesting processor transmits a request to the requesting processor and receives a response. When the request source and the request destination belong to different nodes, inter-node communication occurs.

  Patent Document 1 discloses a technology related to a memory access control circuit for guaranteeing latency in a flexible and reliable manner with respect to competition between a plurality of access masters for one memory. The memory access control circuit disclosed in Patent Document 1 is provided between a plurality of access masters and a memory. Priority comparison circuit. Compare the priorities held in the priority registers. The selector permits access to the access master with the highest priority. The priority held in the priority register increases by subtracting the value of the subtraction value register every time access is waited. This facilitates access. The continuous access number register holds the number of continuous accesses. When the continuous access count reaches the value of the access upper limit count register, the priority of the initial value held in the priority register when the next access request is made is kept low.

  In general, in order to improve the request processing performance in inter-node communication, a priority is given to a specific request, a request with a higher priority is sent first, and the request is processed with priority. Has improved. For example, when there are dependencies among a plurality of requests, the subsequent requests can be efficiently processed by setting the priority of the request to be processed first in advance. Since the dependency relationship between such a plurality of requests is logically determined, priority can be set in advance.

JP 2005-173859 A

  However, in recent large-scale computer systems using a plurality of nodes, the number of nodes is large, and the connection relationship between the nodes is complicated. The connection relationship between the nodes is basically irrelevant to the dependency relationship logically determined in a plurality of requests. For example, the connection relationship between nodes varies depending on the overall processing performance and the cost that can be spent on hardware. Therefore, even for the same request, depending on the arrangement and number of nodes, there may be a large difference in the number of nodes that pass through, that is, the time required for the request to reach the request destination. In that case, there is a difference in the overall processing time for the same request. Therefore, there is a problem that there is a limit in setting the priority of the request in advance based on the dependency relationship described above.

  For example, if the number of HOPs of subsequent requests is larger, a request with a smaller number of HOPs may be transmitted first according to the priority. In that case, even if processing of a request with a high priority is completed, subsequent requests are not completed, so that further subsequent requests cannot be executed. For this reason, depending on the timing of participating in the arbitration of the request transmission order, it may take time to start the processing, and the performance may deteriorate.

  Note that Patent Document 1 is not intended to solve the above-described problem in inter-node communication.

  The present invention has been made in order to solve such a problem. A node controller for improving the overall processing performance of a plurality of requests when accessing other nodes by inter-node communication, An object is to provide an output order determination method and an inter-node communication system.

  The node controller according to the first aspect of the present invention is connected to a plurality of nodes, receives a plurality of requests from a plurality of processors in its own node to a processor belonging to any of the plurality of nodes, and For each request, a priority calculation circuit that calculates a priority according to a request destination node of the request, and a request to be output among the plurality of received requests is determined based on the calculated priority. A determination circuit; and a selection circuit that selects the determined request and outputs the selected request to the requested node.

  The method for determining the output order of requests according to the second aspect of the present invention includes: a first request from a first processor in a first node to a processor in a second node; The second request from the second processor to the processor in the third node is received at the same time, and the first priority and the second priority according to the request source of the first request and the second request Calculating a degree, determining whether to output the first request or the second request based on the first priority and the second priority, and selecting the determined request To the requested node.

  The inter-node communication system according to the third aspect of the present invention is connected to a plurality of nodes, receives a plurality of processors, and a plurality of requests from the plurality of processors to a processor belonging to any of the plurality of nodes, For each of the plurality of requests, priority calculation means for calculating a priority according to the request destination node of the request, and a request to be output among the plurality of received requests based on the calculated priority A node controller comprising: a determining unit that determines a request; and a selecting unit that selects the determined request and outputs the selected request to the requested node.

  According to the present invention, it is possible to provide a node controller, a request output order determination method, and an inter-node communication system for improving overall processing performance of a plurality of requests when accessing other nodes by inter-node communication.

It is a block diagram which shows the structure of the communication system between nodes concerning Embodiment 1 of this invention. It is a flowchart which shows the flow of a process of the access arbitration method concerning Embodiment 1 of this invention. It is a block diagram which shows the structure of the computer system concerning Embodiment 2 of this invention. It is a block diagram which shows the structure of the node controller concerning Embodiment 2 of this invention. It is a figure which shows the example of the table concerning Embodiment 2 of this invention. It is a flowchart for demonstrating the flow of the access arbitration method concerning Embodiment 2 of this invention. It is a flowchart for demonstrating the flow of the reset process of the selection coefficient concerning Embodiment 2 of this invention. It is a figure for demonstrating the processing speed of a request at the time of applying a round robin. It is a figure for demonstrating the processing speed of the request concerning Embodiment 2 of this invention.

  Hereinafter, specific embodiments to which the present invention is applied will be described in detail with reference to the drawings. In the drawings, the same elements are denoted by the same reference numerals, and redundant description will be omitted as necessary for the sake of clarity.

<Embodiment 1 of the Invention>
FIG. 1 is a block diagram showing a configuration of an inter-node communication system 100 according to the first exemplary embodiment of the present invention. The inter-node communication system 100 includes at least a node 1, a node 2, and a node 3. Each of the nodes 1 to 3 is a general-purpose computer device equipped with a plurality of processors. The nodes 1 to 3 are connected by signal lines or the like. Thereby, the processor contained in each node can transmit / receive the processing request with respect to the processor contained in another node.

  The node 1 includes processors 11a, 11b,... And 11n, and a node controller 12. The processors 11a, 11b,... And 11n are, for example, CPUs (Central Processing Units). Each processor is connected to each other. Each processor performs a predetermined process independently. At that time, each processor performs inter-processor communication as necessary. For example, the processor 11a transmits a processing request (request) to the processor 11b. Then, the processor 11b executes processing according to the request and returns a request result to the processor 11a. Thereafter, the processor 11a executes subsequent processing in accordance with the request result received from the processor 11b.

  The processors 11a, 11b,..., And 11n are connected to the node controller 12, respectively. Each processor may transmit the request to another node, that is, a processor belonging to either node 2 or 3. In that case, each processor communicates with a processor belonging to another node via the node controller 12.

  The node controller 12 receives a plurality of requests for which the node 2 or 3 is a request destination from each processor, and controls output of the received plurality of requests. Further, the node controller 12 receives a request from the node 2 or 3, and outputs the request to any of the processors 11a, 11b,.

  The node controller 12 includes a priority calculation circuit 13, a determination circuit 14, and a selection circuit 15. The priority calculation circuit 13 receives a plurality of requests from a plurality of processors in its own node to a processor belonging to any of the plurality of nodes, and for each of the plurality of requests, it corresponds to a request destination node of the request. Calculate the priority. The determination circuit 14 determines a request to be output from among the plurality of received requests based on the calculated priority. The selection circuit 15 selects the determined request and outputs it to the requested node. In practice, the node controller 12 performs a predetermined process on the request output from the selection circuit 15 and then outputs the request to the outside of the node 1. The predetermined process is general. Therefore, detailed description is omitted.

  The node 2 includes a plurality of processors 21 and a node controller 22. The node 3 includes a plurality of processors 31 and a node controller 32. Since the nodes 2 and 3 have the same function as the node 1, detailed description thereof is omitted. That is, the processors 21 and 31 are equivalent to the processor 11a and the like. The node controllers 22 and 32 are equivalent to the node controller 12.

  Note that the number of processors mounted on the nodes 1 to 3 is not limited to the illustrated one. For example, the node 1 may be equipped with one or more processors.

  FIG. 2 is a flowchart showing a process flow of the access arbitration method according to the first exemplary embodiment of the present invention. First, the node controller 12 receives a plurality of requests from the processors 11a to 11n (S11). Next, the priority calculation circuit 13 calculates the priority of each request (S12). Then, the determination circuit 14 determines a request to be output based on the priority (S13). Thereafter, the selection circuit 15 selects and outputs the determined request (S14).

  In addition, the access arbitration method according to the first exemplary embodiment of the present invention can be paraphrased as follows at least when the inter-node communication system 100 includes three nodes. First, a first request from a first processor in a first node to a processor in a second node, and a second request from a second processor in the first node to a processor in a third node. 2 requests are accepted at the same time. Next, the first priority and the second priority corresponding to the request sources of the first request and the second request are calculated. Then, based on the first priority and the second priority, it is determined which of the first request and the second request should be output. Then, a request output order determination method, wherein the determined request is selected and output to the request destination node.

  For example, when the request destination nodes of a plurality of requests are different, the priority is calculated not according to the request type but according to the request destination node. Accordingly, the priority can be obtained in consideration of a case where a difference occurs in the request transmission time depending on the arrangement and connection state of the nodes. Therefore, according to the first embodiment of the present invention, it is possible to improve the overall processing performance of a plurality of requests when accessing other nodes by inter-node communication, compared to the case where the positional relationship of the nodes is ignored. .

<Embodiment 2 of the Invention>
FIG. 3 is a block diagram showing a configuration of a computer system 100a according to the second embodiment of the present invention. The computer system 100a is an example of the inter-node communication system 100 according to the first embodiment described above. The computer system 100a includes nodes 101 to 108. Note that the number of nodes included in the computer system 100a is not limited to this.

  The node 101 includes a node controller 111 and processors 112 to 115. That is, the node controller 111 and the processors 112 to 115 are regarded as one unit, and a combination of them is called a node 101. The node controller 111 and the processors 112 to 115 are connected one by one with signal lines. Similarly, the node 102 includes a node controller 121 and processors 122 to 125. The node controller 121 and the processors 122 to 125 are connected one by one with signal lines.

  In addition, the nodes 103, 104, 105, 106, 107, and 108 include node controllers 131, 141, 151, 161, 171 and 181 and a plurality of processors, but they are not shown.

  Here, the connection relationship between the nodes according to FIG. 3 will be described below. In FIG. 3, in each node, node controllers between adjacent nodes are connected one-to-one by signal lines. Thereby, access between nodes is realized.

  Specifically, the node controller 111 is connected to adjacent node controllers 121, 131, 141, 171 and 181 on a one-to-one basis via signal lines 305, 306, 307, 301 and 302. Similarly, the node controller 121 is connected to the adjacent node controllers 111, 131, 141, 171 and 181 on a one-to-one basis via signal lines 305, 308, 309, 303 and 304. The node controller 131 is connected to the adjacent node controllers 111, 121, 141, 151 and 161 in a one-to-one manner via signal lines 306, 308, 310, 311 and 312. The node controller 141 is connected to the adjacent node controllers 111, 121, 131, 151 and 161 on a one-to-one basis via signal lines 307, 308, 310, 313 and 314. The node controller 151 is connected to the adjacent node controllers 131, 141, and 161 via signal lines 311, 313, and 315 on a one-to-one basis. The node controller 161 is connected to adjacent node controllers 131, 141, and 151 in a one-to-one manner via signal lines 312, 314, and 315. The node controller 171 is connected to the adjacent node controllers 111, 121, and 181 on a one-to-one basis through signal lines 301, 303, and 316. The node controller 181 is connected to the adjacent node controllers 111, 121, and 171 on a one-to-one basis through signal lines 302, 304, and 316. In addition, illustration and description of the connection relationship between the nodes 105, 106, 107, and 108 are omitted.

  Access between node controllers that are not connected to each other is performed with another node controller in between. That is, FIG. 3 shows that the nodes 101 and 102 and the nodes 105 and 106 are not directly connected, and it is necessary to perform inter-node communication via the node 103 or 104. For example, when accessing the node controller 161 from the node controller 111, access is made via the node controller 131 via the signal lines 306 and 312 or via the node controller 141 via the signal lines 307 and 314. to access. Since a known technique can be used to determine the route to be accessed at this time, detailed description thereof is omitted.

  FIG. 4 is a block diagram showing a configuration of the node controller 111 according to the second exemplary embodiment of the present invention. In particular, FIG. 4 illustrates a configuration for determining an output order when outputting requests received from the processors 112 to 115 among the configurations of the node controller 111. Therefore, illustration and description of other configurations in the node controller 111 are omitted.

  The node controller 111 includes a table 201, request storage buffers 202 to 205, select coefficient storage registers 206 to 209, select coefficient generation circuits 210 to 213, request holding registers 214 to 217, and select coefficient holding registers 218 to 221. And select coefficient arbitration circuits 222 to 225, a request arbitration circuit 226, and a selector 227.

  The table 201 is a storage unit that stores a request destination node included in a request issued from a processor and the number of hops in association with each other. Here, the number of hops is the number of nodes through which the request passes to reach the requested node from its own node. Alternatively, the number of hops may indicate a unit of time taken from the current request position to the request transmission destination.

  FIG. 5 is a diagram illustrating an example of a table according to the second embodiment of the present invention. Here, as an example, it is assumed that five records # 401 to # 405 are registered in the table 201 in advance. “DIND” is a value representing the request destination included in the request in binary. “HOP number” indicates the number of hops described above. Note that the values shown in FIG. 5 do not correspond to the nodes shown in FIG. 3 and their connection relationships. In addition, the values registered in the table 201 are appropriately changed when the node connection relationship in the computer system 100a is changed.

  Here, the request storage buffer 202, the request holding register 214, the select coefficient generation circuit 210, the select coefficient storage register 206, the select coefficient arbitration circuit 222, and the select coefficient holding register 218 perform processing on the request output from the processor 112. Similarly, the request storage buffer 203, the request holding register 215, the select coefficient generation circuit 211, the select coefficient storage register 207, the select coefficient arbitration circuit 223, and the select coefficient holding register 219 perform processing for the request output from the processor 113. The request storage buffer 204, the request holding register 216, the select coefficient generation circuit 212, the select coefficient storage register 208, the select coefficient arbitration circuit 224, and the select coefficient holding register 220 perform processing on the request output from the processor 114. The request storage buffer 205, request holding register 217, select coefficient generation circuit 213, select coefficient storage register 209, select coefficient arbitration circuit 225, and select coefficient holding register 221 perform processing on the request output from the processor 115. Therefore, in the following description, the configuration corresponding to the processor 112 will be mainly described, and the description corresponding to the configuration corresponding to the processors 113 to 115 will be omitted as appropriate.

  The request storage buffer 202 is a buffer that stores a request output from the processor 112. The request storage buffer 202 can store a plurality of requests, and outputs a request to the subsequent request holding register 214 by a FIFO (First In First Out) method.

  The select coefficient storage register 206 is a register that stores a select coefficient that is a value indicating a priority when a request arbitration circuit 226 described later arbitrates a plurality of requests. The number of values that can be stored in the select coefficient storage register 206 is the same as the number of requests that can be stored in the request storage buffer 202.

  The select coefficient generation circuit 210 extracts a request destination from the request output from the processor. Then, the select coefficient generation circuit 210 acquires the number of hops corresponding to the extracted request destination from the table 201. Thereafter, the select coefficient generation circuits 210 to 213 decode the acquired number of hops. That is, for the request received from the processor 112, the select coefficient generation circuit 210 obtains the number of hops associated with the request destination node from the table 201, and calculates the select coefficient.

  For this reason, the select coefficient generation circuits 210 to 213 accept a plurality of requests from processors 112 to 115 that request processors belonging to external nodes as request destinations, and each of the plurality of requests corresponds to the request destination node of the request. It can be said that the selection coefficient is calculated. Further, it can be said that the select coefficient generation circuits 210 to 213 calculate the select coefficient higher as the number of hops is larger.

  The select coefficient generation circuit 210 also stores each of the requests stored in the select coefficient storage register 206 when the request held in the request holding register 214 is not determined as a request to be output by arbitration in the request arbitration circuit 226. Add 1 to the select coefficient. That is, the select coefficient generation circuit 210 selects a select coefficient in a request that is not subject to arbitration when the request is stored in the request storage buffer 202 and the request is not output to the request holding register 214. Update to a higher priority. Therefore,

  Therefore, the value calculated by the select coefficient generation circuit 210 is stored in the select coefficient storage register 206 as a select coefficient.

  The request holding registers 214 to 217 are registers that hold requests that are subject to arbitration in the request arbitration circuit 226. For example, the request holding register 214 stores the requests in the order in which the requests are stored in the request storage buffer 202. When no request is stored in the request storage buffer 202, the request output from the processor 112 is directly stored in the request holding register 214 without going through the request storage buffer 202.

  The select coefficient holding register 218 is a register that stores a select coefficient corresponding to a request to be arbitrated in the request arbitration circuit 226. Specifically, the select coefficient output in the select coefficient arbitration circuit 222 described later is stored in the select coefficient holding register 218. That is, the select coefficient holding registers 218 to 221 correspond to the request holding registers 214 to 217, respectively.

  The select coefficient arbitration circuit 222 arbitrates between the select coefficient generation circuit 210, the select coefficient storage register 206, and the three select coefficients output from the request arbitration circuit 226. That is, the select coefficient arbitration circuit 222 selects any one of the above-described three select coefficients and outputs it to the select coefficient holding register 218. For example, when the request arbitration circuit 226 determines that the request stored in the request holding register 214 is to be output, the select coefficient arbitration circuit 222 selects the select coefficient output from the select coefficient generation circuit 210 or the select coefficient storage register 206. Output coefficients. At this time, if the request has been stored in the request storage buffer 202, the select coefficient output from the select coefficient storage register 206 is selected. If the request is not stored in the request storage buffer 202, the select coefficient is selected. A select coefficient output from the generation circuit 210 is selected. If the request arbitration circuit 226 determines that the request stored in the request holding register 214 is not a request to be output, the selection coefficient output from the request arbitration circuit 226 is selected.

  The request arbitration circuit 226 arbitrates based on the select coefficient stored in the select coefficient holding registers 218 to 221, determines a request to be output, and notifies the selector 227. That is, the request arbitration circuit 226 determines a request to be output from among a plurality of requests stored in the request holding registers 214 to 217, that is, requests to be arbitrated, and determines which of the request holding registers 214 to 217 should be selected. Notify the selector 227.

  Further, the request arbitration circuit 226 resets the select coefficient based on the determined rule for the request leaked from the output target due to the arbitration, and outputs it to the select coefficient arbitration circuits 222 to 225. In other words, the request arbitration circuit 226 updates the select coefficient higher for the undecided requests that have not been determined as requests to be output among the requests to be arbitrated based on the predetermined criteria. At this time, the select coefficient generation circuits 210 to 213 calculate select coefficients for subsequent requests received after the request to be arbitrated. Thereafter, the request arbitration circuit 226 determines a request to be output based on the select coefficient updated for the undecided request and the select coefficient calculated for the subsequent request.

  Furthermore, when the request source of the subsequent request and the request source of the undetermined request are the same processor, the request arbitration circuit 226 excludes the subsequent request from the arbitration target. Then, the select coefficient generation circuits 210 to 213 update the select coefficient of the subsequent request that has been excluded from higher.

  The selector 227 selects and outputs the request received from the request arbitration circuit 226. That is, the selector 227 selects a request that has been determined to be output by the request arbitration circuit 226 and outputs the request to the requested node.

  Here, the first request and the second request are accepted, the select coefficient calculated for the first request is the first priority, and the select coefficient calculated for the second request is the second priority. An operation according to the second embodiment of the present invention will be described. The select coefficient generation circuit calculates the first priority higher than the second priority when the number of hops in the first request is larger than the number of hops in the second request. Then, the request arbitration circuit 226 determines the first request as a request to be output.

  FIG. 6 is a flowchart for explaining the flow of the access arbitration method according to the second exemplary embodiment of the present invention. First, as a premise, it is assumed that the number of hops corresponding to the request destination of each request is already stored in the table 201 from its own node.

  Then, the node controller 111 receives requests from the processors 112 to 115 and stores them in the request storage buffers 202 to 205 (S21). The request to be arbitrated is held in the request holding registers 214 to 217. Next, the select coefficient generation circuits 210 to 213 calculate a select coefficient for the received request with reference to the table 201 and store them in the select coefficient storage registers 206 to 209 (S22). In the example of FIG. 5, when the DNID of the request destination of the request is “000”, the hop count is “10” (# 401).

  Thereafter, the request arbitration circuit 226 arbitrates (S23). In other words, the request arbitration circuit 226 compares the select coefficients stored in the reselect coefficient holding registers 218 to 221 to determine which of the requests stored in the corresponding request holding registers 214 to 217 should be output. Then, the request arbitration circuit 226 notifies the selector 227 of the determined request.

  At this time, as a criterion for determination of the request arbitration circuit 226, arbitration is given priority from the one with the larger select coefficient, and second, when the select coefficient has the same value, the arbitration is started from the smaller selector number. Shall be. However, the criterion for determination by the request arbitration circuit 226 is not limited to this.

  Thereafter, the selector 227 selects and outputs the request determined by the request arbitration circuit 226 (S24). Further, the request arbitration circuit 226 updates the selection coefficient of the undetermined request (S25). During this time, when a subsequent request is accepted in step S21, in step S22, the select coefficient generation circuits 210 to 213 calculate a select coefficient in the subsequent request. In addition to the step S25, the select coefficient generation circuits 210 to 213 update the select coefficient of the subsequent request of the undetermined request as described above.

  Then, returning to step S23, the request arbitration circuit 226 determines which of the subsequent request of the output request and the undecided request should be output. Thereafter, it is repeatedly executed until the request is not accepted.

  Here, an example of a selection coefficient resetting method in the request arbitration circuit 226 will be described. Note that the method of resetting the select coefficient according to the second embodiment of the present invention is not limited to this. The request arbitration circuit 226 uses a request selection coefficient determined as a request to be output, a selection coefficient of an undetermined request, and a plurality of nodes as predetermined criteria when updating the selection coefficient for an undetermined request. The maximum value of the number of nodes through which a request reaches the request destination node from its own node is used.

  FIG. 7 is a flowchart for explaining a flow of the selection coefficient resetting process according to the second embodiment of the present invention. First, the request arbitration circuit 226 calculates the difference between the selection coefficients of the decision request and the undecided request (S31). A decision request is a request that is determined to be output by arbitration. An undecided request is a request that was the next point due to arbitration.

Next, the request arbitration circuit 226 determines whether or not the difference calculated in step S31 is greater than or equal to ½ of the maximum hop count that is the maximum value among the hop counts stored in the table 201 (S32). . That is, it is determined whether or not the following expression (1) is satisfied.
Difference ≥ Maximum number of hops x 1/2 (1)

If it is determined in step S32 that it is equal to or greater than 1/2, the request arbitration circuit 226 adds a value obtained by adding 1 of the arbitration wait time to the value of 1/2 of the difference to the select coefficient (S33). That is, the select coefficient is updated by the following equation (2).
Select coefficient = Select coefficient + Difference x 1/2 + 1 (2)

If it is determined in step S32 that the value is less than ½, the request arbitration circuit 226 adds a value obtained by adding 1 for the arbitration waiting to the difference to the select coefficient (S34). That is, the select coefficient is updated by the following equation (3).
Select coefficient = Select coefficient + Difference + 1 (3)

  When the decimal point of the select coefficient is generated, it is rounded up and calculated. Then, the request arbitration circuit 226 executes the process of FIG. 7 for all the undecided requests.

  Below, a specific example is shown and demonstrated. First, in the example of FIG. 5, the maximum number of hops is “25”. Therefore, the comparison value used for the comparison in step S32 is “12.5”, which is ½ of the maximum hop count. In the following, requests A, B, C, and D are targeted. The DINDs of the requests A, B, C, and D are “010”, “100”, “011”, and “001”. The request D is a request that can become an access bottleneck in the system. Hereinafter, a description will be given with reference to FIGS. 6 and 7.

  First, the node controller 111 simultaneously receives requests A, B, and C from the processors 112 to 114 and stores them in the request storage buffers 202 to 204 (S21). The requests A, B, and C are stored in the request holding registers 214 to 216. That is, it is assumed that three requests A, B, and C are subject to arbitration at the same time.

  Next, the select coefficient generation circuits 210 to 212 obtain the hop numbers “5”, “5”, and “20” from the table 201 based on the DINDs of the requests A, B, and C, and select coefficient storage registers 206 as selector coefficients. To 208 (S22). In addition, the select coefficient is also stored in the select coefficient holding registers 218 to 220.

  Then, the request arbitration circuit 226 compares the three selector coefficients, and determines that the request C corresponding to the maximum value “20” is to be output (S23). Then, the request arbitration circuit 226 notifies the selector 227 that the request C has been determined (S24).

  At the same time, the request arbitration circuit 226 calculates the difference “15” between the selection number “20” of the request C that is the arbitration winner and the selection coefficient “5” of the requests A and B that are the next points of the arbitration (S31). ). Then, the request arbitration circuit 226 compares the difference “15” with the above-described comparison value “12.5” (S32). Here, since the difference “15” is equal to or greater than the comparison value “12.5”, the request arbitration circuit 226 adds “8” that is ½ of the difference “15” to the select coefficient “5” of the requests A and B. The selection coefficient “14” is calculated by adding “1” and “1” (S33), and is output to the selection coefficient arbitration circuits 222 and 223. Therefore, “14” is stored in the select coefficient holding registers 218 and 219, respectively.

  Here, it is assumed that the node controller 111 receives the request D as a subsequent request from the processor 115 after step S21 described above (S21). Therefore, the node controller 111 stores the request D in the request storage buffer 205 and then in the request holding register 217. The select coefficient generation circuit 213 acquires the hop count “25” from the table 201 based on the DIND of the request D, and stores it in the select coefficient storage register 209 as a selector coefficient (S22). In addition, the select coefficient is also stored in the select coefficient holding register 221.

  Subsequently, the next arbitration is performed in step S23. At this time, arbitration target requests are requests A, B, and D stored in the request holding registers 214, 215, and 217. Therefore, the request arbitration circuit 226 makes a determination based on the select coefficients stored in the select coefficient holding registers 218, 219, and 221.

  Here, since the selection coefficients of the requests A, B and D are “14”, “14” and “25”, the request arbitration circuit 226 should output the request D corresponding to the maximum value “25”. The request is determined (S23). Then, the request arbitration circuit 226 notifies the selector 227 that the request D has been determined (S24).

  In addition, the request arbitration circuit 226 calculates a difference “11” between the selection number “25” of the request D that is the winner of the arbitration and the selection coefficients “14” of the requests A and B that are the next points of the arbitration. (S31). Then, the request arbitration circuit 226 compares the difference “11” with the above-described comparison value “12.5” (S32). Here, since the difference “11” is less than the comparison value “12.5”, the request arbitration circuit 226 adds the differences “11” and “1” to the select coefficients “14” of the requests A and B. The select coefficient “26” is calculated (S34) and output to the select coefficient arbitration circuits 222 and 223. Therefore, “26” is stored in the select coefficient holding registers 218 and 219, respectively.

  Thereafter, the third arbitration is performed in step S23. At this time, the arbitration target requests are requests A and B stored in the request holding registers 214 and 215. Therefore, the request arbitration circuit 226 makes a determination based on the select coefficients stored in the select coefficient holding registers 218 and 219.

  Here, since the selection coefficients of the requests A and B are “26” and “26”, the request arbitration circuit 226 determines that the request A having a smaller selector number is to be output (S23). Then, the request arbitration circuit 226 notifies the selector 227 that the request A has been determined (S24).

  In addition, the request arbitration circuit 226 calculates a difference “0” between the selection number “26” of the request A that is the winner of the arbitration and the selection coefficient “26” of the request B that is the next point of the arbitration (S31). ). Then, the request arbitration circuit 226 compares the difference “0” with the above-described comparison value “12.5” (S32). Here, since the difference “0” is less than the comparison value “12.5”, the request arbitration circuit 226 adds the differences “0” and “1” to the select coefficient “26” of the request B and selects it. The coefficient “27” is calculated (S 34) and output to the select coefficient arbitration circuit 223. Therefore, “27” is stored in the select coefficient holding register 219.

  Thereafter, a fourth arbitration is performed in step S23. At this time, the request to be arbitrated is only the request B stored in the request holding register 215. Therefore, the request arbitration circuit 226 determines the request B as a request to be output because it is a single arbitration (S23). Then, the request arbitration circuit 226 notifies the selector 227 that the request B has been determined (S24).

  Subsequently, problems and effects solved by the second embodiment of the present invention will be described. As an arbitration method in the case of transmitting a request to an external node, round robin can be used in addition to the method of assigning the priority described above in the problem. However, when these methods are used, arbitration is performed regardless of the number of hops to the transmission destination where the request is processed. Therefore, depending on the arbitration timing of the selector, a request with a large number of hops is postponed. Therefore, it may take time to start processing the request. At that time, a request with a large number of hops to be processed first becomes a bottleneck for accessing a certain memory. Along with this, the processing speed is lowered, and the performance may be lowered.

  Here, the case where the arbitration method by round robin is applied will be described. As in the example described above, it is assumed that three requests A, B, and C participate in arbitration at the same time, and request D participates in arbitration at the next arbitration. Similarly, the DNIDs of the requests A, B, C, and D are also “010”, “100”, “011”, and “001”, and the number of hops at that time is the value shown in FIG. Shall. A request that can become an access bottleneck in the system is referred to as request D.

  FIG. 8 is a diagram for explaining the request processing speed when round robin is applied. First, when the current priority is at the lowest number, when applying a round robin to determine the winner by arbitration, the arbitration right is given from the lower number. Therefore, as shown in FIG. 8, the arbitration order is the order of request A, request B, request C, and request D. Each request is output to the requested node according to the arbitration order. At that time, the elapsed time is shaded for each request. That is, after the request A has elapsed from time 1 to time 5, the target request destination is reached, and processing of the request A is started at the request destination. Similarly, requests B and C are output, and finally, request D is output at time 4. Therefore, the request D that can be an access bottleneck in the system reaches the request destination after 28 hops at the fastest after the selector 227 receives the request.

  Further, the maximum value of the number of request transmission processes per unit time is “4”, but the time during which transmission processing is performed at the maximum value is only between two hops. That is, communication between nodes is most efficiently used between two hops. Therefore, the processing is horizontally long, and it takes 28 hops for all requests to start processing at the request destination.

  Here, in a large-scale computer system using a plurality of nodes in recent years, further improvement in request processing performance is required. Thus, it will be described that the request processing performance is further improved according to the second embodiment of the present invention.

  FIG. 9 is a diagram for explaining the request processing speed according to the second embodiment of the present invention. In the second embodiment of the present invention, when a winner is determined by arbitration, the arbitration order is request C, request D, request A, and request B. Here, the request D that can be an access bottleneck in the system is received by the request destination 25 hops after the selector 227 receives the request.

  Further, the maximum value of the number of request transmission processes per unit time is “4”, but the time during which transmission processing is performed at the maximum value is between four hops. For this reason, the transmission processing period is shorter than when round robin processing is performed, and all requests have 26 hops before processing is started at the request destination.

  From the above, the effect in the second embodiment of the present invention will be described. First, when access to the same memory or the like occurs frequently, a request with the slowest overall performance may be pulled. Therefore, in the second embodiment of the present invention, by processing a request with a large number of hops first, the overall request processing speed can be improved.

  In addition, by giving priority to requests that take a long time to reach the request destination from the selector, the number of request transmission processes per unit time in the entire system increases, and the processing time for all requests can be shortened on average. .

<Other embodiments of the invention>
Embodiment 2 of the present invention can improve the overall processing speed in a large-scale system by prioritizing arbitration of a request with a large number of hops in a selector.
Further, according to the second embodiment of the present invention, the request arbitration circuit 226 that is a mechanism for determining the priority based on the number of hops from the selector 227 to the request destination of the request is provided in the node controller 111. Further, by arbitrating arbitration preferentially for requests with a larger hop count, local performance degradation can be suppressed by processing a request with a larger hop count that may become an access neck first.

  Furthermore, the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the gist of the present invention described above.

  A part or all of the above embodiments can be described as in the following supplementary notes, but is not limited thereto.

(Appendix 1) Connected to multiple nodes,
Priority that receives a plurality of requests from a plurality of processors in its own node to a processor belonging to any of the plurality of nodes, and calculates a priority according to the request destination node for each of the plurality of requests. A degree calculation circuit;
A determination circuit for determining a request to be output among the plurality of received requests based on the calculated priority;
A selection circuit that selects the determined request and outputs the selected request to the requested node;
A node controller comprising:

  (Supplementary Note 2) The priority calculation circuit calculates the priority higher as the number of hops, which is the number of nodes through which each request passes from its own node to reach the request destination node, is larger. The node controller according to Supplementary Note 1.

(Supplementary Note 3) A storage unit that stores the request destination node of the request and the number of hops in association with each other,
The priority calculation circuit, for each of the plurality of received requests, acquires the number of hops associated with a request destination node of the request from the storage unit, and calculates the priority. The node controller according to appendix 2.

(Additional remark 4) The said determination circuit updates the said priority higher based on a predetermined | prescribed reference | standard about the undecided request which was not determined as the said request which should be output among the said some received requests,
The priority calculation circuit calculates the priority for subsequent requests received after receiving the plurality of requests,
The determination circuit determines the request to be output based on the updated priority of the undecided request and the calculated priority of the subsequent request. The node controller according to any one of the above.

  (Additional remark 5) The said determination circuit, as the said predetermined reference | standard at the time of updating the said priority regarding the said undetermined request, the priority of the request determined as the said request which should be output, and the priority of the said undetermined request The node controller according to appendix 4, wherein the node controller uses a degree and a maximum value of the number of nodes through which a request reaches a request destination node from the self node among the plurality of nodes.

(Supplementary Note 6) When the request source of the subsequent request and the request source of the undecided request are the same processor, the determination circuit excludes the subsequent request from the determination target.
The node controller according to appendix 4 or 5, wherein the priority calculation circuit updates the priority of the subsequent request that is excluded from the target higher.

(Supplementary note 7) A first request from a first processor in a first node to a processor in a second node, and a second processor in the first node to a processor in a third node Simultaneously with the second request for
Calculating a first priority and a second priority according to a request source of the first request and the second request;
Determining whether to output the first request or the second request based on the first priority and the second priority;
A request output order determination method comprising: selecting the determined requests and outputting the selected requests to the request destination node.

(Supplementary Note 8) The number of hops, which is the number of nodes through which the first request passes to reach the second node, is the number of nodes through which the second request passes through to reach the third node. If greater, calculate the first priority higher than the second priority;
The output order determination method according to appendix 7, wherein the first request is determined as the request to be output.

(Supplementary Note 9) For the second request that has not been determined as the request to be output, update the second priority higher based on a predetermined criterion,
Calculating a third priority for a third request received after receiving the first request and the second request;
The output order determination method according to appendix 8, wherein the request to be output is determined based on the updated second priority and the calculated third priority.

  (Supplementary Note 10) As the predetermined reference when the second priority is updated, the first priority, the second priority, and a request from the first node to the requesting node The output order determination method according to appendix 9, wherein a maximum value of the number of nodes that are passed through in order to reach is used.

(Supplementary Note 11) When the request source of the third request and the request source of the second request are the same processor, the third request is excluded from the determination target,
The output order determination method according to appendix 9 or 10, wherein the third priority is updated higher.

(Supplementary Note 12) Connected to multiple nodes,
Multiple processors,
Priority calculating means for receiving a plurality of requests from the plurality of processors to a processor belonging to any of the plurality of nodes, and calculating a priority according to a request destination node for each of the plurality of requests; ,
Determining means for determining a request to be output among the plurality of received requests based on the calculated priority;
Selecting means for selecting the determined request and outputting it to the requested node;
An inter-node communication system including a node having a node controller.

  (Additional remark 13) The said priority calculation means calculates the said priority higher, so that the number of hops which are the number of nodes through which each request | requirement passes from its own node to a request destination node is large. The inter-node communication system according to appendix 12.

(Supplementary Note 14) The node controller further includes storage means for storing the request destination node of the request in association with the hop count,
The priority calculation means acquires the number of hops associated with a request destination node of the request from each of the plurality of received requests from the storage means, and calculates the priority. The inter-node communication system according to Supplementary Note 13.

(Additional remark 15) The said determination means updates the said priority higher based on a predetermined | prescribed reference | standard about the undetermined request which was not determined as the said request which should be output among the received several requests,
The priority calculation means calculates the priority for subsequent requests received after receiving the plurality of requests,
The determination means determines the request to be output based on the updated priority of the undecided request and the calculated priority of the subsequent request. The inter-node communication system according to any one of the above.

  (Additional remark 16) The said determination means, as the said predetermined reference | standard at the time of updating the said priority about the said undetermined request, the priority of the request determined as the said request which should be output, and the priority of the said undetermined request 16. The inter-node communication system according to supplementary note 15, wherein a maximum number of nodes through which a request reaches a request destination node from its own node among the plurality of nodes is used.

(Supplementary Note 17) When the request source of the subsequent request and the request source of the undecided request are the same processor, the determination unit excludes the subsequent request from the determination target.
The inter-node communication system according to appendix 15 or 16, wherein the priority calculation means updates the priority of the subsequent request that is excluded from the target higher.

100 node communication system 1 node 11a processor 11b processor 11n processor 12 node controller 13 priority calculation circuit 14 decision circuit 15 selection circuit 2 node 21 processor 22 node controller 3 node 31 processor 32 node controller 100a computer system 101 node 102 node 103 node 104 node 105 node 106 node 107 node 108 node 111 node controller 112 processor 113 processor 114 processor 115 processor 121 node controller 122 processor 123 processor 124 processor 125 processor 131 node controller 141 node controller 151 node controller 161 no Controller 171 Node controller 181 Node controller 301 Signal line 302 Signal line 303 Signal line 304 Signal line 305 Signal line 306 Signal line 307 Signal line 308 Signal line 309 Signal line 310 Signal line 311 Signal line 312 Signal line 313 Signal line 314 Signal line 315 Signal line 316 Signal line 201 Table 202 Request storage buffer 203 Request storage buffer 204 Request storage buffer 205 Request storage buffer 206 Select coefficient storage register 207 Select coefficient storage register 208 Select coefficient storage register 209 Select coefficient storage register 210 Select coefficient generation circuit 211 Select Coefficient generation circuit 212 Select coefficient generation circuit 213 Select coefficient generation circuit 214 Request holding Register 215 Request holding register 216 Request holding register 217 Request holding register 218 Select coefficient holding register 219 Select coefficient holding register 220 Select coefficient holding register 221 Select coefficient holding register 222 Select coefficient arbitration circuit 223 Select coefficient arbitration circuit 224 Select coefficient arbitration circuit 225 Select Coefficient Arbitration Circuit 226 Request Arbitration Circuit 227 Selector

Claims (10)

Connected to multiple nodes,
Priority that receives a plurality of requests from a plurality of processors in its own node to a processor belonging to any of the plurality of nodes, and calculates a priority according to the request destination node for each of the plurality of requests. A degree calculation circuit;
A determination circuit for determining a request to be output among the plurality of received requests based on the calculated priority;
A selection circuit that selects the determined request and outputs the selected request to the requested node;
A node controller comprising:   The priority calculation circuit calculates the priority higher as the number of hops, which is the number of nodes through which each request passes from its own node to reach the request destination node, is larger. The node controller according to 1. A storage unit that stores the request destination node of the request in association with the hop count;
The priority calculation circuit, for each of the plurality of received requests, acquires the number of hops associated with a request destination node of the request from the storage unit, and calculates the priority. The node controller according to claim 2. The determination circuit updates the priority higher based on a predetermined criterion for an undecided request that has not been determined as the request to be output among the plurality of received requests,
The priority calculation circuit calculates the priority for subsequent requests received after receiving the plurality of requests,
The determination circuit determines the request to be output based on the updated priority of the undecided request and the calculated priority of the subsequent request. 4. The node controller according to any one of 3 above.   The determination circuit, as the predetermined reference when updating the priority for the undecided request, the priority of the request determined as the request to be output, the priority of the undecided request, 5. The node controller according to claim 4, wherein a maximum number of nodes through which a request reaches a request destination node from its own node among a plurality of nodes is used. If the request source of the subsequent request and the request source of the undecided request are the same processor, the determination circuit excludes the subsequent request from the determination target,
The node controller according to claim 4, wherein the priority calculation circuit updates the priority of the subsequent request that is excluded from the target higher. A first request from a first processor in a first node to a processor in a second node and a second request from a second processor in the first node to a processor in a third node; Accept requests at the same time,
Calculating a first priority and a second priority according to a request source of the first request and the second request;
Determining whether to output the first request or the second request based on the first priority and the second priority;
A request output order determination method comprising: selecting the determined requests and outputting the selected requests to the request destination node. If the number of hops, which is the number of nodes through which the first request passes to reach the second node, is greater than the number of nodes through which the second request passes to reach the third node; Calculating the first priority higher than the second priority;
The output order determination method according to claim 7, wherein the first request is determined as the request to be output. Connected to multiple nodes,
Multiple processors,
Priority calculating means for receiving a plurality of requests from the plurality of processors to a processor belonging to any of the plurality of nodes, and calculating a priority according to a request destination node for each of the plurality of requests; ,
Determining means for determining a request to be output among the plurality of received requests based on the calculated priority;
Selecting means for selecting the determined request and outputting it to the requested node;
An inter-node communication system including a node having a node controller.   The priority calculation means calculates the priority higher as the number of hops, which is the number of nodes through which each request passes to reach the request destination node from its own node, is larger. 10. The inter-node communication system according to 9.

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