JP2012093893A - Reconfigurable lsi - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a reconfigurable LSI capable of converting signal lines differing in bit width.SOLUTION: The reconfigurable LSI includes a first reconfiguration array having a plurality of processor elements having a first bit width, and an inter-processor-element network configured such that the plurality of processor elements are in an arbitrary connection state based upon reconfiguration data, a second reconfiguration array having a second bit width different from the first bit width, a reconfiguration data memory which stores the reconfiguration data, and a reconfiguration control circuit which reads the data out of the reconfiguration data memory in response to a predetermined event, and sets the data in the first and second reconfiguration arrays. The first or second reconfiguration array has a bit-width conversion element which converts signal interconnects having the first bit width to signal interconnects having the second bit width.

Description

  The present invention relates to a reconfigurable LSI.

  A reconfigurable LSI has a plurality of processor elements and a network for connecting the processor elements, and a processor based on configuration data set by a control circuit as a sequencer in response to an external or internal event. The configuration of the element and the configuration of the network between the processor elements are constructed in an arbitrary calculation state or calculation circuit.

  Reconfigurable LSIs are pre-installed with multiple types of processor elements such as logical operation units (ALU) that have functions such as adders, multipliers, and comparators, and delay circuits, counters, selectors, and registers. In addition, a network for connecting the processor elements is provided. Then, the processor element and the network are reconstructed into a desired configuration based on the configuration data from the reconfiguration control unit including the sequencer, and a predetermined calculation is executed in the calculation state. If a plurality of arithmetic circuits are constructed by a plurality of processor elements, the arithmetic circuits can simultaneously perform data processing. When the data processing in one calculation state is completed, another calculation state is constructed by another configuration data, and different data processing is performed in that state.

  In this way, a reconfigurable LSI can dynamically reconstruct different computation states, thereby improving the data processing capability for large amounts of data and increasing the overall processing efficiency.

JP 2005-122546 A Japanese Patent No. 3509047 Japanese Unexamined Patent Publication No. 01-017121 JP 2007-257216 A JP 2001-314881 A

  In recent LSI design environments, logic design is performed using the RTL language, which is a hardware description language, and a logic circuit (netlist) is constructed by logically synthesizing the RTL description file to perform logic verification, layout design, timing verification, etc. As a result, LSIs that support logic design have been developed. LSI design environments using such RTL languages are becoming increasingly popular.

  Therefore, it is required to generate reconfigurable LSI configuration data by logic design using the RTL language.

  However, reconfigurable LSIs have a uniform data bus width within or between processor elements, and construct complex data processing circuits such as image processing and communication processing using configuration data. . Such data processing circuits are generally configured to process data of the same bit width at high speed or in parallel.

  On the other hand, in logical design using the RTL language, descriptions that define various bit width data, synthesize different bit width data, or extract some bit data from a certain bit width data There are many. In that case, the data processing circuit can be constructed by a processor having the maximum bit width, but since the bit width is wider than the bit width of the data to be processed, an optimum circuit configuration cannot be performed.

  Therefore, an object of the present invention is to provide a reconfigurable LSI capable of adjusting the bit width.

The first aspect of the reconfigurable LSI is a reconfigurable LSI constructed in an arbitrary state based on configuration data,
A first reconfiguration array comprising a plurality of processor elements having a first bit width and an inter-processor element network configured to establish an arbitrary connection state between the plurality of processor elements based on the reconfiguration data;
A plurality of processor elements having a second bit width different from the first bit width, and a network between processor elements that constructs the plurality of processor elements in an arbitrary connection state based on the reconfiguration data; Two reconfiguration arrays,
A reconfiguration data memory for storing the reconfiguration data;
A reconfiguration control circuit that reads the reconfiguration data in the reconfiguration data memory in response to a predetermined event and sets the data in the first and second reconfiguration arrays;
The first or second reconfiguration array includes a bit width conversion element that converts the signal wiring having the first bit width into the signal wiring having the second bit width.

  According to the first aspect, it is possible to provide a reconfigurable LSI capable of performing bit conversion such as data combination and division between reconfigurable arrays of processor elements having different bit widths.

It is a schematic block diagram of LSI which can be reconfigured in this Embodiment. It is a figure which shows the some reconfiguration array in this Embodiment. It is a figure which shows the bit width conversion element in this Embodiment. It is a figure which shows the reconfiguration array R_ARRAY in the reconfigurable integrated circuit R_LSI in this Embodiment. It is a figure which shows the specific example of reconfiguration array R_ARRAY in this Embodiment. It is another figure which shows the specific example of reconfiguration array R_ARRAY in this Embodiment. It is a figure shown about the development environment of the reconfigurable integrated circuit of this Embodiment. It is a flowchart figure which shows the starting sequence of the reconfigurable integrated circuit in this Embodiment. It is a timing chart figure which shows the starting sequence of the reconfigurable integrated circuit in this Embodiment. It is a figure explaining switching of the configuration data of the reconfigurable integrated circuit in this Embodiment. It is a figure which shows the example of a processing circuit which implement | achieves a certain RTL description. This is an example in which the data processing circuit of FIG. 11 is constructed with a 16-bit reconfiguration array R_ARRAY_2. It is a figure which shows the example of a processing circuit which implement | achieves a certain RTL description. This is an example in which the RTL description in FIG. This is an example in which the RTL description in FIG. It is a figure which shows the example of a processing circuit which implement | achieves an RTL description. It is an example which constructed | assembled the RTL description of FIG. 16 (A) (B) with the reconfiguration array. It is a figure which shows the example which constructed | assembled the example of the processing circuit which implement | achieves a certain RTL description, and it with the reconfiguration array. It is a figure which shows the example which constructed | assembled the processing circuit which implement | achieves the RTL description of FIGS. 20-22 by the reconfiguration array. It is a figure which shows the example of a processing circuit which implement | achieves an RTL description. It is a figure which shows the example of a processing circuit which implement | achieves a certain RTL description. It is a figure which shows the example of a processing circuit which implement | achieves a certain RTL description. It is a figure which shows the reconfiguration array group of the integrated circuit which can be reconfigured. It is a figure of the 1st example of an RTL description file. FIG. 25 is a diagram in which a logic circuit that realizes the RTL description file of FIG. 24 and the logic circuit are constructed in a reconfiguration array. It is a figure of the 2nd example of an RTL description file. FIG. 27 is a diagram of a logic circuit that realizes the RTL description file of FIG. 26 and the logic circuit built in a reconfiguration array.

  FIG. 1 is a schematic configuration diagram of a reconfigurable LSI according to the present embodiment. A reconfigurable (reconfigurable) integrated circuit R_LSI includes a plurality of reconfiguration arrays R_ARRAY having a plurality of processor elements PE and an inter-processor element network NW that connects their input / outputs, and processor elements PE. And an input / output port 10 for inputting data and outputting data from the PE.

  FIG. 1 shows only one reconfiguration array R_ARRAY. However, the reconfigurable integrated circuit R_LSI in the present embodiment has a plurality of reconfiguration arrays each having a processor element and a network having different bit widths.

  The plurality of processor elements PE are an ALU having functions such as an adder, a multiplier, and a comparator, and a plurality of types of processor elements such as a delay circuit, a counter, and a selector. The processor element PE is constructed in an arbitrary state based on the configuration data. The inter-processor element network NW is constructed in an arbitrary connection state based on the reconfiguration data. Therefore, by setting the reconfiguration data, the reconfiguration array R_ARRAY can be reconfigured to an arbitrary data processing circuit by connecting a plurality of processor elements to an arbitrary state.

  In the reconfiguration array R_ARRAY in FIG. 1, a processor element PE having an ALU function, a processor element PE having a multiplier MPY function, a processor element PE having a memory RAM function, and a processor having a register file RegFile function Element PE etc. are included. The memory processor element stores, for example, table data.

  The reconfigurable integrated circuit R_LSI further includes a configuration data memory 14 for storing a plurality of types of configuration data, and a reconfiguration control for reading predetermined configuration data from the memory 14 and setting it in the reconfiguration array R_ARRAY. Circuit 12. The reconfiguration control circuit 12 is a register group having an instruction code for instructing data reading to the memory and setting of the reconfiguration data, for example, in response to an event such as an interrupt signal or a status signal. Run the code. By executing the instruction code, the corresponding configuration data is read from the reconfiguration data memory 14 and set in the reconfiguration array R_ARRAY.

  The reconfigurable integrated circuit R_LSI reads information including configuration data stored in an external memory 1 such as a flash memory, and via a decoder 18, a reconfiguration control circuit 12 and a configuration data memory 14. Among the processor elements and stored in either the register file RegFile or the memory RAM.

  In this embodiment, a file logically designed by the RTL language, which is one of the hardware description languages, is logically synthesized, and information RD including configuration data generated by the logical synthesis is stored in the memory 1 outside the chip. Stored. In the reconfigurable integrated circuit R_LSI, for example, when the power is turned on, the built-in loader 16 reads the information RD from the external memory 1 and loads it into the reconfiguration array R_ARRAY or the configuration data memory 14. After the initial loading, when the loader 16 outputs a ready signal to the reconfiguration control circuit 12, the reconfiguration control circuit 12 executes a predetermined instruction code and sets the reconfiguration array R_ARRAY according to the reconfiguration data. Build in the processing circuit. When the initial setting is completed, the processing circuit built in the reconfiguration array processes input data from the input / output port 10 and outputs processed output data from the input / output port 10.

  FIG. 2 is a diagram showing a plurality of reconfiguration arrays in the present embodiment. FIG. 2 shows an example of three reconfiguration arrays built in one reconfigurable integrated circuit R_LSI. The reconfiguration array R_ARRAY_1 has an 8-bit (or 4-bit) processor element PE and an inter-processor network NW connecting them. Therefore, 8-bit (or 4-bit) data is input from the input / output port 10, predetermined processing is performed, and 8-bit (or 4-bit) processed data is output. Further, it has a processor element comprising a comparator CMP that compares 8-bit (or 4-bit) data with a predetermined value and outputs 1-bit comparison result data.

  Similarly, the reconfiguration array R_ARRAY_2 has a processor element PE of 16 bits (or 8 bits), which is twice as many as 8 bits (or 4 bits), and an interprocessor network NW connecting them. Accordingly, 16-bit (or 8-bit) data is input from the input / output port 10, predetermined processing is performed, and 16-bit (or 8-bit) processed data is output. Further, it has a processor element composed of a comparator CMP that compares 16-bit (or 8-bit) data with a predetermined value and outputs 1-bit comparison result data.

  The third reconfiguration array R_ARRAY_0 includes a processor element including a comparator CMP and a decoder DEC that process a 1-bit control signal, and an inter-processor network NW that connects them. Although not shown, this array R_ARRAY_0 may be a processor element such as a predetermined logic circuit or selector that processes 1-bit data.

  The three reconfiguration arrays R_ARRAY have different bit widths. For this reason, one of the reconfiguration arrays is provided with bit width conversion elements BND and SPL for converting signal lines having different bit widths.

  Among the bit width conversion elements, the bit coupling element BND is a signal line having a larger bit width by coupling another signal line or a signal line having a predetermined value to a signal line having a smaller bit width. Convert. In the figure, the bit combination element BND in the reconfiguration array R_ARRAY_2 has a 1-bit signal line as a 16-bit (or 8-bit) signal line, or an 8-bit (or 4-bit) signal line as 16 bits (or (8 bit) signal line. The bit coupling element BND in the reconfiguration array R_ARRAY_1 converts a 1-bit signal line into an 8-bit (or 4-bit) signal line.

  Of the bit width conversion elements, the bit separation element SPL separates a part of a signal line having a large bit width and converts it into a signal line having a smaller bit width. In the figure, the bit separation element SPL in the reconfiguration array R_ARRAY_2 separates 1 bit of a 16-bit (or 8-bit) signal line and outputs it to a 1-bit signal line or a 16-bit (or 8-bit) signal. The 8 bits (or 4 bits) of the line are separated and converted to an 8 bit (or 4 bit) signal line. Further, the bit separation element SPL in the reconfiguration array R_ARRAY_1 separates one bit of the 8-bit (or 4-bit) signal line and converts it into a 1-bit signal line.

  In the following description, as shown in FIG. 2, the reconfiguration array R_ARRAY_2 is 16 bits and R_ARRAY_1 is 8 bits.

  FIG. 3 is a diagram showing a bit width conversion element in the present embodiment. FIG. 3 is a diagram for further explaining the bit width conversion element of FIG. 2. In the figure, 16-bit, 8-bit, and 1-bit networks NW are respectively shown, and a bit separation element 20-is formed between the 16-bit signal line, the 8-bit signal line, and the 1-bit signal line from these networks. The bit width is converted by 22 and the bit coupling elements 23 and 24.

  For example, the bit separation element 20 separates 8 bits or a part of a 16-bit signal line, outputs the separated 8 bits, or adds a signal line of a predetermined value to a part of the bits to obtain 8 bits. Output. Similarly, the bit separation element 22 separates one bit of the 8-bit signal line and outputs the separated one bit. The bit separation element 21 separates one bit of the 16-bit signal line and outputs the separated one bit.

  On the other hand, the bit coupling element 23 combines two sets of 8-bit signal lines to output a 16-bit signal line, or adds another signal line having a value of 8 bits to the 8-bit signal line. Output a line. Alternatively, the bit coupling element 23 adds a signal line having a 15-bit value to the 1-bit signal line and outputs 16 bits, or couples the 1-bit signal line and the 8-bit signal line to obtain a 7-bit value. A 16-bit signal is output by adding a signal line. The bit coupling element 24 adds a signal line having a 7-bit value to the 1-bit signal line and outputs 8 bits.

  In the figure, bit separation elements 20 and 21 correspond to the bit separation element SPL in the reconfiguration array R_ARRAY_2 in FIG. The bit separation element 22 corresponds to the bit separation element SPL in the reconfiguration array R_ARRAY_1 in FIG. Further, the bit combination elements 23 and 24 correspond to the bit combination elements BND in the reconfiguration arrays R_ARRAY_2 and R_ARRAY_1 in FIG. 2, respectively.

  As shown in FIGS. 2 and 3, the reconfigurable integrated circuit R_LSI has a processor element having a calculation accuracy of an integer multiple of 8 bits such as 8 bits, 16 bits, 32 bits, etc., with a general unit of 8 bits as a minimum unit. It has a plurality of reconfiguration arrays having a network between processor elements, and a reconfiguration array having a processor element for processing 1-bit control signals and a network. Then, a bit width conversion element for converting the bit width between the reconfiguration arrays having different calculation precisions is provided, thereby enabling connection and separation processing of signals having different bit widths.

  FIG. 4 is a diagram showing a reconfiguration array R_ARRAY in the reconfigurable integrated circuit R_LSI according to the present embodiment. As described with reference to FIG. 1, the reconfiguration array R_ARRAY is connected to a plurality of processor elements PE constructed in an arbitrary circuit by configuration data, and is constructed in an arbitrary connection state by configuration data. It has a network NW between processor elements. The plurality of processor elements PE include the above-described bit width conversion element.

  One reconfiguration array R_ARRAY has a single bit width. Therefore, the input / output ports 10 (IN) and 10 (OUT) also have the same bit width.

  FIG. 5 is a diagram showing a specific example of the reconfiguration array R_ARRAY in the present embodiment. The processor elements PE0 to PE3, the memory processor element PE5, and the other processor elements PE4 are configured to be connectable via a selector 41 that is a switch in the inter-processor element network SW. Each processor element PE0-PE5 can be constructed in any configuration based on the configuration data CD0-CD5. The selector 41 (41a, 41b, 41c) in the network NW can also be constructed in an arbitrary configuration based on the configuration data CDs.

  Each processor element PE outputs end signals CS0 to CS3 upon completion of the respective arithmetic processing. This end signal is given as an event to the reconfiguration control circuit 12, and the next configuration data CD is supplied to the processor element PE at an appropriate timing, and is constructed in another arithmetic circuit.

  The selector 41 includes a register 42 that stores configuration data CD and a selector circuit 43 that selects an input according to the data in the register 42, as shown as an example in the lower left of the figure. Further, a flip-flop 44 that latches the output of the selector circuit 43 in synchronization with the clock CK may be provided. The network NW also enables desired connection to the data input port 10 (IN) and the output port 10 (OUT) via a selector.

  FIG. 6 is another diagram showing a specific example of the reconfiguration array R_ARRAY in the present embodiment. As illustrated, the processor element PE receives data from the inter-processor element network NW, the arithmetic unit 52 processes the data, and the output unit 53 outputs the data to the network NW. Each processor element PE has a configuration data register 50. Information including the configuration data CD is set and held in the register 50 from the configuration data memory 14.

  Based on the information, the calculation unit 52 in the processor element PE has a predetermined function built in the calculation circuit. Similarly, the output unit 53 is constructed based on the information. Further, the information is stored as table data or register values in the processor element PE of the memory or register file. The network NW is also constructed in an arbitrary connection state based on the configuration data DC.

  FIG. 7 is a diagram showing the development environment of the reconfigurable integrated circuit of this embodiment. FIG. 7 shows a schematic development process.

  First, a circuit description file described in the RTL description language is generated by the designer (S10). In FIG. 7, three types of circuit description files are generated. Further, in addition to the circuit description file in the RTL description language, the circuit description file in which the circuit cells in the library are combined is generated by the designer (S12). This circuit description file becomes data of the logic circuit.

  When these circuit description files are logically synthesized, configuration information including configuration data is created (S14). This configuration information is written into the flash memory 1 shown in FIG. 1 (S16).

  As described above, the reconfigurable integrated circuit according to the present embodiment can be arbitrarily configured according to the configuration data information obtained by logically synthesizing the circuit description file logically designed in the RTL description language. It is possible to build. Therefore, the reconfigurable integrated circuit according to the present embodiment incorporates a processor element suitable for combining and separating data having different bit widths, which often appears in the RTL description language.

  FIG. 8 is a flowchart showing a start-up sequence of the reconfigurable integrated circuit in this embodiment. When the power source of the integrated circuit is turned on (S20), the built-in loader 16 instructs to read the flash memory 1 outside the chip (S21). Thereby, reading of information including configuration data in the flash memory 1 is started (S22). The decoder 18 in the integrated circuit interprets the configuration information sequentially read from the flash memory 1, and reconfigures the control unit 12, the configuration data memory 14, the memory processor element RAM (PE), and the processor element ( Distribute to RegFile (PE) etc. and install (S23).

  When the writing of the data is finished, for example, the loader 16 outputs a ready signal indicating that the setting of the configuration data is finished to the reconfiguration control unit 12. As a result, the reconfigurable integrated circuit becomes operable (S24). In response to this ready signal, the reconfiguration control circuit 12 reads the first configuration data from the configuration data memory 14, loads it to the processor element PE or network NW in the reconfiguration array R_ARRAY, and performs the first processing. Build a circuit. Then, the constructed processing circuit performs signal processing of the constructed function on the input data (S25).

  FIG. 9 is a timing chart showing a start-up sequence of the reconfigurable integrated circuit in the present embodiment. When the power-on reset PON becomes L level in response to the power activation, the reset Reset_r in the reconfiguration array becomes L level, and the reset operation starts. In response to this, the loader 16 outputs the address ADR to the external memory 1 while clearing the configuration data memory 14, and reads the configuration information stored therein.

  When the clearing of the configuration data memory 14 is completed, the loader 16 sets the write signal Confg_WR to the H level and writes the configuration information to the configuration data memory 14 while performing a CRC check. At this time, the configuration information is also written to the memory processor element RAM (PE) and the processor element RegFile (PE) of the register file. When this writing is completed, the internal reset signal Reset_r is canceled by the loader 16 and a ready signal is issued to the reconfiguration control circuit 12.

  FIG. 10 is a diagram for explaining switching of configuration data of a reconfigurable integrated circuit according to the present embodiment. In FIG. 10, four types of configuration data are stored at four addresses 00-11 of the configuration data memory 14, and these four types of configuration data are countered according to interrupt signals and interrupt conditions. It can be switched by 12_2 and interrupt control circuit 12_3, or can be switched directly from the outside.

  As shown in FIG. 10, the mode set 12_1 can have three mode states. That is, the first mode is Simple mode, and the counter changes to 000-011 in response to an interrupt signal INT indicating predetermined processing completion End0-End3, and switches to different configuration data in the configuration data memory 14. It is done. Second, in the Factor mode, in response to an interrupt signal INT indicating a predetermined processing condition Int0-Int3, the configuration data is switched to the configuration data corresponding to each processing condition. Furthermore, by directly rewriting the register 12_4 in the control circuit from the outside, it is possible to switch to the corresponding configuration data.

[Example of bit width conversion element]
The outline of the reconfigurable integrated circuit in the present embodiment has been described above. A specific example of a bit width conversion element that performs bit width conversion between reconfiguration arrays according to the present embodiment will be described below, and a specific example of a reconfiguration array that realizes the last RTL description will be described.

FIG. 11 is a diagram illustrating an example of a processing circuit for realizing a certain RTL description. Specifically, it is the following RTL description.
assign X [15: 0] = (A [15: 0] + B [15: 0]-C [15: 0]) * 16'h0003;
As described above, the reconfigurable integrated circuit has a 1-bit control system reconfiguration array, an 8-bit data processing reconfiguration array, and a 16-bit data processing reconfiguration array. The above-described calculation having only a 16-bit width is realized only by a 16-bit data processing reconfiguration array.

  As shown in FIG. 11, in the 16-bit reconfiguration array, the addition of the operation A + B is assigned to the processor element PE0, the processor element PE1 is assigned to the subtraction of subtracting C from the addition value A + B, and the result is fixed. An operation to multiply the value “16′h0003” is assigned to the processor element PE4. All of these operations are 16bit precision.

  FIG. 12 shows an example in which the data processing circuit of FIG. 11 is constructed with a 16-bit reconfiguration array R_ARRAY_2. Based on configuration data (not shown), the processor element PE0 is constructed as an adder, the processor element PE1 is constructed as a subtracter, and the processor element PE4 is constructed as a multiplier. Further, according to the configuration data, the inter-processor element network NW receives input data A and B of the input port 10 (IN) as input to the processor element PE0, and outputs and input data C as input to the processor element PE1. The variable “16′h0003” in the memory processor RAM (PE) is input to the processor element PE4, and the output is configured to be output to the output port 10 (OUT).

  Constructing the processing circuit of FIG. 11 in the same 16-bit reconfiguration array as shown in FIG. 12 is equivalent to the prior art.

FIG. 13 is a diagram illustrating an example of a processing circuit for realizing a certain RTL description. This example is a circuit that outputs the result of computing 16-bit or 8-bit data as a 1-bit signal. FIG. 13A shows the following RTL description.
if (X [15: 0] = 16'h0001)
In other words, the comparator circuit determines whether or not 16-bit data X is equal to a constant “16′h0001”. The output is a 1-bit output that indicates whether they are equal.

FIG. 13B shows the following RTL description, which is a comparator circuit that determines whether 8-bit data X is equal to a constant “8′h01”. Again, the output is a 1-bit output that indicates whether they are equal.
if (X [7: 0] = 8'h01)
FIGS. 14 and 15 are examples in which the RTL description of FIG. 13A is constructed by a reconfiguration array. First, since the RTL description in FIG. 13A is a comparator circuit that determines whether or not the 16-bit data X is equal to the constant “16'h0001”, the comparator processor element CMP in the 16-bit reconfiguration array R_ARRAY_2 It is realized by. The example of FIG. 14 is a configuration example in which constants can be set in the comparator processor element CMP, and the example of FIG. 15 is a configuration example that cannot be set.

  In FIG. 14, the network NW and the comparator processor element CMP60 are constructed so that constants are set in the comparator processor element CMP60 from the input port 10 (IN) and data X is input from the input port 10 (IN). Yes. Then, the 1-bit data of the determination result is output to the network of the 1-bit reconfiguration array R_ARRAY_0.

  In FIG. 15, a constant cannot be set in the comparator processor element CMP60. Therefore, the processor element PE62 that can set a constant is constructed so that the constant "16'h001" can be set from the input port 10 (IN). Further, the processor element PE62, the comparator processor element CMP60, and the network NW in the 16-bit reconfiguration array R_ARRAY_2 are configured so that the data X is input from the input port 10 (IN) and the constant is input from the processor element PE62 to the comparator processor element CMP60. And are built. Furthermore, the 1-bit data of the determination result is constructed so as to be output to the network of the 1-bit reconfiguration array R_ARRAY_0.

FIG. 16 is a diagram illustrating an example of a processing circuit for realizing a certain RTL description. This example is a circuit example of a bit division element that converts 16-bit data into 8-bit data. The RTL description in FIG. 16 (A) is as follows.
assign X [7: 0] = IN_DATA [9: 2];
However, IN_DATA is 16bit data.

  In this case, the value of [9: 2] bits of 16-bit data IN_DATA is realized by a bit division element SPL (PE) that is converted to X [7: 0] of 8-bit data.

On the other hand, the RTL description of FIG. 16B is as follows.
assign X [7: 0] = IN_DATA [6: 2];
However, IN_DATA is 16bit data.

  In this case, the [6: 2] bit value of 16-bit data IN_DATA is converted to X [7: 0] of 8-bit data. The [6: 2] bits of data IN_DATA are 5 bits, and the bit width does not match the prepared 8-bit and 16-bit reconfiguration arrays. Therefore, 5-bit data is expanded by a bit width conversion element (bit division element) to be 8-bit data and processed by an 8-bit reconfiguration array.

  When data X [7: 0] is Unsigned data, the upper 3 bits are filled with "0". That is, the upper 3 bits are "3'b000". In other words, the bit division element SPL separates the [6: 2] bit value of the 16-bit data IN_DATA into the lower 5 bits of the data X (X [4: 0]), and the upper 3 bits are "3'b000". To do.

  When the data X [7: 0] is signed data, the upper 3 bits are sign-extended. That is, the upper 3 bits are "3 {X [4]}". That is, the bit division element SPL separates the [6: 2] bit value of the 16-bit data IN_DATA into the lower 5 bits of the data X (X [4: 0]), and the upper 3 bits are the sign bits X [4] Let “3 {X [4]}” expanded in

  FIG. 17 is an example in which the RTL description of FIGS. 16A and 16B is constructed by a reconfiguration array. In either case, the bit division element SPL64 in the 16-bit reconfiguration array R_ARRAY_2 is constructed so as to perform the bit division and the combination of the upper bits. Then, the 8-bit data whose bit width has been converted is output to the network in the 8-bit reconfiguration array R_ARRAY_1.

FIG. 18 is a diagram showing an example of a processing circuit that realizes a certain RTL description and an example in which the processing circuit is constructed by a reconfiguration array. The example of FIG. 18A is a circuit example of a bit division element that converts 16-bit data into 1-bit data. The RTL description in FIG. 18 (A) is as follows.
assign X = IN_DATA [1];
That is, the value of the first bit of the 16-bit input data IN_DATA is converted into 1-bit data X.

  As shown in FIG. 18B, 16-bit input data IN_DATA [15: 0] input from the input buffer 10 (IN) is converted into bit division elements via the network NW in the 16-bit reconfiguration array R_ARRAY_2. Built to be input to SPL64. In the bit division element SPL64, the value of the first bit of the 16-bit input data IN_DATA [15: 0] is separated and converted to 1-bit data X, and the output is sent to the network NW of the 1-bit reconfiguration array R_ARRAY_0. Built to supply. Thus, the 1-bit reconfiguration array R_ARRAY_0 processes not only 1-bit control signals but also 1-bit data signals.

  20 to 22 are diagrams showing examples of processing circuits for realizing a certain RTL description. Here, six types of RTL descriptions and their processing circuit examples are shown. These RTL descriptions are examples in which 8-bit input data IN_DATA0 [7: 0] and IN_DATA1 [7: 0] are combined as they are, or some bits are combined and the rest are filled with other values. In this case, it can be realized by a bit coupling element.

  FIG. 19 is a diagram illustrating an example in which a processing circuit that realizes the RTL description of FIGS. 20 to 22 is constructed by a reconfiguration array. Two 8-bit data of the 8-bit reconfiguration array R_ARRAY_1 is constructed by the bit combination element BND66 in the 16-bit reconfiguration array R_ARRAY_2.

The RTL description in FIG. 20 (A) is as follows.
assign X [15: 0] = {IN_DATA1 [7: 0], IN_DATA0 [7: 0]};
Inputs IN_DATA0 and IN_DATA1 are 8-bit data, and data X [15: 0] is 16-bit data.

  This RTL description is realized by the bit combination element BND (PE) that inputs IN_DATA0 and IN_DATA1 combine 8-bit data to lower 8 bits and upper 8 bits and output as 16-bit data X [15: 0]. .

  Therefore, in the reconfigurable integrated circuit, as shown in FIG. 19, for example, two 8-bit input data IN_DATA1 [7: 0] and IN_DATA0 [7: 0] input from the input port 10 (IN) are 8 bits. It is constructed such that it is input to the bit combination element BND66 in the 16-bit reconfiguration array R_ARRAY_2 via the network NW in the reconfiguration array R_ARRAY_1, combined, and output to the network NW.

The RTL description in FIG. 20B is as follows.
assign X [15: 0] = {3 {1'b0}, IN_DATA1 [4: 0], IN_DATA0 [7: 0]};
Input IN_DATA0 is 8-bit data, IN_DATA1 is 5-bit data, and data X [15: 0] is 16-bit data. In other words, the input IN_DATA1 [4: 0] is 5 bits wide and is 13 bits wide even if coupled to the input IN_DATA0 [7: 0], and does not match the bit width of any reconfiguration array. Therefore, this bit combination element BND (PE) fills the upper 3 bits with “0”. As a result, 16-bit data X [15: 0] can be processed as unsigned data by the 16-bit reconfiguration array R_ARRAY_2.

  This RTL description is also constructed by the bit coupling element BND66 as shown in FIG. 19 in the reconfigurable integrated circuit.

The RTL description in FIG. 21C is as follows.
assign X [15: 0] = {3 {IN_DATA1 [4]}, IN_DATA1 [4: 0], IN_DATA0 [7: 0]};
Input IN_DATA0 is 8-bit data, IN_DATA1 is 5-bit data, and data X [15: 0] is 16-bit data. In other words, the input IN_DATA1 [4: 0] is 5 bits wide and is 13 bits wide even if coupled to the input IN_DATA0 [7: 0], and does not match the bit width of any reconfiguration array. In this case, unlike FIG. 20B, the bit combination element BND (PE) fills the upper 3 bits with the sign bit IN_DATA1 [4]. That is, the combined 16-bit data X [15: 0] becomes Signed data.

  This RTL description is also constructed by the bit coupling element BND66 as shown in FIG. 19 in the reconfigurable integrated circuit.

The RTL description in FIG. 21 (D) is as follows.
assign X [15: 0] = {IN_DATA1 [7: 0], 3 {1'b0}, IN_DATA0 [4: 0]};
Input IN_DATA0 is 5-bit width data, IN_DATA1 is 7-bit width data, and data X [15: 0] is 16-bit data. That is, the input IN_DATA0 [4: 0] is 5 bits wide and is 13 bits wide even when coupled to the input IN_DATA1 [7: 0]. Therefore, the bit combination element BND (PE) fills the lower 3 bits with “0”. As a result, the 16-bit data X [15: 0] is 8-bit data, one of which is unsigned data, and can be processed by the 16-bit reconfiguration array R_ARRAY_2.

  This RTL description is also constructed by the bit coupling element BND66 as shown in FIG. 19 in the reconfigurable integrated circuit.

The RTL description in FIG. 22 (E) is as follows.
assign X [15: 0] = {IN_DATA1 [7: 0], 3 {IN_DATA0 [4]}, IN_DATA0 [4: 0]};
Input IN_DATA0 is 5-bit width data, IN_DATA1 is 8-bit width data, and data X [15: 0] is 16-bit data. The bit combination element BND (PE) fills the lower 3 bits with the sign bit IN_DATA0 [4]. In other words, the combined 16-bit data X [15: 0] is 8-bit data, and one of them is signed data, and can be processed by the 16-bit reconfiguration array R_ARRAY_2.

  This RTL description is also constructed by the bit coupling element BND66 as shown in FIG. 19 in the reconfigurable integrated circuit.

The RTL description in FIG. 22 (F) is as follows.
assign X [15: 0] = {7 {1'b0}, IN_DATA1 [3: 0], IN_DATA0 [4: 0]};
Input IN_DATA0 is 5-bit width data, IN_DATA4 is 4-bit width data, and data X [15: 0] is 16-bit data. Therefore, the bit combination element BND (PE) fills the upper 7 bits with “0” and sets the input data IN_DATA1 [3: 0] and IN_DATA0 [4: 0] to the lower 9 bits, respectively. In this way, two sets of data are combined at arbitrary bit positions. As a result, 16-bit data X [15: 0] can be processed as unsigned data by the 16-bit reconfiguration array R_ARRAY_2.

  This RTL description is also constructed by the bit coupling element BND66 as shown in FIG. 19 in the reconfigurable integrated circuit.

[Concrete example]
In the following, two RTL description file examples, their circuit examples, and construction examples of the reconfigurable integrated circuit of this embodiment are shown.

  FIG. 23 is a diagram showing a reconfiguration array group of integrated circuits that can be reconfigured. FIG. 23 shows a reconfiguration array R_ARRAY_0 having 1-bit processor elements and a network, and similarly, reconfiguration arrays R_ARRAY_1 and R_ARRAY_2 having processor elements and networks of 8 bits, 16 bits and 32 bits. , R_ARRAY_3. In each reconfiguration array, only processor elements are shown, but a network for arbitrarily connecting the processor elements is also provided.

  The processor element in FIG. 23 has an input terminal on the top side of the rectangle and an output terminal on the bottom side. For example, the processor element CMP of the comparator has two input terminals and one output terminal, and the processor element SEL of the selector has three input terminals (two inputs and one select signal terminal) and one output terminal. Have. The bit coupling element BND, which is a bit width conversion element, has two input terminals and one output terminal, and the bit division elements SPL and BND have one input terminal and one output terminal. Further, the processor element DEC of the decoder has four input terminals and one output terminal.

  In addition to the above, the processor element is provided with a register REG, an arithmetic logic unit ALU, and the like.

  Two RTL description files described below are logically synthesized to generate configuration data, and the reconfiguration array group shown in FIG. 23 is constructed in a desired circuit based on the configuration data.

  FIG. 24 is a first example of an RTL description file. The 100th line indicates that the variable CODE is "0" if START = 1 and IN_DATA [12: 7] if START = 0. Therefore, this description includes the necessity of bit conversion from 16-bit IN_DATA to 8-bit variable CODE. The 101st line shows FLAG1 = 1 if the variable CODE = 6'b100010 is true, and FLAG1 = 0 if it is false. Therefore, the circuit of the comparator processor element is shown. Line 102 shows that the logical AND of the logical OR of FLAG0, FLAG1, and FLAG2 and the inversion of INH becomes FLAG.

  Furthermore, lines 103 to 110 operate in response to the rising edge of the clock CLK (line 103). If FLAG = 1, set TEST = 0 (lines 104-106). If FLAG = 0, TMODE = 1 This indicates that TEST = A (lines 107-109).

  FIG. 25 is a diagram in which a logic circuit for realizing the RTL description file of FIG. 24 and the logic circuit are constructed in a reconfiguration array group. 100 lines of RTL consist of a bit division element SPL70 that separates 16-bit input IN_DATA [15: 0] and changes 6 bits of [12: 7] to 8 bits, a register 72 that stores constant “6'b0”, It consists of a selector 71 that selects IN_DATA [12: 7] when START = 0 and selects “6'b0” when START = 1 and outputs CODE.

  Further, line 101 of the RTL includes a register 74 that stores a constant “6′b100010” and a comparator 73 that compares CODE with the constant “6′b100010” and outputs a comparison result FLAG1. Line 102 of the RTL is composed of a logic circuit 75 that performs logical operations on inputs FLAG0, FLAG1, FLAG2, and INH. Lines 103 to 110 of the RTL select register 78 that stores the constant “32'b0”, and whether the constant “32'b0” or the output of the selector 76 is selected according to FLAG, and set TEST [31: 0] A selector 77 for outputting and a selector 76 for selecting A [31: 0] or TEST [31: 0] according to TMODE are included.

  In the reconfiguration array group in FIG. 25B, the cited document numbers of the elements of the logic circuit in FIG. 25A are appended. That is, from within the 16-bit reconfiguration array R_ARRAY_2, the bit division element 70, the registers 72 and 74 in the 8-bit reconfiguration array R_ARRAY_1, the comparator 73, the selector 71, the register 78 in the 32-bit reconfiguration array R_ARRAY_3, The selectors 76 and 77 and the decoder (logic circuit) 75 in the 1-bit reconfiguration array R_ARRAY_0 are connected to each other by a network, and the logic circuit of FIG.

  In this example, the 16-bit bit division element 70 can convert 6 bits of the 16-bit input IN_DATA into 8-bit data and perform 8-bit logical operations. A 1-bit control signal such as FLAG is directly input as a selector selection signal in the 32-bit reconfiguration array R_ARRAY_3.

  FIG. 26 is a first example of an RTL description file. Line 200 operates at the rising edge of CLK or the falling edge of RESET, and lines 201-203 are! If RESET = 1, it indicates that LO and HI are reset to 0. Lines 204-224 are LO = 9 if LO = 9, otherwise LO = LO + 1, and when LO = 9, HI = 5 if HI = 5 and HI = HI otherwise. It shows that it increments with +1. That is, the counter LO of the lower digits 0-9 and the counter HI of the upper digits 0-5 are shown.

  FIG. 27 is a diagram in which a logic circuit for realizing the RTL description file of FIG. 26 and the logic circuit are constructed in a reconfiguration array group. In FIG. 27A, the comparator 81 determines whether LO is equal to the constant “4′h9”. If the determination result is YES = 1, the selector 83 sets the constant “4′h0” in the register 82. If the determination result is NO = 0, the selector 83 selects LO + 1 of the adder 85, and if the selector 84 is COUNTON = 1, the output of the selector 83 is selected as a new counter value, and the COUNTON This indicates that the output LO is held when = 0. The above configuration is the lower counter.

  Further, the register 86, the comparator 87, the register 88, the selector 89, the adder 90, and the selector 92 have the same configuration as the above-described lower counter. Then, when the selector 91 is LO = 4, the output of the selector 89 is selected. When the selector 91 is other than LO = 4, the output is held and the output is not changed. These configurations are the upper counters.

  In FIG. 27B, a lower counter is constructed by the processor elements 80-85 in the 16-bit reconfiguration array R \ ARRAY_2, and the processor elements 86-92 in the 8-bit reconfiguration array R \ ARRAY_1. Thus, the upper counter is constructed. In this RTL description example, the bit conversion element is not used.

  As described above, according to the present embodiment, the reconfigurable integrated circuit has a plurality of reconfiguration arrays having different bit widths and has a processor element for converting the bit width. Thus, even when there are many descriptions of conversion to variables with different bit widths, it is possible to construct a circuit corresponding to RTL description flexibly.

  The above embodiment is summarized as follows.

(Appendix 1)
A reconfigurable LSI constructed in an arbitrary state based on configuration data,
A first reconfiguration array comprising a plurality of processor elements having a first bit width and an inter-processor element network configured to establish an arbitrary connection state between the plurality of processor elements based on the reconfiguration data;
A plurality of processor elements having a second bit width different from the first bit width, and a network between processor elements that constructs the plurality of processor elements in an arbitrary connection state based on the reconfiguration data; Two reconfiguration arrays,
A reconfiguration data memory for storing the reconfiguration data;
A reconfiguration control circuit that reads the reconfiguration data from the reconfiguration data memory and sets the first and second reconfiguration arrays in response to a predetermined event;
The first or second reconfiguration array is a reconfigurable LSI having a bit width conversion element for converting the signal wiring having the first bit width into the signal wiring having the second bit width.

(Appendix 2)
In Appendix 1,
The reconfigurable LSI, wherein the bit width conversion element includes a bit coupling element that couples the first bit width signal line and converts the signal line to the second bit width signal line.

(Appendix 3)
In Appendix 1,
The reconfigurable LSI, wherein the bit width conversion element includes a bit division element for converting a part of the signal line having the second bit width into the signal line having the first bit width.

(Appendix 4)
In any one of appendices 1 to 3,
The reconfigurable LSI, wherein the first and second bit widths are integer multiples of 8 bits.

(Appendix 5)
In any one of appendices 1 to 3,
The reconfigurable LSI, wherein the first bit width is 1 bit, and the second bit width is a bit width that is an integral multiple of 4 bits.

(Appendix 6)
In any one of appendices 1 to 3,
Furthermore, a reconfigurable LSI having a loader that loads the configuration data from an external memory when the power is turned on and stores the configuration data in the configuration memory.

(Appendix 7)
In Appendix 6,
Configuration data obtained by logical synthesis of a file described in RTL is stored in the external memory,
Based on the configuration data corresponding to the description for converting the first bit width data in the RTL description into the second bit width data, the bit width conversion element has the first bit width data. A reconfigurable LSI constructed to convert a data signal line to a data signal line of the second bit width.

(Appendix 8)
In Appendix 2,
The bit coupling element is a reconfigurable LSI that adds a value other than the signal line having the first bit width to the signal line having the second bit width.

R_ARRAY: Reconfiguration array PE: Processor element
SPL: Bit division element BND: Bit combination element
NW: Network between processor elements

Claims (5)

A reconfigurable LSI constructed in an arbitrary state based on configuration data,
A first reconfiguration array comprising a plurality of processor elements having a first bit width and an inter-processor element network configured to establish an arbitrary connection state between the plurality of processor elements based on the reconfiguration data;
A plurality of processor elements having a second bit width different from the first bit width, and a network between processor elements that constructs the plurality of processor elements in an arbitrary connection state based on the reconfiguration data; Two reconfiguration arrays,
A reconfiguration data memory for storing the reconfiguration data;
A reconfiguration control circuit that reads the reconfiguration data from the reconfiguration data memory and sets the first and second reconfiguration arrays in response to a predetermined event;
The first or second reconfiguration array is a reconfigurable LSI having a bit width conversion element for converting the signal wiring having the first bit width into the signal wiring having the second bit width. In claim 1,
The reconfigurable LSI, wherein the bit width conversion element includes a bit coupling element that couples the first bit width signal line and converts the signal line to the second bit width signal line. In claim 1,
The reconfigurable LSI, wherein the bit width conversion element includes a bit division element for converting a part of the signal line having the second bit width into the signal line having the first bit width. In any one of Claims 1 thru | or 3,
The reconfigurable LSI, wherein the first and second bit widths are integer multiples of 4 bits. In any one of Claims 1 thru | or 3,
Furthermore, a reconfigurable LSI having a loader that loads the configuration data from an external memory when the power is turned on and stores the configuration data in the configuration memory.

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