JP2012090897A - Game machine - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a game machine achieving high-speed communication.SOLUTION: The game machine generates a special game status for awarding a privilege to a player based on a result of a variation/display game, and includes a game control unit for generally controlling a game, and a presentation control unit for controlling a presentation device. In the game machine, the presentation device is divided into a plurality of groups, group control units are provided for controlling the groups, the presentation control unit is configured as a general group control unit for generally controlling the group control units, a timing signal line for transmitting a timing signal and a data line for transmitting a data signal are provided, and the general group control unit includes a voltage output unit for outputting voltage having a predetermined level through the data line. The voltage output unit sequentially transmits data by outputting the voltage level to the data line corresponding to transmitted data. The group control unit includes a bidirectional control unit for outputting a response signal or a unidirectional control device not outputting the response signal.

Description

  The present invention relates to a gaming machine provided with a plurality of group unit control means for controlling the effect devices divided into groups and a group overall control means for controlling the plurality of group unit control means.

  A technique disclosed in Patent Document 1 is known as a technique for realizing a gaming machine that has simple wiring of the effect control device and the decoration control device and has good assemblability.

  The gaming machine disclosed in Patent Document 1 includes a plurality of decoration control devices connected to the effect control device, and the plurality of decoration control devices are connected in series between the decoration control devices and have a unique address. When decoration control data is input, if the address included in the input decoration control data matches the address of the control device, an effect based on the decoration data is performed.

JP 2010-88667 A

  In the gaming machine described in Patent Document 1, a pull-up resistor is connected to a data line for transmitting decoration control data and an open drain circuit is connected to the data line to enable transmission of decoration control data.

  In such an open drain circuit, a current flows through a source grounded at the time of LOW level output, so that the pull-up resistance cannot be made very small.

  For this reason, at the HIGH level output, the rise of the signal voltage is delayed due to the influence of the pull-up resistor, so that high-speed communication cannot be realized.

  Therefore, an object of the present invention is to provide a gaming machine that realizes high-speed communication.

  In a typical embodiment of the present invention, when the game ball passes through a predetermined start winning area provided in the game area, a variable display game is displayed in which a plurality of identification information is displayed in a variable manner, corresponding to the result of the variable display game. In a gaming machine capable of generating a special gaming state that gives a bonus to a player, a game control means for comprehensively controlling a game in the game area, a plurality of effect devices for effecting the game, and the game control And an effect control means for controlling the plurality of effect devices in response to a command from the means, and each of the systems of the effect devices is divided into a plurality of groups, and the effect devices belonging to the divided groups are controlled. Group unit control means for each group is provided, and the effect control means is configured as a group overall control means for overall control of each of the group unit control means A timing signal line for transmitting a timing signal from the group control unit to the group unit control unit; and a data line for transmitting a data signal from the group control unit to the group unit control unit. Data can be transmitted from the control means to each group unit control means, and the group overall control means includes voltage output means for outputting a predetermined voltage level to the group unit control means via the data line, The voltage output means sequentially transmits the data to the group unit control means by changing the voltage level output to the data line corresponding to the data to be transmitted to the group unit control means, and the group unit control means Is the data addressed to itself transmitted by the group overall control means. A bidirectional unit control means for outputting the response signal to the group overall control means via the data line to which data has been transmitted by the group overall control means, or a unidirectional unit that does not output the response signal Consists of control means.

  According to one embodiment of the present invention, communication is possible without being affected by a pull-up resistor, so that high-speed communication can be performed.

It is explanatory drawing of the game machine of the 1st Embodiment of this invention. It is a front view of the game board of a 1st embodiment of the present invention. It is a disassembled perspective view of the center case of the 1st Embodiment of this invention. It is a figure which shows the state before the movable production apparatus of the 1st Embodiment of this invention operate | moves. As a result of the operation of the movable effect device according to the first embodiment of the present invention and the operation of the first effect unit and the second effect unit, the contact parts (first contact part and second contact part) It is a figure which shows the state which has contact | connected. It is a disassembled perspective view of the 1st production member of the 1st Embodiment of this invention. It is a disassembled perspective view of the 2nd production member of the 1st Embodiment of this invention. It is a figure explaining wiring of game machine 1 of a 1st embodiment of the present invention. It is a block diagram which shows the structure of the game machine 1 of the 1st Embodiment of this invention. It is a block diagram which shows the structure of the presentation control apparatus of the 1st Embodiment of this invention. It is a block diagram which shows the structure of the 1st master IC with which the presentation control apparatus of the 1st Embodiment of this invention was equipped, and the presentation apparatus with which the game board was equipped. It is a block diagram which shows the structure of the 2nd master IC with which the presentation control apparatus of the 1st Embodiment of this invention was equipped, and the presentation apparatus with which the front frame was equipped. It is a figure which shows the structure of the game board of the 1st Embodiment of this invention. It is a figure which shows the structure of the front frame of the 1st Embodiment of this invention. It is a figure explaining the connection state of the production | generation control apparatus of the 1st Embodiment of this invention, the relay board | substrate contained in a game board, and a decoration control apparatus. It is a figure explaining the connection state of the production | presentation control apparatus of the 1st Embodiment of this invention, the simple relay board | substrate contained in a normal version front frame, and a decoration control apparatus. It is a block diagram of the decoration control apparatus of the 1st Embodiment of this invention. It is a block diagram showing a configuration of a first embodiment of the I ² CI / O expander of the present invention. It is a circuit diagram around the I ² CI / O expander of the decoration control device that controls the decoration device according to the first embodiment of the present invention. It is a circuit diagram around the I ² CI / O expander of the decoration control device of the first exemplary embodiment of the present invention, and shows a case where a motor and a solenoid are controlled. It is a figure for demonstrating the circuit structure of the decoration control apparatus of the 1st Embodiment of this invention, a relay board | substrate, and a simple relay board | substrate, and in particular for demonstrating the connection state regarding the input / output of a signal line or a power supply line FIG. It is explanatory drawing of the slave address contained in the data output to the decoration control apparatus from the presentation control apparatus of the 1st Embodiment of this invention. It is an explanatory view of I ² CI / O expander address table according to the first embodiment of the present invention. It is a diagram for explaining a first embodiment of the I ² CI / O Aix work register assigned to the output setting register provided in expander of the present invention. It is explanatory drawing of the start condition and stop condition which the master IC of the 1st Embodiment of this invention outputs data via the connection line SDA and the connection line SCL. It is a timing chart which the decoration control apparatus into which the data output from the master IC of the 1st Embodiment of this invention was input outputs a response signal. It is a timing chart of the signal level of the connection line SDA and the connection line SCL when the master IC according to the first embodiment of the present invention outputs effect control data. When the master IC according to the first embodiment of the present invention specifies the individual address of the slave and sets the effect control data in the decoration control device, transmission / reception is performed between the master IC and the I ² CI / O expander. It is a figure explaining the format of data to be performed. When the master IC according to the first embodiment of the present invention specifies the individual address of the slave and sets the effect control data in the decoration control device, transmission / reception is performed between the master IC and the I ² CI / O expander. It is the figure which applied the specific numerical value to the production control data to be performed. It is a figure explaining the order which transmits the production | presentation control data of the master IC of the 1st Embodiment of this invention. When the first embodiment of the master IC of the present invention initializes the I ² CI / O expander, describing the format of the initialization instruction data transmitted to the I ² CI / O expander from the master IC FIG. It is a figure explaining the abnormality determination table of the 1st master IC of the 1st Embodiment of this invention. It is a figure explaining the abnormality determination table of the 2nd master IC of the 1st Embodiment of this invention. Information transmitted / received between the CPU and the master IC (first master IC or second master IC) when each decoration control device (slave) according to the first embodiment of the present invention is initialized (reset) will be described. FIG. Information transmitted and received between the CPU and the master IC (the first master IC or the second master IC) when transmitting the effect control data to each decoration control device (slave) according to the first embodiment of the present invention. It is a figure explaining. It is a figure explaining the step which transmits production | presentation control data to the master IC (1st master IC or 2nd master IC) from the production | presentation control apparatus of the 1st Embodiment of this invention. It is a flowchart which shows the procedure of the process by the presentation control apparatus of the 1st Embodiment of this invention. It is a flowchart which shows the procedure of the slave initialization start process by the side of the 1st master IC of the 1st Embodiment of this invention, and the slave initialization start process by the side of the 2nd master IC. It is a flowchart which shows the procedure of the presentation control regular process of the 1st Embodiment of this invention. It is a flowchart which shows the procedure of the process at the time of the transmission interruption interrupt generation | occurrence | production of the 1st master IC side of the 1st Embodiment of this invention, and the time-out interruption generation | occurrence | production. It is a flowchart which shows the procedure of the process at the time of the transmission interruption interrupt generation | occurrence | production of the 2nd master IC side of the 1st Embodiment of this invention, and the time-out interruption generation | occurrence | production. It is a flowchart which shows the procedure of the transmission resumption process of the initialization instruction | indication data of the 1st Embodiment of this invention. It is a flowchart which shows the procedure of the transmission resumption process of the production control data of the 1st Embodiment of this invention. It is a figure which shows an example of the transmission process continuation determination table for determining continuation of the transmission restart process of the data of the 1st Embodiment of this invention. It is a flowchart which shows the procedure of the data transmission process by the master IC of the 1st Embodiment of this invention. It is a flowchart which shows the procedure of the start condition output process of the 1st Embodiment of this invention. It is a flowchart which shows the procedure of the SCL release monitoring process of the 1st Embodiment of this invention. It is a flowchart which shows the procedure of the SDA release monitoring process of the 1st Embodiment of this invention. It is a flowchart illustrating a procedure of data transmission processing to the first 1 I ² of the slave side of the embodiment of the CI / O expander of the present invention. It is a flowchart which shows the procedure of the stop condition output process of the 1st Embodiment of this invention. The procedure of processing in the 1 I ² of the slave side of the embodiment of the CI / O expander of the present invention is a flow chart showing. The 1 I ² of the slave side of the embodiment of the CI / O Aix address recognition processing in expander of the present invention is a flow chart illustrating a procedure such. Is a flowchart illustrating a procedure of data read processing in the 1 I ² of the slave side of the embodiment of the CI / O expander of the present invention. It is a timing chart which shows the state by which the process by 1st master IC and 2nd master IC is performed in parallel by the instruction | indication from CPU of an effect control apparatus at the time of VDP interruption of the 1st Embodiment of this invention. A first I ² CI / O expander decoration control device in an embodiment of the present invention, a view showing a connection example of a decoration device, two 8-set amount of LED I ² CI / O expander It is a figure which shows the structure controlled by these. It is a figure which shows the timing which the decoration control apparatus in the 1st Embodiment of this invention receives data, and controls a production | presentation apparatus, and is a figure explaining the case where the data received at the time of outputting a stop condition are reflected. is there. It is a figure which shows the timing which the decoration control apparatus in the 1st Embodiment of this invention receives data, and controls a light-emitting device. In the first embodiment of the present invention, a state occurs in which the I ² CI / O expander 615 that has started to occupy the connection line SDA waits for the connection line SCL to fall, and the connection is made after a predetermined time has elapsed. I ² CI / O expander which occupies the line SDA has to reset itself, is a diagram for explaining a procedure to attempt to release the bus. In the first embodiment of the present invention, a state in which the connection line SDA is occupied for some reason occurs, and the I ² CI / O expander that detects the occupation of the connection line SDA resets itself, and the bus It is a figure explaining the procedure which tries to release | release. When the bus by I ² CI / O expander slave in the first embodiment of the present invention has been occupied, I ² CI / O expander slave releases the bus in response to a command from the master IC It is a figure explaining a procedure. In the first embodiment of the present invention, when a read mode occurs in the slave I ² CI / O expander due to an erroneous command from the master IC and the bus is occupied, the command from the master IC The slave side I ² CI / O expander explains the procedure for releasing the bus. It is a block diagram showing a configuration of a second embodiment of the I ² CI / O expander of the present invention. It is a figure which shows an example of the mode register 1 and the mode register 2 of the 2nd Embodiment of this invention. It is a flowchart which shows the procedure of the transmission resumption process of the initialization instruction | indication data of the 2nd Embodiment of this invention. It is a figure which shows a response | compatibility with the initialization stage number of the 2nd Embodiment of this invention, and the output buffer setting value set to the buffer for output. It is a figure explaining the structure of the data transmitted to each slave of the 2nd Embodiment of this invention, and is a figure which shows the case where an individual address is designated and a parameter is set. It is a figure explaining the structure of the data transmitted to each slave of the 2nd Embodiment of this invention, and is a figure which shows the case where an all call address is designated and a parameter is set. It is a figure explaining the timing which transmits / receives data between the master IC and the slave in the 2nd Embodiment of this invention. It is a block diagram which shows the structure of the presentation control apparatus of the 3rd Embodiment of this invention. It is a flowchart which shows the procedure of the process at the time of the transmission interruption interrupt generation | occurrence | production of the 1st master IC side of the 3rd Embodiment of this invention, and a timeout interruption generation | occurrence | production. FIG. 10 is a diagram illustrating a procedure for releasing a bus when the bus is occupied by a slave I ² CI / O expander in the third embodiment of the present invention. It is a figure which shows the example of a connection of the decoration control apparatus and decoration apparatus in the 4th Embodiment of this invention, and is a figure which shows the structure which controls LED for 5 sets by one decoration control apparatus. Information transmitted and received between the CPU and the master IC (first master IC or second master IC) when transmitting the effect control data to each decoration control device (slave) according to the fourth embodiment of the present invention. It is a figure explaining. It is a flowchart which shows the procedure of the presentation control regular process of the 4th Embodiment of this invention. It is a flowchart which shows the procedure of the transmission resumption process of the presentation control data of the 4th Embodiment of this invention. It is a figure explaining the structure of the data transmitted to each slave of the 4th Embodiment of this invention. It is a figure explaining the timing which transmits / receives data between the master IC and the slave in the 4th Embodiment of this invention. It is a figure explaining the case where the received data is reflected in the light emission state of LED at the time of outputting ACK to the master IC when the decoration control device receives data in the fourth embodiment of the present invention. It is a block diagram which shows the structure of the 1st master IC with which the presentation control apparatus of the 5th Embodiment of this invention was equipped, and the presentation apparatus with which the game board was equipped. It is a block diagram showing a configuration of a fifth embodiment of the I ² CI / O expander of the present invention. It is a diagram illustrating the connection of the first master IC of the fifth embodiment and the slave (I 2 ^CI / O expander) of the present invention. It is a flowchart which shows the procedure of the data transmission process by the master IC of the 5th Embodiment of this invention. It is a flowchart which shows the procedure of the start condition output process of the 5th Embodiment of this invention. It is a flowchart which shows the procedure of the stop condition output process of the 5th Embodiment of this invention. It is a flowchart illustrating the first half of the procedure of the data transmission processing to the I ² CI / O expander of the fifth embodiment of the slave side of the present invention. Is a flow chart showing the second half of the procedure of the data transmission process to the first 5 I ² CI / O expander slave embodiment of the present invention. It is a diagram illustrating an example of a fifth embodiment of the I ² CI / O expander address table of the present invention. It is a flowchart which shows the procedure of the condition prior output change process of the 5th Embodiment of this invention. It is a timing chart which shows the procedure which transmits data from the 1st master IC of the 5th Embodiment of this invention to a slave. FIG. 87A is a timing chart when data is transmitted to the unidirectional slave, and FIG. 87B is a timing chart when data is transmitted to the bidirectional slave. It is explanatory drawing of the slave address contained in the data output to the decoration control apparatus from the presentation control apparatus of the modification of the 5th Embodiment of this invention. It is a diagram illustrating an example of I ² CI / O expander address table of a modification of the fifth embodiment of the present invention. It is a timing chart which shows the procedure which transmits data to the slave from the 1st master IC of the modification of the 5th Embodiment of this invention. It is a block diagram explaining the structure of the 1st master IC of another modification of the 5th Embodiment of this invention. It is a figure which shows an example of the setting value of the mode selection setting register contained in the 1st master IC of another modification of the 5th Embodiment of this invention.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(First embodiment)
FIG. 1 is an explanatory diagram of the gaming machine 1 according to the first embodiment of this invention.

  A front frame (game frame) 3 of the gaming machine 1 is assembled to the main body frame (outer frame) 2 via a hinge 4 so as to be openable and closable on the front surface of the gaming machine 1. A game board 10 (see FIG. 2) is accommodated on the front side of the front frame 3. Further, a glass frame 18 having a cover glass (transparent member) covering the front surface of the game board 10 is attached to the front frame 3.

  Around the cover glass of the glass frame 18, decoration members 9 a and 9 b that emit decoration light are provided. The decoration members 9a and 9b are provided with a decoration device composed of a lamp, an LED, or the like. By causing the decoration device to emit light in a predetermined light emission mode, the decoration members 9a and 9b emit light in a predetermined light emission mode.

  Speakers 30 that emit sound (for example, sound effects) are provided on the left and right sides of the glass frame 18. An illumination unit 11 is provided above the glass frame 18.

  In the illumination unit 11, a first movable illumination 13 and a second movable illumination 14 are arranged on the left and right. The first movable illumination 13 and the second movable illumination 14 include an illumination drive first motor (MOT) 13a and an illumination drive second motor (MOT) 14a in addition to an illumination member such as an LED. It is controlled so as to operate according to the contents of the production.

  An abnormality notification LED 29 for notifying that an abnormality has occurred in the gaming machine 1 is provided at the lower right of the lighting unit 11.

  The open / close panel 20 below the front frame 3 is provided with an upper plate for supplying a game ball to a ball hitting device (not shown), and the fixed panel 22 is provided with a lower plate 23 and an operation unit 24 of the ball hitting device. The lower tray 23 is provided with a lower tray ball removing mechanism 16 for discharging the game balls stored in the lower tray 23. A key 25 for locking the glass frame 18 is provided on the lower right side of the front frame 3.

  Further, when the player turns the operation unit 24, the hitting ball launching device launches a game ball supplied from the upper plate 21.

  In addition, the upper edge portion of the upper plate 21 is provided with an effect button 17 for receiving an operation input from the player. When the player operates the effect button 17, the effect content of the special figure variation display game on the display device 53 (see FIG. 2) provided on the game board 10 is selected, and the special figure variation display game on the display device 53 is selected. In addition, it is possible to perform an effect in which the player's operation is intervened.

  The special figure variation display game is started when the launched game ball wins a start opening 36 (see FIG. 2) provided in the game board 10. In the special figure fluctuation display game, a plurality of pieces of identification information are variably displayed on the display device 53. Then, when the identification information that has been variably displayed is stopped and the result mode of the stopped identification information is a specific result mode, the state of the gaming machine 1 is advantageous to the player (a state where a privilege is granted) Transition to a special gaming state.

  In the upper right portion of the upper plate 21, a ball lending button 26 that is operated when a player borrows a game ball and a discharge button 27 that is operated to discharge a prepaid card from a card unit (not shown) are provided. . Further, a balance display unit 28 for displaying the balance of the prepaid card is provided between the ball lending button 26 and the discharge button 27.

  FIG. 2 is a front view of the game board 10 according to the first embodiment of this invention.

  The gaming machine 1 shown in FIG. 1 fires a game ball in an internal game area 10a (bounces it) to play a game, and a game area 10a is provided on the back side of the cover glass of the glass frame 18. The game board 10 which comprises is installed.

  The game board 10 includes a flat game board main body 10b (made of wood or synthetic resin) serving as a mounting base for various members, and has a game area 10a surrounded by a guide rail 32 on the front surface of the game board main body 10b. ing. A front component 33 is attached to the front surface of the game board main body 10 b and outside the guide rail 32. Then, a game ball (hit ball; game medium) is launched from the launching device into the game area 10a surrounded by the guide rail 32 to play a game.

  A center case 51 that forms a window 52 serving as a display area for a special figure variation display game is attached to the approximate center of the game area 10a. Behind the window 52 formed in the center case 51, a display device 53 is arranged as an effect display device capable of executing an effect of a special figure variable display game that displays a plurality of identification information in a variable manner. The display device 53 includes, for example, a liquid crystal display, and is arranged so that a display portion 53 a whose display contents can be changed is visible from the front side of the game board 10 through the window portion 52 of the center case 51. Note that the display device 53 is not limited to a device including a liquid crystal display, and may include a display such as an EL or a CRT.

  In addition, a reliability notification device 15 that notifies the possibility of jackpot (reliability) is provided on the upper portion of the center case 51. The reliability notification device 15 includes LEDs of a plurality of colors (for example, LEDs of three colors of red, blue, and green) and is controlled to emit light in a color and manner according to the reliability.

  Further, a ball introduction path (warp flow path) 50 through which a game ball can flow down is provided on the left portion of the center case 51, and is opened with the entrance 50a open toward the game area 10a. The ball introduction path 50 communicates with the inside of the center case 51, and the game ball that has flowed from the inlet 50a passes through the back side of the center case 51 and is discharged onto the unit-side stage portion 49b. Further, the game ball that rolls on the unit-side stage portion 49b can flow down onto the base-side stage portion 49a disposed below the unit-side stage portion 49b.

  A plurality of ornaments 47 are arranged on the peripheral edge of the center case 51. A decorative lamp 48 is disposed at the lower left portion of the center case 51, and a plurality of decorative pieces 46 are disposed in an upper and lower movable state at the upper portion of the center case 51. The decoration tool 47, the decoration lamp 48, and the decoration piece 46 perform an effect operation according to a command from an effect control device 550 described later. The configuration of the center case 51 will be described in more detail with reference to FIG.

  Further, in the game area 10a, below the center case 51, a start opening 36 for starting a special figure changing display game that can receive (win) a game ball is arranged. Further, on the side of the center case 51 (on the left side), a general map start gate 34 for starting the general map change display game is arranged.

  Further, in the game area 10a, side lamps 45 that perform various decorative displays by light emission are arranged on the lower left and lower right of the center case 51. The side lamp 45 is provided with a general winning opening 44.

  Further, a big winning opening 42 is arranged below the start opening 36, and an out opening for collecting the game balls that have flowed down without winning at the lower edge of the gaming area 10a below the big winning opening 42. 43 is established. The special winning opening 42 includes an attacker-type opening / closing door 42a that can be opened by rotating in a direction in which the upper end side is tilted to the near side. The state of the open / close door 42a is changed from a closed state (a disadvantageous state for the player) to an open state (a state advantageous for the player) according to the result of the special figure variation display game.

  In addition, in the game area 10a excluding attachment portions such as the center case 51, the start port 36, the side lamp 45, etc., there are a windmill (not shown) as a hitting direction changing member, and many No. nails (not shown) are provided. A vertically arcuate game ball passage 57 is formed between the center case 51 and the front structural member 33 located on the opposite side of the normal start gate 34 with the center case 51 interposed therebetween.

  Further, the game board 10 is provided with a special figure / special figure display 35 for executing a special figure change display game and a normal figure change display game. The general-purpose / special-figure display 35 displays the number of unprocessed times (special figure start memory number) of the special-figure display game and the unprocessed number of general-purpose variable display games (number of general figure start memory). The general-purpose / special-purpose display 35 is provided as a segment LED together with a game state display LED (not shown) representing a game state.

  A gate SW 34a (see FIG. 9) for detecting a game ball that has passed through the general chart start gate 34 is provided in the general chart start gate 34. Then, when the game ball that has been driven into the game area 10a passes through the normal figure start gate 34, the normal figure change display game is started.

  In addition, when the game ball passes through the general chart start gate 34 in a state where the normal map variable display game cannot be started, if the general chart start memory number is less than the upper limit number, the general chart start memory number is incremented by one, One random number indicating whether or not the normal figure change display game is won is stored as a normal figure start memory.

  The state in which the general map change display game cannot be started is, for example, a state in which the general map change display game has already been performed and the normal map change display game has not been completed, Is the state that has been converted to the open state.

  It should be noted that the universal map change display game may display the universal map change display game in a part of the display area of the display device 53. In this case, for example, numbers, symbols, character designs, etc. are used as identification symbols. This identification symbol is displayed by variably displaying for a predetermined time and then stopped and displayed.

  When the stop display of the normal map change display game becomes a special result mode, the opening / closing member 36a of the start port 36 is opened for a predetermined time (for example, 0.5 seconds) as a win for the normal map change display game. Is done. Thereby, it becomes easy to win a game ball in the start opening 36, and the special figure variation display game can be started easily. The opening / closing member 36a of the start port 36 normally maintains a closed state (a disadvantageous state for the player) with an interval of about the diameter of the game ball. When the stop display mode is entered (when the normal-game fluctuation display game is won), the game ball is opened in the reverse “C” shape by the solenoid (Fuden SOL 36b, see FIG. 9), and the game ball is placed at the start port 36. It is changed to a state that is easy to flow in (a state that is advantageous to the player).

  Further, the gaming machine 1 according to the first embodiment of the present invention shortens the variation display time of the special figure variation display game on the display device 53 as a gaming state based on the result aspect of the special figure variation display game. An operation state (second operation state) can be generated. The short-time operation state (second operation state) is a state in which the opening / closing member 36a of the start port 36 is likely to be open compared to the normal operation state (first operation state).

  In the short-time operation state, the execution time of the normal variation display game is controlled to be shorter than the execution time in the normal operation state (for example, 10 seconds is 1 second), and the number of opening of the start port 36 per unit time is It is controlled to increase substantially. Further, in the short-time operation state, when the start port 36 is opened due to the winning of the normal fluctuation display game, the opening time is controlled to be longer than the opening time of the normal operation state (for example, 0 3 seconds is 1.8 seconds). Further, in the short-time operation state, the start port 36 is opened a plurality of times (for example, two times) instead of once for the one-time winning result of the normal map display game. Further, in the short-time operation state, control is performed so that the probability of winning the normal-variation display game is higher than that in the normal operation state. That is, the number of times of opening of the start port 36 is increased as compared with the normal operation state, and it becomes easy to win a game ball in the start port 36, and the special figure variation display game can be started easily.

  In addition, a start port SW 36 d (see FIG. 9) for detecting a game ball that has passed through the start port 36 is provided inside the start port 36. When a game ball is detected by the start port SW36d, a start right for starting a special figure variation display game as an auxiliary game is generated. At this time, the right to start the special figure variation display game is stored as a special figure start memory within a predetermined upper limit number (for example, 4).

  When the special figure fluctuation display game cannot be started immediately, for example, when the special figure fluctuation display game has already been performed and the special figure fluctuation display game has not been completed, or when the special game state has been entered, the start port 36 When the game ball wins, if the special figure start memory number is less than the upper limit number (for example, less than 4), the special figure start memory number is incremented by 1 and extracted at the timing when the game ball wins the start opening 36. One random number is stored as a special figure start memory. When the special figure fluctuation display game is ready to start, the special figure fluctuation display game is started based on the special figure start memory.

  The special figure variation display game as an auxiliary game is executed by the general figure / special figure display device 35 provided on the game board 10, and after a plurality of identification information is variably displayed, a predetermined result mode is stopped and displayed. Done. Further, a plurality of types of identification information (for example, numbers, symbols, character designs, etc.) are displayed in a variable manner on the display device 53 in correspondence with the special figure fluctuation display game. And as a result of the special figure variation display game, when the display mode of the general figure / special map display 35 becomes a special result mode, it becomes a big win and becomes a special game state (so-called big hit state). Correspondingly, the display mode of the display device 53 is also a special result mode (for example, any one of the numbers in the flat order such as “7, 7, 7”). In addition, you may comprise so that a special figure fluctuation display game may be performed only with the display apparatus 53 instead of the general figure and special figure display 35. FIG.

  Further, the gaming machine 1 according to the first embodiment of the present invention can generate a probability variation state (second probability state) as a gaming state based on the result form of the special figure variation display game. This probability variation state (second probability state) is a state in which the probability of a hit result in the special figure variation display game is higher than the normal probability state (first probability state). Note that the probability variation state and the above-described short-time operation state can be generated independently, and both can be generated at the same time, or only one of them can be generated.

  FIG. 3 is an exploded perspective view of the center case 51 according to the first embodiment of the present invention.

  The center case 51 includes a frame decoration portion 65 disposed as a front surface configuration portion on the front surface side of the game board main body 10b (game board 10), and a frame base portion 60 disposed as a back surface configuration portion on the back surface side of the game board main body 10b. And are polymerized before and after. The frame decoration portion 65 includes an annular decoration base 66 that is fixed to the surface of the game board main body 10b. On the back side of the decoration base 66, there is provided a decoration panel unit 67 that is substantially the same size as the decoration base 66 and formed in a circular shape, and the frame decoration portion 65 superimposes the decoration base 66 and the decoration panel unit 67 back and forth. Configured.

  Under the decoration base 66, a base side stage portion 49a capable of rolling a game ball in the front-rear direction and the left-right direction is disposed on the upper surface, and a decoration lamp is provided between the base side stage portion 49a and the game ball passage 57. 48 is arranged (see FIG. 2). A ball introduction path (warp flow path) 50 through which a game ball can flow down is provided on the opposite side of the decoration lamp 48 across the base side stage portion 49a, and the entrance 50a of the ball introduction path 50 is connected to the decoration base 66. The outlet 50b of the ball introduction path 50 is communicated with the back side of the decorative panel unit 67 described later.

  The decorative panel unit 67 includes a cover panel portion 69 formed of a substantially circular transparent resin plate, and a plurality of decorative tools 47 are arranged on the peripheral edge of the front side of the cover panel portion 69. When the decorative panel unit 67 and the decorative base 66 are overlapped, the decorative tool 47 is set to be disposed along the inner peripheral edge of the decorative base 66 (see FIG. 2). In addition, a reliability notification device 15 is disposed on the upper portion of the cover panel unit 69.

  In addition, a unit-side stage portion 49b capable of rolling a game ball in the front-rear direction and the left-right direction is disposed on the upper surface at the lower portion on the back side of the cover panel portion 69. The unit side stage portion 49b is disposed above the base side stage portion 49a of the decorative base 66.

  Further, a sphere inlet 68 is opened at a location where the cover panel 69 overlaps with the outlet 50 b of the sphere introduction path 50, and the sphere introduction path 50 and the unit side stage portion 49 b communicate with each other via the sphere inlet 68. is doing. Therefore, when a game ball flowing down the game area 10a flows into the ball introduction path 50, the ball introduction path 50 is configured so that the game ball can be introduced onto the unit side stage portion 49b.

  The frame base 60 includes a frame-like base case 61 that is fixed to the back side of the game board 10 in a state where the front side is open, and is opened inside the base case 61 (in other words, inside the center case 51). The part 62a forms a concave chamber 62 provided on the front side.

  In addition, a rectangular window 52 is opened in the front-rear direction behind the concave chamber 62 in the base case 61, and a display device 53 is attached from the rear of the base case 61 to display the display portion of the display device 53. 53 a faces the front of the center case 51 through the window 52 and the recessed chamber 62.

  Further, a plurality of decorative pieces 46 that can be moved up and down by an accessory driving solenoid (not shown) are disposed on the front side of the upper edge of the window 52, and display portions are provided on the left and right edges of the window 52. A movable effect device 58 that moves forward 53a and performs an effect operation is provided.

  Then, when the frame decoration portion 65 is overlapped in front of the frame base portion 60, the opening 62a and the window portion 52 of the concave chamber 62 are covered with the cover panel portion 69 from the front, and the display portion 53a of the display device 53 is covered with the frame decoration portion. It is configured to face the front of the center case 51 from the inside of 65 (where the cover panel portion 69 is exposed).

  4 and 5 are diagrams illustrating the configuration of the movable effect device 58 according to the first embodiment of this invention.

  The movable effect device 58 is configured by providing the first effect unit 63 and the second effect unit 64 at positions separated from each other, and the first effect unit 63 and the second effect unit 64 are operated in conjunction with each other. .

  FIG. 4 is a diagram illustrating a state before the movable effect device 58 is operated, and FIG. 5 is a result of the movable effect device 58 being operated and the first effect unit 63 and the second effect unit 64 being operated. It is a figure which shows the state contact | abutted in a part (1st contact part 121 and 2nd contact part 122).

  The first effect unit 63 is disposed on the left side of the center case 51, that is, on the left side of the peripheral edge of the window portion 52 of the base case 61. Further, the second effect unit 64 is disposed on the right side of the center case 51. When viewed from the front of the center case 51, the concave chamber 62 and the window 52 are arranged so as to face between the first effect unit 63 and the second effect unit 64.

  The first effect unit 63 includes a first effect member 70 that can move forward of the display unit 53a, and an accessory driving first motor (MOT) that serves as a first effect drive source that generates the driving force of the first effect member 70. ) 71 and a first effect transmission mechanism (a first main arm member 73 and a first sub arm member 74) that transmits the driving force (rotational power) generated from the accessory driving first MOT 71 to the first effect member 70. .

  Further, an output shaft (first output shaft) 71a of the accessory driving first MOT 71 extends in the front-rear direction of the center case 51, and a first drive gear 76 is rotatably mounted on the first output shaft 71a. Yes.

  The first main arm member 73 is formed with a first main arm gear 77 that meshes with the first drive gear 76, and is pivotally mounted above the first drive gear 76. The first sub arm member 74 is formed with a first sub arm gear 78 that meshes with the first drive gear 76, and is pivotally attached to the lower side of the first drive gear 76. The first main arm member 73 and the first sub arm member 74 are axially attached to the first effect member 70 at positions where the end portions opposite to the end portions axially attached to the base case 61 are different from each other. 70 is supported.

  When the first effect unit 63 drives the accessory driving first MOT 71 and rotates the first driving gear 76 in the clockwise direction when viewed from the front of the center case 51, the driving force (rotation power) of the accessory driving first MOT 71 is generated. The first main arm member 73 is transmitted to the first main arm member 73 via the first drive gear 76 and the first main arm gear 77, and the first main arm member 73 is rotated counterclockwise when viewed from the front of the center case 51 by this driving force. To do. The driving force of the accessory driving first MOT 71 is transmitted to the first sub arm member 74 via the first driving gear 76 and the first sub arm gear 78, and the first sub arm member 74 is transmitted to the first main arm 74 by this driving force. It rotates in the same counterclockwise direction as the arm member 73. As a result, the first effect member 70 rises while being supported by the first main arm member 73 and the first sub arm member 74.

  Then, when the first main arm member 73 and the first sub arm member 74 are extended upward by the driving force of the accessory driving first MOT 71 and set in the vertical posture, as shown in FIG. The first effect stop state is set to be deviated from the front of the display portion 53a, and the first effect member 70 is located on the side of the window portion 52 and is hidden behind the frame decoration portion 65 and behind the game board main body 10b. (See FIG. 2).

  On the other hand, when the first driving gear MOT 71 is driven from the first effect stop state and the first driving gear 76 is rotated counterclockwise when viewed from the front of the center case 51, the driving force (rotational power) of the first driving gear MOT 71 is rotated. ) Is transmitted to the first main arm member 73 via the first drive gear 76 and the first main arm gear 77, and the first main arm member 73 rotates clockwise as viewed from the front of the center case 51 by this drive force. Move.

  The driving force of the accessory driving first MOT 71 is transmitted to the first sub arm member 74 via the first driving gear 76 and the first sub arm gear 78, and the first sub arm member 74 is transmitted to the first main arm 74 by this driving force. It rotates in the same clockwise direction as the arm member 73. As a result, the first effect member 70 is lowered while being supported by the first main arm member 73 and the first sub arm member 74.

  Then, when the first main arm member 73 and the first sub arm member 74 are extended to the front of the display unit 53a and set in the horizontal posture by the driving force of the accessory driving first MOT 71, as shown in FIG. The first effect execution state is reached in which the member 70 is positioned in front of the display unit 53a, and the first effect member 70 is in front of the central portion of the display unit 53a in the space between the display unit 53a and the cover panel unit 69. To position.

  The second effect unit 64 includes a second effect member 80 that can move to the front of the display unit 53a, and an accessory driving second motor (MOT) as a second effect drive source that generates the drive force of the second effect member 80. ) 81 and a second effect transmission mechanism (second main arm member 83 and second sub arm member 84) that transmits the driving force (rotation power) generated from the accessory driving second MOT 81 to the second effect member 80. .

  Further, the accessory driving second MOT 81 has an output shaft (second output shaft) 81a extending in the front-rear direction of the center case 51, and a second drive gear 86 is pivotally attached to the second output shaft 81a so as to be able to rotate together. Yes.

  The second main arm member 83 is formed with a second main arm gear 87 that meshes with the second drive gear 86, and is pivotally attached to a position closer to the first effect unit 63 than the second drive gear 86. The second sub arm member 84 is formed with a second sub arm gear 88 that meshes with the second drive gear 86, and is pivotally attached to the lower side of the second drive gear 86. The second main arm member 83 and the second sub arm member 84 are pivotally attached to the second effect member 80 at positions where the end portions opposite to the end portions that are axially attached to the base case 61 are different from each other. 80 is supported.

  When the second effect unit 64 drives the accessory driving second MOT 81 and rotates the second driving gear 86 in the clockwise direction when viewed from the front of the center case 51, the driving force (rotation power) of the accessory driving second MOT 81 is generated. This is transmitted to the second main arm member 83 via the second drive gear 86 and the second main arm gear 87, and the second main arm member 83 rotates counterclockwise when viewed from the front of the center case 51 by this driving force. To do. Further, the driving force of the accessory driving second MOT 81 is transmitted to the second sub arm member 84 via the second driving gear 86 and the second sub arm gear 88, and the second sub arm member 84 is transmitted to the second main arm member 84 by this driving force. It rotates in the same counterclockwise direction as the arm member 83. As a result, the second effect member 80 is lowered while being supported by the second main arm member 83 and the second sub arm member 84.

  Then, the second main arm member 83 and the second sub arm member 84 are rotated by the driving force of the accessory driving second MOT 81 to cause the second effect member 80 to reach the bottom dead center, and then the second main arm member 83 and When the second sub-arm member 84 is rotated to extend obliquely downward and set in a vertical posture and the second effect member 80 is slightly raised from the bottom dead center, as shown in FIG. The second effect stop state is reached in which the member 80 is positioned away from the front of the display unit 53a, and the second effect member 80 is hidden behind the frame decoration part 65 and behind the game board main body 10b (see FIG. 2).

  On the other hand, when the accessory driving second MOT 81 is driven from the second effect stop state and the second driving gear 86 is rotated counterclockwise as viewed from the front of the center case 51, the driving force (rotational power) of the accessory driving second MOT 81 is rotated. ) Is transmitted to the second main arm member 83 via the second drive gear 86 and the second main arm gear 87, and the second main arm member 83 rotates clockwise as viewed from the front of the center case 51 by this driving force. Move.

  Further, the driving force of the accessory driving second MOT 81 is transmitted to the second sub arm member 84 via the second driving gear 86 and the second sub arm gear 88, and the second sub arm member 84 is transmitted to the second main arm member 84 by this driving force. It rotates in the same clockwise direction as the arm member 83. As a result, the second effect member 80 rises while being supported by the second main arm member 83 and the second sub arm member 84.

  Then, when the second main arm member 83 and the second sub arm member 84 are extended to the front of the display unit 53a and set in the horizontal posture by the driving force of the accessory driving second MOT 81, as shown in FIG. The second effect execution state in which the member 80 is positioned in front of the display unit 53a is entered, and the second effect member 80 is in front of the central portion of the display unit 53a in the space between the display unit 53a and the cover panel unit 69. To position.

  FIG. 6 is an exploded perspective view of the first effect member 70 according to the first embodiment of the present invention.

  The first effect member 70 is a substantially semicircular member when viewed from the front of the center case 51, and is set in a posture in which an arc surface is disposed on the first effect unit 63 side.

  The first effect member 70 is provided with a first effect base 100 serving as a base. The first effect base 100 is formed of a transparent resin. Formed on the upper part of the first effect base 100 is a first main arm shaft attachment portion 101 for axially attaching the first main arm member 73 from the front of the first effect base 100, and on the lower part of the first effect base 100, A first sub-arm shaft attachment portion 102 for attaching the first sub-arm member 74 from the rear of the first effect base 100 is formed.

  A first light diffusion sheet 103 that can transmit light while diffusing light is superposed on the front surface of the first effect base 100. Furthermore, the transparent first protective panel 104 is polymerized on the front surface of the first light diffusing sheet 103 to prevent the first light diffusing sheet 103 from falling off the first effect member 70.

  Further, the rear portion of the first production base 100 is recessed forward to form a first substrate storage space portion 105, and a light emitting device such as an LED (decoration device 620, see FIG. 17) is formed in the first substrate storage space portion 105. The mounted first light emitting substrate 106 is accommodated. Further, in this state, the first substrate housing space portion 105 is closed with the first base lid portion 107 to prevent the first light emitting substrate 106 from falling off the first effect member 70.

  Then, when light is generated from the light emitting device of the first light emitting substrate 106, the light passes through the first effect base 100, the first light diffusion sheet 103, and the first protective panel 104 and is irradiated to the front of the center case 51. It is configured as follows.

  Further, a first effect magnet holder 124 whose rear part is opened is formed on the first substrate housing space 105 side of the first contact part 121 so as to be recessed. The first effect magnet holder 124 has a first magnet 125 made of a button-shaped permanent magnet in a posture in which the magnetic pole faces the second effect member 80 side, and the first magnet 125 is connected to the first contact portion 121 (first effect). The magnet holder 124) is stored so as not to fall off.

The first light-emitting substrate 106 is equipped with an I ² CI / O expander 615 (see FIG. 17) for controlling the light emission of the decoration device 620, and a control signal (electric signal) output from the effect control device 550, etc. A data line (data signal line) and a clock line (signal line) for transmission are connected. Further, a power line for supplying power necessary for causing the decoration device 620 to emit light is connected. These connection lines are connected together as a cable 108.

  FIG. 7 is an exploded perspective view of the second effect member 80 according to the first embodiment of the present invention.

  The second effect member 80 has a substantially parallelogram shape with a cutout portion at the top when viewed from the front of the center case 51. In the second effect stop state, the upper and lower side surfaces of the second effect member 80 are inclined downward from the second effect unit 64 side toward the first effect unit 63 side (see FIG. 4), and in the second effect execution state, The left and right side surfaces of the second effect member 80 are set in a posture to incline downward from the second effect unit 64 side toward the first effect unit 63 side (see FIG. 5).

  The second effect member 80 includes a second effect base 110 that serves as a base. The second effect base 110 is formed of a transparent resin. In the upper part of the second effect base 110, a second main arm axis attaching part 111 for axially attaching the second main arm member 83 from the front of the second effect base 110 is formed, and in the lower part of the second effect base 110, A second sub-arm shaft attachment portion 112 for attaching the second sub-arm member 84 from the rear of the second effect base 110 is formed.

  Further, a second light diffusing sheet 113 that can transmit light while diffusing light is superposed on the front surface of the second effect base 110. By superposing the transparent second protective panel 114 on the front surface of the second light diffusing sheet 113, the second light diffusing sheet 113 is prevented from falling off the second effect member 80.

  In addition, the rear portion of the second effect base 110 is recessed forward to form a second substrate storage space 115, and a light emitting device (decoration device 620) such as an LED is mounted in the second substrate storage space 115. The second light emitting substrate 116 is accommodated, and in this state, the second substrate accommodating space 115 is closed by the second base lid portion 117 to prevent the second light emitting substrate 116 from dropping from the second effect member 80. .

  Then, when light is generated from the light emitting device of the second light emitting substrate 116, the light passes through the second effect base 110, the second light diffusion sheet 113, and the second protection panel 114 and is irradiated to the front of the center case 51. It is configured as follows.

  Further, a second effect magnet holder 128 having an open rear portion is formed on the second substrate housing space 115 side of the second contact portion 122 so as to be recessed. In the second effect magnet holder 128, a second magnet 129 made of a button-shaped permanent magnet is stored at a position symmetrical to the first magnet 125 across the first contact portion 121 and the second contact portion 122. Has been.

Similarly to the first light emitting substrate 106, the second light emitting substrate 116 is equipped with an I ² CI / O expander 615 (see FIG. 17) for controlling the light emission of the decoration device 620, and is output from the effect control device 550. A data line and a clock line (signal line) for transmitting the transmitted control signal and the like are connected. Further, a power line for supplying power necessary for causing the decoration device 620 to emit light is connected. These connection lines are connected together as a cable 118.

  The movable effect device 58 includes the first contact member 121 on the first effect member 70 and the second contact member 122 on the second effect member 80. When the first effect unit 63 is converted to the first effect execution state and the second effect unit 64 is converted to the second effect execution state, the first contact portion 121 and the second contact portion 122 contact each other. The first effect member 70 and the second effect member 80 form one decorative body. At this time, the first magnet 125 and the second magnet 129 are arranged so as to generate an attractive force between the first magnet 125 and the second magnet 129. Further, the decorative body thus formed is configured to be positioned in front of the central portion of the display portion 53a.

  FIG. 8 is a diagram illustrating wiring of the gaming machine 1 according to the first embodiment of this invention.

  FIG. 8 shows a state before the center case 51 is attached to the game board main body 10 b and the display device 53 is attached to the center case 51. An effect control device 550 is attached to the back surface of the display device 53. The effect control device 550 is provided with a connection terminal 90, and transmits a control signal and supplies power to the effect device to be controlled via the connection terminal 90. Specifically, it is connected via a cable 91 to a relay board 600 described later.

  In addition, a game control device 500 and a control unit 700 including various control boards are arranged at the lower back of the game board main body 10b. The control board mounted on the control unit 700 includes a relay board 600 that relays the control signal transmitted from the effect control apparatus 550 to the decoration control apparatus 610 (see FIG. 11). Although the details will be described later, the decoration control device 610 controls an effect device such as a light emitting device (for example, LED) or a movable object (for example, a motor) for effecting a game. The relay board 600 can be connected to a light emitting device or a movable object, similarly to the decoration control device 610.

  The relay board 600 is provided with an upstream connector 601 connected to the effect control device 550 via the cable 91. One connector 91a of the cable 91 is connected to the connection terminal 90 of the effect control device 550 as described above. The other connector 91 b of the cable 91 is connected to the upstream connector 601 of the relay board 600. Furthermore, connectors 602a to 602e for connecting to a decoration control device 610 that controls each effect device provided in the gaming machine 1 are provided.

  Further, the relay board 600 is provided with a vacant terminal monitor 603 indicating the connection state of the connected cables. Details of the empty terminal monitor 603 will be described with reference to FIG.

  Although illustration is omitted, units constituting the game control device 500 are provided so as to cover the connector mounting surface of the relay board 600. Therefore, the game control apparatus 500 has an arrangement configuration that is attached after attaching necessary cables to the connectors of the relay board 600.

  Connected to the front frame 3 is a cable 3b for transmitting signals for controlling the speaker 30 and the decorative members 9a, 9b and the like disposed on the front frame 3. The connector of the cable 3b is connected to the connection terminal 92 of the effect control device 550.

  An opening 45b for attaching the side lamp 45 is formed in the game board main body 10b. A cable 45a for transmitting power and signals is connected to the side lamp 45, and is introduced from the opening 45b to the back side of the game board 10. The cable 45a introduced to the back side of the game board 10 is connected to the relay board 600, for example, connected to the connector 602d.

  Further, as shown in FIG. 2, a starting port 36 and a special winning port 42 are arranged at the lower part of the game board 10. On the back side of the game board 10 on which the start port 36 is arranged, there is arranged a general electric solenoid (SOL) 36b for opening and closing an open / close member 36a that is opened when a win-win game is won. In addition, a special winning opening SOL 42 b for opening and closing the special winning opening 42 when the special figure variation display game is won is also arranged on the back side of the game board 10. A cable (not shown) for receiving an input of a control signal is connected to the general electric power SOL 36 b and the special winning opening SOL 42 b, and these cables are connected to the game control device 500. The cable 42C is connected to the relay board 600 as a cable for transmitting power and a signal for lighting the effect LED provided in the special winning opening 42, and is connected to the connector 602f, for example.

  As described above, the center case 51 is attached to the center of the game board 10. Inside the center case 51, a movable effect device 58 constituted by the first effect member 70 and the second effect member 80 is provided. In FIG. 8, the first effect member 70 and the second effect member 80 are in contact with each other at the contact surfaces (121, 122).

  Further, as described above, the first effect unit 63 and the second effect unit 64 of the movable effect device 58 include the motor (the accessory driving first motor) for operating the first effect member 70 and the second effect member 80. 71, an accessory driving second motor 81) is provided. A cable 652 for supplying signals for controlling these motors and power for driving the motors is connected to the movable effect device 58. In addition, the movable rendering device 58 is provided with a motor position detection sensor (not shown) for detecting the operation state of these motors, and a cable 651 for receiving a sensing result is connected. The cable 652 and the cable 651 extend from the opening 51 b of the center case 51 to the back side of the game board 10 and are connected to the relay board 600. For example, the cable 652 is connected to the connector 602C, and the cable 651 is connected to the connector 602e.

  Furthermore, a cable 653 is connected to transmit the control signal output from the effect control device 550 to a decoration control device 610 (see FIG. 11) for controlling the effect device such as an LED disposed inside the center case 51. The The cable 653 is connected to the relay board 600 on the back side of the game board 10 through an opening 51a provided in the center case 51, and is connected to, for example, a connector 602a.

  FIG. 9 is a block diagram showing a configuration of the gaming machine 1 according to the first embodiment of this invention.

  The gaming machine 1 includes a game control device 500 that controls the game in an integrated manner, an effect control device 550 that controls the display device 53 and the speaker 30 to perform various effects, and a payout motor (not shown) for paying out game balls. A payout control device 580 for controlling is provided.

  First, the configuration of the game control device 500 will be described. The production control device 550 will be described with reference to FIG.

  The game control device 500 includes a game microcomputer 501, an input I / F (Interface) 505, an output I / F (Interface) 506, and an external communication terminal 507.

  The gaming microcomputer 501 includes a CPU 502, a ROM (Read Only Memory) 503, and a RAM (Random Access Memory) 504.

  The CPU 502 is a main control device that controls the game in an integrated manner, and controls the game. The ROM 503 stores invariant information (programs, data, etc.) for game control. The RAM 504 is used as a work area during game control.

  The external communication terminal 507 connects the game control device 500 to an external device such as an inspection device that inspects the setting information of the game control device 500.

  The CPU 502 receives various input devices (start opening SW36d, general winning openings SW44a to 44n, gate SW34a, count SW42d, glass frame opening SW18a, front frame opening SW3a, ball break SW54, vibration sensor 55, and the like via the input I / F 505. In response to the detection signal from the magnetic sensor 56), various processes such as a big hit lottery are performed.

  The start port SW36d is a switch that detects that a game ball has won the start port 36. The general winning ports SW 44 a to 44 n are switches that detect that a game ball has won the general winning port 44.

  The gate SW 34a is a switch that detects that a game ball has passed through the usual start gate 34. The count SW 42d is a switch that detects that a game ball has won a prize winning opening 42.

  The glass frame opening SW 18a is a switch that detects that the glass frame 18 has been opened. The front frame opening SW 3a is a switch for detecting that the front frame 3 is opened.

  The ball cut SW 54 is a switch that detects that the number of game balls stored in the gaming machine 1 and used for payout has become a predetermined number or less.

  The vibration sensor 55 is a sensor that detects vibration applied to the gaming machine 1 and detects an illegal act such as vibrating the gaming machine 1. The magnetic sensor 56 is provided in the vicinity of the second start winning opening, the general winning opening 44, the large winning opening 42, and the normal start gate 34 of the start opening 36, and is a sensor for detecting magnetic force. The magnetic sensor 56 detects a fraud that brings a magnet close to each winning hole and guides the game ball launched to the gaming area 10a to each winning hole.

  In addition, the CPU 502 transmits a command signal to the ordinary / special-purpose display 35, the ordinary electric power SOL 36b, the special winning opening SOL 42b, the payout control device 580, and the effect control device 550 via the output I / F 506, thereby playing the game Overall control.

  As described above, the special figure change display game and the universal figure change display game are executed on the special figure / special figure display unit 35. Furthermore, the number of unprocessed times (special figure start memory number) of the special figure change display game and the number of unprocessed times (standard figure start memory number) of the normal figure change display game are displayed. A general chart start memory including a random number indicating whether or not the special figure fluctuation display game is won and a special figure start memory including a random number indicating whether or not the special figure fluctuation display game is a win are stored.

  The general electric power SOL 36b opens the opening / closing member 36a when the stop display of the general-purpose variable display game becomes a special result mode, thereby making it easy for the game ball to win the start opening 36.

  The special winning opening SOL42b opens the open / close door 42a of the special winning opening 42 when the result of the special figure change display game becomes a special result mode and becomes a special gaming state (a big hit state), and a game ball Is converted to a state where it is easy to win.

  The game control device 500 outputs game machine data from the external information terminal 508 to a game hall management device (not shown) via an information collection terminal device (not shown). The gaming hall management device is a computer that collects and manages gaming data of the gaming machines 1 installed in the gaming hall.

  The payout control device 580 receives, from the game control device 500, a payout command for the number of game balls corresponding to the winning port when the game ball wins the general winning port 44 or the big winning port 42. Further, even when the ball lending button 26 is operated, a payout command for paying out a predetermined number of game balls is received from the game control device 500. The payout control device 580 controls a payout motor (not shown) based on the received payout command, and pays out the number of game balls specified in the payout command.

  The game control device 500 uses a change start command, a customer waiting demo command, a fanfare command, a probability information command, an error designation command, and the like as game data indicating the game situation via the output I / F 506, and the effect control device 550. Send to.

  FIG. 10 is a block diagram illustrating a configuration of the effect control device 550 according to the first embodiment of this invention.

  The effect control device 550 determines the contents of the effect based on the game data input from the game control device 500, controls the display device 53, and controls various effect devices provided in the game board 10 and the front frame 3. To do. The rendering device includes a light emitting device such as an LED and a movable object such as a motor or a solenoid.

  The production control device 550 includes a CPU 551, a control ROM 552, a RAM 553, an image ROM 554, a sound ROM 555, a VDP 556, a sound LSI 557, an input I / F 558b, an output I / F 558a, a power-on detection circuit 559, a first master IC 570a, a second master IC 570b, A NOR gate circuit 561 and a monitoring timer circuit 562 are provided. Further, the effect control device 550 includes a connection terminal 90 connected to the game board 10 and a connection terminal 92 connected to the front frame 3. The functions common to the first master IC 570a and the second master IC 570b will be described simply as “master IC”.

  The CPU 551 receives the command signal transmitted from the game control device 500 as an interrupt signal (INT) as a communication interrupt, and controls various effects based on the input command signal. The CPU 551 receives an interrupt signal (INT) as a master interrupt from the first master IC 570a and the second master IC 570b, and also receives an interrupt signal (INT) as an image update interrupt from the VDP 556. Is done.

  Further, the CPU 551 receives an interrupt signal (INT) as a timeout interrupt also from the monitoring timer circuit 562. The monitoring timer circuit 562 includes a plurality of types of monitoring timers, and outputs an interrupt signal to the CPU 551 when the monitoring timer value set by the CPU 551 is up. When the CPU 551 receives an input of an interrupt signal, the CPU 551 interrupts the process being executed and executes a process corresponding to the input interrupt signal.

  The control ROM 552 stores invariant information (program, data, etc.) for effect control. The RAM 553 is used as a work area during production control.

  The image ROM 554 is connected to the VDP 556 and stores image data displayed on the display device 53. The VDP 556 is a processor that controls image output to the display device 53.

  In addition, the VDP 556 includes a synchronization signal generating unit that generates a synchronization signal that is synchronized with a cycle (33 ms cycle) for updating an image displayed on the display device 53. Every time the synchronization signal is generated, the synchronization signal generation means inputs the generated synchronization signal to the CPU 551 as an interrupt signal.

  The sound ROM 555 is connected to the sound LSI 557 and stores sound data output from the speaker 30 provided in the front frame 3. The sound LSI 557 is a circuit that controls the sound output from the speaker 30.

  The input I / F 558b is an interface that receives information input from the outside via the filters 565a and 565b. Specifically, input of a signal indicating that the effect button 17 provided on the front frame 3 has been operated is received, position information of each motor detected by a motor position detection sensor provided on the game board 10, etc. Or accept input.

  The power-on detection circuit 559 generates a reset signal that initializes the registers of the first master IC 570a and the second master IC 570b to a default state (all 0) when the effect control device 550 is powered on, and generates a NOR gate. Output to the circuit 561.

  Further, the CPU 551 outputs a reset signal to the output I / F 558a via the bus 563 when a predetermined condition is satisfied. The output I / F 558a outputs the input reset signal to the NOR gate circuit 561, and further outputs the reset signal from the NOR gate circuit 561 to the first master IC 570a and the second master IC 570b. The predetermined condition is, for example, a case where an error flag is “ON” in all the decoration control devices 610 (see FIGS. 32 and 33).

  Further, the output I / F 558a outputs a control signal to an effect device (an effect device driven by a movable object such as a motor or a solenoid) provided in the game board 10 or the front frame 3 via the driver 564a and the driver 564b. .

  Note that the reset signal input from the power-on detection circuit 559 to the NOR gate circuit 561 and the reset signal input from the CPU 551 to the NOR gate circuit 561 via the output I / F 558a are in a LOW level state in any case. It functions as a signal for commanding reset at the time. Therefore, if a reset signal is output to the NOR gate circuit 561 from at least one of the power-on detection circuit 559 and the CPU 551, the reset signal is input to the first master IC 570a and the second master IC 570b via the NOR gate circuit 561. .

  FIG. 11 is a block diagram showing the configuration of the first master IC 570a provided in the effect control device 550 and the effect device provided in the game board 10 according to the first embodiment of the present invention.

  The game board 10 includes a relay board 600 connected to the first master IC 570a, a decoration device board 625 connected to the relay board 600, and an auxiliary game device unit 12.

  The relay board 600 transmits (relays) the electrical signal transmitted from the first master IC 570 a to the decoration control device 610 provided in the game board 10. In addition, the relay board 600 has a function of controlling the effect device, similarly to the decoration control device 610, and controls the decoration device board 625 directly connected to the relay board 600.

The decoration device 620 is a light-emitting device that is controlled by an I ² CI / O expander 615 (see FIG. 17) provided in the decoration control device 610 and flashes light when current is applied. It is. The decoration device substrate 625 is a substrate provided on the side lamp 45 (see FIG. 8), and a light emitting device (LED) of the side lamp 45 is mounted thereon. The light emitting device of the side lamp 45 is directly controlled by an I ² CI / O expander 615 provided on the relay board 600.

  The auxiliary gaming device unit 12 includes a decoration device 620 that is a light emitting device such as an LED, a first accessory driving first motor (MOT) 71 that is a movable object, and a second accessory driving second MOT 81. The decoration device 620 in the auxiliary gaming device unit 12 is controlled by the decoration control device 610 included in the auxiliary gaming device unit 12. In the first embodiment of the present invention, the accessory driving first MOT 71 and the accessory driving second MOT 81 are configured to be controlled by the relay board 600, but the auxiliary gaming device unit is similar to the decoration device 620. 12 may be configured to be controlled by a decoration control device 610 included in the control unit 610.

The first accessory driving MOT 71 and the second accessory driving MOT 81 are driving devices that perform an effect operation by rotating when current flows. Since the accessory driving first MOT 71 and the accessory driving second MOT 81 are directly controlled by the driver 564 of the effect control device 550 via the relay board 600, the process of interposing the I ² CI / O expander 615 is not performed. .

  In the first embodiment of the present invention, the accessory driving first MOT 71 and the accessory driving second MOT 81 are included in the movable effect device 58. Specifically, the accessory driving first MOT 71 is the first effect unit 63, The object driving second MOT 81 is included in the second effect unit 64.

  The effect control device 550 controls the first and second effect units driving MOT 71 and second MOT 81 to cause the first effect unit 63 and the second effect unit 64 to perform an effect operation.

The first master IC 570a designates an address individually assigned to the decoration control device 610 that controls the decoration device 620 to be controlled, and outputs the control contents of the decoration device 620 to the decoration control device 610 of the designated individual address. To do. The individual address of the decoration control device 610 is precisely the individual address of the I ² CI / O expander 615 (see FIG. 17) included in the decoration control device 610.

  The first master IC 570a is connected to a relay board (decoration control device) via seven types of connection lines: a connection line SDA, a connection line SCL, a connection line GND, a connection line Vcc, a connection line Vled, a connection line Vms, and a connection line Vse. ) 600. These connection lines are configured by a cable 91 (see FIG. 8) that connects the first master IC 570a and the relay substrate 600.

  Connection line SDA is a connection line for exchanging data signals between effect control device 550 and decoration control device 610, and functions as a data line in the first embodiment of the present invention. The connection line SCL is a connection line for inputting / outputting a clock signal used for data communication on the connection line SDA, and functions as a timing signal line in the first embodiment of the present invention. The connection line GND is a ground of the power supplied by the connection line Vcc, the connection line Vled, the connection line Vms, and the connection line Vse.

  The connection line Vcc is a connection line for supplying logic power to the relay board 600 and the decoration control device 610. The connection line Vled is a connection line for supplying power for causing the LED (decoration device 620) to emit light. The connection line Vms is a connection line for supplying power to the motors and solenoids (specifically, the accessory driving first MOT 71 and the accessory driving second MOT 81) included in the auxiliary gaming device unit 12. The connection line Vse is a connection line for supplying power to various sensors (a state detection sensor that detects the state of the motor included in the rendering device, and specifically corresponds to the motor position detection sensor 560a). is there.

  Between the relay board 600 and the auxiliary gaming device unit 12, seven types of connection lines that connect the effect control device 550 and the relay board 600 are connected. In the first embodiment of the present invention, the motor position detection sensor 560a, the accessory driving first MOT 71, and the accessory driving second MOT 81 are directly controlled by the relay board 600. Therefore, among the seven types of connection lines described above, Five types of connection lines other than the connection line Vms and the connection line Vse are connected to the decoration control device 610 disposed in the uppermost stream of the auxiliary gaming device unit 12. Specifically, a connection line Vcc, a connection line Vled, a connection line SDA, a connection line SCL, and a connection line GND are connected between the relay board 600 and the decoration control device 610.

  When the wiring (cable) shown in FIG. 8 is associated with each connection line, various connection lines (connection line Vcc, connection line Vled, connection line SDA, connection line SCL) delivered from the effect control device 550 to the relay board 600 are provided. , Connection line Vms, connection line Vse, and connection line GND) are included in the cable 91.

  These various connection lines are further branched from the relay board 600 and delivered to another board. The connection line Vcc, the connection line Vled, the connection line SDA, and the connection line SCL branched from the relay board 600 are connected to the cable 653. The connection line Vms is included in the cable 652, and the connection line Vse is included in the cable 651. Further, the connection line GND branched from the relay board 600 is included in all the cables 651 to 653.

  The first master IC 570a and the decoration control device 610 perform two-line bidirectional communication using the connection line SDA and the connection line SCL. The first master IC 570a functions as a (first) signal level control means for controlling each signal level of the connection line SDA and the connection line SCL connected to the decoration control device 610 based on a command from the CPU 551. To do.

  When transmitting data to the relay board 600 and the decoration control device 610, the first master IC 570a first changes the signal level of the connection line SDA from HIGH to LOW while maintaining the signal level of the connection line SCL at HIGH. As a result, a start condition for starting data output to the decoration control device 610 is satisfied (a start condition is issued (output) to the decoration control device 610).

  Thereafter, the first master IC 570a changes the signal level of the connection line SCL to LOW, and sets the signal level of the connection line SDA to the level of the first bit of the transmission data while the signal level of the connection line SCL is LOW. Then, after a predetermined time, the signal level of the connection line SCL is changed from LOW to HIGH. When the signal level of the connection line SCL changes to HIGH, the decoration control device 610 acquires the signal level of the connection line SDA and recognizes it as the first bit of the transmission data. Next, the first master IC 570a returns the signal level of the connection line SCL from HIGH to LOW.

  When this procedure is executed once, 1-bit data is transmitted from the first master IC 570a to the decoration control device 610. Finally, this procedure is repeated 8 times, so that all 8 bits of the transmission data are transferred to the first master. The data is transmitted from the IC 570a to the decoration control device 610 (1 byte of data is transmitted).

  Then, when the data transmission of the last 8 bits is completed, the first master IC 570a releases the connection line SDA and returns a response from the decoration control device 610 when the signal level of the connection line SCL is returned from HIGH to LOW. A reception standby state in which a signal is received is set.

  In the reception standby state, the decoration control device 610 returns a 1-bit response signal (ACK or NACK described later) to the first master IC 570a via the connection line SDA. Next, when the first master IC 570a changes the signal level of the connection line SCL from LOW to HIGH to capture the level of the response signal, and changes the signal level of the connection line SCL from HIGH to LOW after a predetermined time, the decoration control device 610 releases the connection line SDA.

  The first master IC 570a alternately repeats such data transmission for 1 byte (transmission of downlink data) and reception of a response signal for 1 bit (reception of uplink data), and outputs the result to the decoration control device 610. Continue until all the data to be output is output. When the output of data to be output is completed, the first master IC 570a changes the signal level of the connection line SDA from LOW to HIGH while maintaining the signal level of the connection line SCL at HIGH, thereby controlling the decoration. A stop condition for ending data output to the device 610 is established (a stop condition is issued to the decoration control device 610).

  The input buffer 571 is a storage device that temporarily stores data input from the decoration control device 610 via the connection line SDA.

  Specifically, when the first master IC 570a is set to the input mode, the data transmitted from the decoration control device 610 to the first master IC 570a is temporarily removed to the input buffer 571 after the noise is removed by the filter 575a. Is remembered.

  The output buffer 572 temporarily stores data output to the decoration control device 610 via the connection line SDA.

  The reset register (REG) 573 is connected to the bus 563, receives a command from the CPU 551 of the effect control device 550, and outputs a reset signal to the controller 574. The controller 574 comprehensively controls the first master IC 570a and executes various processes.

  The filter 575a removes noise from data input from the connection line SDA. When the driver 576a outputs data from the connection line SDA, the driver 576a applies a voltage at which the transistor 578a can operate to the transistor 578a.

  A predetermined voltage is applied to the connection line SDA by a pull-up resistor R (see FIG. 21), and the connection line SDA is connected to the filter 575a and the transistor 578a.

  As the transistor 578a, a field effect transistor (FET) is used in order to suppress power consumption. The gate of the transistor 578a is connected to the driver 576a, the drain is connected to the connection line SDA to which a predetermined voltage is applied by the pull-up resistor R, and the source is grounded.

  If the voltage applied to the gate of the transistor 578a is smaller than a predetermined value for operating the transistor 578a, no current flows between the drain and the source, so that the voltage applied to the connection line SDA does not drop, and as a result The connection line SDA becomes HIGH level. On the other hand, if the voltage applied to the gate of the transistor 578a is equal to or higher than a predetermined value for operating the transistor 578a, a current flows from the drain to which the voltage of the predetermined value is applied to the grounded source. As a result, the connection line SDA becomes LOW level.

Note that the transistor 578a has a specification that does not break even when a current of about 10 milliamperes flows from the drain to the source. For this reason, it is possible to pass a current of about 10 milliamperes, which is much larger than the current value used when using a normal I ² C bus, to the connection line SDA, and the effect control device 550 and the decoration control device 610 The data transmission between them is configured to withstand failures due to noise.

  When the driver 576a outputs data from the connection line SDA, the driver 576a applies a voltage having a value at which the transistor 578a can operate to the gate of the transistor 578a so that a current flows between the drain and the source of the transistor 578a. Then, the driver 576a outputs data from the connection line SDA by setting the voltage of the connection line SDA to the HIGH level or the LOW level.

  Further, the filter 575b removes noise from data input from the connection line SCL. When the driver 576b outputs data from the connection line SCL, the driver 576b applies a voltage at which the transistor 578b can operate to the transistor 578b.

  A predetermined voltage is applied to the connection line SCL by the pull-up resistor R (see FIG. 21), and the connection line SCL is connected to the filter 575b and the transistor 578b.

  A field effect transistor (FET) is used as the transistor 578b in order to reduce power consumption. The gate of the transistor 578b is connected to the driver 576b, the drain is connected to the connection line SCL to which a predetermined voltage is applied by the pull-up resistor R, and the source is grounded.

  If the voltage applied to the gate of the transistor 578b is smaller than a predetermined value for operating the transistor 578b, no current flows between the drain and the source, so that the voltage applied to the connection line SCL does not drop, and as a result The connection line SCL becomes HIGH level. On the other hand, if the voltage applied to the gate of the transistor 578b is equal to or higher than a predetermined value for operating the transistor 578b, a current flows from the drain to which the predetermined voltage is applied to the grounded source, whereby the connection line SCL As a result, the connection line SCL becomes the LOW level.

Note that the transistor 578b has a specification that does not break even when a current of about 10 milliamperes flows from the drain to the source. Therefore, a current of about 10 milliamperes, which is much larger than the current value used when using a normal I ² C bus, can be passed through the connection line SCL, and between the effect control device 550 and the decoration control device 610. The data transmission is configured to withstand failures due to noise.

  When the driver 576b outputs a clock signal from the connection line SCL, the driver 576b applies a voltage having a value at which the transistor 578b can operate to the gate of the transistor 578b so that a current flows between the drain and the source of the transistor 578b. Then, the driver 576b outputs a clock signal from the connection line SCL by repeatedly changing the voltage of the connection line SCL between a HIGH level and a LOW level.

  The power-on reset circuit 577 defaults storage areas such as the input buffer 571 and the output buffer 572 when the first master IC 570a is powered on and the voltage in the power-on reset circuit 577 reaches a predetermined value. A reset signal for setting the state is output to the controller 574. The power-on reset circuit 577 may be provided outside the first master IC 570a and shared with the second master IC 570b described later.

  The command register (REG) 581 is a register for receiving a command from the CPU 551 of the effect control device 550. In the first embodiment of the present invention, each bit of STA, STO, SI, and MODE is pre-assigned to the command register 581, and “0” or “1” is individually set for each bit by the CPU 551. It can be set.

  The STA is a bit for the first master IC 570a to instruct the decoration control device 610 to be controlled to output a start condition (start condition). When “1” is set in the STA, the first master IC 570a issues (outputs) a start condition to the decoration control device 610 to be controlled to establish the start condition.

  The STO is a bit for the first master IC 570a to instruct the decoration control device 610 to be controlled to output a stop condition (stop condition). When “1” is set in the STO, the first master IC 570a issues (outputs) a stop condition to the decoration control device 610 to be controlled to establish the stop condition.

  SI is a bit that is set when an interrupt is generated in the effect control device 550 from the first master IC 570a. When an interrupt is generated from the first master IC 570 a to the CPU 551, “1” is set to SI by the controller 574 and an interrupt signal (INT) is input to the CPU 551. Thereafter, while the SI is set to “1”, the first master IC 570a suspends processing. However, when the CPU 551 sets SI to “0”, the first master IC 570a interrupts. Suspend and resume processing.

  MODE is a bit for designating a mode for transmitting data, and “buffer mode” is designated when “1” is set, and “byte mode” is designated when “0” is set. . The buffer mode is a mode for transmitting a plurality of continuous bytes of data at a time and transmitting a maximum of 68 bytes of data. The byte mode is a mode in which only one byte of data can be transmitted in one transmission, and is used for data transmission / reception in units of bytes.

  The status register (REG) 582 stores information indicating the status of the first master IC 570a. “0” is always set in the lower 2 bits, and the status code is set in the upper 5 bits.

  The own address setting register (REG) 583 is a register that is set when the first master IC 570a functions as a slave (decoration control device). A commercially available master IC usually has a function as a master and a function as a slave, and is used according to the application. In the own address setting REG 583, an address for specifying itself when the first master IC 570a functions as a slave is set.

  FIG. 12 is a block diagram showing the configuration of the second master IC 570b provided in the effect control device 550 and the effect device provided in the front frame 3 according to the first embodiment of the present invention.

  The front frame 3 includes a simple relay board 1600 connected to the second master IC 570b, a decoration control device 610 connected to the simple relay board 1600, a speaker 30, a motor position detection sensor 560b, an illumination drive first MOT 13a, and an illumination drive first. 2MOT 14a and the like are included.

The simple relay board 1600 transmits (relays) the electrical signal transmitted from the second master IC 570 b to the decoration control device 610 provided in the front frame 3. Unlike the relay board 600, the simple relay board 1600 does not include the I ² CI / O expander 615. Therefore, the electronic component provided in the simple relay board 1600 includes arithmetic processing for controlling the effect device. Does not have a function to execute. Therefore, since the illumination driving first MOT 13a and the illumination driving second MOT 14a that are directly connected to the simple relay board 1600 cannot be controlled by their own judgment, the simple relay board 1600 receives the electric signal received from the second master IC 570b. Thus, it plays a role of relaying to the illumination driving first MOT 13a and the illumination driving second MOT 14a.

  The illumination drive first MOT 13a and the illumination drive second MOT 14a drive the light emitting member provided inside based on the signal transmitted from the effect control device 550, and execute various effects.

  In addition, the effect control device 550 receives a signal indicating that the effect button 17 has been operated from the effect button 17 via the simple relay board 1600. Further, the position information of the illumination drive first MOT 13 a and the illumination drive second MOT 14 a detected by the motor position detection sensor 560 b is input via the simple relay board 1600.

  Further, the simple relay board 1600 receives a signal from the sound LSI 557 of the effect control device 550 and outputs it from the speaker 30.

  Since the configuration of the second master IC 570b is the same as that of the first master IC 570a, the same reference numeral is assigned to each configuration of the second master IC 570b, and description thereof is omitted. Similarly to the first master IC 570a, the second master IC 570b controls the signal levels of the connection line SDA and the connection line SCL connected to the decoration control device 610 based on a command from the CPU 551 ( It functions as a second) signal level control means.

  The connection method between the effect control device 550 and the relay board 600 and the connection method between the relay board 600 and the decoration control device 610 other than the relay board 600 will be described in detail later with reference to FIGS. The configuration of the relay board 600 and the decoration control device 610 will be described in detail later with reference to FIGS.

  The decoration control device 610 is mainly attached to the game board 10 and the front frame 3. The decoration device (LED) 620 controlled by the decoration control device 610 attached to the front frame 3 irradiates the decoration members 9a and 9b, the illumination unit 11, and the abnormality notification LED 29. On the other hand, the decoration control device 610 attached to the game board 10 is included in the auxiliary game device unit 12 configured by integrating the center case 51, the display device 53, and the effect control device 550.

  In FIG. 13, a configuration and connection form of the decoration control device 610 included in the relay board 600 and the auxiliary game device unit 12 provided in the game board 10 will be described. In FIG. 14, configurations and connection forms of the simple relay board 1600 and the decoration control device 610 provided in the front frame 3 will be described.

  FIG. 13 is a diagram illustrating a configuration of the game board 10 according to the first embodiment of this invention.

  As described above, the center case 51 constituting the auxiliary gaming device unit 12 is configured by combining the frame decoration portion 65 and the frame base portion 60.

  The frame decoration unit 65 is provided with a plurality of effect devices for performing auxiliary games such as a variable display game, and a decoration control device 610 for controlling the effect devices. These decoration control devices 610 are connected to each other by a predetermined signal cable, and the effect device controlled by the decoration control device 610 is also connected by a cable, whereby the frame decoration portion 65 is integrally configured.

  The frame base 60 is also provided with a plurality of effect devices for performing an auxiliary game such as a variable display game, and a plurality of decoration control devices 610 for controlling the effect devices. By connecting these decoration control devices 610 to each other by a predetermined signal cable, and also connecting the effect device controlled by the decoration control device 610 with a cable, the frame base 60 is integrally configured.

  Therefore, the frame decoration part 65 and the frame base 60 constitute an integrated production unit in the present embodiment. On the other hand, since the side lamps 45 and the like are single production devices that are not included in the integrated production unit, they constitute a separate production device.

  Note that not all of the effect devices included in the auxiliary gaming device unit 12 need be controlled by the decoration control device 610 inside the auxiliary gaming device unit 12. For example, in the first embodiment of the present invention, the movable object arranged in the center case 51 is directly controlled by the effect control device 550 via the relay board 600.

As described above, the decoration control device 610 includes the I ² CI / O expander 615 for controlling the decoration device 620, and the I ² CI / O expander 615 includes individual I ² CI / O expanders. An individual address for identifying the expander 615 is assigned. In the first embodiment of the present invention, the individual address of the I ² CI / O expander 615 is used as the individual address of the decoration control device 610 as described above.

The effect control device 550 can perform the effect operation by individually controlling the decoration device 620 by specifying the individual address of the I ² CI / O expander 615 and transmitting the control signal. In principle, different individual addresses (indicated by “ad =” in the figure) are assigned to the respective decoration control devices 610.

  Further, the decoration control device 610 is classified into three types according to a connection form: a branch type (branch substrate), a connection type (connection substrate), and a termination type (termination substrate). The decoration device 620 can be connected to any one of the branch type, the connection type, and the terminal type decoration control device 610, and the connected decoration device 620 can be controlled.

  In the branch type decoration control device 610, a plurality of decoration control devices 610 are directly connected to the downstream side, and the received control signals are transmitted to the plurality of decoration control devices 610. The connected decoration control device 610 is connected to one decoration control device 610 on the downstream side, and transmits the received control signal to the connected decoration control device 610. The terminal-type decoration control device 610 does not connect the decoration control device 610 on the downstream side, and only controls the decoration device 620. Details of the branch type, connected type, and terminal type decoration control device 610 will be described later with reference to FIG.

  The upstream side refers to the side that transmits the electrical signal in the configuration in which the electrical signal is transmitted from the effect control device 550 to the terminal decoration control device 610 through the decoration control device 610 on the way. On the other hand, the downstream side is the side that receives this electrical signal.

  That is, when the signal cable from the effect control device 550 to the end decoration control device 610 is sequentially traced, the decoration control device 610 connected to the side closer to the effect control device 550 becomes the upstream side, and the decoration at the end is further increased. The decoration control device 610 connected to the side closer to the control device 610 is on the downstream side. For example, the decoration control devices 610A and 610C are arranged on the upstream side of the decoration control device 610H, and the decoration control devices 610I and 610J are arranged on the downstream side of the decoration control device 610H.

  Here, in the first embodiment of the present invention, as described above, the decoration control device 610 is arranged on the movable parts of the first effect member 70 and the second effect member 80 that constitute the movable effect device 58. . In other words, in FIG. 6, the decoration control device 610 (first light emitting substrate 106) is disposed on the movable part (first effect base 100) of the first effect member 70, and in FIG. 7, the movable part of the second effect member 80. The decoration control device 610 (second light emitting substrate 116) is disposed on the (second effect base 110).

  At this time, if each decoration control device 610 is wired in a daisy chain as in the conventional shift register, only one of the decoration control devices 610 at the end of the daisy chain is connected to an input cable. That's it. However, it is necessary to connect an input cable and an output cable to the other decoration control device 610 configured to be connected in the middle of the daisy chain. When a plurality of cables are connected to the movable part, the decoration control device 610 (the first light emitting board 106 and the second light emitting board 116) itself moves together with the movable part, and the cable also moves. It can be difficult. Furthermore, the movement of the cable may cause a disconnection of the connection line constituting the cable, which may affect the production.

  In the first embodiment of the present invention, the decoration control device 610 disposed in the first effect member 70 and the second effect member 80 is a terminal type, and a branch type decoration control device is provided upstream of these decoration control devices 610. 610 is arranged. Therefore, the terminal-type decoration control device 610 (the first light-emitting board 106 and the second light-emitting board 116) sends a signal to the other decoration control devices 610 provided outside the first effect member 70 and the second effect member 80. The structure is such that the transmitting cable is not connected. If the decoration control device 610 is arranged in this way, only the input cable needs to be connected to the decoration control device 610 arranged in the movable part. Therefore, the wiring can be easily routed and the possibility of disconnection can be reduced as compared with the case of wiring by daisy chain.

  When the destination address of the received control signal is not addressed to itself, the decoration control device 610 transmits the received control signal if the decoration control device 610 is further connected to the downstream side. If there is no transmission destination, the received control signal is discarded.

The decoration control device 610 can control the LEDs corresponding to the 16 ports. The decoration control device 610 includes an LED mounted on the decoration control device 610 and an external decoration device substrate 625 connected to the decoration control device 610. If the total number of mounted LEDs is 16 or less, both LEDs can be controlled. In other words, in the integrated decoration control device 610 (corresponding to the main active substrate on which both the I ² CI / O expander 615 and the decoration device 620 are arranged), the decoration device substrate 625 (the I ² CI / O expander 615 is arranged). In addition, it is possible to control both the decoration device 620 provided inside and the decoration device 620 connected to the outside by further connecting a driven substrate on which the decoration device 620 is disposed.

  By doing so, it is possible to control the decoration devices 620 arranged at a distance by one decoration control device 610, and the number of decoration control devices 610 can be minimized.

The relay board 600 is connected to the first master IC 570a mounted on the effect control device 550 on the upstream side, and receives a control signal transmitted from the first master IC 570a. Further, on the downstream side, it is connected to a decoration control device 610A included in the auxiliary gaming device unit 12 (more precisely, a decoration control device 610A included in the frame base 60 which is an integrated production unit). Further, the relay board 600 is connected to a decoration device board 625 (a board provided on the side lamp 45 (see FIG. 8)) which is a separation type effect device provided in the game board 10, and is provided in the relay board 600. The decoration device 620 mounted on the decoration device substrate 625 is controlled by the I ² CI / O expander 615.

  The auxiliary gaming device unit 12 includes decoration control devices 610A to 610J. The decoration control device 610A is a branch type decoration control device, and transmits the control signal received from the first master IC 570a to the decoration control device 610B and the decoration control device 610C. In addition, a decoration device substrate 625B is connected to the decoration control device 610B, and an effect device (decoration device 620) such as an LED disposed on the decoration device substrate 625B is controlled by the decoration control device 610B.

  The decoration control device 610C is a branch type decoration control device 610, and transmits the received control signal to the decoration control device 610D and the decoration control device 610H on the downstream side. The decoration control device 610D is connected to a branch type decoration control device 610E, and further controls the decoration device 620D included in the decoration device substrate 625D.

  The decoration control device 610E is connected to a decoration control device 610F that controls the first effect member 70 and a decoration control device 610G that controls the second effect member 80. The first effect member 70 and the second effect member 80 perform an effect operation in conjunction with each other. The decoration control device 610F is disposed on the first light emitting substrate 106 included in the first effect member 70 (FIG. 6), and the decoration control device 610G is disposed on the second light emitting substrate 116 included in the second effect member 80. (FIG. 7).

  The first light emitting substrate 106 itself may function as the decoration control device 610F, and the second light emitting substrate 116 itself may function as the decoration control device 610G.

  In the first embodiment of the present invention, the decoration control device 610F controls the LEDs included in the first effect member 70, and the decoration control device 610G controls the LEDs included in the second effect member 80. Note that the accessory driving first MOT 71 and the accessory driving second MOT 81 for outputting the driving force for moving the first effect member 70 and the second effect member 80 to the front of the display unit 53a are controlled by the relay board 600. Is done.

  The effect control device 550 controls the first effect unit 63 (the first effect member 70) and the second effect unit 64 (the second effect member 80) when the predetermined condition is satisfied, such as when the variable display game is executed. Perform the action. Specifically, in order to control the accessory driving first MOT 71 included in the first effect unit 63 and the accessory driving second MOT 81 included in the second effect unit 64, the individual address (“0000”) of the relay board 600 is set. Designate and send control signals to operate these motors. Furthermore, a control signal for controlling a light emitting device such as an LED included in the first effect member 70 is transmitted by designating the individual address (“0110”) of the decoration control device 610F for controlling the first effect member 70. Similarly, a control signal for controlling a light emitting device such as an LED included in the second effect member 80 is transmitted by designating the individual address (“0111”) of the decoration control device 610G for controlling the second effect member 80. After that, issue a stop condition.

  The decoration control device 610H is a connection type decoration control device 610, and is further connected to a connection type decoration control device 610I and a terminal type decoration control device 610J. The terminal-type decoration control device 610J controls the decoration device 620J included in the decoration device substrate 625J.

  In the first embodiment of the present invention, the decoration control device 610H and the decoration control device 610I control an effect device (LED) included in the reliability notification device 15. When the predetermined condition is satisfied, a control signal for indicating a predetermined mode is transmitted from the first master IC 570a of the production control device 550, and the production is performed in the designated mode.

  FIG. 14 is a diagram illustrating a configuration of the front frame 3 according to the first embodiment of this invention.

  The gaming machine 1 according to the first embodiment of the present invention has a plurality of specifications, and there are a normal version gaming machine 1 and an inexpensive version gaming machine 1. The normal version gaming machine 1 includes a front frame 3 (hereinafter, referred to as a normal version front frame 3) having a standard decorative member. The low-priced gaming machine 1 includes a front frame 3 (hereinafter referred to as a low-priced front frame 3 ') that includes a decorative member configured at a lower cost than a standard decorative member. The upper side of FIG. 14 shows the configuration of the normal version front frame 3, and the lower side shows the configuration of the inexpensive version front frame 3 ′. In the gaming machine 1, only the front frame 3 of one of the specifications is shown. Is attached and connected to the production control device 550, so that only one of the normal plate front frame 3 and the inexpensive plate front frame 3 ′ is connected to the second master IC 570b.

  The normal plate front frame 3 and the inexpensive plate front frame 3 ′ are different in the number of decoration devices 620 included in the decoration members 9 a and 9 b, and also in the number of decoration control devices 610 that control the decoration device 620. Specifically, the decoration members 9a and 9b of the normal plate front frame 3 are controlled by seven decoration control devices 610, and the decoration members 9a 'and 9b' of the inexpensive plate front frame 3 'are controlled by five decoration control devices 610. Is done. Since the decorative members 9a and 9b irradiate with more LEDs than the decorative members 9a ′ and 9b ′, the normal plate front frame 3 becomes brighter than the inexpensive plate front frame 3 ′, which increases the variation of executable effects. It is also possible. Therefore, the control of the decoration device 620 when the normal plate front frame 3 is attached is different from the control of the decoration device 620 when the inexpensive plate front frame 3 ′ is attached.

  For this reason, when the same address is assigned to the individual address of the decoration control device 610 attached to the normal plate front frame 3 and the individual address of the decoration control device 610 attached to the inexpensive plate front frame 3 ′, the effect control device 550 Since the production control data to be transmitted to the decoration control device 610 needs to be different between the case of the normal version front frame 3 and the case of the inexpensive version front frame 3 ′, it is usually determined according to the front frame 3 attached to the gaming machine 1. The production control device 550 for the plate and the production control device 550 for the low cost version must be prepared. Therefore, when the manufacturer ships the gaming machine 1, the production control device 550 for the normal version and the production control device 550 for the low-priced version must be prepared, resulting in an increase in manufacturing cost.

  Therefore, in the first embodiment of the present invention, different addresses are assigned to the individual addresses of the decoration control device 610 whose control is different between the normal version front frame 3 and the low price version front frame 3 ′. The effect control data to be transmitted to the decoration control device 610 is configured so as to be common to the case of the normal version front frame 3 and the case of the low cost version front frame 3 ′, so that one effect control device 550 is used for the normal version. And control for the low cost version can be executed. By doing so, it is not necessary to prepare the production control device 550 for the normal version and the production control device 550 for the low-priced version, and the manufacturing cost can be suppressed. In the first embodiment of the present invention, the game board 10 has the same configuration regardless of whether it is a normal version or a low-priced version.

  Hereinafter, the configurations of the normal plate front frame 3 and the inexpensive plate front frame 3 'will be described in detail.

  The normal plate front frame 3 includes a simple relay board 1600 connected to the second master IC 570b. A branch type decoration control device 610K and illumination drive motors (13a, 14a) are connected to the simple relay board 1600.

  The decoration control device 610K is arranged in the lighting unit 11 and controls the decoration device 620 provided on the decoration device substrate 625K. Specifically, the LED included in the illumination unit 11 and the abnormality notification LED 29 are controlled.

  The decoration control device 610K is a branch type decoration control device, and transmits the received control signal to the decoration control device 610L and the decoration control device 610P. The decoration control devices 610 </ b> L to 610 </ b> N control the decoration member 9 a on the left side portion of the normal plate front frame 3. Further, the decoration control devices 610P to 610R control the decoration member 9b on the right side portion of the normal plate front frame 3.

  The decoration member 9a on the left side portion of the normal plate front frame 3 includes connection type decoration control devices 610L and 610M and a terminal type decoration control device 610N. The decoration control device 610L receives the control signal transmitted from the second master IC 570b of the effect control device 550 from the decoration control device 610K and transmits it to the decoration control devices 610M and 610N.

  As described above, the decoration member 9b on the right side portion of the normal plate front frame 3 includes the connection type decoration control devices 610P and 610Q and the terminal type decoration control device 610R. The decoration control device 610P receives the control signal transmitted from the second master IC 570b of the effect control device 550 from the decoration control device 610K and transmits the control signal to the decoration control devices 610Q and 610R.

  Also, different individual addresses are assigned to the decoration control devices 610L to 610R included in the decoration member 9a and the decoration member 9b, and different rendering operations are performed based on the control signals transmitted from the second master IC 570b. Can be executed. Specifically, “0000” is used for the individual address of the decoration control device 610K included in the lighting unit 11, and “0001” “0010” is used for the individual addresses of the decoration control devices 610L, 610M, and 610N included in the decoration member 9a. “001”, “0100”, “0101”, and “0110” are assigned to the individual addresses of the decoration control devices 610P, 610Q, and 610R included in the decoration member 9b.

  On the other hand, the low-priced front frame 3 ′ is similar to the normal plate front frame 3 in that the simple relay board 1600 connected to the second master IC 570 b and a board having substantially the same function (hereinafter referred to as the low-priced simple relay board 1600). 'And). However, in the low-priced front frame 3 ′, only the branch type decoration control device 610 </ b> S is connected to the simple relay board 1600 ′, and the cost is reduced without the illumination drive motor (13 a, 14 a).

  The decoration control device 610S is disposed in the lighting unit 11, and controls the decoration device 620 provided on the decoration device substrate 625S. Specifically, the LED included in the illumination unit 11, the abnormality notification LED 29, and the like are controlled and are the same as those of the normal plate front frame 3. The decoration control device 610S is the same substrate as the decoration control device 610K that controls the illumination unit 11 of the normal plate front frame 3, and is assigned the same individual address (“0000”). Therefore, the same control is executed in the decoration control device 610K of the normal plate front frame 3 and the decoration control device 610S of the inexpensive plate front frame 3 '.

  The decoration control device 610S is a branch type decoration control device, and transmits the received control signal to the decoration control device 610T and the decoration control device 610V. The decoration control devices 610T and 610U control the decoration member 9a 'on the left side portion of the normal plate front frame 3. Further, the decoration control devices 610V and 610W control the decoration member 9b 'on the right side portion of the normal plate front frame 3.

  Further, in the inexpensive plate front frame 3 ', decoration control devices 610T and 610U for controlling the left decoration member 9a' and decoration control devices 610V and 610W for controlling the right decoration member 9b 'are attached. The decoration control device 610T is the same substrate as the decoration control device 610L of the normal plate front frame 3, and is assigned the same individual address (“0001”). Similarly, the decoration control device 610V is the same substrate as the decoration control device 610P of the normal plate front frame 3, and is assigned the same individual address (“0001”). Therefore, the same control is executed in the decoration control device 610L of the normal plate front frame 3 and the decoration control device 610T of the inexpensive plate front frame 3 ′, and the decoration control device 610P of the normal plate front frame 3 and the inexpensive plate front frame 3 are controlled. In the 'decoration control device 610V, the same control is executed.

  The same individual address (“0111”) is assigned to the decoration control devices 610U and 610W. Therefore, in the low-price front frame 3 ′, the same control is executed by the decoration control devices 610 </ b> U and 610 </ b> W with the left and right decoration members, that is, the irradiation with the LED to be controlled is executed at the same timing. In addition, the decoration control devices 610U and 610W are assigned individual addresses that are not assigned to the decoration control device 610 of the normal front frame 3.

The decoration control device included in the decoration members 9a, 9b, 9a ′, and 9b ′ is used from the effect control device 550 regardless of whether the normal version front frame 3 or the inexpensive plate front frame 3 ′ is used. Production control data is transmitted to all individual addresses assigned to the I ² CI / O expander 615 of 610.

  As described above, the low price front frame 3 'corresponds to the decoration control devices 610M, 610N, 610Q and 610R (first specification-dependent group unit control means) among the decoration control devices provided. Instead, decoration control devices 610U and 610W (second specification-dependent group unit control means) are attached. The normal plate front frame 3 is equipped with decoration control devices 610M, 610N, 610Q and 610R (first specification-dependent group unit control means), whereas the inexpensive plate front frame 3 ′ has fewer. A number of decoration control devices 610U and 610W (second specification-dependent group unit control means) are attached.

  The decoration control device 610K and the decoration control device 610S, the decoration control device 610L and the decoration control device 610T, and the decoration control device 610V and the decoration control device 610P are common to the normal plate front frame 3 and the inexpensive plate front frame 3 ′. It is configured as a usable substrate.

  Therefore, the production control device 550 according to the first embodiment of the present invention can share the control for the normal version and the control for the inexpensive version, and there is no need to change the control for each front frame. The manufacturing cost of the production control device 550 can be reduced.

  In the following description, unless otherwise specified, it is assumed that the normal version front frame is attached to the gaming machine 1 according to the first embodiment of the present invention.

In the low price front frame 3 ′, the I ² CI / O expander 615 with individual addresses “0010”, “0011”, “0101”, and “0110” is not used. The I ² CI / O expander 615 with the individual address “0111” is not used. Therefore, in any front frame 3, there is an unconnected I ² CI / O expander 615 in the abnormality determination table 3300 (see FIG. 33). However, as will be described later, if data is normally transmitted between at least one I ² CI / O expander 615 registered in the abnormality determination table 3300 and the second master IC 570b, Since it is determined to be operating, the process is not interrupted due to this.

  FIG. 15 is a diagram illustrating a connection state between the effect control device 550 and the relay board 600 and the decoration control device 610 included in the game board 10 according to the first embodiment of this invention.

  In FIG. 15, connection of the effect control device 550, the relay board 600, and the decoration control devices 610A, 610B, and 610C will be described. For convenience of explanation, description of the decoration control device 610 is omitted for one relay board 600 and each decoration control device (610D to 610J) connected downstream from the decoration control device 610C. The connection between the decoration control devices 610 is the same.

  The production control device 550 includes a connection line Vcc, a connection line Vled, a connection line SDA, a connection line SCL, a connection line GND, connection lines M11 to M14, connection lines M21 to M24, connection lines M31 to M34, a connection line SL1, and a connection line. The relay board 600 is connected by SL2, the connection lines SE1 to 3, the connection line Vms, and the connection line Vse.

  The connection line Vcc, the connection line Vled, the connection line SDA, the connection line SCL, the connection line GND, the connection line Vms, and the connection line Vse are as described in FIG.

  Signals for controlling the first to fourth phases of the accessory driving first MOT 71 included in the first effect unit 63 are transmitted to the connection lines M11 to M14. Signals for controlling the first to fourth phases of the accessory driving second MOT 81 included in the second effect unit 64 are transmitted to the connection lines M21 to M24. The accessory driving first MOT 71 and the accessory driving second MOT 81 use a four-phase driving stepping motor.

  The connection lines M31 to M34 are connection lines for controlling the motor. However, in the first embodiment of the present invention, since the motor corresponding to the relay board 600 is not connected, an empty terminal monitor that displays the connection state. 603 is connected. The vacant terminal monitor 603 includes four LEDs corresponding to the connection lines M31 to M34, and can check whether or not each connection line is disconnected. Therefore, when some or all of the connection lines are disconnected, a part of the vacant terminal monitor 603 is not lit, so that it can be determined that the quality of the cable is bad.

  In particular, as in the gaming machine 1 according to the first embodiment of the present invention, the cable 91 that connects the first master IC 570a and the relay board 600 has a connection line GND, a connection line Vcc, The connection line Vled, the connection line Vms, and the connection line Vse are included (see FIG. 11 or FIG. 15). These wires for supplying electric power are originally used as cables having a large (thick) cross-sectional area that can secure a sufficient amount of current in order to realize a stable operation.

  However, when a flat cable such as the cable 91 is used, the cross-sectional area of each cable needs to be the same (common) because of the connection of the connectors. Therefore, it is conceivable to supply power using a plurality of connection lines instead of a cable having a large cross-sectional area. For example, six cables are used as the connection lines GND and three cables are used as the connection lines Vms. A configuration such as use can be realized.

  At this time, even if a part of the connection line for supplying power is disconnected, if all the connection lines are not disconnected, it will operate without any problem, so that the LED is turned on, Although it is possible to drive the motor, there is a possibility that abnormal heat generation may occur on the cable because a sufficient amount of current cannot be secured. In such a case, by connecting a power supply line to the vacant terminal monitor 603, a cable with inferior quality such that some of the connection lines are disconnected even though it seems to be operating normally at first glance is discovered. It is possible to perform replacement or perform necessary maintenance before a failure occurs.

  In addition, the relay board 600 supplies the electric power supplied from the connection line Vms to each motor in order to drive the accessory driving motor (the accessory driving first MOT 71, the accessory driving second MOT 81). The electric power supplied to the accessory driving solenoid for moving the decoration piece 46 up and down is also supplied from the connection line Vms.

  The relay board 600 is connected to a motor position detection sensor 560a for detecting the rotational position of the accessory driving motor. Connection lines SE1 to SE3 are connection lines for receiving the detection result by the motor position detection sensor 560, and the relay board 600 indicates the rotation position of the accessory driving motor detected by the motor position detection sensor 560a. It transmits to production control device 550 via SE1-3.

  The connection line SL1 and the connection line SL2 are connection lines for controlling the accessory driving solenoid. When the accessory driving solenoid is not used, the connection line SL1 and the connection line SL2 are also connected to the vacant terminal monitor 603 for displaying the connection state, similarly to the connection lines M31 to M34 described above.

  The decoration control device 610 including the relay board 600 includes a connection line Vcc, a connection line Vled, a connection line SDA, a connection line SCL, and a connection line GND (hereinafter, a bundle of these five types of connection lines is referred to as one harness). Are connected to each other.

  In addition, a decoration control device 610B and a decoration control device 610C are connected to the decoration control device 610A via a harness, and a decoration control device 610D (not shown) is connected to the decoration control device 610C via a harness.

  Each decoration control device 610 includes a connector serving as an attachment port for connecting the harness to itself. Since this connector is common to each decoration control device 610, the connection order of each connection line is common, and erroneous wiring can be prevented.

  FIG. 16 is a diagram illustrating a connection state between the effect control device 550 according to the first embodiment of this invention, the simple relay board 1600 and the decoration control device 610 included in the normal plate front frame 3.

  In FIG. 16, connection of the effect control device 550, the simple relay board 1600, and the decoration control devices 610K, 610L, and 610P will be described. For convenience of explanation, the description of the decoration control devices 610L and the decoration control devices connected downstream of the decoration control device 610P will be omitted.

  The production control device 550 includes a connection line Vcc, a connection line Vled, a connection line SDA, a connection line SCL, a connection line GND, connection lines M11 to M14, connection lines M21 to M24, connection lines M31 to M34, a connection line SL1, and a connection line. In addition to the SL2, the connection lines SE1 to 3, the connection line Vms, and the connection line Vse, the connection line that receives the button signal from the effect button 17 and the connection line that transmits the sound signal to the speaker 30 are connected to the simple relay board 1600. The

  For the connection line Vcc, the connection line Vled, the connection line SDA, the connection line SCL, the connection line GND, the connection line Vms, and the connection line Vse, as described with reference to FIG. 15, the effect control device 550 and the game board 10 are connected. Similar to the case of connection, various signals are transmitted to and received from each decoration control device 610 arranged on the downstream side.

  Signals for controlling the illumination driving first MOT 13a of the first movable illumination 13 included in the illumination unit 11 are transmitted to the connection lines M11 to M14. Signals for controlling the illumination drive second MOT 14a of the second movable illumination 14 included in the illumination unit 11 are transmitted to the connection lines M21 to M24.

  The connection lines M31 to M34 are connection lines for controlling the motor. However, in the first embodiment of the present invention, the corresponding motor is not connected to the simple relay board 1600. An empty terminal monitor 603 for displaying the connection state is connected.

  Further, in order to drive the illumination drive motor (the illumination drive first MOT 13a and the illumination drive second MOT 14a), the electric power supplied from the connection line Vms is supplied to each motor.

  The simple relay board 1600 is connected to a motor position detection sensor 560b for detecting the rotation position of the illumination drive motor. The simple relay board 1600 transmits the rotation position of the illumination drive motor detected by the motor position detection sensor 560b to the effect control device 550 via the connection lines SE1 to SE3.

Here, a method in which the I ² CI / O expander 615 (described later in FIG. 18) provided in the decoration control device 610 controls the decoration device 620 will be described.

The effect control device 550 determines the output mode of the effect device (decoration device 620) based on the game data input from the game control device 500. Then, the production control device 550 produces production control data (production control) including the individual address of the decoration control device 610 to be controlled (the individual address of the I ² CI / O expander 615) so that the determined output mode is obtained. Information) is output to the relay board 600. At this time, the effect control data is output from the relay board 600 to all the decoration control devices 610 to be controlled through the connection line SDA.

  In the first embodiment of the present invention, the rendering device controlled by the decoration control device 610 is mainly a light emitting device such as an LED, and therefore the light emission mode of the LED corresponds to the output mode of the rendering device. In this case, lighting / flashing / extinguishing of the LED is instructed by the effect control data, and further, the flashing cycle and the lighting brightness of the LED are also instructed.

Each decoration control device 610 is previously set with a unique individual address as described above. When the presentation control data is input, the address included in the input presentation control data and the set individual address It is determined whether or not. If it is determined that the address included in the input effect control data matches the set individual address, the I ² CI / O expander 615 of the decoration control device 610 captures the effect control data. Thus, the output mode of the corresponding decoration device 620 is controlled, and a response signal is output to the master IC (first master IC 570a, second master IC 570b) immediately after the 8th bit data is input.

  As described above, the master IC transmits the effect control data to all the decoration control devices 610 connected to the master IC, and requested in the decoration control device 610 corresponding to the individual address included in the effect control data. The rendering device can be controlled so as to be in the output mode.

Each decoration control device 610 is set with a reset address for initializing the I ² CI / O expander 615 of the decoration control device 610 in addition to the individual address. This reset address is an address provided in common to all the I ² CI / O expanders 615 and cannot be used as an individual address. The reset address value cannot be changed (details will be described later).

When the effect control device 550 initializes the decoration control device 610 (more precisely, the I ² CI / O expander 615 of the decoration control device 610), the effect control device 550 receives initialization instruction data including the common address for resetting. And output to the relay board 600 or the simple relay board 1600. At this time, the initialization instruction data effect control data is output from the connection line SDA to all the decoration control devices 610 connected to the effect control device 550 via the relay substrate 600 or the simple relay substrate 1600.

Since a common address for reset is set in advance in each decoration control device 610, it is determined whether or not the address included in the input data matches the common address for reset. If it is determined that the two match, the I ² CI / O expander 615 of the decoration control device 610 outputs a response signal to the master IC, captures the input data as initialization instruction data, and outputs the I ² CI / O expander. The panda 615 itself is initialized.

When the I ² CI / O expander 615 is initialized, the rendering device controlled by the initialized I ² CI / O expander 615 is turned off.

As described above, the decoration control device 610 performs control based on a command from the effect control device 550, and therefore, the relationship between the effect control device 550 and the decoration control device 610 is the first master IC 570a of the effect control device 550 and the second master IC 570a. The master IC 570b is a master, and the I ² CI / O expander 615 of each decoration control device 610 is a slave.

  15 and 16, the control target of the decoration control device 610 other than the relay board 600 is a decoration device 620 that is a light emitting device such as an LED, but it is also possible to control a movable object such as a motor or a solenoid. It is. In this case, since the effect device serves as a drive source such as a motor or a solenoid, the operation mode of these drive sources corresponds to the output mode of the effect device. The effect control data includes an operation / stop instruction for the drive source, and it is also possible to specify the operation speed.

  Note that, even if the gaming machine 1 is provided with a low-priced front frame 3 ′ instead of the normal-price front frame 3, the connection state of various substrates included in the low-priced front frame 3 ′ is almost the same as FIG. It becomes the composition of.

  However, since the illumination drive motors (illumination drive first MOT 13a, illumination drive second MOT 14a) are not provided on the inexpensive plate front frame 3 ′, the illumination drive motor is connected to the inexpensive relay board 1600 ′. There is no connector, and the connection lines M11 to M14 and the connection lines M21 to M24 are not used. Therefore, in the low-price simple relay board 1600 ', the empty terminal monitor 603 is also connected to the connection lines M11 to M14 and the connection lines M21 to M24.

  Further, since the low-price front frame 3 'is not provided with the motor position detection sensor 560b, in the low-price simple relay board 1600', the connection lines SE1 to 3 are connected to the ground so that a signal of a certain level is obtained. However, it is configured such that it is always input to the production control device 550.

  FIG. 17 is a block diagram of the decoration control device 610 according to the first embodiment of this invention.

  As described above, the decoration control device 610 according to the first embodiment of the present invention is classified into three types: a branch type, a connection type, and a termination type, based on the connection form. FIG. 17 shows an example in which a terminal type decoration control device 610Y is connected to a branch type decoration control device 610X. Further, a decoration device substrate 625 is connected to the decoration control device 610Y.

The branch type decoration control device includes an I ² CI / O expander 615, a connector for receiving a signal received by the I ² CI / O expander 615 (upstream connector), and a signal received from the upstream connector. A connector (downstream connector) for transmitting to a plurality of decoration control devices 610 is provided. For example, like a decoration control device 610X in the figure, an I ² CI / O expander 615 and an LED (decoration device 620) are provided inside, and further, one upstream connector 611 and two downstream connectors 612A and 612B are provided. .

The connection line SDA and the connection line SCL are branched into two in the decoration control device 610, and one is connected to the downstream connector 612B for output to the next decoration control device 610Y as it is. The other branches further, one connected to the I ² CI / O expander 615 and the other connected to another downstream connector 612A.

Also, a decoration device 620 to be controlled is connected to the output side of the I ² CI / O expander 615 of the decoration control device 610X. The output side of the I ² CI / O expander 615 includes ports 0 to 15 described with reference to FIG. Further, all the ports of the decoration control device 610 are connected to internal LEDs via current limiting resistors R0 to R15 described later in FIG. Note that the current control resistors R0 to R15 are also provided in the decoration control device 610.

As described above, the I ² CI / O expander 615 includes an address included in the effect control data input from the effect control device 550 and an individual address set in the I ² CI / O expander 615. Only when they match, the decoration device 620 connected to the I ² CI / O expander 615 is controlled based on the decoration data included in the effect control data.

  Since only one downstream connector is provided, a decoration control device that can transmit a signal received from the upstream connector to only one decoration control device 610 is a connected decoration control device. For example, the decoration control device 610X described above includes only the downstream connector 612B and does not include the downstream connector 612A.

The terminal-type decoration control device has an I ² CI / O expander 615 and a connector (upstream connector) for receiving a signal received by the I ² CI / O expander 615. This signal is not transmitted to the other decoration control device 610. For example, the decoration control device 610Y in the figure includes an I ² CI / O expander 615 and an LED (decoration device 620), and allows a current to flow through the LED provided on the decoration device substrate 625 connected to the outside of the decoration control device 610Y. The decoration control device 610 and the decoration device substrate 625 are connected to each other through a connection line for supplying power to the LEDs of the decoration device substrate 625 and a connection wire grounded to the ground.

The decoration device substrate 625 does not include the I ² CI / O expander 615 but is a substrate including only a light emitting device such as an LED. In this case, a current limiting resistor connected to the LED provided on the decoration device board 625 is provided on the decoration device board 625, but is provided on the decoration control device 610 provided with the I ² CI / O expander 615. Also good.

It should be noted that the number of connection lines for passing current to these LEDs to be passed from the decoration control device 610 to the decoration device substrate 625 is determined in accordance with the number of LEDs provided on the decoration device substrate 625. . For example, when the decoration device substrate 625 includes two LEDs, two control lines for connecting a port of the I ² CI / O expander 615 and the corresponding LED, and power supplied from the Vled At least one power supply line is required.

The I ² CI / O expander 615 provided in the decoration control device 610Y is also set in the address included in the effect control data input from the effect control device 550 and the I ² CI / O expander 615. The decoration device 620 connected to the I ² CI / O expander 615 is controlled based on the decoration data included in the effect control data only when the address matches the existing address. In this case, both the decoration device 620 provided in the central decoration control device 610 and the decoration device 620 provided on the decoration device substrate 625 are controlled by the I ² CI / O expander 615.

In this manner, by providing the decoration device substrate 625 and separating some of the decoration devices (LEDs) from the decoration control device 610, even if the LEDs are arranged at remote locations, a common I ² CI / It can be controlled by the O expander 615.

  As described above, the decoration control device 610 can control a movable object such as a solenoid or a motor instead of a light emitting device such as an LED, and will be described in detail later with reference to FIG.

FIG. 18 is a block diagram illustrating a configuration of the I ² CI / O expander 615 according to the first embodiment of this invention.

The I ² CI / O expander 615 includes a transistor 630 connected to the connection line SDA, a filter 631 connected to the connection line SDA, a driver 632 connected to the connection line SDA, a filter 633 connected to the connection line SCL, Bus controller 634, output setting register 635, output controller 636, driver 637 connected to ports 0-15 on the output side of I ² CI / O expander 615, transistors 638A-638P connected to ports 0-15 , And a reset signal generation circuit 639. Further, in the first embodiment of the present invention, a bus monitoring WDT (watchdog timer) 640 for determining whether or not the connection line SDA is occupied by another I ² CI / O expander 615, and A self-occupied WDT 641 is provided for determining whether or not the I ² CI / O expander 615 itself occupies the connection line SDA.

  The filter 631 is connected to the connection line SDA, removes noise of data input from the connection line SDA, and outputs the data from which noise has been removed to the bus controller 634. When the driver 632 outputs a response signal from the connection line SDA, the driver 632 applies a voltage at which the transistor 630 can operate to the transistor 630.

  When the driver 632 outputs data (response signal) from the connection line SDA, the driver 632 applies a voltage at which the transistor 630 can operate to the transistor 630.

  The transistor 630 uses a field effect transistor (FET) to suppress power consumption. The gate of the transistor 630 is connected to the driver 632, and the drain is connected to a connection line SDA to which a predetermined voltage is applied by the pull-up resistor R. And the source is grounded.

  If the voltage applied to the gate of the transistor 630 is smaller than a predetermined value for operating the transistor 630, no current flows between the drain and the source. On the other hand, if the voltage applied to the gate of the transistor 630 is greater than or equal to a predetermined value that causes the transistor 630 to operate, a current flows from the drain to which the voltage of the predetermined value is applied to the grounded source. The voltage drops. Note that the transistor 630 has a specification that does not break even when a current of about 10 milliamperes flows from the drain to the source.

  When the driver 632 outputs data (response signal) from the connection line SDA, the driver 632 applies a voltage of a value that allows the transistor 630 to operate to the gate of the transistor 630 so that a current flows between the drain and the source. To do. The driver 632 outputs data from the connection line SDA by repeatedly changing the voltage of the connection line SDA from HIGH to LOW.

  The filter 633 is connected to the connection line SCL, removes noise of data input from the connection line SCL, and outputs the data from which noise has been removed to the bus controller 634.

In ^addition, the I 2 CI / O expander 615, is set a unique address by the address setting terminals A0~A3 provided in the ^I 2 CI / O expander 615 is input to the bus controller 634. Further, an address for resetting the I ² CI / O expander 615 is also set in advance.

The bus controller 634 determines whether or not the address of the data input from the connection line SDA matches the unique address set in the I ² CI / O expander 615. Capture as production control data.

In addition, the bus controller 634 determines whether or not the address of the data input from the connection line SDA matches the reset address set in the I ² CI / O expander 615. The data is fetched as initialization instruction data, and the I ² CI / O expander 615 is initialized.

  In addition, the bus controller 634 changes the signal level of the connection line SCL from LOW to HIGH, and when the signal level of the connection line SCL changes from HIGH to LOW after fetching the eighth bit data. The response signal is output from the connection line SDA to the first master IC 570a. Furthermore, when it is confirmed that the signal level of the connection line SCL changes from LOW to HIGH, and the signal level of the connection line SCL changes from HIGH to LOW again, the connection line SDA is released. In other words, the response signal is output at the timing when the signal level of the connection line SCL changes from LOW to HIGH.

In the output setting register 635, the operation mode of the I ² CI / O expander 615 and the output state of the ports 0 to 15 are set. When the bus controller 634 fetches the initialization instruction data from the connection line SDA and the I ² CI / O expander 615 is initialized, the output setting register 635 causes a current to flow to all the ports 0 to 15. The initial state is set so that there is no.

  Based on the data set in the output setting register 635, the output controller 636 causes the directing device connected to each of the ports 0 to 15 to actually output the output state of the directing device through the port driver 637. To control. This output state is updated to the contents specified in the effect control data when the bus controller 634 fetches the effect control data from the connection line SDA.

That is, based on the effect control data received from the first master IC 570a, it is set in the output setting register 635, and when the stop condition is received, the output state of each port 0-15 is updated and reflected in the effect device. Therefore, it is not necessary to receive the LAT signal as in the shift register, that is, the production control can be performed without the need for wiring for receiving the LAT signal. In particular, it is effective when the port output state needs to be updated by a plurality of I ² CI / O expanders 615 at the same time, and even if the rendering device is controlled by different I ² CI / O expanders 615, Since it can be controlled to execute the production operation at the same time, the production effect can be further enhanced.

Note that, when the stop condition is received, the output state of each port 0 to 15 is not updated and reflected in the effect device, but can be reflected in the effect device when the response signal is output. In the case where an effect device that is required to execute an effect operation at the same time is controlled by one I ² CI / O expander 615, it may be reflected in the effect device when a response signal is output. By doing so, it is not necessary for the master IC to output a stop condition, and it is possible to transmit the effect control information continuously, so that the effect control can be performed at high speed.

  When a current flows through a port, the driver 637 applies a voltage at which the transistors 638A to 638P connected to the port through which the current flows can operate.

  The gates of the transistors 638A to 638P are connected to the driver 637, the drain is connected to a port terminal connected to a connection line to which a voltage for operating the effect device is applied as shown in FIGS. 19 and 20, and the source is grounded Has been.

  If the voltage applied to the gates of the transistors 638A to 638P is smaller than a predetermined value for operating the transistors 638A to 638P, no current flows between the drain and the source. On the other hand, if the voltage applied to the gates of 638A to 638P is equal to or higher than a predetermined value for operating the transistor 638, the predetermined voltage applied to the gate from the power supply Vled shown in FIG. 19 or the power supply Vmot or the power supply Vsol shown in FIG. Current flows to the source grounded through the drain of the transistor 638, so that the output state of the effect device connected to the port terminal can be controlled.

Further, the I ² CI / O expander 615 of the decoration control device 610 can simultaneously control all effect devices (decoration devices 620 such as LEDs) connected to the port terminals of the I ² CI / O expander 615. Since it is possible, one rendering device connected to the port terminal of the I ² CI / O expander 615 can be controlled as one group.

Since the I ² CI / O expanders 615 included in each decoration control device 610 are assigned different individual addresses, the rendering device is divided into a plurality of groups. That is, the I ² CI / O expander 615 included in each decoration control device 610 is configured as a group unit control unit that can control the effect device in units of groups.

  Therefore, the effect control device 550 that controls each decoration control device 610 functions as a group control unit that controls the group unit control unit.

The reset signal generation circuit 639 is connected to a Vcc terminal connected to a connection line Vcc that supplies power to the I ² CI / O expander 615 and a RESET terminal that receives an external reset signal.

The reset signal generation circuit 639 generates a reset signal when the I ² CI / O expander 615 is turned on and the voltage rises to a predetermined value. The generated reset signal is sent to the bus controller 634, the output setting register 635, And initialization by inputting to the output controller 636.

Therefore, when the harness (FIG. 15) is removed, the connection line Vcc is temporarily disconnected, and when the harness is reinserted, the power supply is restored and the reset signal generating circuit 639 outputs a reset signal. In other words, the I ² CI / O expander 615 can be reset by inserting and removing the harness when repairing or inspecting the gaming machine.

  Note that when a LOW level reset signal is input from the outside, the reset signal generation circuit 639 outputs a reset signal, and therefore, from the CPU 551 of the effect control device 550 via the NOR gate circuit 561, from the RESET terminal. A reset signal may be input. When the RESET terminal is not used, the RESET terminal may be pulled up to HIGH as shown in FIGS.

The bus monitor WDT 640 is used to detect that another I ² CI / O expander 615 occupies the connection line SDA. The bus monitoring WDT 640 is connected between the filter 631 and the bus controller 634, takes in the signal level of the connection line SDA, and measures the time during which the signal is continuously at the LOW level. Further, the bus monitoring WDT 640 is connected to the reset signal generation circuit 639. When a predetermined time has elapsed after the connection line SDA is occupied, the bus monitoring WDT 640 operates its own reset signal generation circuit 639, and the I ² CI / The O expander 615 is initialized.

Since the connection line SDA is also connected to other I ² CI / O expanders 615, in all the I ² CI / O expanders 615 to which the connection line SDA is connected, the connection line SDA is occupied. Will be detected. Then, the reset signal generation circuit 639 provided in the I ² CI / O expander 615 operates, so that all the I ² CI / O expanders 615 to which the connection line SDA is connected are initialized. Is done.

The self-occupied WDT 641 is used to detect the occupation of the connection line SDA by itself (I ² CI / O expander 615). The bus controller 634 operates the self-occupied WDT 641 while operating the driver 632 to drive the connection line SDA to the low level, and stops the self-occupied WDT 641 while not driving the connection line SDA to the low level. . When the self-occupied WDT 641 continuously operates for a predetermined time, the self-occupied WDT 641 generates a reset signal in the reset signal generation circuit 639 to initialize the I ² CI / O expander 615.

This makes it possible to monitor the period during which the bus controller 634 itself drives the connection line SDA to a low level (the period during which the I ² CI / O expander 615 occupies the connection line SDA). The self-occupied WDT 641 starts measuring time at the timing when the connection line SDA is occupied to transmit a response signal (ACK, NACK) for the data received from the master IC, and when a predetermined time elapses, the reset signal generating circuit A reset signal is generated at 639. With this configuration, when the occupation of the connection line SDA is detected by the self-occupied WDT 641, only its own I ² CI / O expander 615 is reset.

FIG. 19 is a circuit diagram around the I ² CI / O expander 615 of the decoration control device 610 that controls the decoration device 620 according to the first embodiment of this invention.

The I ² CI / O expander 615 includes an NC terminal, a RESET terminal, an SCL terminal, an SDA terminal, a Vcc terminal, an A0 to A3 terminal, and a GND terminal as input terminals, and includes PORT0 to PORT15 as output terminals.

A power source supplied to the I ² CI / O expander 615 is connected to the RESET terminal via a pull-up resistor R. For this reason, the voltage applied to the reset terminal is always maintained HIGH.

  The SCL terminal is connected to the connection line SCL, and the SDA terminal is connected to the connection line SDA.

A power supply supplied to the I ² CI / O expander 615 is connected to the Vcc terminal. Further, a capacitor CP for removing power supply noise is connected to the Vcc terminal.

The A0 to A3 terminals are terminals for setting individual addresses in the I ² CI / O expander 615. The individual address of the I ² CI / O expander 615 is normally expressed by 4 bits. When the power of the I ² CI / O expander 615 is applied to this terminal, “1” is given to the bus controller 634. ”Is set, and when this terminal is connected to the ground,“ 0 ”is set in the bus controller 634.

Accordingly, the individual address of the I ² CI / O expander 615 shown in FIG. 19 is “0100”. The GND terminal is a terminal for grounding a voltage.

  The PORT0 terminal to the PORT15 terminal are connected to a decoration device 620 including the LEDs 0 to 15 via current limiting resistors R0 to R15. Note that one LED may be connected to one port as in PORT0, but a plurality of LEDs may be connected to one port as in PORT1-15.

When one LED is provided for every port, a maximum of 16 LEDs can be controlled by one I ² CI / O expander 615. Further, when the number of LEDs connected to each port is different, if all LEDs connected in series to one port are referred to as one type of LED, one I ² CI / O expander is used. By 615, up to 16 kinds of LEDs can be controlled.

  When a voltage is applied from the driver 637 to the gates of the transistors 638A to 638P (see FIG. 18) connected to the PORT0 terminal to the PORT15 terminal, a current flows from the drain to the source of the transistors 638A to 638P to which the voltage is applied. Thus, a current flows through the LED0 to LED15 connected to the PORT0 terminal to the PORT15 terminal, and each of the LED0 to LED15 lights up.

  On the other hand, if the driver 637 does not apply a voltage to the gates of the transistors 638A to 638P, no current flows through each LED0 to LED15, and each LED0 to LED15 is not lit.

  In addition, while the harness (FIG. 15) is pulled out from the connector, the connection line Vled is disconnected, so that no current is supplied to the LEDs 0 to 15 and the LED is turned off. Since the power supply from the connection line Vled can be interrupted simply by removing the harness, the repair and inspection work of the gaming machine can be performed safely.

It should be noted that a motor or a solenoid can be connected to the PORT0 terminal to the PORT15 terminal of the I ² CI / O expander 615 instead of the LED, and the motor or solenoid can be configured as an effect device that is used for gaming. . Hereinafter, a case where a motor and a solenoid are controlled using the I ² CI / O expander 615 will be described with reference to FIG.

FIG. 20 is a circuit diagram around the I ² CI / O expander 615 of the decoration control device 610 according to the first embodiment of this invention, and shows a case where a motor and a solenoid are controlled.

  The motor used here is constituted by a stepping motor, and rotates by sequentially applying a predetermined voltage to signal terminals of each phase that drive the stepping motor. In the first embodiment of the present invention, the signal terminals of the respective phases of the motor are connected to the PORT0 terminal to the PORT3 terminal.

  When a voltage is applied from the driver 637 to any one of the gates of the transistors 638A to 638D connected to the PORT0 terminal to the PORT3 terminal connected to the motor, the drain to the source of the transistors 638A to 638D to which the voltage is applied Current flows to the motor, current flows to the motor connected to the PORT0 terminal to the PORT3 terminal, and the accessory driving motor is driven.

  The connection lines connecting the PORT0 to PORT3 terminals and the motor are branched, and one of the branched connection lines is connected to a power source supplied to the motor via a diode D and a Zener diode ZD.

  The PORT terminal 15 is connected to a solenoid to be used. When a voltage is applied from the driver 637 to the gate of the transistor 638P connected to the PORT15 terminal connected to the solenoid, a current can flow from the drain to the source of the transistor 638P to which the voltage is applied, A current flows through a solenoid connected to the PORT 15 terminal, and an effect device (not shown) driven by the solenoid is driven.

In FIG ^20, although both the motors and solenoids to I 2 CI / O expander 615 is connected, for one ^I 2 CI / O expander 615, connected by one of the motors and solenoids It may be configured.

For example, a dedicated I ² CI / O expander 615 as a group that controls only the stepping motor or a dedicated I ² CI / O expander 615 as a group that controls only the solenoid may be provided. Also good. With such a configuration, it is possible to control the rendering devices belonging to the same group at the same timing, and therefore it becomes possible to group and control only the rendering devices that require high-speed processing.

  FIG. 21 is a diagram for explaining circuit configurations of the decoration control device 610, the relay board 600, and the simple relay board 1600 according to the first embodiment of the present invention, and particularly relates to input / output of signal lines and power supply lines. It is a figure for demonstrating a connection state.

  In this figure, among the decoration control device 610, the relay board 600, and the simple relay board 1600, the branch type decoration control device 610 (for example, the decoration control device 610A) will be described. Differences between the decoration control device 610, the terminal-type decoration control device 610, the relay board 600, and the simple relay board 1600 will be described.

  In the figure, description will be made with the same reference numerals as the parts provided in the above-described branch type decoration control device 610X.

The branch type decoration control device 610 includes an upstream connector 611, a downstream connector 612 (612A, 612B), and an I ² CI / O expander 615.

  The upstream connector 611 is a connector connected to the decoration control device 610 upstream from the decoration control device 610. The downstream connectors 612A and 612B are connected to the decoration control device 610 on the downstream side of the decoration control device 610.

  In order to connect the connection line SDA to the two downstream connectors 612A and 612B, the internal connection line SDA2111 extending from the upstream connector 611 branches at a branch 2101 into a first connection line SDA2121 and a second connection line SDA2131. The first connection line SDA2121 is connected to the downstream connector 612A, and the second connection line SDA2131 is connected to the downstream connector 612B.

  Similarly, the internal connection line SCL2112 extending from the upstream connector 611 branches at a branch 2102 into a first connection line SCL2122 and a second connection line SCL2132. The first connection line SCL2122 is connected to the downstream connector 612A, and the second connection line SCL2132 is connected to the downstream connector 612B.

Further, in order to connect the connection line SDA to the I ² CI / O expander 615, the second connection line SDA 2131 branches at the branch 2103, and the branched second connection line SDA 2131 is a diagram of the I ² CI / O expander 615. 19 and the SDA terminal shown in FIG. Further, in order to connect the connection line SCL to the I ² CI / O expander 615, the second connection line SCL 2132 branches at the branch 2104, and the branched second connection line SCL 2132 is a diagram of the I ² CI / O expander 615. 19 and the SCL terminal shown in FIG. Hereinafter, the I ² CI / O expander 615, the connection line SDA connected from the branch 2103 to the I ² CI / O expander 615, and the connection line SCL connected from the branch 2104 to the I ² CI / O expander 615 will be described. The configuration including this is an I ² CI / O expander unit 2181.

Note that the I ² CI / O expander 615 is supplied with a voltage Vcc that is a power supply voltage of the I ² CI / O expander 615. Although not shown in FIG. 21, from the I ² CI / O expander 615, signal lines (FIG. 19) of ports 0 to 15 for driving LEDs (decoration device 620) provided in the decoration control device 610 are provided. Reference) is output.

Further, the signal output from the I ² CI / O expander 615 of the decoration control device 610 to the upstream decoration control device 610 via the connection line SDA, and the I of the decoration control device 610 from the upstream decoration control device 610. ^A zener diode ZD2141 is connected to the internal connection line SDA2111 in order to remove noise of a signal input to the ² CI / O expander 615 via the connection line SDA.

  Specifically, the internal connection line SDA2111 branches at the branch 2105, the branched internal connection line SDA2111 is connected to the cathode side of the Zener diode ZD2141, and the anode side of the Zener diode ZD2141 is grounded.

  For this reason, a voltage (for example, a pulsed noise signal) higher than a predetermined voltage applied to the internal connection line SDA2111 is released by the Zener diode ZD2141.

Further, in order to remove noise of a signal input from the upstream decoration control device 610 to the I ² CI / O expander 615 of the decoration control device 610 via the connection line SCL, the internal connection line SCL2112 has a Zener. A diode ZD2142 is connected.

  Specifically, the internal connection line SCL2112 branches at a branch 2106, the branched internal connection line SCL2112 is connected to the cathode side of the Zener diode ZD2142, and the anode side of the Zener diode ZD2142 is grounded.

  For this reason, a voltage (for example, a pulse noise signal) higher than a predetermined voltage applied to the internal connection line SCL2112 is released by the Zener diode ZD2142.

In addition, the I ² CI / O expander 615 of the decoration control device 610 outputs a signal output to the decoration control device 610 connected to the downstream connector 612A via the connection line SDA, and the decoration control connected to the downstream connector 612A. A zener diode ZD2143 is connected to the first connection line SDA2121 in order to remove noise of a signal input from the apparatus 610 to the I ² CI / O expander 615 of the decoration control device 610 via the connection line SDA. .

  Specifically, the first connection line SDA2121 branches at a branch 2107, the branched first connection line SDA2121 is connected to the cathode side of the Zener diode ZD2143, and the anode side of the Zener diode ZD2143 is grounded.

  For this reason, a voltage (for example, a pulsed noise signal) higher than a predetermined voltage applied to the first connection line SDA2121 is released by the Zener diode ZD2143.

  Similarly to the Zener diode ZD2143 connected to the first connection line SDA2121, the Zener diode ZD2145 is also connected to the second connection line SDA2131.

The first connection line is used to remove noise from a signal input from the I ² CI / O expander 615 of the decoration control device 610 to the decoration control device 610 connected to the downstream connector 612A via the connection line SCL. A Zener diode ZD2144 is connected to the SCL2122.

  Specifically, the first connection line SCL2122 branches at a branch 2108, the branched first connection line SCL2122 is connected to the cathode side of the Zener diode ZD2144, and the anode side of the Zener diode ZD2144 is grounded.

  For this reason, a voltage (for example, a pulsed noise signal) higher than a predetermined voltage applied to the first connection line SCL2122 is released by the Zener diode ZD2144.

  Similarly to the Zener diode ZD2144 connected to the first connection line SCL2122, the Zener diode ZD2146 is also connected to the second connection line SCL2132.

Further, from the internal connection line Vcc 2171 extending from the Vcc terminal of the upstream connector 601 connected to the connection line Vcc for supplying the power supply voltage to the I ² CI / O expander 615 of the decoration control device 610 and the GND terminal of the upstream connector 601 The extended and grounded internal connection line GND 2172 is connected via a smoothing capacitor C 2161 and a bypass capacitor CP 2162.

  The smoothing capacitor C2161 is a capacitor for smoothing the voltage waveform of the power supply, and the bypass capacitor CP2162 is a capacitor for removing noise of the power supply voltage.

Therefore, the power supply voltage supplied to the I ² CI / O expander 615 of the decoration control device 610 is smoothed by the smoothing capacitor C2161, noise is removed by the bypass capacitor CP2162, and the I ² CI / O expander is removed. The panda 615 is supplied.

  Similarly, the internal connection line Vcc2173 extending from the Vcc terminal of the downstream connectors 612A and 612B and the internal connection line GND2174 extending from the GND terminal are connected via a smoothing capacitor C2161 and a bypass capacitor CP2162. As a result, the smoothed and noise-free voltage is applied to the connection line Vcc connected to the downstream decoration control device 610.

  The branch type decoration control device 610 has been described above. Next, the connection type decoration control device 610 will be described.

  In addition to the downstream connector 612A, a Zener diode ZD2143 connected to the connection line SDA, a Zener diode ZD2144 connected to the connection line SCL, an internal connection line Vcc2173, an internal connection line GND2174, a smoothing capacitor C2161, and a bypass capacitor CP2162 are provided. The configuration is a first downstream connector portion 2182.

  In addition to the downstream connector 612B, a Zener diode ZD2145 connected to the connection line SDA, a Zener diode ZD2146 connected to the connection line SCL, an internal connection line Vcc2173, an internal connection line GND2174, a smoothing capacitor C2161, and a bypass capacitor CP2162 are provided. The configuration is a second downstream connector portion 2183.

  In the case where the decoration control device 610 is a connection type, since only one downstream connector is provided in the board, the downstream connector 612A exists but the downstream connector 612B does not exist.

  Therefore, the internal connection line SDA2111 and the internal connection line SCL2112 are configured so as not to branch at the branches 2103 and 2104, and the second connection line SDA2131 and the second connection line SCL2132 are not present, which is different from the branch type decoration control device 610. It becomes composition.

  The connection type decoration control device 610 is different from the branch type decoration control device 610 in that there is no electronic component constituting the second downstream connector portion 2183. Other configurations are the same as those of the branch type decoration control device 610.

  Next, the terminal type decoration control device 610 will be described.

  In the case where the decoration control device 610 is a terminal type, the downstream connector is not provided in the board, and therefore neither of the downstream connectors 612A and 612B exists.

Therefore, the internal connection line SDA2111 and the internal connection line SCL2112 are connected to the I ² CI / O expander 615 without branching at the branches 2101, 2102, 2103, and 2104. Are different configurations.

  The terminal-type decoration control device 610 is also different from the branch-type decoration control device 610 in that there are no electronic components constituting the first downstream connector portion 2182 and the second downstream connector portion 2183. Other configurations are the same as those of the branch type decoration control device 610.

  Next, the relay board 600 will be described.

  Since the relay board 600 is configured to include only one downstream connector in the board, similarly to the connection type decoration control device 610, the downstream connector 612A exists but the downstream connector 612B does not exist.

  Therefore, the internal connection line SDA2111 and the internal connection line SCL2112 are configured not to branch at the branches 2103 and 2104, and the second connection line SDA2131 and the second connection line SCL2132 do not exist. Therefore, the configuration is the same as that of the connection type decoration control device 610. It becomes.

  However, the relay board 600 is different from the connection type decoration control device 610 in that it includes a pull-up resistor for pulling up the voltages of the connection line SDA and the connection line SCL.

  Specifically, as shown in FIG. 21, in the relay board 600, the voltages of the upstream connection line SDA connected to the first master IC 570a and the downstream connection line SDA connected to the decoration control device 610 are set. A pull-up resistor R2151 for pulling up is connected to the first connection line SDA2121. Similarly, a pull-up resistor R2152 for pulling up the voltage of the upstream connection line SCL connected to the first master IC 570a and the downstream connection line SCL connected to the decoration control device 610 includes the first connection line. Connected to SCL2122.

  More specifically, the first connection line SDA2121 branches at the branch 2109, and the branched first connection line SDA2121 is connected to the pull-up resistor R2151. Similarly, the first connection line SCL2122 branches at the branch 2110, and the branched first connection line SCL2122 is connected to the pull-up resistor R2152. Hereinafter, the pull-up resistor R2151 for pulling up the voltage of the connection line SDA and the pull-up resistor R2152 for pulling up the voltage of the connection line SCL are collectively referred to as a pull-up resistor unit 2180.

  Next, the simple relay board 1600 will be described.

The simple relay board 1600 includes a plurality of downstream connectors (downstream connectors 612A and 612B) in the board, similarly to the branch type decoration control device 610. However, the simple relay board 1600 does not include a circuit corresponding to the I ² CI / O expander unit 2181. Instead, a circuit corresponding to the pull-up resistor unit 2180 provided in the relay board 600 is provided. This is a configuration different from the branch type decoration control device 610. Other configurations are the same as those of the branch type decoration control device 610.

  In the present embodiment, the configuration of the pull-up resistor 2180 described above is provided only on the relay board 600 and the simple relay board 1600, and is not provided in the decoration control device 610 or the effect control device 550. However, as long as the levels of the connection line SDA and the connection line SCL can be correctly generated, the decoration control device 610 and the effect control device 550 may be provided. That is, it is only necessary that the pull-up resistors R2151 and 2152 be provided at locations where the voltage Vcc can be supplied to the drain terminals of the transistors that drive the connection line SDA and the connection line SCL.

  For example, if the pull-up resistors R2151 and 2152 are provided in the first master IC 570a, it is not necessary to provide the pull-up resistor unit 2180 in the relay board 600, the simple relay board 1600, or the decoration control device 610.

  FIG. 22 is an explanatory diagram of the slave address 2200 included in the data output from the presentation control device 550 to the decoration control device 610 according to the first embodiment of this invention.

  The slave address 2200 includes a fixed address part 2201 composed of upper 3 bits and a variable address part 2202 composed of lower 5 bits.

The fixed address unit 2201 is preset with a value of “110” and cannot be changed by the I ² CI / O expander 615.

The variable address unit 2202 can be set by the I ² CI / O expander 615. The variable address unit 2202 includes a 4-bit I ² CI / O expander address 2203 corresponding to the pattern set in the terminals A0 to A3 of the I ² CI / O expander 615 to be controlled, and the data It consists of 1-bit R / W identification data 2204 indicating whether it is a read request (“1”) or a write request (“0”).

  Since the effect control data output from the effect control device 550 to the decoration control device 610 is a write request, “0” is normally registered in the R / W identification data 2204.

FIG. 23 is an explanatory diagram of the I ² CI / O expander address table 2300 according to the first embodiment of this invention.

The I ² CI / O expander address table 2300 is a table managed by the first master IC 570a. The I ² CI / O expander address table 2300 shows the correspondence between the slave address 2301 and the I ² CI / O expander address 2302.

The slave address 2301 stores the slave address of the decoration control device 610 specified by the effect control device 550 as a transmission / reception target. As described above with reference to FIG. 20, the slave address is configured by combining a fixed address portion consisting of upper 3 bits, a 4-bit I ² CI / O expander address, and 1-bit R / W identification data. .

In the I ² CI / O expander address 2302, a 4-bit I ² CI / O expander address corresponding to each slave address is registered as described above with reference to FIGS.

However, among the I ² CI / O expander addresses, the address “1000” and the address “1011” (shaded entries in FIG. 23) are used to identify each I ² CI / O expander 615 from each other. It cannot be used as a unique address.

  The address “1000” is used as a default value at power-on of an address (all call address) specified when a common command is output to all the decoration control devices 610. The address “1011” is a common address used when all the decoration control devices 610 connected to the first master IC 570a are unconditionally reset by software.

As described above, since there are 14 addresses that can be set in the I ² CI / O expander 615 of the decoration control device 610, the effect control device 550 controls the 14 I ² CI / O expanders 615. be able to. Since each decoration control device 610 includes PORT0 to PORT15, it is possible to control 16 (in other words, 16 types) LEDs. Therefore, the effect control device 550 can control 224 (in other words, 224 types) LEDs.

FIG. 24 is a diagram for describing work registers assigned to the output setting register 635 provided in the I ² CI / O expander 615 according to the first embodiment of this invention.

A work register (device register) and a control register (control register) are allocated to the output setting register 635 of the I ² CI / O expander 615.

Work ^register, I 2 CI / O Aix information and for performing settings that are predefined for Panda ^615, I 2 CI / O Aix effect device connected to the expander 615 (decoration device 620, for example, The information for specifying the output mode of LED) is stored.

  In addition, the control register stores information defining a procedure for writing data to the work register. The work register is configured to store a plurality of pieces of information in different storage areas, and a different register number is assigned to each storage area.

The register number “00h” and the register number “01h” correspond to a mode register for performing the initial setting of the I ² CI / O expander 615. The register name “MODE1” is assigned to the storage area of the register number “00h”. The register name “MODE2” is assigned to the storage area of the register number “01h”. When values are written in the storage areas of the register numbers “00h” and “01h”, the I ² CI / O expander 615 is initialized based on the written values.

Note that bit 3 (OCH) of the “MODE2” register is a parameter that defines the timing at which the effect control data stored in the output setting register 635 of the I ² CI / O expander 615 is actually reflected in the effect device. . In the first embodiment of the present invention, as described with reference to FIG. 18, “0” is set, and the presentation control data stored in the output setting register 635 is output when the stop condition is received. The output state of the rendering device is set to be actually controlled. In the fourth embodiment, the value of bit 3 (OCH) of the “MODE2” register is set to “1”, and the output signal stored in the output setting register 635 when the response signal (ACK) is output. An embodiment in which control data is output and set so as to actually control the output state of the rendering device will be described.

Parameters to be controlled such as LEDs included in the decoration device 620 are set in the register numbers “02h” to “11h” (register names “PWM0” to “PWM15”). When a value is written in any of the storage areas of register numbers “02h” to “11h”, among the 16 LEDs constituting the light emitting device (decoration device 620) connected to the I ² CI / O expander 615 The brightness of the LED corresponding to the register number in which the value is written is adjusted based on the written value. For example, when a value is written in the storage area of the register number “02h”, the luminance of the LED 0 connected to the port 0 shown in FIG. 19 is adjusted.

Note that the I ² CI / O expander 615 can also control a movable object such as a motor or a solenoid as described above. When a solenoid is connected to the I ² CI / O expander 615, the register number corresponding to the port to which the solenoid is connected is operated by energizing the solenoid or not energized. A value indicating whether to do is written. When a motor is connected to the I ² CI / O expander 615, a value indicating the target rotational position of the motor is written in the register number corresponding to the port to which the motor is connected.

  In the register number “12h” (register name “GRPPWM”) and the register number “13h” (register name “GRPFREQ”), parameters for specifying the operation pattern of the entire control target are set. When a value is written in the storage areas of the register numbers “12h” and “13h”, the blinking pattern of the entire LED (16 LEDs) is set based on the written value. Specifically, a duty cycle that is an on / off ratio of the entire LED is set in the register number “12h”, and a blinking cycle of the entire LED is set in the register number “13h”.

  In register numbers “14h” (register name “LEDOUT0”) to “17h” (register name “LEDOUT3”), the output state of the LED controlled by each port is set. Each register can set four LED output states.

  When a value is written in the storage area of the register number “14h”, the output states of the LEDs 0 to LED3 are set based on the written value. Similarly, the output state of LED4 to LED7 is stored in the storage area of register number “15h”, the output state of LED8 to LED11 is stored in the storage area of register number “16h”, and the LED12 to LED15 are stored in the storage area of register number “17h”. Output status is set.

  Sub-addresses are set in the register numbers “18h” to “1Ah” (register names “SUBADR1” to “SUBADR3”). When values are written in the storage areas of the register numbers “18h” to “1Ah”, the first subaddress to the third subaddress are set based on the written values.

  In the register number “1Bh” (register name “ALLCALLADR”), an all call address for outputting a command to all the decoration control devices 610 is set. The all call address is used, for example, when the initialization processing is executed in all the decoration control devices 610 when the power is turned on.

  FIG. 25 is an explanatory diagram of a start condition and a stop condition in which the master IC according to the first embodiment of this invention outputs data via the connection line SDA and the connection line SCL.

  The connection line SCL has a signal level of HIGH when data is not transmitted. When outputting data to the decoration control device 610, the master IC changes the signal level of the connection line SCL from LOW to HIGH so that the decoration control device 610 acts as a strobe signal for taking in the data of the connection line SDA.

  The connection line SDA has a high signal level when data is not transmitted, and data is output from the connection line SDA in accordance with the clock signal of the connection line SCL.

  The master IC changes the signal level of the connection line SDA from HIGH to LOW while maintaining the signal level of the connection line SCL at HIGH, and outputs a signal serving as a start condition indicating that data output starts. .

The I ² CI / O expander 615 of the decoration control device 610 recognizes that output of data is started when a signal serving as a start condition is input from the connection line SDA and the connection line SCL.

  The master IC changes the signal level of the connection line SDA from LOW to HIGH while maintaining the signal level of the connection line SCL at HIGH, and outputs a signal that becomes a stop condition indicating that the output of data ends. .

The I ² CI / O expander 615 of the decoration control device 610 recognizes that the output of data is finished when a signal serving as a stop condition is input. In the first embodiment of the present invention, as described above, when the decoration control device 610 receives a signal that is a stop condition, control of the effect device (decoration device 620) controlled by the decoration control device 610 is started. .

  FIG. 26 is a timing chart at which the decoration control device 610 to which data output from the master IC according to the first embodiment of this invention is input outputs a response signal.

  The decoration control device 610 counts the number of changes in the signal level of the connection line SCL after the start condition is satisfied, and takes in data input from the connection line SDA in accordance with the clock signal of the connection line SCL.

  Then, the decoration control device 610 outputs a response signal to the master IC via the connection line SDA immediately before the start condition is satisfied and immediately before the number of changes in the signal level of the connection line SCL reaches nine. In other words, the decoration control device 610 outputs a response signal via the connection line SDA when the signal level of the connection line SCL changes from HIGH to LOW after taking the 8th bit data from the connection line SDA. To do.

  As shown in FIG. 26, a response signal (ACK response signal) indicating that data reception has been successful is indicated by a LOW level, and a response signal (NACK response signal, indicating that data reception has failed), In the figure, this corresponds to no ACK output) is indicated by a HIGH level.

  Further, when the signal level of the connection line SCL changes eight times after the start condition is satisfied, the master IC waits for a response signal from the decoration control device 610 by releasing the connection line SDA. Then, the master IC changes the signal level of the connection line SCL while releasing the connection line SDA, and takes in the response signal from the decoration control device 610.

  FIG. 27 is a timing chart of signal levels of the connection line SDA and the connection line SCL when the master IC according to the first embodiment of the present invention outputs effect control data.

  First, when starting output of data, the master IC changes the signal level of the connection line SDA from HIGH to LOW while maintaining the signal level of the connection line SCL at HIGH, thereby indicating a start condition signal. And the decoration control device 610 is notified that data output is to be started.

  Next, the master IC outputs the slave address of the decoration control device 610 to be controlled, which consists of a total of 7 bits. Further, the master IC outputs information indicating whether the request is a write request, which is a read request, at the eighth bit.

  The master IC receives a response signal from the decoration control device 610 when the signal level of the connection line SCL becomes HIGH for the ninth time. Therefore, if the response signal is an ACK response signal, the signal level of the connection line SDA is LOW. If the response signal is NACK, the signal level of the connection line SDA changes to HIGH.

  Next, after outputting the address data, the master IC outputs the data with a bit number that is a multiple of eight. Further, after the eighth bit of data is output, the ninth bit of data is output after an ACK response signal is input. Thereafter, when data of a bit corresponding to a multiple of 8 is output, after confirming that an ACK response signal is input, a (multiple of 8 + 1) th bit is output and all data is output. Repeat until.

  If the master IC outputs a bit that is a multiple of 8 after the data has been output and the ACK response signal is not input even after a predetermined time has elapsed, the master IC assumes that the data transmission has failed and starts again. Send the condition. Next, the address data is output again via the connection line SDA, and the data is output again from the first bit while confirming the ACK response signal.

  The master IC outputs the signal indicating the stop condition after outputting the data of the last bit of the data and waiting for the ACK response signal to be input.

  In FIG. 27, a total of 24 bits (slave address 8 bits, data 16 bits) of data is output after the signal indicating the start condition is output until the signal indicating the stop condition is output. Depending on the size of data to be transmitted, it may be 24 bits or more, or 24 bits or less.

FIG. 28 shows the master IC and the I ² CI / O expander when the master IC according to the first embodiment of the present invention specifies the slave individual address and sets the effect control data in the decoration control device 610. 6 is a diagram illustrating a format of data transmitted / received to / from 615. FIG.

The 8-bit data 2801 that is output first includes an address “A0 to A6” of the decoration control device 610 that is a target of data transmission, and a 1-bit that indicates whether the data is a read request or a write request. R / W identification data is included. Among the addresses “A0 to A6”, “A4 to A6” are fixed address portions having a value “110”, and “A0 to A3” are set to the terminals A0 to A3 of the I ² CI / O expander 615. (Refer to FIG. 19). The data 2801 is data corresponding to “ADDRESS” and “R / W” in FIG.

The 8-bit data 2802 to be output next includes setting data for the control register assigned to the output setting register 635 (see FIG. 18) of the I ² CI / O expander 615. Data 2802 is data corresponding to “DATA” transmitted first in FIG.

  Here, the control register will be described. The control register consists of 8 bits, and the upper 3 bits “AI0 to AI2” are automatic write parameters for designating the writing or reading method to the work register of the output setting register 635, and the lower 5 bits “D0 to D4” are the work. This is a register address that specifies an access start position (a start position at which writing starts or a start position at which reading starts) in the register.

  The auto-write parameter is accessed by the master IC including only the access start position area specified by the register address (auto-increment is prohibited) or including the area adjacent to the access start position area specified (auto-increment). (Specifically, “000”, “100”, “101”, “110”, “111”) can be set.

  When a value of “000” is set in the automatic writing parameter, auto-increment is prohibited, and only the area at the access start position specified by the register address is accessed, and the area other than the start position is not accessed. For example, if the register address is “10100”, only the storage area with the register number “14h” is accessed, and the other storage areas are not accessed. That is, it is used when only the value of the storage area of a specific register address is changed. When the values of the storage areas of a plurality of register addresses are changed continuously, the address designation can be omitted by permitting auto-increment as described below.

  When the value of “100” is set in the auto-write parameter, auto-increment is permitted, and after accessing the area at the access start position specified by the register address, access is made sequentially while moving the area in the direction of increasing register numbers repeat. Then, after accessing the storage area where the register number is “1Bh” at the end, the storage area where the register number is “00h” is accessed and accessed again sequentially while moving the area in the direction in which the register number increases. repeat. For example, if the register address is “10100”, after accessing the storage area where the register number is “14h”, the register number is “15h” → “16h” →→→ “1Bh” → “00h” → “01h” →... (Ie, all areas) are repeatedly accessed.

  When the value of “101” is set in the automatic write parameter, the register number is set after accessing the area at the access start position specified by the register address, as in the case of setting the value of “100” in the automatic write parameter. Access is repeated in order while moving the area in the direction of increasing. However, once the storage area whose register number is “11h” is accessed, the storage area whose register number is “02h” is accessed, and thereafter, the section where the register numbers are “02h” to “11h”. The recording area (area relating to LED brightness adjustment) is repeatedly accessed. For example, if the register address is “10100”, after accessing the storage area where the register number is “14h”, the register number is “15h” → “16h” →. →→ “1Bh” → “00h” → The area which becomes “01h” →... Is accessed in order. After accessing the storage area where the register number is “11h”, the area where the register number is “02h” → “03h” → ··· “11h” → “02h” → “03h” → ··· , Repeatedly access.

  When the value “110” is set in the automatic write parameter, the register number is set after accessing the area at the access start position specified by the register address, as in the case where the value “100” is set in the automatic write parameter. Access is repeated in order while moving the area in the direction of increasing. However, once the storage area whose register number is “13h” is accessed, the storage area whose register number is “12h” is accessed, and thereafter, the section where the register numbers are “12h” to “13h”. The recording area (area related to the LED blinking cycle) is repeatedly accessed. For example, if the register address is “10100”, after accessing the storage area where the register number is “14h”, the register number is “15h” → “16h” →. →→ “1Bh” → “00h” → The area which becomes “01h” →... Is accessed in order. Then, after accessing the storage area where the register number is “13h”, the area where the register number is “12h” → “13h” → “12h” → “13h” →... Is repeatedly accessed.

  When the value “111” is set in the automatic write parameter, the register number is set after accessing the access start position area specified by the register address, as in the case where the value “100” is set in the automatic write parameter. Access is repeated in order while moving the area in the direction of increasing. However, once the storage area whose register number is “13h” is accessed, the storage area whose register number is “02h” is accessed, and thereafter, the section where the register numbers are “02h” to “13h”. The recording area (area related to LED brightness and blinking cycle) is repeatedly accessed. For example, if the register address is “10100”, after accessing the storage area where the register number is “14h”, the register number is “15h” → “16h” →. →→ “1Bh” → “00h” → The area which becomes “01h” →... Is accessed in order. After accessing the storage area where the register number is “13h”, the area where the register number is “02h” → “03h” → ··· “13h” → “02h” → “03h” → ··· , Repeatedly access.

  Here, returning to the description of FIG. 28, the work register setting data 2803 is output following the control register setting data 2802. The setting data 2803 is data corresponding to “DATA” transmitted after the second in FIG.

  When the automatic writing parameter is “000”, the setting data 2803 is 8-bit data for updating one storage area designated by the register address. When the automatic writing parameter is set to a value other than “000”, the setting data 2803 is a multiple of 8 necessary for repeatedly updating a plurality of areas starting from the storage area specified by the register address. Bit data.

FIG. 29 shows the master IC and the I ² CI / O expander when the master IC according to the first embodiment of the present invention specifies the individual address of the slave and sets the effect control data in the decoration control device 610. 615 is a diagram in which specific numerical values are applied to effect control data transmitted to and received from 615. FIG. FIG. 29 shows effect control data for prohibiting auto-increment and updating only one specific storage area of the work register. Specifically, the PORT0 terminal of the I ² CI / O expander 615 A case where the light emission state of the LED connected to the PORT3 terminal is updated will be described.

First, “1101100” indicating the slave address of the I ² CI / O expander 615 of the destination decoration control device 610 is assigned to the 8-bit data 2901 output first.

The 8-bit data 2902 to be output next is set in the control register of the output setting register 635 of the I ² CI / O expander 615 assigned to set the automatic writing parameter and LED output data. Value to be included.

Here, since the light emission state of the LED connected to the PORT0 terminal to the PORT3 terminal of the I ² CI / O expander 615 is set, LEDOUT0 (address = 10100) is designated as the register address.

  Note that “000” is designated in the auto-write parameter to prohibit auto-increment.

Next, the output 8-bit data 2903 includes data for setting the light emission mode of the decoration device 620 controlled by the destination decoration control device 610. Specifically, data set in the LEDOUT0 register is assigned. As a result, the light emission state (lighted, extinguished, blinking, etc.) of the LED connected to the PORT0 terminal to the PORT3 terminal of the I ² CI / O expander 615 is designated, and the LED emits light in the designated state.

In this ^way, the light emission state of the LED PORT0 terminal ~PORT3 terminal I 2 CI / O expander 615 is ^controlled, the other PORT terminal I 2 CI / O expander 615 (PORT4~PORT15) also Individual control is possible by designating the value of the control register data 2902 and setting the output data 2903. Even if a motor or a solenoid is connected to the PORT terminal, the same control is performed.

  FIG. 30 is a diagram illustrating the order in which the production control data of the master IC according to the first embodiment of this invention is transmitted. In FIG. 30, the order in which each data included in the effect control data is transmitted when auto-increment is permitted and all the storage areas of the work register are updated is defined.

  First, the master IC transmits 8-bit data (data having the same format as the data 2801 in FIG. 28) that can specify the individual address of the decoration control device 610 to be controlled.

Next, the master IC transmits data set in the control register of the output setting register 635 of the I ² CI / O expander 615 to be controlled (data having the same format as the data 2802 in FIG. 28). In FIG. 30, in order to update all the storage areas of the work register by permitting auto-increment, “100” is designated as the automatic write parameter, and the register address designating the start position of writing or reading is “00h” which is the head area of the work register is designated.

For this reason, in the I ² CI / O expander 615 of the decoration control device 610 to be controlled after receiving the control register setting value, the storage area (mode register 1) of the register number “00h” is updated first. Will be.

Next, after transmitting the control register set value, the master IC transmits values to be written to the mode register 1 (total 8 bits). When the I ² CI / O expander 615 receives the write value, the I ² CI / O expander 615 updates the value of the mode register 1, increments the register number, and prepares to update the next “01h” storage area (mode register 2). do.

Further, the master IC transmits values to be written to the mode register 2 (8 bits in total), and thereafter transmits setting values to the remaining storage area registers whose register numbers are “02h” to “1Bh” in order. To do. Each time the I ² CI / O expander 615 receives the write value, the I ² CI / O expander 615 updates the corresponding register value, increments the register number, and repeats preparation for updating the next storage area. The values of all the registers “00h” to “1Bh” assigned to are updated.

When the I ² CI / O expander 615 updates the storage area of “1Bh” that is the last of the work registers, the I ² CI / O expander 615 changes the register number to “00h” and waits for the mode register 1 to be updated.

31, when the master IC of the first embodiment of the present invention initializes the ^I 2 CI / O expander 615, the initialization instruction transmitted from the master IC to the ^I 2 CI / O expander 615 It is a figure explaining the format of data.

  When the CPU 551 of the effect control device 550 instructs the master IC to initialize the decoration control device 610, the master IC transmits initialization instruction data to all the decoration control devices 610 connected to the master IC. .

  The 8-bit data 3101 output first includes a fixed address “110” shown in FIG. 29 and a reset address “1011” (see FIG. 23), which is a common address. The data 3101 corresponds to “ADDRESS” in FIG. 27, and “0” indicating writing is set in the bit of “R / W”.

  The first predetermined value “10100101” is set in the 8-bit data 3102 to be output next, and the second predetermined value “01011010” is set in the 8-bit data 3103 to be output next. The data 3102 corresponds to “DATA” transmitted first in FIG. 27, and the data 3103 corresponds to “DATA” transmitted second in FIG.

When all the I ² CI / O expanders 615 connected to the master IC receive initialization instruction data including a reset address, a first predetermined value, and a second predetermined value, the I ² CI / O expander 615 initializes itself.

The reason why both the first predetermined value and the second predetermined value are output after the reset address is output is that the master IC does not transmit the reset address “1011”, but the influence of noise or the like. This is because the I ² CI / O expander 615 erroneously fetches the reset address “1011” to prevent initialization from being executed at an incorrect timing.

The reset address is an address common to all (in other words, a plurality of) I ² CI / O expanders 615, unlike the individual address. Therefore, only transmit once initialization instruction data including the reset address, since all will be initialized by selecting I ² CI / O expander 615 (s), I 2 ^CI / O Aix Compared with the method of individually selecting the panda 615 and instructing initialization, it is possible to instruct initialization at high speed.

  In FIG. 31, the first predetermined value and the second predetermined value are different from each other, but may be the same value. Further, either the first predetermined value or the second predetermined value may be transmitted once.

  FIG. 32 is a diagram illustrating the abnormality determination table 3200 of the first master IC 570a according to the first embodiment of this invention.

The abnormality determination table 3200 is stored in the RAM 553 of the effect control device 550. The abnormality determination table 3200 is provided to monitor the connection state between the first master IC 570a of the effect control device 550 and the I ² CI / O expander 615 connected to the first master IC 570a. The abnormality determination table 3200 stores information corresponding to each I ² CI / O expander 615 in accordance with the connection state.

  The abnormality determination table 3200 includes an I / O expander address 3201, a slave address 3202, an error counter 3203, a comparison value 3204, and an error flag 3205.

The I / O expander address 3201 corresponds to the address (see FIG. 19) set at the terminals A0 to A3 of the I ² CI / O expander 615 connected to the first master IC 570a.

In the slave address 3202, the slave address registered in the I ² CI / O expander address table 2300 shown in FIG. 23 is registered.

The error counter 3203 transmits the effect control data from the first master IC 570a to the I ² CI / O expander 615, and increments when the ACK cannot be received twice consecutively from the I ² CI / O expander 615. Is done.

In the comparison value 3204, a value to be compared with the value of the error counter 3203 is registered in order to determine whether or not a failure has occurred in the I ² CI / O expander 615. Note that the value of the comparison value 3204 may be set according to the type of the rendering device to be controlled.

Registered in the error flag 3205 is an error flag indicating whether or not an abnormality has occurred in the connection state of the entry with the I ² CI / O expander 615.

The method for determining whether or not a failure has occurred in the I ² CI / O expander 615 will be described in detail. If the value of the error counter 3203 reaches a predetermined value set in the comparison value 3204, an error will occur. “ON” is set in the flag 3205, and it is registered that a failure has occurred in the I ² CI / O expander 615 corresponding to the entry.

  In the first embodiment of the present invention, as will be described later, the production control data output process (see FIG. 37) is executed in synchronization with a VDP interrupt (a period of about 33.3 ms). .

As described above, if the ACK from the I ² CI / O expander 615 cannot be received for the ^second transmission of the presentation control data from the first master IC 570a to the I ² CI / O expander 615, an error occurs. Counter 3003 is incremented.

Therefore, if an abnormality has occurred, the execution period of the data output process is 33.3 ms and the comparison value 3004 is “300”, so the I ² CI / O expander is 33.3 ms × 300≈10 s. It is detected that an abnormality relating to 615 has occurred.

  FIG. 33 is a diagram illustrating the abnormality determination table 3300 of the second master IC 570b according to the first embodiment of this invention.

Similar to the abnormality determination table 3200 of the first master IC 570a, the abnormality determination table 3300 of the second master IC 570b is stored in the RAM 553 of the effect control device 550. The abnormality determination table 3300 is provided to monitor the connection state between the second master IC 570b of the effect control device 550 and the I ² CI / O expander 615 connected to the second master IC 570b. The abnormality determination table 3300 stores information corresponding to each I ² CI / O expander 615 according to the connection state. The configuration of the abnormality determination table 3300 is the same as that of the abnormality determination table 3200 of the first master IC 570a.

  In the first embodiment of the present invention, since there is no decoration control device 610 connected to both the first master IC 570a and the second master IC 570b, the I / O expander address of each decoration control device 610 to be controlled. Is set for each master IC. Therefore, in FIG. 32 and FIG. 33, the same value I / O expander address is set. Since only one address can be set as the I / O expander address, it is necessary to set a common address when a plurality of master ICs control one decoration control device 610.

  The master IC according to the first embodiment of the present invention includes a plurality of registers that are used to configure device operation and transmit / receive serial data. The command register (REG) 581 shown in FIGS. 11 and 12 is one of such registers, and instructs the connected decoration control device 610 to output a start condition or a stop condition.

  The effect control device 550 transmits an effect instruction to the decoration control device (slave) 610 via the master IC, and executes various effect processes. FIG. 34 shows a procedure for initializing each slave, and FIG. 35 shows an outline of a procedure for transmitting the effect control data to each slave.

  FIG. 34 is transmitted / received between the CPU 551 and the master IC (the first master IC 570a or the second master IC 570b) when each decoration control device (slave) according to the first embodiment of the present invention is initialized (reset). It is a figure explaining information.

  When the slave initialization start process is started, the CPU 551 of the effect control device 550 sets “1” to a bit instructing execution of the start condition (STA) and the stop condition (STO) of the command REG 581 (3401).

  In accordance with the information (STO, STA) set in the command REG581, the master IC first outputs a stop condition to each decoration control device (slave) 610 to be controlled, and then outputs a start condition (3411). . By outputting a stop condition, each slave is notified that data transmission has been completed, and thereafter, by outputting a start condition, preparation for receiving an input of a command is completed in each slave.

  When outputting the start condition, the master IC inputs an interrupt signal (INT) to the CPU 551 to generate an interrupt. The CPU 551 that has generated the interrupt starts the transmission resumption process (1) of the transmission instruction data (3402). In the transmission resumption process (1) of the transmission instruction data, a reset address is set in the output buffer 572. The reset address is a fixed address determined in advance for resetting each slave. At this time, “0” is set in the STA and STO of the command REG581.

  The master IC outputs predetermined data (reset command) to the reset address set in the output buffer 572 (3412). The reset command corresponds to the first predetermined value (data 3102) and the second predetermined value (data 3103) described in FIG.

  When the master IC outputs the reset address, the master IC inputs an interrupt signal to the CPU 551 to generate an interrupt. The CPU 551 that has generated the interrupt starts the transmission resumption process (2) of the transmission instruction data (3403). In the transmission restart process (2) of the transmission instruction data, the first half value of the reset command is set in the output buffer 572. The first half value of the reset command corresponds to the first predetermined value (data 3102) described in FIG. At this time, “0” is set in the STA and STO of the command REG581. The master IC outputs the first half value of the reset command set in the output buffer 572 (3413).

  Thereafter, when the master IC outputs the first half value of the reset command, it inputs an interrupt signal to the CPU 551 to generate an interrupt. The CPU 551 that has generated the interrupt starts transmission restart processing (3) of the transmission instruction data (3404), and sets the latter half value of the reset command in the output buffer 572. At this time, “0” is set in the STA and STO of the command REG581. The master IC outputs the latter half value of the reset command set in the output buffer 572 (3414). The latter half value of the reset command corresponds to the second predetermined value (data 3103) described with reference to FIG.

  Further, when the master IC outputs the second half value of the reset command, it inputs an interrupt signal to the CPU 551 to generate an interrupt. The CPU 551 that has generated the interrupt starts transmission restart processing (4) of the transmission instruction data (3405), sets “0” to the STA of the command REG581, sets “1” to the STO, and outputs the stop condition to the master IC. Instruct.

  The master IC outputs a stop condition to each slave according to the information set in the command REG 581 (3415).

  Through the above processing, each slave is initialized. If the initialization fails (3406), the process is restarted from step 3402.

  FIG. 35 shows transmission / reception between the CPU 551 and the master IC (the first master IC 570a or the second master IC 570b) when transmitting the effect control data to each decoration control device (slave) according to the first embodiment of the present invention. It is a figure explaining the information to be performed.

  When performing the effect control, the CPU 551 of the effect control device 550 first sets “1” to a bit instructing execution of the start condition (STA) and the stop condition (STO) of the command REG581 (3501).

  The master IC outputs a stop condition to each slave based on the values (“1”) set in the STA and STO of the command REG 581, and then outputs a start condition (3511).

  When the master IC outputs a start condition to each slave, the master IC is ready to receive the presentation control data at each slave. Therefore, the master IC inputs an interrupt signal to the CPU 551 to generate an interrupt. The CPU 551 that has generated the interrupt sets presentation control data indicating the address of the slave to be controlled and the control content in the output buffer 572 (3502). At this time, “0” is set in the STA and STO of the command REG581.

  The master IC outputs the address and effect control data set in the output buffer 572 to each slave (3512). At this time, the slave corresponding to the output address executes effect processing based on the received effect control data.

  When the master IC outputs the address and the effect control data to each slave, the master IC inputs an interrupt signal to the CPU 551 to generate an interrupt. The CPU 551 that has generated the interrupt sets “1” to the STA of the command REG 581 and “0” to the STO (3503). Thereafter, the master IC outputs a so-called restart condition that outputs a start condition again (3513).

  Subsequently, the CPU 551 and the master IC perform similar processing by designating another address (3504, 3514, 3505, 3515). When the CPU 551 completes the output of the presentation control data for the last nth slave (3506), and the master IC outputs the presentation control data to the corresponding slave (3516), the output of all the data is completed, so Output the condition. Specifically, when the master IC has finished outputting the production control data to the final slave, an interrupt signal is input to cause the CPU 551 to generate an interrupt, and the CPU 551 that generated the interrupt generates “0” in the STA of the command REG581. ", STO is set to" 1 "(3507), and then the master IC outputs a stop condition (3517).

  In the first embodiment of the present invention, it is configured to update the effect mode of the effect device by outputting a stop condition. However, in the fourth embodiment to be described later, a response signal ( ACK) An example in which the effect mode of the effect device is updated at the time of transmission will be described.

  FIG. 36 is a diagram illustrating the stage of transmitting effect control data from the effect control device 550 according to the first embodiment of this invention to the master IC (first master IC 570a or second master IC 570b).

  When the slave output data editing process described later is executed, the CPU 551 of the effect control device 550 secures an output data preparation area in the RAM 553 and stores the effect control data for each slave in the output data preparation area.

  In addition, the output data preparation area is further divided for each slave, and stores the production control data corresponding to the address and production content corresponding to each slave. Specifically, the address corresponds to the data of the transmission order 1 shown in FIG. 30, and the effect control data corresponds to the data of the transmission orders 2 to 30 shown in FIG.

  Further, the CPU 551 further secures an output data save area in the RAM 553 so that untransmitted effect control data is not overwritten, and saves the data stored in the output data preparation area by the slave output data save process to the output data save area. Let Thereafter, the saved data is set in the output buffer 572 of the master IC at a predetermined timing.

  The output data preparation area and the output data saving area are secured in the RAM 553 for each master IC, and areas corresponding to the first master IC 570a and the second master IC 570b are secured in the first embodiment of the present invention. .

  FIG. 37 is a flowchart showing a procedure of processing performed by the effect control device 550 according to the first embodiment of this invention. This process is a process executed by the CPU 551 of the effect control device 550.

  When the effect control device 550 is turned on, the effect control device 550 first executes the processes of steps 3701 to 3706. Then, every time a synchronizing signal (for example, a synchronizing signal having a 33.3 ms second period) synchronized with the image update period is input from the VDP 556 to the CPU 551 as an interrupt signal, the effect control periodic process in step 3707 is repeatedly executed.

  First, the effect control device 550 executes initialization processing including initialization of the RAM 553 of the effect control device 550 (3701). At this time, an initialization stage number relating to the first master IC 570a described later and an initialization stage number relating to the second master IC 570b are both set to “0”.

  Then, the effect control device 550 inputs a reset pulse to the first master IC 570a and the second master IC 570b via the output I / F 558a and the NOR gate circuit 561, and initially sets the first master IC 570a and the second master IC 570b in hardware. (3702).

Subsequently, the effect control device 550 outputs initialization instruction data from the first master IC 570a in order to initialize the I ² CI / O expander 615 of all the decoration control devices 610 connected to the first master IC 570a. The first master IC 570a side slave initialization start process is executed (3703). Similarly, the second master IC 570b side that outputs initialization instruction data from the second master IC 570b in order to initialize the I ² CI / O expander 615 of all the decoration control devices 610 connected to the second master IC 570b. Slave initialization start processing is executed (3704). Details of the slave initialization start process will be described with reference to FIG.

  Further, the effect control device 550 waits until both the initialization stage number related to the first master IC 570 and the initialization stage number related to the second master IC 570b become “0” (3705). The initialization stage number is a number indicating the progress of the initialization process for each of the first master IC 570a and the second master IC 570b, and is “0” immediately after the presentation control device 550 is activated immediately after the power is turned on. However, when the initialization process is started, it is incremented from “1” to “4” step by step, and when the initialization process is completed, it is returned to “0” again. In the initialization instruction data transmission restart process described with reference to FIG. 42, processes corresponding to the set initialization stage number are sequentially executed.

  When the initialization of all the masters and slaves is completed, the effect control device 550 permits the reception of the synchronization signal (VDP interrupt) synchronized with the image update cycle and the reception of the timer interrupt from the VDP 556 (3706).

  Thereafter, the effect control device 550 executes an effect control periodic process that is executed each time a VDP interrupt occurs (3707). Details of the effect control periodic processing will be described later with reference to FIG.

  FIG. 38 is a flowchart illustrating a procedure of slave initialization start processing on the first master IC 570a side and slave initialization start processing on the second master IC 570b side according to the first embodiment of this invention.

  The slave initialization start process on the first master IC 570a side is executed in the process of step 3703 in FIG. 37 and step 3923 in the effect control regular process (FIG. 39). Similarly, the slave initialization start process on the second master IC 570b side is executed in the processes of step 3704 and step 3927.

  In the initialization start process on the first master IC 570a side, first, the CPU 551 of the effect control device 550 prohibits a master interrupt and a timeout interrupt (3801). Then, the first master IC 570a is selected as the master to be initialized (3802).

  In the slave initialization start process on the second master IC 570b side, the CPU 551 prohibits a master interrupt and a timeout interrupt as in the first master IC 570a side slave initialization start process (3811). Then, the second master IC 570b is selected as the master to be initialized (3812).

  In the subsequent processes, a common process is executed for the selected master for the first master IC 570a side slave initialization start process and the second master IC 570b side slave initialization start process.

  The CPU 551 sets “1” to the initialization stage number of the selected master (3803). Further, a monitoring timer for the selected master is set (3804), and timeout monitoring is started (3805).

  In response to the selected master command REG581, the CPU 551 sets “1” in the STA, “1” in the STO, “0” in the SI, and “0” in the MODE (3806).

  As described above, the STA is a bit for instructing the output of the start condition, and the STO is a bit for instructing the output of the stop condition. When “1” is set in each bit, a corresponding signal is output by the master IC. In the process of step 3806, signals of both a start condition and a stop condition are output.

  SI is a bit for notifying the occurrence of the aforementioned master interrupt. When “1” is set, the master IC requests the CPU 551 to generate an interrupt, and this bit is set to “0”. The master IC that generated the interrupt is in a state of waiting for processing until changed to. When the CPU 551 sets “0” to this bit, the interrupt generated in the CPU 551 is canceled, and the master IC waiting for processing resumes the next processing to be performed. In the process of step 3806, since “0” is set, the generation of the interrupt is canceled, and the master IC that has been waiting for the process resumes the operation.

  MODE is a bit for designating a mode for transmitting data. When “1” is set, “buffer mode” is designated, and when “0” is set, “byte mode” is designated. Is done. In step 3806, since “0” is set, data is exchanged in the byte mode.

  Thereafter, the CPU 551 permits a master interrupt and a timeout interrupt (3807), and returns to the caller.

  FIG. 39 is a flowchart illustrating a procedure of the effect control regular processing according to the first embodiment of this invention.

The regular production control process is a process executed in step 3707 in FIG. 37, and production control data to be transmitted from each master to each slave (I ² CI / O expander 615) each time a VDP interrupt occurs. This is a process for editing and transmitting the effect control data.

  First, the CPU 551 of the effect control device 550 outputs data serving as a command to display an image on the VDP 556 in order to display the image on the display device 53 (3901). Further, sound control data is output to the sound LSI 557 in order to output a sound corresponding to the gaming state from the speaker 30. The sound LSI 557 outputs sound from the speaker 30 based on the input sound control data (3902).

  Furthermore, as described with reference to FIG. 36, the CPU 551 executes a slave output data saving process for saving the effect control data stored in the RAM 553 so as not to be overwritten (3903). As described above, the output data saved in the save area is set in the master IC at a predetermined timing.

  Subsequently, the CPU 551 prohibits a master interrupt and a timeout interrupt (3904). Next, the update stage number corresponding to the first master IC 570a is set to “0” (3905). Furthermore, the monitoring timer of the first master IC 570a is set (3906), and timeout monitoring processing is started (3907). The update stage number is a number indicating the stage at which the effect mode of the effect device is updated by the effect control data, and is set for each master IC. The update stage number is stored in the RAM 553 of the effect control device 550.

  Further, in response to the command REG 581 of the first master IC 570a, the CPU 551 sets “1” to the STA, “1” to the STO, “0” to the SI, and “1” to the MODE (3908). In the processing of step 3908, “1” is set in MODE, so that data is transmitted and received in the buffer mode.

  Similarly, for the second master IC 570b, the CPU 551 sets the update stage number of the second master IC 570b to “0” (3909). Further, a monitoring timer is set (3910), and timeout monitoring processing is started (3911). Further, in response to the command REG 581 of the second master IC 570b, “1” is set in the STA, “1” in the STO, “0” in the SI, and “1” in the MODE (3912).

  The CPU 551 selects the first slave (decoration control device 610) of each master (3913). In each master IC, the order of slaves for transmitting the effect control data is set in advance. The first slave in the order is set in the process of step 3910, and the effect control data is sequentially transmitted to each slave connected to the first master IC 570a in the effect control data transmission restart process described later. Then, output data to each selected slave is prepared (3914).

  Further, the CPU 551 sets the retry counters of all master ICs to 0 (3915). The retry counter is a counter that is incremented when transmission fails when the production control data is transmitted to each master. When the retry counter becomes larger than a predetermined value, it can be determined that some trouble has occurred. Thereafter, the master interrupt and the timeout interrupt are permitted (3916).

  Subsequently, the CPU 551 edits the next data output to the VDP 556 (3917), and further edits the speaker related data output to the sound LSI 557 (3918).

  Further, the effect control device 550 executes slave output data editing processing for editing effect control data to be transmitted to the decoration control device 610 that controls the light emitter (3919). In the slave output data editing process, as described with reference to FIG. 36, the production control data of each slave is generated and stored in the output data preparation area secured on the RAM 553.

  Next, the effect control device 550 refers to the abnormality determination table 3200 shown in FIG. 32, and executes an error determination process related to the light emission control slave connected to the first master IC 570a (3920).

  In the error determination process, the effect control device 550 determines whether or not the error flags 3205 of the entries corresponding to the light emission control slaves in the abnormality determination table 3200 are all “ON”, that is, an error occurs in all the light emission control slaves. It is determined whether or not. In other words, it is determined whether or not there is at least one light emission control slave in which the error flag 3205 is “OFF”. If it is determined by this error determination process that an error has occurred in all the light emission control slaves, the conditions for resetting all the light emission control slaves connected to the first master IC 570a and the first master IC 570a are satisfied. It is assumed that.

  The effect control device 550 determines whether or not the reset condition is satisfied based on the result of the error determination process in step 3920 (3921). As described above, when the error flag 3205 of all the light emission control slaves is “ON” at the time of the error determination process in step 3920, it is determined that the reset condition is satisfied.

When it is determined that the reset condition is satisfied (the result of 3921 is “Y”), the effect control device 550 initializes the first master IC 570a (3922), and all the I connected to the first master IC 570a. ^2. The first master IC side slave initialization start process is executed to output initialization instruction data simultaneously to the CI / O expander 615 (decoration control device 610) (3923).

As described above, when it is determined that the reset condition is satisfied, in step 3717, all the I ² CI / O expanders 615 connected to the first master IC 570a are instructed to initialize at the same time. To do. That is, since all the I ² CI / O expanders 615 are selected and initialized at the same time, it is faster than the method of individually selecting the I ² CI / O expanders 615 and instructing the initialization. The I ² CI / O expander 615 can be quickly returned to the normal state. At this time, the CPU 551 writes the initialization instruction information to the reset REG 573 via the bus 563, thereby resetting the first master IC 570a in software.

  If it is determined that the reset condition is satisfied in the process of step 3921, an abnormality may have occurred in the first master IC 570a, so the first master IC 570a is also initialized in the process of step 3722. Yes.

  Since the first master IC 570a functions as signal level control means for controlling the signal levels of the connection lines SDA and SCL in response to a command from the CPU 551, an abnormality relating to data transmission has occurred in all the light emission control devices. In this case, an abnormality may have occurred in the first master IC 570a itself.

  Therefore, if an abnormality related to data transmission occurs in all the decoration control devices 610, the first master IC 570a is initialized by the CPU 551 (arithmetic processing means) just in case. Thus, even if an abnormality has occurred in the first master IC 570a, the first master IC 570a can be reliably controlled.

  Further, the effect control device 550 similarly executes error determination processing for the second master IC 570b (3924), and determines whether the reset condition is satisfied (3925). If the reset condition is satisfied, the second master IC 570b is reset (3926), and the second master IC side slave initialization start process for initializing the slave connected to the second master IC 570b is executed. (3927). Thereafter, the process returns to the process shown in FIG. 37 and waits until a synchronization signal is input from the VDP 556 to the CPU 551.

As described above, in the processing shown in FIGS. 37 to 39, the first master IC 570a and the second master IC 570b of the effect control device 550 are synchronized with the cycle of updating the image of the display device 53, and the decoration control device 610 I is synchronized. ² Transmit the effect control data to the CI / O expander 615. Since the I ² CI / O expander 615 controls the decoration device 620 based on the received effect control data, the effect on the display device 53 and the effect on the decoration device 620 are harmonized, giving the player a sense of discomfort. Because there is no, it can raise interest.

Further, whenever the decoration control device 610 receives the effect control data transmitted from the first master IC 570a and the second master IC 570b in synchronization with the cycle of updating the image on the display device 53, the I ² CI / O is received. The expander 615 updates the value of the work register (see FIG. 24). Therefore, since the value of the work register is updated to the latest state every time, even if the value of the work register is destroyed due to noise or the like, it can be restored to a normal value.

  In addition, since the error determination process is executed in Step 3920 and Step 3924 in synchronization with the cycle of updating the image of the display device 53, the frequency for determining the error can be set appropriately. That is, if the error determination process is executed too frequently, the processing load on the CPU 551 of the effect control device 550 increases. Conversely, if the error determination process is executed too little, the occurrence of an abnormality can be detected at an appropriate timing. Disappear. By performing the error determination in synchronization with the cycle of updating the image of the display device 53, it becomes possible to detect the error at an appropriate timing, and to appropriately cope with the occurrence of a defect in each process.

  FIG. 40 is a flowchart illustrating a processing procedure when a transmission interruption interrupt and a timeout interrupt occur on the first master IC 570a side according to the first embodiment of this invention.

  The transmission interruption interrupt is a so-called master interruption, and processing is executed according to the state at the time of interruption. The timeout interrupt is an interrupt that occurs when the monitoring timer set in the monitoring timer circuit 562 times out, and is used to monitor whether the transmission processing by the first master IC 570a is not completed within a predetermined time. It is. When a time-out interrupt occurs, the first master IC 570a is initialized.

First, when a master interrupt is generated from the first master IC 570a, the CPU 551 stops updating the monitoring timer of the monitoring timer circuit 562 and ends the timeout monitoring for the first master IC 570a (4001). Further, it is confirmed whether or not the status code of the first master IC 570a corresponds to “recovery” (4002). The status code is a value indicating the state of the master IC, and is set in the status register (REG) 582. In the process of step 4002, with reference to a transmission process continuation determination table 4400 described later with reference to FIG. 44, if the set status code is “70h” or “78h”, it is assumed that it corresponds to “recovery”. Determined. When the status code corresponds to “recovery”, the connection line SDA or the connection line SCL is occupied and released by the first master IC 570a or the slave (I ² CI / O expander 615) connected to the first master IC 570a. It is in a state where it cannot be done.

  The CPU 551 determines whether or not the status code of the first master IC 570a corresponds to “recovery” (4003). If not applicable (the result of 4003 is “N”), the initialization stage number and the update stage number of the first master IC 570a are acquired (4004).

  The CPU 551 determines whether or not the initialization stage number of the master IC to be initialized is “0” (4005). The case where the initialization stage number is “0” indicates that the initialization process is not being executed. That is, when the initialization stage number is other than “0”, it indicates that the initialization process is being executed.

  If the initialization stage number of the master IC to be initialized is not “0” (the result of 4005 is “N”), the CPU 551 is in the initialization process as described above, so the initialization instruction data A transmission resumption process is executed (4006). Details of the transmission restart processing of the initialization instruction data will be described later with reference to FIG.

  On the other hand, when the initialization stage number of the master IC to be initialized is “0” (result of 4005 is “Y”), the CPU 551 has already completed the initialization process, and transmits the effect control data. Since it is in the middle of the transmission, the transmission control processing for effect control data is executed (4007). Details of the transmission restart processing of the effect control data will be described later with reference to FIG.

  If the CPU 551 determines in the branch of step 4003 that the status code of the first master IC 570a corresponds to “recovery” (the result of 4003 is “Y”), the CPU 551 performs a soft reset on the first master IC 570a ( 4011) Next, in order to initialize the decoration control device 610 connected to the first master IC 570a, a first master-side slave initialization start process is executed (4011). The first master-side slave initialization start process is the same as the process described above with reference to FIG.

  FIG. 41 is a flowchart illustrating a processing procedure when a transmission interruption interrupt and a timeout interrupt occur on the second master IC 570b side according to the first embodiment of this invention.

  The processing when the transmission interruption interrupt and the timeout interruption occur on the second master IC 570b side is the same as the processing for the first master IC 570a shown in FIG. 40. Since it is good, explanation is omitted.

  FIG. 42 is a flowchart illustrating a procedure of the initialization restart data transmission restart process according to the first embodiment of this invention.

  The CPU 551 first determines whether or not to continue the transmission process of the initialization instruction data based on the status code (4201), and branches the process according to the determination result (4202). As described above, the status code is a value indicating the state of the master IC, and is set in the status register (REG) 582. In the process of step 4201, the transmission process of the initialization instruction data is continued with reference to the transmission process continuation determination table 4400 described later with reference to FIG. 44 based on the combination of the set status code and the current initialization stage number. It is determined whether or not to do. The relationship between the initialization stage number and the status code will be described in detail with reference to FIG.

  The initialization stage number is set to any value from “1” to “4” according to the processing stage when the master IC is being initialized. When completed, it is set to “0”. However, when initialization of the master IC is completed and the initialization stage number becomes “0”, the transmission restart process of the initialization instruction data is not called (the branch of step S4005 in the caller process of FIG. 40). Therefore, here, description will be made on the assumption that the initialization stage numbers are “1” to “4”.

  If the determination result based on the combination of the initialization stage number and the status code is not “continuous” (the result of 4202 is “N”), the CPU 551 is not in a normal state (for example, the data transmission has failed). Therefore, the value “1” indicating the start of initialization is set as the initialization stage number (4203). Further, a monitoring timer is set, and timeout monitoring is started (4204).

  Finally, the CPU 551 outputs “1” to the STA of the command REG581 of the master IC to be processed, “1” to the STO, “0” to the SI, and “0” to the MODE so as to output the stop condition and the start condition. The setting is made (4205), and the process returns to the calling process.

  On the other hand, when the determination result based on the combination of the initialization stage number and the status code is “continuation” (the result of 4202 is “Y”), the CPU 551 is executing the initialization process normally. Then, the process branches based on the initialization stage number (4206).

  When the initialization stage number is “1”, the CPU 551 sets a reset address in the output buffer 572 of the processing target master IC (4207).

  When “1” is set in the initialization stage number, it means that a start condition is output from the master IC. Referring to the transmission processing continuation determination table 4400 of FIG. 44, the status code is set to “08h” or “10h” indicating that a start condition or a restart condition is transmitted. Therefore, when the initialization stage number is set to “1” and the status code is set to “08h” or “10h”, the processing after step 4207 is executed.

  The CPU 551 increments the initialization stage number (4208), sets a monitoring timer, and starts time-out monitoring (4209). Finally, in order to continue the processing, “0” is set in each of the STA, STO, SI, and MODE of the command REG 581 of the processing target master IC (4210), and the processing returns to the calling source processing.

  When the initialization stage number is “2”, the CPU 551 sets the first half of the value indicating the reset command in the output buffer 572 of the master IC to be processed (4211).

  When “2” is set in the initialization stage number, it means that the reset address is set in the output buffer 572 of the master IC. Referring to the transmission processing continuation determination table 4400 in FIG. 44, the status code includes an ACK indicating that the slave address (here, the reset address) has been transmitted and that the signal has been normally received from each slave. “18h” indicating that the response has been made is set. However, the status code is set to “20h” when a NACK indicating that the signal cannot be normally received from each slave is returned. Accordingly, when “2” is set as the initialization stage number and “18h” is set as the status code, the processing after step 4211 is executed.

  When a value is set in the output buffer 572, the CPU 551 executes the processing from steps 4208 to 4210 as in the case where the initialization stage number is “1”.

  If the initialization stage number is “3”, the CPU 551 sets the latter half of the value indicating the reset command in the output buffer 572 of the master IC to be processed (4212).

  When “3” is set as the initialization stage number, it means that the first half value of the reset command is set in the output buffer 572 of the master IC. Referring to the transmission processing continuation determination table 4400 in FIG. 44, the status code is returned as an ACK indicating that the data set in the output buffer 572 has been transmitted and that the signal has been normally received from each slave. "28h" indicating that this is set. However, the status code is set to “30h” when a NACK indicating that the signal cannot be normally received from each slave is returned. Accordingly, when “3” is set as the initialization stage number and “28h” is set as the status code, the processing after step 4212 is executed.

  When a value is set in the output buffer 572, the CPU 551 executes the processing from steps 4208 to 4210 as in the case where the initialization stage number is “1”.

  When “4” is set in the initialization stage number, it means that the latter half value of the reset command is set in the output buffer 572 of the master IC. Referring to the transmission processing continuation determination table 4400 in FIG. 44, as in the case where the initialization stage number is “3”, “28h” or “30h” is set in the status code, and “28h” is set in the status code. In this case, the processing after step 4212 is executed.

  When the initialization stage number is “4”, the processing necessary for the initialization processing is completed, so the CPU 551 sets the error flags of all the decoration control devices 610 connected to the master IC to be processed to OFF. (4213) Further, the error counter is set to 0 and initialized (4214). Then, the initialization stage number is set to “0” indicating that the initialization process is not in progress. Finally, in order to complete the initialization process and to output a stop condition from the master IC to be processed to all the decoration control devices 610 connected to the master IC, the STO of the command REG 581 of the master IC to be processed is output. “1”, STA, SI, and MODE are set to “0” (4216), and the process returns to the caller process.

  FIG. 43 is a flowchart illustrating a procedure of resumption transmission processing of effect control data according to the first embodiment of this invention.

  The CPU 551 first determines processing to be executed based on the status code (4301), and determines whether the processing is “retransmission” (4302). In the process of step 4301, based on the combination of the value set in the status code and the update stage number, the process to be executed is determined with reference to the transmission process continuation determination table 4400 (FIG. 44).

  The update stage number is a number for controlling the timing of transmitting the presentation control data for each of the first master IC 570a and the second master IC 570b. Specifically, when the effect control periodic process (step 3707 in FIG. 37, FIG. 39) is executed, the update stage number is set to “0”. As will be described later, when the presentation control data is set in the output buffer 572, the update stage number is set to “1”.

  As described above, the status code is a value indicating the state of the master IC, and is set in the status register (REG) 582. The relationship between the update stage number and the status code will be described in detail with reference to FIG.

  If it is determined that the process is not “retransmission” based on the status code (the result of 4302 is “N”), the CPU 551 further determines whether or not the value of the update stage number is “0”. (4303). At this time, referring to FIG. 44, processing that is not “retransmission” includes “continuation” or “recovery”, but when the processing is “recovery” when a transmission interruption interrupt occurs, it is shown in FIG. 40 and FIG. As described above, the initialization process is executed without executing the transmission restart process of the production control data. Therefore, when the process is not “retransmission”, the process is always “continuation”.

  If the value of the update stage number is “0” (the result of 4303 is “Y”), the CPU 551 sets the data prepared on the RAM 553 in the output buffer 572 (4304). In this case (the update stage number value is “0” and the process is “continuation”), the status code is “08h” or “10h”, which corresponds to the state after the start condition is output.

  Further, the CPU 551 sets the value of the update stage number to “1” (4305), sets a monitoring timer, and starts monitoring timeout (4306). Finally, STA, STO and SI of the command REG 581 of the master IC to be processed are set to “0”, and MODE is set to “1” in order to transmit the data set in the output buffer 572 in the buffer mode. The setting is made (4307), and the process returns to the calling process.

  On the other hand, when the value of the update stage number is “1” (the result of 4303 is “N”), the CPU 551 sets the error flag corresponding to the selected slave (decoration control device 610) to “off”. (4308) Further, an error counter is initialized (4309). When the value of the update stage number is “1”, if the process is normally performed, “28h” indicating that data transmission has been completed normally is set in the status code.

  Thereafter, the CPU 551 determines whether or not the transmission resumption process has been completed for all the slaves (4310). When the processing is completed for all the slaves (result of 4310 is “Y”), a stop condition is output, and the STO of the command REG 581 is set so that the mode for transmitting data is designated as “buffer mode”. Then, “1” is set in MODE and MODE, and “0” is set in STA and SI (4311), and the process returns to the calling process.

  If the processing has not been completed for all the slaves (the result of 4310 is “N”), the CPU 551 sets the retry counter to 0 (4312) and selects the next slave to be processed (4313). ). Then, output data to the selected slave is prepared (4314), the update stage number is set to “0” (4315), a monitoring timer is set, and timeout monitoring is started (4316).

  Finally, the CPU 551 outputs a start condition and sets “1” to STA and MODE of the command REG581 and “0” to STO and SI so as to designate the mode for transmitting data as “buffer mode” (4317). ), Return to the calling process.

  When the CPU 551 determines that the process is retransmission based on the status code (the result of 4302 is “Y”), the CPU 551 increments the value of the retry counter (4318). Then, it is determined whether or not the value of the retry counter has reached the designated value (4319). The value designated at this time is set in the abnormality determination table 3200 or the abnormality determination table 3300 shown in FIG. 32 or 33, and corresponds to the comparison value 3204 corresponding to the currently selected slave.

  When the value of the retry counter has not reached the specified value (result of 4322 is “N”), the CPU 551 selects the slave again during the current selection (4320), and prepares data to be output to the selected slave. (4314), the processing after step 4315 is executed.

  On the other hand, when the value of the retry counter reaches the specified value (result of 4322 is “Y”), the CPU 551 sets “ON” to the error flag 3205 of the selected slave, and the processing after step 4310 Execute.

  FIG. 44 is a diagram illustrating an example of a transmission processing continuation determination table 4400 for determining continuation of data transmission resumption processing according to the first embodiment of this invention.

  The transmission process continuation determination table 4400 stores information for determining whether to continue the data transmission restart process as described above. The data transmission restart process includes an initialization instruction data transmission restart process (FIG. 42) and an effect control data transmission restart process (FIG. 43). The transmission process continuation determination table 4400 includes a process for each case. Continuation judgment is registered.

  The transmission process continuation determination table 4400 includes a status code 4401, initialization instruction data transmission resumption process continuation determination 4402, effect control data transmission resumption process continuation determination 4403, and state 4404.

  The status code 4401 is a value indicating the state of the master IC as described above.

  A state 4404 is a state of the master IC corresponding to the status code 4401. For example, when the status code is “08H”, it indicates a state where the transmission of the start condition is completed. Further, when the status code is “10H”, it indicates that the transmission of the start condition, that is, the transmission of the restart condition is completed.

  In the first embodiment of the present invention, if the connection line SDA or the connection line SCL is occupied for some reason and cannot be released, “70H” or “78H” is set in the status code 4401. Is done.

  Next, the continuation determination 4402 of the initialization instruction data transmission restart process corresponding to the status code and the continuation determination 4403 of the effect control data transmission restart process will be described.

  In the initialization instruction data transmission restart process, the process is executed for each stage corresponding to the initialization stage number, and the continuation determination 4402 of the initialization instruction data transmission restart process is defined for each initialization stage number. Specifically, as shown in the figure, “continuation”, “resumption” or “recovery” is defined corresponding to the combination of the value of the initialization stage number and the value of the status code.

  When the value of the continuation determination 4402 is “continuation”, it indicates that the initialization instruction data transmission restart process is being processed normally. Specifically, when the output of the start condition is successful when the initialization stage number is 1, or when the address transmission is successful when the initialization stage number is 2, the value of the continuation determination 4402 is “continue”. become. That is, when the process executed in the initialization instruction data transmission restart process and the status code set in the status register (REG) 582 match, the value of the continuation determination 4402 becomes “continue”.

  On the other hand, when the value of the continuation determination 4402 is “restart”, this indicates that the initialization instruction data transmission restart process is not normally processed, and the initialization instruction data transmission restart process needs to be restarted. It is shown that. That is, when the processing executed in the initialization instruction data transmission restart processing and the status code set in the status register (REG) 582 do not match, the value of the continuation determination 4402 becomes “restart”. This state occurs when transmission fails.

  Further, when the value of the continuation determination 4402 is “recovery”, it indicates that the connection line SDA or the connection line SCL is occupied and cannot be released. In this case, it is necessary to initialize the master IC corresponding to the occurrence of a transmission interruption interrupt and the slave connected to the master IC.

  In the effect control data transmission restart process, the process is executed based on the setting value of the update stage number, and the continuation determination 4403 of the effect control data transmission restart process is defined for each set value of the update stage number. Specifically, as shown in the figure, “continuation”, “retransmission” or “recovery” is defined corresponding to the combination of the value of the update stage number and the value of the status code.

  The update stage number is set to “1” at the first data transmission timing after the start condition is output, and is set to “0” when the data output preparation for one slave is completed. That is, when the initial setting is completed, the update stage number is set to “1”, and then data is continuously transmitted. The value of the continuation determination 4403 becomes “continuation” when the status code is set to “08H” or “10H” after the start condition transmission (update stage number “0”) and after the data transmission ( This is a case where the status code “28H” indicating the successful data transmission is set in the update stage number “1”).

  On the other hand, if the connection line SDA or the connection line SCL is occupied for some reason and cannot be released, data cannot be transmitted / received, so the master IC and the slave connected to the master IC are initialized. To restore the occupied state. Specifically, the status code 4401 is “70H” or “78H”.

  In other cases, that is, when the status code and the setting value of the update stage number do not match in a state where transmission / reception of data is possible, “retransmission” is set, and processing for retransmitting the presentation control data is performed. Executed.

  FIG. 45 is a flowchart illustrating a procedure of data transmission processing by the master IC according to the first embodiment of this invention. This process is common to the first master IC 570a and the second master IC 570b. When the CPU 551 sets “0” in the SI bit of the command register 581 (see FIGS. 11 and 12), the interrupt process is performed. The master IC that has been waiting due to the occurrence starts the processing.

  First, the controller 574 of the master IC determines whether or not the output of the start condition is requested, that is, whether or not “1” is set in the STA of the command REG 581 (4501).

  When the output of the start condition is requested (the result of 4501 is “Y”), the controller 574 executes the start condition output process (4502). The start condition output process executes a process necessary for outputting a start condition according to the signal levels of the connection line SCL and the connection line SDA. Details of the start condition output processing will be described later with reference to FIG.

  When the execution of the start condition output process is completed, the controller 574 sets the value of STCD as the status code (4503). STCD is a variable for substituting a status code to be set, and a predetermined value is set in a start condition output process, a data transmission process to a slave described later, and a stop condition output process. When a value is set in the status code, a transmission interruption interrupt is generated by setting “1” in the SI of the command REG581.

  Next, when the output of the start condition is not requested (the result of 4501 is “N”), the controller 574 determines whether or not the output of the stop condition is requested, that is, the STO of the command REG 581 is “1”. It is determined whether "" is set (4504).

  When the output of the stop condition is not requested (the result of 4504 is “N”), the controller 574 executes the data transmission process to the slave (4505). Then, the STCD value set in the data transmission process to the slave is set in the status code (4503). Thereafter, a transmission interruption interrupt is generated by setting “1” to the SI of the command REG581.

  When the output of the stop condition is requested (the result of 4504 is “Y”), the controller 574 executes the stop condition output process (4506). The stop condition output process executes a process necessary for executing the stop condition according to the signal levels of the connection line SCL and the connection line SDA. Details of the stop condition output processing will be described later with reference to FIG. After that, the STCD value set in the data transmission process to the slave is set in the status code (4507), and this process ends (a transmission interruption interrupt does not occur).

  FIG. 46 is a flowchart illustrating a procedure of start condition output processing according to the first embodiment of this invention.

  The start condition is output by changing the signal level of the connection line SDA from HIGH to LOW while maintaining the signal level of the connection line SCL at HIGH. In the start condition output process, a process corresponding to the signal level of each connection line at the start of the process is executed.

  When starting the start condition output process, the controller 574 first sets “08H” in the status code variable (STCD). “08H” indicates that the output of the start condition is completed.

  The controller 574 determines whether stop condition output is requested, that is, whether the value of STO of the command REG 581 is set to “1” (4602).

  The controller 574 sets the signal level of the connection line SCL to LOW when the output of the stop condition is requested and the signal level of the connection line SCL and the signal level of the connection line SDA are both HIGH (4603). Further, the signal level of the connection line SDA is set to LOW (4604), and the SCL release monitoring process is executed (4605). Details of the SCL release monitoring process will be described later with reference to FIG.

  The controller 574 releases the connection line SDA by turning off the transistor 578a (FIG. 11 or FIG. 12) (4606). At this time, if all other ICs (I / O expander 615, etc.) connected to the connection line SDA release the connection line SDA, the signal level of the connection line SDA is changed to HIGH.

  The controller 574 determines whether or not the signal level of the connection line SDA is HIGH (4607). If the signal level of the connection line SDA is HIGH (the result of 4607 is “Y”), the connection line SDA can be released. At this time, both the signal level of the connection line SCL and the signal level of the connection line SDA are HIGH. Is set.

  Then, the controller 574 sets the signal level of the connection line SDA to LOW by setting the transistor 578a (FIG. 11 or FIG. 12) to ON (4608). By performing the processing in this way, the start condition is established because the signal level of the connection line SDA is changed from HIGH to LOW while the signal level of the connection line SCL is maintained at HIGH.

  Subsequently, the controller 574 sets the signal level of the connection line SCL to LOW by setting the transistor 578b to ON (4609). Further, the FBF value is set to ON (4610). The FBF is a flag indicating that the start condition has been established. For example, when data is transmitted after the start condition is established, if the FBF is ON, the slave address since it is the first transmitted data. Judge. Then, by setting the FBF to OFF after receiving the address, each slave can recognize that the received data is presentation control data.

  On the other hand, if the signal level of the connection line SDA is not HIGH (the result of 4607 is “N”), the controller 574 determines whether or not the signal level of the connection line SDA has become HIGH until a predetermined time has elapsed. Determination is made (4611). When the predetermined time has elapsed (the result of 4611 is “Y”), it is determined that the connection line SDA is in the occupied state, and processing for releasing the connection line SDA from step 4612 is executed. Specifically, by not applying an operable voltage to the transistor 578a by the driver 576a, the signal level of the connection line SCL is changed at least nine times without turning on the transistor 578a (with the connection line SDA released). Let

  First, the controller 574 sets 0 to the value of a variable LP indicating the number of times that a signal has been input to the connection line SCL (4612). Further, the signal level of the connection line SCL is set to LOW by turning on the transistor 578a (4613). At this time, the signal level of the connection line SCL changes from HIGH to LOW. Further, by adding 1 to LP (4614), the number of changes in the signal level of the connection line SCL is counted.

  Subsequently, the controller 574 executes an SCL release monitoring process described later with reference to FIG. 47 (4615). Then, it is determined whether or not the value of LP has reached 9, that is, whether or not the number of signal level changes of the connection line SCL has reached 9 (4616). If the LP value has not reached 9 (the result of 4616 is “N”), the processing from step 4613 to 4615 is executed again.

The I ² CI / O expander 615 that has become a read mode (details will be described later) by the processing from steps 4612 to 4616 outputs data to the connection line SDA in accordance with the change in the signal level of the connection line SCL. While the signal level of the connection line SCL is changed at least nine times, a timing for confirming an acknowledge (ACK) signal from the master IC occurs. At this time, since the connection line SDA is released, the signal level becomes HIGH, and the I ² CI / O expander 615 that has entered the read mode determines that the acknowledge signal has not been received. SDA will be released.

In this way, the connection line SDA is forcibly released from the I ² CI / O expander 615 that has entered the read mode, so that the signal level of the connection line SDA is maintained high.

  When the number of changes in the signal level of the connection line SCL reaches 9 (the result of 4616 is “Y”), the controller 574 determines whether or not the output of the stop condition is requested (4617).

  When the output of the stop condition is requested (the result of 4617 is “Y”), the controller 574 sets the signal level of the connection line SCL to LOW (4618). Further, the signal level of the connection line SDA is set to LOW by setting the transistor 578a to ON (4619). Thereafter, the SCL release monitoring process is executed (4620), and then the SCL release monitoring process is executed (4621). Thereafter, the processing from step 4608 to 4610 is executed, and the processing returns to the calling source processing.

  Further, at the time of branching in step 4602, the controller 574 is requested to output a stop condition, and when the signal level of the connection line SCL is LOW and the signal level of the connection line SDA is HIGH, step 4604 and the subsequent steps. Execute the process. Further, when the output of the stop condition is requested at the time of branching in step 4602, the signal level of the connection line SCL is HIGH, and the signal level of the connection line SDA is LOW, the processing after step 4606 is executed. .

  The controller 574 sets the transistor 578a to OFF when the output of the stop condition is requested at the time of branching in step 4602 and both the signal level of the connection line SCL and the signal level of the connection line SDA are LOW. Thus, the connection line SDA is released (4622). Further, it is determined whether or not the signal level of the connection line SDA is HIGH (4623).

  If the signal level of the connection line SDA is not HIGH (the result of 4623 is “N”), the controller 574 determines whether or not the signal level of the connection line SDA has become HIGH until a predetermined time has elapsed. (4625). When a predetermined time elapses (the result of 4625 is “Y”), it is determined that the connection line SDA is occupied, SCL release monitoring processing is executed (4626), and the connection line SDA after step 4612 is released. Execute the process.

  On the other hand, if the signal level of the connection line SDA is HIGH (the result of 4623 is “Y”), the controller 574 further determines whether or not a stop condition is requested (4624). When the stop condition is requested (the result of 4624 is “Y”), the processing after step 4604 is executed.

  When the stop condition is not requested (the result of 4624 is “N”), the controller 574 executes the SCL release monitoring process (4627) and confirms that the start condition re-output (restart condition) has been completed. “10H” shown is set in the STCD (4628). Thereafter, the processing after step 4608 is executed.

  In addition, the controller 574 determines that the number of changes in the signal level of the connection line SCL reaches nine (the result of 4616 is “Y”), and further, when the output of the stop condition is not requested (the result of 4617 is "N"), it is determined whether or not the signal level of the connection line SDA is HIGH (4629).

  If the signal level of the connection line SDA is not HIGH (the result of 4629 is “N”), the controller 574 determines whether or not the signal level of the connection line SDA has become HIGH until a predetermined time has elapsed. (4630). When a predetermined time elapses (result of 4630 is “Y”), it is determined that the connection line SDA is occupied, “70H” is set in the status code (4631), and a transmission interruption interrupt is generated. .

  At the time of branching of step 4602, the controller 574 does not require the output of the stop condition, and if the signal level of the connection line SCL is HIGH and the signal level of the connection line SDA is LOW, the connection line SDA Is set to LOW (4632), and the processing after step 4622 is executed.

  At the time of branching in step 4602, the controller 574 does not request output of a stop condition, and if both the signal level of the connection line SCL and the signal level of the connection line SDA are LOW, the controller 574 performs the processing from step 4622 onward. Execute.

  At the time of branching in step 4602, the controller 574 is not required to output a stop condition, and when the signal level of the connection line SCL is LOW and the signal level of the connection line SDA is HIGH, step 4627 and subsequent steps. Execute the process.

  If the controller 574 does not request stop condition output at the time of branching in step 4602 and both the signal level of the connection line SCL and the signal level of the connection line SDA are HIGH, the processing after step 4608 is performed. Execute.

  FIG. 47 is a flowchart illustrating a procedure of SCL release monitoring processing according to the first embodiment of this invention.

  When the SCL release monitoring process is started, the controller 574 releases the connection line SCL by turning off the transistor 578b (FIG. 11 or FIG. 12) (4701). At this time, if all other ICs (I / O expander 615, etc.) connected to the connection line SCL release the connection line SCL, the signal level of the connection line SCL is changed to HIGH. Subsequently, it is determined whether the signal level of the connection line SCL is changed to HIGH and the connection line SCL is released (4702).

  When the signal level of the connection line SCL is HIGH (the result of 4702 is “Y”), the controller 574 returns to the caller process because the process was successful. On the other hand, if the signal level of the connection line SCL is not HIGH (the result of 4702 is “N”), it is determined whether or not the signal level of the connection line SCL has become HIGH until a predetermined time has elapsed. (4703).

  If the signal level of the connection line SCL does not become HIGH even after a predetermined time has elapsed (the result of 4703 is “Y”), the controller 574 displays “78H” indicating that the connection line SCL cannot be released as a status code. (4704) to generate a transmission interruption interrupt.

  FIG. 48 is a flowchart illustrating a procedure of SDA release monitoring processing according to the first embodiment of this invention.

  When the SDA release monitoring process is started, the controller 574 releases the connection line SDA by turning off the transistor 578a (FIG. 11 or FIG. 12) (4801). At this time, if all other ICs (I / O expander 615, etc.) connected to the connection line SDA release the connection line SDA, the signal level of the connection line SDA is changed to HIGH.

  Then, the controller 574 determines whether or not the signal level of the connection line SDA is HIGH (4802). If the signal level of the connection line SDA is HIGH (the result of 4802 is “Y”), the connection line SDA can be released, and the process returns to the caller process.

  On the other hand, if the signal level of the connection line SDA is not HIGH (the result of 4802 is “N”), the controller 574 determines whether the signal level of the connection line SDA has become HIGH until a predetermined time has elapsed. It is determined whether or not (4802).

  If the signal level of the connection line SDA does not become HIGH even after a predetermined time has elapsed (the result of 4803 is “Y”), the controller 574 performs an SCL release monitoring process (FIG. 47) for releasing the connection line SCL. Execute and release the connection line SCL (4804). Thereafter, “70H” indicating that the connection line SDA cannot be released is set in the status code (4805), and a transmission interruption interrupt is generated.

FIG. 49 is a flowchart illustrating a procedure of data transmission processing to the slave-side I ² CI / O expander 615 according to the first embodiment of this invention.

  First, the controller 574 initializes a variable CTR for storing the number of data transmissions to 0 (4901). Subsequently, the signal level of the connection line SCL is set to LOW by turning on the transistor 578b (FIG. 11 or FIG. 12) (4902). Then, by executing the SDA release monitoring process (4903), the signal level of the connection line SDA is set to be changed to HIGH. At this time, all other ICs (I / O expander 615, etc.) connected to the connection line SDA have released the connection line SDA.

  The controller 574 determines whether or not the value of the variable CTR is 8, that is, whether or not the number of data transmissions has reached 8 (4904). If the number of data transmissions has not reached eight (the result of 4904 is “N”), data is output to the slave via the connection line SDA, and 1 is added to CTR (4905). Subsequently, the SCL release monitoring process is executed (4906), and further data is output by executing the processes after step 4902.

On the other hand, when the number of data transmissions reaches 8 (the result of 4904 is “Y”), the controller 574 outputs a response signal from the I ² CI / O expander 615 on the slave side via the connection line SDA. (4907).

  The controller 574 fetches the output response signal from the connection line SDA (4908), and executes SCL release monitoring processing (4909). Further, it is determined whether or not the content of the response signal fetched in the process of step 4908 is “ACK” (4910).

  When the content of the response signal from the slave is “ACK” (result of 4910 is “Y”), the controller 574 sets the signal level of the connection line SCL to LOW by turning on the transistor 578b ( 4911), the connection line SDA is released by the slave (4912). Further, it is determined whether or not the current data transmission mode is the buffer mode (4913).

  If the current data transmission mode is the buffer mode (the result of 4913 is “Y”), the controller 574 determines whether or not the transmission of the last byte has been completed (4914). When transmission of the last byte is not completed and data is transmitted (result of 4914 is “N”), the FBF value is set to OFF, and the variable CTR indicating the number of data transmissions is set to 0. (4915). As described above, the FBF is a flag indicating that the start condition has been established, and is set to OFF after the initial data transmission, thereby indicating that the transmission of the slave address has been completed. Can be handled.

  Thereafter, the controller 574 determines whether or not the signal level of the connection line SDA is HIGH (4916). When the signal level of the connection line SDA is not HIGH (the result of 4916 is “N”), the process waits for a predetermined time (4917). If the signal level of the connection line SDA is not HIGH even after the predetermined time has elapsed (the result of 4917 is “Y”), the status code is set to 70H (4918), and a transmission interruption interrupt is generated. On the other hand, when the signal level of the connection line SDA is HIGH (the result of 4916 is “Y”), the processing after step 4902 is executed to transmit the next data.

  When the current data transmission mode is not the buffer mode, that is, in the byte mode (result of 4913 is “N”), or when the last byte transmission is completed (the result of 4914 is “Y ]), It is determined whether or not the FBF is set to ON (4919). When the FBF is set to ON (the result of 4919 is “Y”), the FBF is set to OFF and the status code “18H” indicating that the address transmission is successful is set to the STCD (status code). (4920). On the other hand, when the FBF is not set to ON (result of 4919 is “N”), the status code “28H” indicating that the data transmission is successful is set in the STCD (4921).

  Further, the controller 574 determines that the response signal from the slave is not “ACK”, that is, “NACK” indicating that data could not be received (result of 4910 is “N”), the signal level of the connection line SCL is set to LOW by setting the transistor 578b to ON (4922).

  Further, the controller 574 determines whether or not the FBF is set to ON (4923). When the FBF is set to ON (result of 4923 is “Y”), the status code 20H indicating that the address transmission has failed is set in the STCD (4924). On the other hand, if the FBF is not set to ON (result of 4923 is “N”), the status code 30H indicating that the data transmission has failed is set in the STCD (4925). When the above process ends, the process returns to the caller process.

  FIG. 50 is a flowchart illustrating a procedure of stop condition output processing according to the first embodiment of this invention.

  The stop condition is output by changing the signal level of the connection line SDA from LOW to HIGH while maintaining the signal level of the connection line SCL at HIGH. In the stop condition output process, the process is executed according to the signal level of each connection line at the start of the process.

  When starting the stop condition output process, the controller 574 branches the process according to the signal levels of the connection line SCL and the connection line SDA (5001).

  When both the signal level of the connection line SCL and the signal level of the connection line SDA are HIGH, the controller 574 sets the signal level of the connection line SCL to LOW by turning on the transistor 578b (FIG. 11 or FIG. 12). Set (5002). After the processing of step 5002 is completed, or when the signal level of the connection line SCL is LOW and the signal level of the connection line SDA is HIGH, the transistor 578a (FIG. 11 or FIG. 12) is set to ON. Then, the signal level of the connection line SDA is set to LOW (5003).

  The controller 574 executes an SCL release monitoring process for releasing the connection line SCL after the processing of step 5003 is completed or when both the signal level of the connection line SCL and the signal level of the connection line SDA are LOW. (5004).

  The SCL release monitoring process is a process for enabling data transmission / reception by setting the signal level of the connection line SCL at the LOW level to HIGH. The details of the SCL release monitoring process are as described in FIG. When the SCL release monitoring process ends normally, the signal level of the connection line SCL is set to HIGH. If the signal level of the connection line SCL cannot be set to HIGH and the connection line SCL cannot be released, a transmission interruption interrupt is generated.

  The controller 574 performs SDA release monitoring for releasing the connection line SDA after the processing of step 5004 is completed or when the signal level of the connection line SCL is HIGH and the signal level of the connection line SDA is LOW. Processing is executed (5005).

  The SDA release monitoring process is a process of changing the signal level of the connection line SDA from LOW to HIGH. If the connection line SDA is occupied for some reason and the signal level remains LOW, it is occupied. A process of releasing the connection line SDA is included. The details of the SDA release monitoring process are as described with reference to FIG. Note that when the SCL release monitoring process ends normally, the signal level of the connection line SDA is changed from LOW to HIGH, and at this time, the signal level of the connection line SCL is maintained at HIGH, so that the stop condition is established. To do. If the connection line SDA cannot be released, a transmission interruption interrupt is generated.

FIGS. 51 to 53 are flowcharts illustrating processing procedures in the slave-side I ² CI / O expander 615 according to the first embodiment of this invention.

FIG. 51 is a flowchart illustrating a processing procedure in the slave I ² CI / O expander 615 according to the first embodiment of this invention.

The slave-side I ² CI / O expander 615 executes various controls by the bus controller 634 as described with reference to FIG.

First, when a reset signal is generated by the reset signal generation circuit 639 (see FIG. 18, the same applies hereinafter), the bus controller 634 executes initialization processing of itself (I ² CI / O expander 615) (5101). At this time, the transistor 630 is turned off by the driver 632 and the connection line SDA is released. In addition, the driver 637 turns off all of the transistors 638A to 638P connected to the ports 0 to 15. Further, the output setting register 635 is set to a predetermined initial state. Next, the signal levels of the connection line SCL and the connection line SDA are captured. And it waits until it becomes the state 5103 in which the signal level of both the connection line SCL and the connection line SDA is HIGH (5102).

  When the connection line SCL and the connection line SDA are in the state 5103 (the result of 5102 is “Y”), the bus controller 634 waits until the signal level of either the connection line SCL or the connection line SDA changes ( 5104).

  When the signal level of the connection line SDA changes to LOW from the state 5103 (result of 5104 is “SDAＤＡ”), the bus controller 634 sets the variable CN to 0, sets the state number to 1, and sets the data Is cleared (5105). The variable CN is a counter indicating the number of times data has been received. Further, the state number is set according to a signal transmitted from the master, and corresponds to, for example, a process requested by the slave (write process, read process, etc.). Note that when the signal level of the connection line SDA changes from LOW in the state 5103 in which the signal levels of the connection line SCL and the connection line SDA are both HIGH, this corresponds to the start condition being output from the master IC. 1 indicates that a start condition has been output.

  At this time, the signal level of the connection line SCL is HIGH and the signal level of the connection line SDA is LOW. The bus controller 634 waits until the signal level of the connection line SCL or the connection line SDA changes (5107).

  When the signal level of the connection line SCL changes to LOW from the state 5106 (the result of 5107 is “SCL ▽”), the bus controller 634 receives the data eight times, that is, whether or not the variable CN has become 8. It is determined whether or not (5108). If the value of the variable CN is not 8 (the result of 5108 is “N”), the signal level of the connection line SCL and the connection line SDA is both LOW at this stage. Thereafter, the process waits until the signal level of the connection line SCL or the connection line SDA changes (5110).

  When the signal level of the connection line SDA changes to HIGH (the result of 5110 is “SDAΔ”), the bus controller 634 indicates that the signal level of the connection line SCL is LOW and the signal level of the connection line SDA is HIGH. The process proceeds to 5111 and waits until the signal level of the connection line SCL or the connection line SDA changes (5112).

  When the signal level of the connection line SDA changes to LOW (the result of 5112 is “SDA ▽”), the bus controller 634 proceeds to the state 5109 until the signal level of the connection line SCL or the connection line SDA changes. Wait (5110).

  On the other hand, when the signal level of the connection line SCL changes to HIGH (the result of 5112 is “SCLΔ”), the bus controller 634 determines whether the state number is 1 or 2, that is, after the start condition is output. Or whether the requested process is a write request (5115).

  When the state number is 1 or 2 (the result of 5115 is “Y”), the bus controller 634 adds 1 to the value of the variable CN and takes in the data stored in the reception buffer (5116). When the state number is not 1 or 2 (the result of 5115 is “N”) or when the processing of step 5116 is completed, the state 5103 in which the signal levels of the connection line SCL and the connection line SDA are both HIGH is obtained, and the connection line SCL or Wait until the signal level of the connection line SDA changes (5104).

  In the state 5103 in which the signal levels of the connection line SCL and the connection line SDA are HIGH, the bus controller 634 changes the signal level of the connection line SCL to LOW (the result of 5104 is “SCL バ ス”). It is determined whether or not 8 has been reached, that is, whether or not data has been received 8 times (5117). If the value of the variable CN is not 8 (the result of 5117 is “N”), the signal level of the connection line SCL is LOW and the signal level of the connection line SDA is HIGH at this stage. Therefore, the processing after step 5112 is executed. On the other hand, when the value of the variable CN becomes 8 (the result of 5117 is “Y”), the processing after step 5201 shown in FIG. 52 is executed.

  In addition, in the state 5106 in which the signal level of the connection line SCL is HIGH and the signal level of the connection line SDA is LOW, the bus controller 634 changes the signal level of the connection line SDA to HIGH (the result of 5107 is “SDA”). Δ ”), it is determined whether or not the state number is 2, that is, the requested process is a read request (5118). Note that the change of the signal level of the connection line SDA from HIGH in the state 5106 in which the signal level of the connection line SCL is HIGH and the signal level of the connection line SDA is LOW corresponds to the output of the stop condition.

  If the state number is 2 (the result of 5118 is “Y”), the bus controller 634 is informed. The data stored in the preparation area is stored in the setting register (5119). When the state number is not 2 (the result of 5118 is “N”) or when the processing of step 5119 is completed, 0 is set to the state number (5120). At this time, since the signal levels of both the connection line SCL and the connection line SDA are in the high state 5103, the process waits until the signal level of the connection line SCL or the connection line SDA changes (5104) and the processing is continued. .

FIG. 52 is a flowchart illustrating a procedure of address recognition processing and the like in the slave-side I ² CI / O expander 615 according to the first embodiment of this invention.

Note that the I ² CI / O expander 615 used in the present embodiment can be used regardless of whether the read mode can be generated or not. Therefore, the flowchart will be described assuming that any type of I ² CI / O expander 615 is provided.

  Here, the reading mode will be described.

In the present embodiment, each time transmitting data of a predetermined unit of bytes from the master IC to the ^I 2 CI / O expander ^615, the configuration for receiving a response signal 1 bit from I 2 CI / O expander 615 to the master IC The production control data is transmitted from the master IC to the I ² CI / O expander 615.

By the way, depending on the gaming machine, it may be more convenient to be able to configure data transmission of a predetermined unit byte from the I ² CI / O expander 615 to the master IC. For example, the I ² CI / O expander 615 may detect a detection state of various sensors related to a game and develop a gaming machine having a specification that can be transmitted to a master IC.

The I ² CI / O expander 615 used in such a game machine generates a “read mode” inside the I ² CI / O expander 615 in response to a request from the master IC, and generates an SCL signal from the master IC. in correspondence with the ^change, transmitted per transmitting data of a predetermined unit of bytes from the I 2 CI / O expander 615 to the master IC, a response signal 1 bit to the ^I 2 CI / O expander 615 from the master IC It is preferable to adopt a configuration to do so.

Specifically, the read mode is generated when the bit of the R / W identification data 2204 is “1” in the address data transmitted from the master IC to the I ² CI / O expander 615 on the slave side. This request is defined in advance as a request (hereinafter referred to as a “read request”).

  When the signal level of the connection line SCL changes to LOW with the signal levels of the connection line SCL and the connection line SDA being HIGH (the result of 5104 in FIG. 51 is “SCL ▽”), the bus controller 634 When reception is performed eight times, that is, when data reception is completed (result of 5117 is “Y”), the connection line SDA is released on the master IC side (5201).

Subsequently, the bus controller 634 determines whether or not the state number is 1, that is, whether or not it is immediately after the start condition is output (5202). If the status number is 1 (the result of 5202 is “Y”), it is confirmed whether or not the received address matches the address assigned to itself (I ² CI / O expander 615) ( 5203, 5204).

If the received address does not match its own address (the result of 5204 is “N”), the state number is set to 0 (5217), and the processing after step 5213 is executed. Here, even when the received address corresponds to the above-mentioned “read request” and the I ² CI / O expander 615 that performs the process cannot generate the read mode, the step 5204 is performed. The determination result is “N”.

  On the other hand, if the received address matches its own address (the result of 5204 is “Y”), it is determined whether or not the requested process is a read request (5205). If the requested process is a read request (the result of 5205 is “Y”), the processes after step 5301 in FIG. 53 are executed.

  On the other hand, if the requested process is not a read request, that is, if it is a write request (result of 5205 is “N”), the bus controller 634 sets 2 as the corresponding state number (5206).

Thereafter, the bus controller 634 drives the driver 632 to turn on the transistor 630, thereby setting the signal level of the connection line SDA to LOW and starting the occupation of the signal line. Further, the self-occupied WDT 641 is operated to start monitoring the bus by the self-occupied WDT 641 (5207). The self-occupied WDT 641 starts a timer when the bus controller 634 starts to occupy the bus, and resets itself (I ² CI / O expander 615) when a predetermined time elapses. By processing in this way, even when the connection line SDA is continuously occupied, the occupation can be released by reset when the time set in the self-occupied WDT 641 has elapsed. At this time, the influence on others can be minimized by resetting only itself.

  At this time, the signal levels of the connection line SCL and the connection line SDA are both LOW, and the bus controller 634 waits until the signal level of the connection line SCL changes to HIGH (5209).

  When the signal level of the connection line SCL changes to HIGH (result of 5209 is “SCLΔ”), the bus controller 634 enters a state 5210 where the signal level of the connection line SCL is HIGH and the signal level of the connection line SDA is LOW. Further, it waits until the signal level of the connection line SCL changes to LOW (5211).

  When the signal level of the connection line SCL changes to LOW (the result of 5209 is “SCL ▽”), the bus controller 634 releases the connection line SDA by driving the driver 632 to turn off the transistor 630, and the self-occupied WDT 641. The bus monitoring by the self-occupied WDT 641 is terminated (5212). Then, the value of the variable CN is set to 0, and the reception buffer is cleared (5213). At this time, the signal level of the connection line SCL is LOW, the signal level of the connection line SDA is HIGH, and the state 5111 in FIG. 51 is obtained, so the processing from step 5112 onward in FIG. 51 is executed.

  If the status number is not 1 in the process of step 5202 (result of 5202 is “N”), the bus controller 634 determines whether the reception is successful (5214, 5215). If the reception is successful (the result of 5215 is “Y”), the data in the reception buffer is stored in the preparation area (5216), and the processing after step 5207 is executed.

  On the other hand, when the data reception has failed (the result of 5215 is “N”), the bus controller 634 sets the state number to 0 (5217), and executes the processing after step 5213.

FIG. 53 is a flowchart illustrating a procedure of data read processing in the slave-side I ² CI / O expander 615 according to the first embodiment of this invention.

  If the processing requested from the master IC is a read request (the result of 5205 in FIG. 52 is “N”), the bus controller 634 sets the state number to 3 corresponding to the read processing (5301).

  Thereafter, the bus controller 634 drives the driver 632 to turn on the transistor 630, thereby setting the signal level of the connection line SDA to LOW and starting the occupation of the signal line. Further, the self-occupied WDT 641 is operated to start monitoring the bus by the self-occupied WDT 641 (5302). At this time, both the signal levels of the connection line SCL and the connection line SDA are in the state 5303 in which they are LOW, and the bus controller 634 waits until the signal level of the connection line SCL changes to HIGH (5304).

  When the signal level of the connection line SCL changes to HIGH (the result of 5304 is “SCLΔ”), the bus controller 634 enters the state 5305 and waits until the signal level of the connection line SCL changes to LOW (5306). .

  When the signal level of the connection line SCL changes to LOW (the result of 5306 is “SCL ▽”), the bus controller 634 releases the connection line SDA by driving the driver 632 to turn off the transistor 630, and the self-occupied WDT 641. And the monitoring of the bus by the self-occupied WDT 641 is terminated (5307).

  Further, the bus controller 634 sets the value of the variable CN to 0 (5308), and outputs data to the connection line SDA (5309). At this time, when a LOW level signal is output to the connection line SDA, the self-occupied WDT 641 is operated to start monitoring the bus by the self-occupied WDT 641. When a HIGH level signal is output to the connection line SDA, the self-occupied WDT 641 is not operated (5310). This is because the bus is not occupied if the signal level of the connection line SDA is HIGH.

  At this time, the bus controller 634 waits until the signal level of the connection line SCL is LOW (5311) and the signal level of the connection line SCL changes to HIGH (5312). When the signal level of the connection line SCL changes to HIGH (the result of 5312 is “Y”), 1 is added to the value of the variable CN (5313). Then, the state 5314 in which the signal level of the connection line SCL is HIGH is entered, and the process waits until the signal level of the connection line SCL changes to LOW (5315). When the signal level of the connection line SCL changes to LOW (the result of 5315 is “SCL ▽”), when the bus is monitored by the self-occupied WDT 641, the self-occupied WDT 641 is stopped and the bus is monitored by the self-occupied WDT 641. The process ends (5316).

  The bus controller 634 determines whether or not the value of the variable CN has reached 8, that is, whether or not all eight data have been output to the connection line SDA (5317). If the output of all the data has not been completed (the result of 5317 is “N”), the next data is output to the connection line SDA (5318), and the processing after step 5310 is executed.

  On the other hand, the bus controller 634 reaches the value of the variable CN, completes transmission of all data (the result of 5317 is “Y”), drives the driver 632, and turns off the transistor 630, thereby connecting the connection line. The SDA is released (5319). However, since the processing of step 5319 is necessary only when the bus controller 634 has set the connection line SDA to the LOW level, the bus controller 634 has set the connection line SDA to the HIGH level. No need to run.

  At this time, since the signal level of the connection line SCL becomes LOW and the signal level of the connection line SDA becomes HIGH (5320), the process waits until the signal level of the connection line SCL becomes HIGH (5321).

At this time, data in units of 8 bits has already been transmitted from the I ² CI / O expander 615 to the master IC 570a (see FIG. 11 and the master IC 570b in FIG. 12). When the next data is received, an ACK response signal is transmitted from the master IC 570a (570b) to the I ² CI / O expander 615.

  When the signal level of the connection line SCL becomes HIGH (the result of 5321 is “SCLΔ”), the bus controller 634 takes in the signal level (response signal) of the connection line SDA (5322). Then, it is determined whether or not the captured response signal is ACK (LOW level), that is, whether or not the master IC is ready to receive the next data (5323).

  At this time, if the captured response signal is ACK (result of 5323 is “Y”), the signal level of the connection line SCL is HIGH and the signal level of the connection line SDA is LOW (5324). The bus controller 634 waits until the signal level of the connection line SCL changes to LOW (5325). When the signal level of the connection line SCL changes to LOW (the result of 5325 is “SCL ▽”), the value of the variable CN is set to 0 (5326), and the processing after step 5318 is performed to output the next data. Execute.

  On the other hand, when the captured response signal is NACK (the result of 5323 is “N”), the bus controller 634 sets the variable CN to 0, the state number to 0, and further clears the reception buffer ( 5327). At this time, the signal levels of the connection line SCL and the connection line SDA are both HIGH, and the processing of step 5104 in FIG. 51 is executed corresponding to the state 5103 in FIG.

  Next, the timing at which data is exchanged between the CPU 551 of the effect control device 550 and the first master IC 570a and the second master IC 570b in the first embodiment of the present invention will be described.

  FIG. 54 is a timing diagram showing a state in which processing by the first master IC 570a and the second master IC 570b is executed in parallel according to an instruction from the CPU 551 of the effect control device 550 at the time of VDP interruption according to the first embodiment of this invention. It is a chart.

  In the first embodiment of the present invention, when a VDP interrupt occurs at the timing of updating the image displayed on the display device 53, the CPU 551 of the effect control device 550 outputs the effect control data to each master IC. Start. When each master IC receives the effect control data from the CPU 551, the master IC performs processing such as transmitting the received effect control data to each slave independently of the other master ICs. When the output of the effect control data is completed for all the slaves, each master IC outputs a stop condition and updates the effect mode of the effect device (decoration device 620) controlled by each slave.

  In this way, the processing by the first master IC 570a and the second master IC 570b is executed in parallel, and further, the effect that is harmonized with the image display is achieved by synchronizing the update timing of the effect mode of each effect device with the VDP interrupt. Can be performed.

  More specifically, when the VDP interrupt occurs, the CPU 551 of the effect control device 550 executes effect control periodic processing (step 3707 in FIG. 37, FIG. 39) and outputs a start condition to each master IC. .

  Then, CPU 551 edits output data to each device controlled by effect control device 550. Specifically, VDP output data editing for performing an effect on the display device 53 (step 3917 in FIG. 39), speaker-related data editing for outputting audio from the speaker 30 (step 3918 in FIG. 39), and an effect device Editing of the effect control data to be output to the decoration control device 610 that controls the LED (step 3919 in FIG. 39) and data editing for controlling a driving body such as a motor are performed. If a master interrupt to the CPU 551 is generated by each master IC during the execution of these editing processes, the edited effect control data is stored in the output buffer 572 of each master IC by the effect resumption data transmission restart process (FIG. 43). Written. Then, the effect control data is output to each slave by the data transmission process by the master shown in FIG.

  In addition, during the pause period (the period marked with * in FIG. 54) from the end of data output to the last slave until the next VDP interrupt occurs, the CPU 551 performs slave output data editing processing, that is, downlink data. Editing. Therefore, since data is processed even when data is not transmitted to the slave (group unit control means), it is possible to utilize the processing capability of the master IC (group overall control means), and the load on the master IC is leveled out. Can be

  Finally, when the production control data is transmitted to all the slaves to be transmitted, a stop condition is output from the master IC to the slave by the transmission restart process of the production control data (step S4311 in FIG. 43). The effect control data received by each slave is reflected in the effect mode of each effect device.

  Thereafter, the CPU 551 waits until the next VDP interrupt occurs. Then, when the next VDP interrupt occurs, the above-described effect control periodic processing (step 3707 in FIG. 37, FIG. 39) is executed, a start condition is output to each master IC, and thereafter the same processing is repeated.

  Next, a configuration example of the grouped effect device (decoration device 620) will be described.

FIG. 55 is a diagram illustrating an example of connection between the I ² CI / O expander 615 of the decoration control device 610 and the decoration device 620 according to the first embodiment of the present invention. it is a diagram showing a configuration for controlling the I ² CI / O expander 615.

  It is assumed that the decoration device 620 is configured by an LED as an example. By controlling the three colors of red (R), green (G), and blue (B) as one set, it is possible to emit light in various colors. Make it possible. For example, when all red, green, and blue LEDs are colored, white light can be emitted.

In the first embodiment of the present invention, one I ² CI / O expander 615 can control the LEDs corresponding to the 16 ports (PORT 0 to 15). Up to 5 sets of LEDs can be connected.

However, in order to produce an effect that further enhances interest, there may be a case where an LED (production device) is connected to more than 16 ports. FIG. 55 illustrates a configuration in which five or more sets (eight sets) of LEDs are connected and controlled across two I ² CI / O expanders 615.

As described above, since the I ² CI / O expander 615 includes 16 ports (PORT 0 to 15), it is possible to connect up to 5 sets of three color LEDs. However, when the presentation is performed with eight sets of LEDs as one group, at least two I ² CI / O expanders 615 are required.

Therefore, in the configuration shown in FIG. 55, one I ² CI / O expander 615 controls the red and green LEDs of each set, and the other I ² CI / O expander 615 (615b) The blue LED is controlled. Then, these two I ² CI / O expanders 615 are controlled as the same group, and, as will be described later with reference to FIG. 56A, the effect control is executed simultaneously after receiving the stop condition output from the effect control device 550. As a result, it is possible to produce an effect by the LEDs controlled by the plurality of I ² CI / O expanders 615 without a sense of incongruity.

  FIG. 56A is a diagram illustrating the timing at which the decoration control device 610 receives data and controls the effect device according to the first embodiment of the present invention, and reflects the data received at the time when the stop condition is output. It is a figure explaining about.

In this figure, first, the start condition is output from the effect control device 550, then the effect control data is sequentially output from the effect control device 550 to the plurality of I ² CI / O expanders 615, and finally, the effect control device. A state in which a stop condition is output from 550 is shown. For convenience of explanation, it is assumed that five I ² CI / O expanders 615 of the decoration control device 610 are provided, and each of them is a first I ² CI / O expander to a fifth I ² CI / O expander.

Here, “data1” in the figure indicates the effect control data transmitted from the effect control device 550 to the first I ² CI / O expander. Hereinafter, “data2” to “data5” The effect control data transmitted from the effect control device 550 to each of the ^{second I 2} CI / O expander to the fifth I ² CI / O expander is shown.

Also, in the drawing, “Production device (1)” indicates an LED or the like connected to the I / O port of the first I ² CI / O expander. "-" effect device (5) "is the first ^2I 2 CI / O expander, second ^5I 2 CI / O Aix LED is connected to the expander of the I / O ports, etc., respectively correspond.

Incidentally, the effect control device 550, when transmitting the performance control data to the ^1I 2 CI / O expander, second ^5I 2 CI / O expander Each ^of timing for switching the selection of the I 2 CI / O expander Thus, a start condition (functioning as a restart condition) is output from the effect control device 550 to the I ² CI / O expander. However, from when the effect control device 550 first outputs the start condition to when the effect control data is transmitted to all of the first I ² CI / O expander to the fifth I ² CI / O expander (in the figure). During the period indicated by T), the stop condition is not output, and the stop condition is output after the elapse of the period T.

In the first embodiment of the present invention, the effect control data is serially transmitted from the connection line SDA, so that there is a time difference in the timing at which the effect control data arrives for each I ² CI / O expander. Each I ² CI / O expander temporarily secures the effect control data received in a buffer (not shown) built in the bus controller 634 (FIG. 18) when the effect control data is received from the effect control device 550. It ’s just that.

Here, it is assumed that each I ² CI / O expander independently performs a process that changes the light emission mode of the LED simultaneously with the reception of the effect control data. Since there is a time difference in the change in the light emission mode of the LED, there is a possibility that an effect with a sense of incongruity is performed.

For example, when red (R), green (G), and blue (B) LEDs are connected across a plurality of I ² CI / O expanders as shown in FIG. There is a possibility that the LED emits light in a color that misleads the player.

  Specifically, the reliability notification device 15 (FIG. 2) described above is set so that the degree of expectation that is a big hit differs depending on the color of light emission, and if the reliability notification device 15 glows red, the big hit is determined. It is assumed that it is in the specification. And the case where the alerting | reporting operation | movement which makes the reliability alerting | reporting apparatus 15 light-emit in purple which does not become a big hit decision is assumed.

When performing such a notification operation, control is performed such that the red LED and the blue LED in the light emitter provided in the reliability notification device 15 are simultaneously turned on and the light emitter emits purple light. As shown in FIG. 55 above, if there is a moment when only the red LED is lit due to the time difference when the LED connected across a plurality of I ² CI / O expanders emits light, the player will win a big hit May cause trouble between the game store and the player.

Therefore, in the first embodiment of the present invention, when the stop condition is received from the effect control device 550, the effect control data in the buffer is overwritten in the output setting register 635, and the storage contents of the output setting register 635 are stored. The output controller 636 reflects the information in the driver 637 and changes the light emission mode of the LED connected to the I ² CI / O expander.

Therefore, as shown in FIG. 56A, when the stop condition is output, the effect control data received by each I ² CI / O expander can be simultaneously reflected in the output mode of each effect device, and an effect without a sense of incongruity is performed. It becomes possible.

In the first embodiment of the present invention, the timing at which the effect control data received by the I ² CI / O expander is reflected in the output mode of each effect device is received as an update command signal. However, other update command signals may be used. An update command signal that can be expressed by a signal change of the connection lines SDA and SCL even if it is transmitted in the middle of the transmission of the production control data, not limited to the one transmitted at the end of the production control data as in the stop condition If so, it is applicable.

  FIG. 56B is a diagram illustrating a timing at which the decoration control device 610 according to the first embodiment of the present invention receives data and controls the light emitting device.

  FIG. 56B illustrates a light emission (control) mode in which two light emitting devices provided in the game board 10 are alternately lit. As described above, the game board 10 is provided with the center case 51, and the center case 51 is provided with the decoration tool 47 and the decoration lamp 48 (see FIG. 2). Here, what is provided in the decoration tool 47 will be described as the light emitting device (1), and what is provided in the decorative lamp 48 will be described as the light emitting device (2). The light emission mode of the light emitting device is set based on the gaming state.

  The gaming state will be specifically described. Until the time t1, the start memory number is 0, and the image display device 53 displays a demonstration screen. At this time, the light emitting device (1) and the light emitting device (2) are alternately lit at the light emission interval 16f. Note that 1f corresponds to the screen update cycle, and at the light emission interval 16f, the light emitting device (1) and the light emitting device (2) are alternately turned on every time the screen is updated 16 times.

Here, light emission control data (effect control data) is transmitted from the effect control device 550 to the I ² CI / O expander 615 that controls the light emitting device (1) at a time interval of 1f. The light emission control data in this case is one of light emission control data for turning on the light emitting device (1) and light emission control data for turning off the light emitting device (1). The control device 550 updates the light emission control data.

Specifically, among the work registers assigned to the output setting register 635 of the I ² CI / O expander 615 in FIG. 24, register numbers “14h” (register name “LEDOUT0”) to “17h” (register name) The light emission control data is updated by switching the on state of the bit corresponding to the light emitting device (1) from “LEDOUT3”) to on and off. The same processing is performed for the light emitting device (2).

  Further, during the period from time t1 to time t2, the game ball is won at the start winning opening and the special figure variation display game is being executed. Therefore, a special figure variation display game is executed on the special figure display of the general figure / special drawing display 35, and a plurality of identification information is variably displayed on the image display device 53 corresponding to the special figure fluctuation display game. . While the special figure variation display game is being executed, the light emitting device (1) and the light emitting device (2) are alternately lit at the light emission interval 8f. Here, the light emission control data is updated by the effect control device 550 every time the time 8f elapses.

  From time t2 to time t3, the special figure variation display game is over and the identification information is stopped and displayed. At this time, only the light emitting device (1) is lit.

  Further, the result of the special figure variation display game being executed at this time is a big hit, and the time shifts to the special game state from time t3, and the image display device 53 outputs a big hit display. At this time, the light emitting device (1) and the light emitting device (2) are alternately lit at the light emission interval 4f. Here, the light emission control data is updated every time 4f by the effect control device 550.

  Thus, the light emission control data for turning on any one of the light emitting devices (for example, the light emitting device (1) and the light emitting device (2)) that can be visually recognized from the player side, and the light emission control data for turning off the light emitting device. By transmitting while switching, the target light emitting device can be blinked. If the light emission control data is not transmitted correctly, the light emitting device stops flashing and is always turned on or off. Can be confirmed.

  Furthermore, so that this confirmation can be made at any time, not only the light emission control data for turning on the light emitting device and the light emission control data for turning off the light emission device are transmitted while switching, but also the variable display game is executed. Even during a period when the light emitting device is not used, the light emission control data for turning on the light emitting device and the light emission control data for turning off the light are switched and transmitted.

  It should be noted that the time interval at which the light emission control data can be updated can be configured to vary between when the variable display game is running and when the variable display game is not running. For example, when the variable display game is not being executed, the light emission control data can be updated at a time interval of 4f, but when the variable display game is being executed, the light emission control data is updated at a time interval of 8f. As such, the processing burden may be reduced.

  By adopting such a configuration, the light emission control is performed in a direction in which the processing load of the effect control device 550 (including the processing load of the CPU 551) is greatly reduced between the execution and non-execution of the variable display game. The burden of data update processing can be distributed.

FIG. 57 shows a state in which the I ² CI / O expander 615 that has started occupying the connection line SDA is waiting for the fall of the connection line SCL in the first embodiment of the present invention. after the lapse, to reset the I ² CI / O expander 615 occupies the connection line SDA self, is a diagram for explaining a procedure to attempt to release the bus.

When a start condition is output from the master IC, the master IC starts outputting data to the I ² CI / O expander 615 on the slave side, and the STA of the master IC is set to ON. Thereafter, the master IC sequentially transmits 8-bit data from B7 to B0 to the I ² CI / O expander 615 while sequentially changing the signal level of the connection line SCL. At this time, the I ² CI / O expander 615 on the slave side sequentially captures data corresponding to the change in the signal level of the connection line SCL.

  When 8 bits (1 byte) of data, that is, 1 time of data is transmitted, the connection line SDA is released on the master IC side (step 5201 in FIG. 52). When the connection line SDA is released, the signal level is set to HIGH. And it waits until a reply signal (ACK, NACK) is transmitted from the slave side.

The I ² CI / O expander 615 on the slave side outputs a response signal (ACK) by changing the signal level of the connection line SDA to LOW. After that, the master IC changes the signal level of the connection line SCL from LOW to HIGH and then changes from HIGH to LOW, and the slave I ² CI / O expander 615 receives the connection line SDA. (Corresponding to steps 5207 to 5212 in FIG. 52).

Referring to FIG. 57, when the seventh bit data is transmitted on the master IC side, it is recognized on the slave side that the signal level of the connection line SCL has changed due to noise or the like, and the I ² CI / O EX on the slave side is recognized. The panda 615 recognizes that 8-bit data has been transmitted. Therefore, the slave sets the signal level to LOW in order to output the response signal (ACK) and occupies the connection line SDA. In the first embodiment of the present invention, monitoring of the occupation of the connection line SDA by the slave is simultaneously started by the self-occupied WDT 641.

At this time, the master IC cannot transmit data (B0) until it is changed to HIGH because the connection line SDA is occupied by the I ² CI / O expander 615 on the slave side and the signal level is LOW. It has become. Furthermore, since the I ² CI / O expander 615 on the slave side is on standby until the signal level of the connection line SCL falls, the slave side I ² CI / O expander 615 is on standby until the signal level changes, and the entire processing is stopped. Resulting in.

Therefore, in the first embodiment of the present invention, as described above, the time during which the slave I ² CI / O expander 615 occupies the connection line SDA is monitored by the self-occupied WDT 641. When a predetermined time elapses after the start of the occupation, the connection line SDA is forcibly released by resetting the slave I ² CI / O expander 615 itself.

  Since the last data cannot be output even if the connection line SDA is released, the CPU 551 resets the master IC. Thereafter, a stop condition and a start condition are output, and the process is resumed.

FIG. 58 shows a state in which the connection line SDA is occupied for some reason in the first embodiment of the present invention, and the I ² CI / O expander 615 that detects the occupation of the connection line SDA It is a figure explaining the procedure which resets and tries to release a bus | bath.

FIG. 57 illustrates the case where the I ² CI / O expander 615 occupying the connection line SDA releases the connection line SDA by resetting itself, but FIG. 58 monitors the entire bus, A procedure for forcibly releasing a bus when another slave (such as another I ² CI / O expander 615 connected to the connection line SDA) does not release the bus because the connection line SDA is occupied. To do.

  The monitoring by the bus monitoring WDT 640 starts when the signal level of the connection line SDA becomes LOW level, and ends when the signal level of the connection line SDA becomes HIGH level. That is, when the signal level of the connection line SDA is continuously LOW, a command for outputting a reset signal is output from the bus monitoring WDT 640 to the reset signal generation circuit 639.

As described with reference to FIG. 57, when the bus is occupied by ^I 2 CI / O expander 615 on the slave side, the input and output of signals between the master IC and the slave side of the ^I 2 CI / O expander 615 Stops, and the signal level of the connection line SDA does not change (becomes waiting until the signal level changes). Therefore, when the signal level of the connection line SDA does not change for a predetermined time, all the I ² CI / O expanders 615 connected to the connection line SDA reset themselves by each determination. To release the bus.

Referring to FIG. 58, after data B1 is output from the master IC, the bus is occupied by another slave. In the case of FIG. 58, since the bus is not occupied by the own slave, the slave that is actually occupied cannot be specified. Therefore, each of the slaves (I ² CI / O expander 615) connected to the connection line SDA releases the bus by resetting itself (exactly, I connected to the connection line SDA). ^{2 Of the} CI / O expanders 615, only those having the function of resetting themselves perform reset processing).

  Thereafter, the CPU 551 resets the master IC, and after a stop condition and a start condition are output from the master IC, the process is resumed.

Figure 59 is a first in embodiment when the bus is occupied by I ² CI / O expander 615 of the slave side, the slave side of the I ² CI / O expander in response to a command from the master IC of the present invention FIG. 615 is a diagram illustrating a procedure for releasing a bus.

When the number of changes in the signal level of the connection line SCL differs between the master side and the slave side due to noise or the like, the connection line SDA is occupied by the I ² CI / O expander 615 on the slave side as described above, and the bus is released. It will not be done.

Therefore, if data transmission from the master IC becomes impossible while the bus is still occupied, the CPU 551 resets the master IC. And it tries to output a stop condition and a start condition to each slave (I ² CI / O expander 615 connected to the master IC).

At this time, the I ² CI / O expander 615 on the slave side first executes the stop condition output process shown in FIG. At this time, since the signal levels of the connection line SCL and the connection line SDA are both LOW, the SCL release processing is executed (5004 in FIG. 50, FIG. 47). Since the connection line SDA is occupied, the SCL release processing is executed normally, and the signal level of the connection line SCL is set to HIGH.

Subsequently, the process of step 5005 in FIG. 50 is executed, and the SDA release monitoring process (FIG. 48) is executed. In the SDA release monitoring process, the signal level of the connection line SDA is changed to HIGH in the process of step 4802. However, since it is occupied by the slave I ² CI / O expander 615, it cannot be set to HIGH. Accordingly, “70H” (“recovery”) is set in the status code in the process of step 4805, and then a transmission interruption interrupt is generated.

  When a transmission interruption interrupt occurs, as shown in FIGS. 40 and 41, the CPU 551 performs a soft reset on the master IC (4011 in FIG. 40, 4111 in FIG. 41).

Thereafter, the master IC changes the signal level of the connection line SCL at least nine times. By doing this, the I ² CI / O expander 615 on the slave side detects a change in the signal level of the connection line SCL from HIGH to LOW while the signal level of the connection line SCL is changed at least nine times. Accordingly, the connection line SDA is released (corresponding to exiting the loop of steps 5208 to 5211 in FIG. 52), and a response signal (ACK) is transmitted to the master IC.

Next, after confirming that the connection line SDA has been released, the master IC outputs a stop condition to the I ² CI / O expander 615 on the slave side, then outputs a start condition, and again transmits data. I do.

FIG. 60 shows a case where the read mode occurs in the slave I ² CI / O expander 615 and the bus is occupied by an erroneous command from the master IC in the first embodiment of the present invention. It is a figure explaining the procedure in which the slave I ² CI / O expander 615 releases the bus in response to a command from the master IC.

In the present embodiment, it is not intended to transmit a command for generating a read mode from the master IC to the slave I ² CI / O expander 615, but due to the influence of noise or the like, I ² A description will be given assuming that the CI / O expander 615 arbitrarily determines and transitions to the read mode.

Even when the I ² CI / O expander 615 is in the read mode, if a predetermined time or more elapses while the bus is occupied, the monitor timer circuit 562 causes the CPU 551 to time out as in the case of the write request. An interrupt occurs (see FIGS. 10 and 41). At this time, as described in FIG. 58, the CPU 551 first initializes the master IC by executing a soft reset. Then, an attempt is made to output a stop condition and a start condition to each slave (I ² CI / O expander 615 connected to the master IC).

When the start condition output is executed and the signal level of the connection line SCL is changed at least nine times, the I ² CI / O expander 615 outputs data to the connection line SDA in accordance with the change of the signal level of the connection line SCL. However, in the middle of changing the signal level of the connection line SCL nine times, the timing for confirming the response signal (ACK) from the master IC occurs. At this time, since the connection line SDA is kept open on the master IC side, the I ² CI / O expander 615 on the slave side receives the signal level of the connection line SDA and the NACK signal that becomes HIGH level. It recognizes that the response signal has been received, determines that the subsequent data transmission should be stopped, and releases the connection line SDA.

  According to the first embodiment of the present invention, each master IC (signal level control means) included in the effect control device 550 (group overall control means) transmits data to the decoration control device 610 (group unit control means). Then, since a response signal is transmitted from the decoration control device 610 to the effect control device 550, it is possible to confirm whether or not data transmission has been performed, and malfunction can be prevented.

  Further, according to the first embodiment of the present invention, the effect control device 550 transmits data to the decoration control device 610 via one data line (connection line SDA), and the effect control device 610 controls the effect control. Since the response signal is also transmitted to the device 550 through the same data line, the wiring between the substrates can be reduced.

Furthermore, according to the first embodiment of the present invention, one data line is connected from the effect control device 550 (master IC, group overall control means) to the decoration control device 610 (I ² CI / O expander 615, The data line is occupied by the decoration control device 610 and cannot be used because it is commonly used for data transmission to the group unit control means) and response signal transmission from the decoration control device 610 to the effect control device 550. However, processing for initializing the decoration control device 610 is performed by the initializing means, and the occupation state of the data line can be released thereby preventing the communication from being stopped.

  Furthermore, according to the first embodiment of the present invention, the decoration control device 610 that occupies the data line itself determines the occurrence of a communication stop state and initializes itself to thereby create another decoration. The data line can be released without affecting the processing of the control device 610.

  Further, according to the first embodiment of the present invention, when the occupation state of the data line is detected, all of the decoration control devices 610 connected to the data line are surely initialized by themselves. The data line can be released.

  According to the first embodiment of the present invention, a command to release the data line can be transmitted from the effect control device 550. Furthermore, since the timing of output start and output end of the response signal is commanded from the effect control device 550, the processing of the decoration control device 610 is simplified. Then, after a response signal starts to be output, if a problem occurs such that an output end command does not arrive, the occupancy cancel command means cancels the problem and the communication can be restored to a normal state.

  Furthermore, according to the first embodiment of the present invention, even if there is an upper limit on the number of decoration control devices 610 that can be connected to one master IC, the production control device 550 includes a plurality of master ICs. More decoration control devices 610 can be used.

  In the first embodiment of the present invention, the first master IC 570a (first signal level control means) controls the effect device provided in the game board 10, and the second master IC 570b (second signal level). Control means) is configured to control the effect device provided in the front frame 3. Thus, when developing the front frame 3 and the game board 10 by making the effect device provided in the game board 10 and the effect device provided in the front frame 3 into different groups, the decoration control device. Since it is only necessary to consider the upper limit number of 610 limited to each group to be developed, it is possible to improve development efficiency, for example, by developing devices in parallel for each configuration.

Furthermore, according to the first embodiment of the present invention, the master IC is selected by the CPU 551, and the plurality of decoration control devices 610 (I ² CI / O expander 615) connected to the selected master IC are Since the initialization is performed collectively, a high-speed initialization process can be performed as compared with a method of selecting and initializing the decoration control devices 610 one by one.

  At this time, it is possible to perform control such that only the decoration control device 610 connected to the selected master IC is initialized and the decoration control device 610 connected to another master IC that is not selected is not initialized.

  Therefore, since only the decoration control device 610 belonging to the minimum necessary range can be initialized among all the decoration control devices 610 provided in the gaming machine, the decoration control device 610 is initialized and the effect device. The frequency at which the operation is interrupted can be reduced.

  Further, according to the first embodiment of the present invention, when all the master ICs are to be reset, a hard reset is performed. Therefore, each master IC is soft reset one by one. In comparison, initialization can be performed at high speed.

  On the other hand, when a part of the master ICs is to be reset, the initialization is executed by a soft reset via the data bus. Therefore, it is complicated to input signals individually to the initialization signal input terminals of all the master ICs. It is sufficient to provide one port without requiring a simple circuit. In other words, all master ICs that are always executed at the time of startup can be reset at high speed, and only a part of master ICs that are executed only in an emergency can be reset with a simplified circuit. Therefore, this is particularly effective in a configuration with a large number of master ICs.

  Further, according to the first embodiment of the present invention, since the processes by the master IC operate in parallel, high-speed processing is possible. Further, since the effect mode of the effect device is controlled to be synchronized with the screen update timing, the effect of light emission in harmony with the screen display becomes possible.

  Furthermore, according to the first embodiment of the present invention, the timing at which the captured data is reflected as the output mode of the rendering device is determined by the signal level change (reception of the stop condition) between the timing signal line and the data line. Therefore, a signal such as a conventional LAT signal is not necessary. This eliminates the need for wiring for transmitting the LAT signal, and makes it possible to simplify the wiring.

  In addition, according to the first embodiment of the present invention, it is possible to transmit individual performance control data to the plurality of decoration control devices 610 using the same signal line, and further, It is possible to simultaneously update the rendering mode of each rendering device.

(Second Embodiment)
In the first embodiment of the present invention described above, the bus monitoring WDT 640 and the self-occupied WDT 641 are configured to operate unconditionally after the power is turned on.

  However, since the bus monitoring WDT 640 and the self-occupied WDT 641 are optional functions for resetting the decoration control device 610 based on the signal level of the connection line SDA, whether or not to use this function can be selected by some method. Is preferred.

  In particular, since the signal level of the connection line SDA is unstable immediately after the power is turned on, the function of resetting the decoration control device 610 while monitoring the signal level of the connection line SDA operates immediately after the power is turned on. If this occurs, an unexpected reset process may occur, which may cause malfunction. Therefore, it is preferable that the bus monitoring WDT 640 and the self-occupied WDT 641 are invalidated immediately after the power is turned on.

  Therefore, a second embodiment in which monitoring by the watchdog timer is enabled or disabled as necessary will be described. In the second embodiment of the present invention, control is performed so that monitoring by the watchdog timer is not performed until the reset process is completed immediately after the gaming machine is turned on or immediately after initialization. Details of the second embodiment of the present invention will be described below with reference to FIGS.

  In the following description of the embodiment, the same reference numerals are assigned to the same configurations and processes as those in the first embodiment, and the description thereof is omitted.

FIG. 61 is a block diagram illustrating a configuration of the I ² CI / O expander 615 according to the second embodiment of this invention.

The I ² CI / O expander 615 according to the second embodiment of the present invention is illustrated in that the functions of the bus monitoring WDT 640 and the self-occupied WDT 641 are enabled or disabled according to the setting value in the output setting register 635. Unlike the I ² CI / O expander 615 of the first embodiment shown in FIG. 18, other configurations are the same.

As described above, a work register (device register) and a control register (control register) are assigned to the output setting register 635 of the I ² CI / O expander 615.

  In the second embodiment of the present invention, the output setting register 635, the bus monitoring WDT 640, and the self-occupied WDT 641 are connected, and based on the value set in the work register of the output setting register 635, the watchdog timer Controls ON / OFF.

  When controlling ON / OFF of the watchdog timer, first, an all call address (ALLCALL address, second common address, see FIG. 23) that can output a common command to all the decoration control devices 610 is obtained. The destination. Then, by setting a predetermined value in the bit for controlling the ON / OFF of the watchdog timer, the ON / OFF of the watchdog timer of all the decoration control devices 610 is set simultaneously.

  At this time, it is possible to specify whether or not to permit all the decoration control devices 610 to set ON / OFF of the watchdog timer at the same time by switching the availability of the all call address. Whether or not the all-call address can be used is set to “0” or “1” in bit 0 of the mode register 1. Further, ON / OFF of the watchdog timer sets “0” or “1” in bit 2 of the mode register 2. Details of the all-call address and watchdog timer availability setting will be described later.

As described above, the mode register 1 and the mode register 2 are mode registers for initial setting of the I ² CI / O expander 615, and are provided as part of the work register of the output setting register 635 ( (See FIG. 24). The mode register 1 corresponds to the register number “00h”, and the mode register 2 corresponds to the register number “01h”. When values are written to the mode register 1 and the mode register 2, that is, the storage areas of the register numbers “00h” and “01h”, the initial setting of the I ² CI / O expander 615 is performed based on the written values. Is called. Details of the mode register 1 and the mode register 2 will be described below with reference to FIG.

  FIG. 62 is a diagram illustrating an example of the mode register 1 and the mode register 2 according to the second embodiment of this invention. FIG. 62A shows the configuration of the mode register 1 and FIG. 62B shows the configuration of the mode register 2. The mode register 1 and the mode register 2 are each 8 bits.

  Each bit of the mode register 1 includes ALLCALL, SUB3, SUB2, SUB1, SLEEP, AI0, AI1, and AI2 in order from bit 0.

  ALLCALL is a parameter indicating whether or not the all-call address can be used, and can be used when “1” is set, and cannot be used when “0” is set. The initial value is set to “1” (usable), and the all-call address is usable immediately after initialization (reset).

  SUB3, SUB2 and SUB1 are parameters indicating whether or not a sub address can be set. SLEEP is a parameter for setting whether or not the power saving mode is set. AI0, AI1, and AI2 are parameters that specify address auto-increment, and the details are as described with reference to FIG.

  Each bit of the mode register 1 includes “WDT PERIOD” (2 bits), “WDT ENABLE”, “OCH”, and “DMBLNK” in order from bit 0. Bit 6 and bit 7 are not used.

  WDT PERIOD represents a parameter corresponding to the monitoring time of the watchdog timer, and is represented by 2 bits. For example, when “00” is set, the monitoring time is 5 ms, and when “11” is set, the monitoring time is 35 ms.

  WDT ENABLE is a parameter that controls ON / OFF of the watchdog timer. It can be used when “1” is set (ON), and cannot be used when “0” is set (OFF). ). Since “0” is set as the initial value, the watchdog timer is set not to operate immediately after initialization. Therefore, the master IC activates the watchdog timer as necessary.

As described with reference to FIG. 24, OCH is a parameter that defines the timing at which the effect control data stored in the output setting register 635 of the I ² CI / O expander 615 is actually reflected in the effect device. Specifically, it can be set so that presentation control data is output when a stop condition or ACK is received. When the value of OCH is set to “0”, the effect control data is actually reflected on the effect device in the stop condition.

DMBLNK is a parameter for adjusting the blinking and brightness of the LED connected to the I ² CI / O expander 615.

  FIG. 63 is a flowchart illustrating a procedure of initialization resume data transmission restart processing according to the second embodiment of this invention. The same processes as those in the first embodiment of the present invention shown in FIG. 42 are assigned the same reference numerals, and different processes will be described.

  In the first embodiment of the present invention, the initialization stage number is set to a value from 0 to 4, but in the second embodiment of the present invention, the initialization stage number is a value from 0 to 10. Is set. Therefore, in the second embodiment of the present invention, the combination of the initialization stage number and the output buffer setting value as shown in FIG. 64 is defined in advance, and the output buffer setting value is determined based on the initialization stage number. Is set in the output buffer 572.

  Specifically, the CPU 551 first determines the matching between the initialization stage number and the status code (6301), and determines whether or not the initialization stage number and the status code match (6302). If the initialization stage number and the status code do not match (the result of 6302 is “N”), the processing after step 4203 is executed. The processing after step 4203 is the same as the processing described in FIG.

  Note that the determination of matching between the initialization stage number and the status code is the same as in the transmission processing continuation determination table 4400 shown in FIG. 44 in the first embodiment of the present invention, but in the second embodiment of the present invention. In this form, the initialization stage number is changed from 1 (0) to 10, so the correspondence is different.

  Hereinafter, the first embodiment of the present invention and the second embodiment of the present invention will be described in detail by associating the initialization stage numbers.

  In the second embodiment of the present invention, when the initialization stage number is 1, it indicates that the initialization process has just been started, and matching is performed according to the same criteria as in the first embodiment of the present invention. Judging sex.

  The case where the initialization stage numbers are 2, 5, and 8 in the second embodiment of the present invention corresponds to the case where the initialization stage number is 2 in the first embodiment of the present invention. When the initialization stage number is 2, 5, or 8, since the address has been transmitted in the immediately preceding process (see FIG. 64), it is determined that it is consistent when the address transmission is successful. .

  In the second embodiment of the present invention, when the initialization stage numbers are 3, 4, 6, 7, 9, and 10, the initialization stage numbers are 3, 4 in the first embodiment of the present invention. This corresponds to the case. When the initialization stage number is 3, 4, 6, 7, 9, or 10, since the data has been transmitted in the immediately preceding process (see FIG. 64), this is consistent with the case where the data transmission is successful. It is judged that

  If the initialization stage number matches the status code (the result of 6302 is “Y”), the CPU 551 determines whether the initialization stage number is 10 (6303). When the initialization stage number is 10 (the result of 6303 is “Y”), it indicates that the initialization process has been completed, and therefore, the termination process after step 4213 is executed. The processing after step 4213 corresponds to the case where the initialization stage number is 4 in the first embodiment of the present invention, and is the same as the processing described in FIG. When the initialization stage number is 10 in the second embodiment of the present invention, the final stage of the initialization process is the same as in the case where the initialization stage number is 4 in the first embodiment of the present invention. Is shown.

  Further, when the initialization stage number is not 10, that is, when the initialization stage number is 1 to 9 (result of 6303 is “Y”), the CPU 551 outputs the value corresponding to the initialization stage number to the output buffer. It is set to 572 (6304). The initialization stage number and the value corresponding to the initialization stage number are defined in advance, and an example is shown in FIG. Subsequently, the CPU 551 executes processing subsequent to step 4208. The processing after step 4208 is the same as the processing described in FIG.

  FIG. 64 is a diagram illustrating a correspondence between the initialization stage number and the output buffer setting value set in the output buffer 572 according to the second embodiment of this invention.

  When the initialization stage number is 1, “D6h” is set in the output buffer 572 as the output buffer setting value. “D6h” indicates a reset address. The reset address is also a common address (a first common address different from the all call address) that can output a common command to all the decoration control devices 610.

  Further, when the initialization stage number is 2, “A5h” is set in the output buffer 572, and when the initialization stage number is 3, “5Ah” is set in the output buffer 572. “A5h” represents the first half value of the reset command (initialization instruction data), and “5Ah” represents the second half value of the reset designation (initialization instruction data). The case where the initialization stage number is 1 to 3 is the same as that of the first embodiment of the present invention described above.

When the initialization stage number is 4, “D0h” is set in the output buffer 572. “D0h” indicates an all call address. That is, the value set in the output buffer 572 next (when the initialization stage number is 5) is transmitted to all the decoration control devices 610 (I ² CI / O expander 615). Note that each decoration control device 610 (I ² CI / O expander 615) is reset by a process (first initialization means) based on the command transmitted in the case of initialization stage numbers 1 to 3. Immediately after the reset, since the value of bit 0 of the mode register 1 is set to 1, the all call address of the I ² CI / O expander 615 is valid.

  When the initialization stage number is 5, “01h” is set in the output buffer 572. “01h” indicates that auto-increment is prohibited and the mode register 2 is designated in the control register.

  When the initialization stage number is 6, “04h” corresponding to the initialization means validation command is set in the output buffer 572. “04h” is a setting value of the mode register 2 and indicates that the monitoring time of the watchdog timer (5 ms in FIG. 64), the watchdog timer can be used, and the output is reflected in the stop condition. Specifically, “0000” is set to “00100” (= “04h”) by setting “00” to WDT PERIOD, “1” to WDT ENABLE, and “0” to OCH. In this way, the process in the case where the initialization stage number is 6 is an initialization means (second initialization means) for detecting that the bus is occupied by monitoring the bus state and initializing it. It functions as a means to validate a watchdog timer.

  When the initialization stage number is 7, “D0h” corresponding to the all call address is set in the output buffer 572 again.

  If the initialization stage number is 8, “00h” is set in the output buffer 572. “00h” indicates that auto-increment is prohibited and the mode register 1 is designated in the control register.

  When the initialization stage number is 9, “00h” corresponding to the common address invalidation command is set in the output buffer 572. “00h” is set in the mode register 1 to invalidate the all call address. The processing executed when the initialization stage number is 9 functions as a common address invalidating means for invalidating the all call address.

  As described above, in the second embodiment of the present invention, when the initialization stage number is 6, monitoring by the watchdog timer is enabled. Thereafter, to prevent the watchdog timer from being invalidated due to noise or the like, when the initialization stage number becomes 9, the use of the all call address is prohibited.

  Further, a command for periodically enabling the watchdog timer to each decoration control device 610 so as to ensure that the enabled state of the watchdog timer continues after the use of the all-call address is prohibited. (A command corresponding to the above-described initialization means validation command) may be output individually. By doing so, even if the watchdog timer of some decoration control devices 610 is invalidated due to the influence of noise or the like, the influence can be minimized and the gaming machine can be operated stably.

In the second embodiment of the present invention, a reset process (reset process by the first initialization unit) is executed when the gaming machine is turned on, and each decoration control device 610 (I ² CI / O expander 615) is executed. ) Is initialized. If data transmission fails in the middle of the reset process, the data may not be retransmitted and may be re-executed from the reset process. With this configuration, the initialization process can be reliably executed.

  It can be set only by reset processing (reset processing by the second initialization means) by the bus monitoring WDT 640 and the self-occupied WDT 641 whether or not to enable by the initialization means validation command from the effect control device 550 can be set. is there.

On the other hand, detection of power-on to the I ² CI / O expander 615 (detected by a rise in the voltage of Vcc in FIG. 61) and detection of an external reset signal to the I ² CI / O expander 615 (FIG. 61). The reset processing (reset processing by the first initialization means) executed by the initialization instruction data transmission to the I ² CI / O expander 615 is detected from the effect control device 550. It is not possible to set whether or not to enable the command.

  Further, the only common address that can be invalidated by the common address invalidation command from the production control device 550 is the all-call address (second common address).

  On the other hand, the reset address (first common address) is always valid and cannot be invalidated by a command from the effect control device 550.

  FIG. 65 is a diagram illustrating the structure of data to be transmitted to each slave according to the second embodiment of this invention, and illustrates a case where parameters are set by specifying individual addresses. In the figure, “S” indicates a start condition, “P” indicates a stop condition, and “ACK” indicates an ACK signal.

  In the second embodiment of the present invention, data is transmitted to all the slaves from the first slave to the last slave in one image update cycle so that an effect synchronized with the image display is possible. At this time, the time required to transmit data to all slaves is shorter than one image update cycle, and as described above, data is processed even when data is not transmitted to the slaves. is doing. Therefore, the resources of the master IC can be used effectively.

  The transmission data includes a transmission address of each slave at the head, a control register for storing information for defining a data writing procedure to the work register, and control data for various effect devices (register number “00h” to register number “1Bh”). ) Is included. Details of the transmission data are as described with reference to FIGS.

  In the control data of the register number “00h” and the register number “01h”, the mode register 1 set value and the mode register 2 set value are set. The mode register 1 set value sets whether the all-call address is valid or invalid. In the mode register 2 set value, it is set whether or not to reflect the set value of the watchdog timer and the transmission data output in the stop condition on various effect devices. That is, the validity / invalidity of the all call address and the parameters of the watchdog timer are periodically set for each image update period.

  In the second embodiment of the present invention, as shown in FIG. 64, after the initialization process is completed, the all call address is invalidated and the watchdog timer is set to be valid. Further, as shown in FIG. 65, the mode register 1 setting value which is the setting value of the watchdog timer is set to “04h” (watchdog timer is enabled), and the mode register 2 setting value which is the setting value of the all-call address is set. Data in which “00h” (all call address invalid) is set is transmitted from the master IC to each slave every image update cycle.

  Therefore, since a command for invalidating the all call address (common address invalidation command) is periodically transmitted to each slave, it is possible to prevent unnecessary parameter setting by the all call address. Specifically, even if the address information coincides with the all call address due to noise or the like, the all call address is set to an invalid state, so that incorrect parameters can be prevented from being set. it can.

  Furthermore, since a command (initialization means enabling command) for enabling the watchdog timer is periodically transmitted to each slave, the watchdog timer can be more reliably enabled.

  In addition, since the set values of the watchdog timer and the all call address are transmitted prior to the production control data, the watchdog timer and the all call address are set even when communication is abnormal within the same transmission cycle. The possibility of being set correctly can be increased.

  In other words, the set values of the mode registers 1 and 2 (FIG. 24) are set before the set values of the registers that determine the effect mode of the effect device 620 (setting values set in the registers of register numbers 02h to 17h in FIG. 24). Set values set in the registers of register numbers 00h to 01h), the set values to the mode registers 1 and 2 transmitted in the first half of the data transmission are transmitted in the second half of the data transmission. This means that there is a high possibility that data will be transmitted correctly than the set value. This is based on the reason that even if a communication abnormality occurs during data transmission, the setting value transmitted before the abnormality occurrence point can be set as a slave register.

  In addition, as shown in FIG. 65, in periodic data transmission, an individual address is specified for each slave without using an all-call address, and valid / invalid of the all-call address and the parameters of the watchdog timer are set. However, as shown in FIG. 66, these parameters may be set for all slaves by designating an all call address even in periodic data transmission.

  FIG. 66 is a diagram illustrating the structure of data to be transmitted to each slave according to the second embodiment of this invention, and is a diagram illustrating a case where parameters are periodically set by specifying an all-call address.

  In the transmission data shown in FIG. 66, a data string for collectively setting the mode register 2 set value is inserted by an all-call address immediately before the data string transmitted to each slave (data string in FIG. 65). Yes. Specifically, the mode register 2 is set to prohibit auto-increment and set the monitoring time to 5 ms.

  Therefore, the parameters of the watchdog timer are set periodically every image update cycle using the all-call address. Also, because the watchdog timer parameters are set by specifying the all-call address at the beginning of the transmission data, a reset occurs in a specific slave due to the influence of noise, etc., and the parameters of that slave return to the initial state However, when data is sent next time, the parameters of the slave can be reset early.

  FIG. 67 is a diagram for explaining the timing for transmitting and receiving data between the master IC and the slave in the second embodiment of the present invention.

  As described above, in the second embodiment of the present invention, the presentation control data is transmitted from the master IC and the response is received from the slave within the image update cycle, that is, the VDP interrupt generation interval (second time value). A signal (ACK) is returned.

  The transmission data is transmitted corresponding to the pulse width output to the connection line SCL. Specifically, as shown in FIG. 67, a pulse for 8 clocks for data transmission and 1 clock for ACK reply is output between the start condition output and the corresponding stop condition output. The

  The VDP interrupt generation interval includes a data transmission period and a pause (waiting) period from the end of the data transmission period until the next VDP interrupt is generated. The data transmission period is a period from when a start condition is output to when a stop condition is output.

  At this time, the monitoring period of the watchdog timer (set by the mode 2 register) is longer than the pulse width (first time value) output to the connection line SCL, and the VDP interrupt generation interval (second time). A period shorter than (value) is set.

  If the monitoring period of the watchdog timer is shorter than the pulse width output to the connection line SCL, there is a possibility that the slave may be reset despite the data being processed normally. In addition, if the monitoring period of the watchdog timer is set to a period shorter than the VDP interrupt generation interval, it is possible to recover from an abnormality early so as to be in time for the image update cycle, that is, the timing of the next data transmission. Become.

As described above, according to the second embodiment of the present invention, the watchdog timer can be validated or invalidated at an arbitrary timing. Therefore, the watchdog timer can be operated or stopped as necessary, so that the versatility of the decoration control device 610 (I ² CI / O expander 615) can be improved.

Further, according to the second embodiment of the present invention, the setting parameters are transmitted to all the decoration control devices 610 (I ² CI / O expander 615) simultaneously using the all call address. Therefore, it becomes possible to switch between enabling and disabling the watchdog timer at high speed.

In particular, the data line occupation release function provided in the I ² CI / O expander 615 is not necessarily used by all game machine manufacturers, so it is preferable that whether or not to use can be arbitrarily set. For this reason, the default initial state when the power is turned on is configured not to use this exclusive release function.

(Third embodiment)
In the first embodiment of the present invention, the occupation of the connection line SDA is released by controlling the signal level of the connection line SCL by controlling the master IC. However, this increases the load on the master IC. There is a risk of it. In the third embodiment of the present invention, by arranging the timing signal line changing means for controlling the signal level of the connection line SCL, the signal level of the signal level of the connection line SCL is controlled without being controlled by the master IC. To do.

  FIG. 68 is a block diagram showing a configuration of an effect control device 550 according to the third embodiment of the present invention.

  The difference between the production control device 550 of the third embodiment of the present invention and the production control device 550 of the first embodiment of the present invention is that a connection line SCL connected to the output I / F 558a and the relay board 600. The transistor 579b is connected between the output I / F 558a and the connection line SCL connected to the simple relay board 1600.

  In addition, since a pull-up resistor R to which a predetermined voltage is applied is connected to the connection line SCL, when the transistor 579a or the transistor 579b is turned on for a certain time, the signal level of the corresponding connection line SCL is forcibly set. Since it is LOW, if the signal level of the immediately preceding connection line SCL is HIGH, a pulse is output on the connection line SCL. As described above, in the third embodiment of the present invention, a dummy pulse can be output to the connection line SCL regardless of the output state of the master IC.

  Note that the CPU 551, the transistor 579a, and the transistor 579b are arranged on the same substrate and a signal line that connects the CPU 551 and each transistor is not disconnected. Therefore, the transistor 579a and the transistor 579b are unexpected. It is possible to prevent the operation at the timing.

  FIG. 69 is a flowchart illustrating a processing procedure when a transmission interruption interrupt and a timeout interrupt occur on the first master IC 570a side according to the third embodiment of this invention.

  The difference from the first embodiment of the present invention is that when the status code is “recovery”, the first master IC 570a is soft reset (6901), and then a dummy pulse is output by the transistor 579a (6902). Thereafter, a first master side slave initialization start process is executed (4012).

  When a transmission interruption interrupt or a timeout interrupt occurs on the second master IC 570b side, a process is performed in which the first master part in the process of this flowchart is replaced with the second master. At this time, in the process corresponding to step 6902, the transistor 579b is driven to output a dummy pulse.

  As described above, when the connection line SDA becomes unoccupiable due to noise or the like, the master IC is reset, and then a dummy pulse is output to the connection line SCL to thereby occupy the connection line SDA. To release. Hereinafter, a more detailed procedure will be described.

FIG. 70 is a diagram illustrating a procedure for releasing a bus when the bus is occupied by the slave I ² CI / O expander 615 in the third embodiment of this invention.

As described above, when the number of changes in the signal level of the connection line SCL differs between the master side and the slave side due to noise or the like, the connection line SDA is occupied by the I ² CI / O expander 615 on the slave side and the bus is released. It will not be done.

  Therefore, if data transmission from the master IC becomes impossible while the bus is still occupied, the CPU 551 resets the master IC. Thereafter, the occupation of the connection line SDA is released by outputting a dummy pulse to eliminate the difference in the number of changes in the signal level of the connection line SCL.

  Specifically, “70H” (“recovery”) is set in the status code due to the occupation of the connection line SDA (4805 in FIG. 48), and then a transmission interruption interrupt occurs. When a transmission interruption interrupt occurs, as shown in FIG. 69, the CPU 551 performs a soft reset on the master IC (6901 in FIG. 69), and then outputs a dummy pulse (69023 in FIG. 69). At this time, the dummy pulse may be output until the occupation of the connection line SDA is released, or may be changed at least nine times.

In this way, the slave-side I ² CI / O expander 615 changes the signal level of the connection line SCL by outputting a dummy pulse, and the signal level of the connection line SCL changes from HIGH to LOW. The connection line SDA is released, and a response signal (ACK) is returned to the master IC. Thereafter, the master IC outputs a start condition and resumes data transmission.

  As described above, after the soft reset of the master IC, each slave is initialized after receiving the ACK and confirming the release of the connection line SDA. Can do.

  Further, according to the third embodiment of the present invention, it is possible to release the occupation of the connection line SDA without increasing the load on the master IC.

  Furthermore, according to the third embodiment of the present invention, the signal level of the connection line SCL is set to HIGH when the master IC is not operating. It becomes possible to output.

  Further, according to the third embodiment of the present invention, since the CPU for controlling the production and the transistor for outputting the dummy pulse are arranged on the same substrate, the transistor cannot be controlled due to poor contact or the like. When the transistor is arranged on another substrate, it can be prevented from operating at an unexpected timing.

(Fourth embodiment)
In the first embodiment of the present invention, the decoration control device 610 (I ² CI / O expander 615) updates the light emission state of the connected LED at the timing of receiving the stop condition from the first master IC 570a. is doing. On the other hand, in the fourth embodiment of the present invention, the light emission state of the connected LED is switched at a timing other than the reception timing of the stop condition from the first master IC 570a. By doing so, it is not necessary to control the signal level for outputting the stop condition, and the data transmission time can be shortened.

  In the fourth embodiment of the present invention, the decoration control device 610 updates the light emission state of the connected LED at the timing when a response signal (ACK) is returned to the master IC. In order to update the aspect of the effect device at the timing when ACK is returned, in the data transmitted from the master IC to each slave, the bit of the OCH (see FIG. 62 (B)) included in the setting value of the mode 2 register It is necessary to set “1”.

  FIG. 71 is a diagram illustrating a connection example of the decoration control device 610 and the decoration device 620 according to the fourth embodiment of the present invention. The decoration device 620 provided with five sets of LEDs is replaced with one decoration control device 610. It is a figure which shows the structure controlled by these. Depending on the lighting state of these five sets of LEDs, each color of red, green, and blue is mixed to express a large number of colors.

  In the fourth embodiment, the above-described reliability notification device 15 (FIG. 2) is described as an example of the decoration device 620. That is, it is assumed that the jackpot is determined when the reliability notification device 15 glows red.

  With the configuration shown in FIG. 71, the light emission state of the five sets of LEDs connected to the decoration control device 610 is updated at the same time, so that unexpected color development is not performed. In other words, it is possible to simultaneously update the light emission state of each set of LEDs at the timing when ACK is returned even if the LED does not emit light at the timing when the stop condition is received.

  FIG. 72 shows transmission / reception between the CPU 551 and the master IC (the first master IC 570a or the second master IC 570b) when transmitting the effect control data to each decoration control device (slave) according to the fourth embodiment of the present invention. It is a figure explaining the information to be performed. In addition, about the procedure which is common in FIG. 35 corresponding to the 1st Embodiment of this invention, a common code | symbol is assigned and description is abbreviate | omitted.

  When performing the effect control, the CPU 551 of the effect control device 550 first sets “1” to a bit for instructing the output of the start condition (STA) of the command REG581 (7201). At this time, unlike the first embodiment of the present invention, “0” is set to the bit indicating the output of the stop condition (STO) to instruct the stop condition not to be output.

  The master IC outputs a start condition to each slave based on the values set in the STA and STO of the command REG581 (7211). The start condition output at this time is a restart condition in the fourth embodiment of the present invention.

  Since the master IC is ready to receive the presentation control data at each slave, the master IC inputs an interrupt signal to the CPU 551 to generate an interrupt. The CPU 551 that has generated the interrupt sets the first presentation control data of the slave to be controlled (data in bytes transmitted first among the data in FIG. 30) in the output buffer 572 (7202). At this time, “0” is set in the STA and STO of the command REG581.

  The master IC outputs the presentation control data (slave address is stored) set in the output buffer 572 to the slave corresponding to the address (3512). At this time, the slave corresponding to the output address executes effect processing based on the received effect control data.

  Then, the slave that has received the effect control data returns ACK. At this time, the slave that has returned ACK updates the light emission mode of the rendering device (LED) to be controlled at this timing.

  Then, the master IC that has received the ACK inputs an interrupt signal to the CPU 551 to generate an interrupt. Even when the master IC receives NACK, the master IC inputs an interrupt signal to the CPU 551 to generate an interrupt. The CPU 551 that generated the interrupt sets the next presentation control data (second-byte data transmitted in FIG. 30) of the slave to be controlled in the output buffer 572, and sets the STA and STO of the command REG581. Sets “0” (7202). Thereby, the next effect control data is transmitted from the master IC to the slave (3512).

  Thereafter, each time the master IC receives ACK or NACK, it inputs an interrupt signal to the CPU 551 to generate an interrupt, and the CPU 551 that has generated the interrupt causes the output buffer 572 to control the next presentation of the slave to be controlled. Data (byte-unit data to be transmitted after the third in FIG. 30) is set, and the process of setting “0” to the STA and STO of the command REG581 is repeated. This process is repeated until all effect control data is transmitted.

  The CPU 551 that generated the interrupt at the timing after all the effect control data has been transmitted sets “1” to the STA of the command REG 581 and “0” to the STO (7203). Thereafter, the master IC outputs a so-called restart condition that outputs a start condition again (3513).

  Subsequently, the CPU 551 and the master IC perform the same processing by sequentially designating the addresses of slaves controlled second and later (7204, 3514, 7205, 3515). When the CPU 551 completes the output of the effect control data to the last nth slave (7206), and the master IC outputs the effect control data to the corresponding slave (3516), the output of all data is completed.

  Thereafter, the CPU 551 maintains the signal level of the connection line SCL at the LOW level (7217). Specifically, when the master IC completes the output of the presentation control data to the final slave, an interrupt signal is input to cause the CPU 551 to generate an interrupt. The CPU 551 that generated the interrupt sets the SI of the command REG581 to “1”. "Is left as it is, and the signal level of the connection line SCL is kept LOW.

  As described above, in the fourth embodiment of the present invention, the effect mode (light emission mode) of the effect device (light emitter) is updated at the timing when the slave returns ACK. Therefore, the master IC transmits the presentation control data to the next slave without waiting for the reception of the ACK transmitted from the slave. Therefore, since it is possible to continuously transmit the effect control data, it is possible to reduce the total time required for transmitting the effect control data.

  Hereinafter, a procedure for specifically transmitting the effect control data will be described with reference to the flowcharts of FIGS. 73 and 74.

  FIG. 73 is a flowchart showing the procedure of the effect control regular processing according to the fourth embodiment of the present invention. In the fourth embodiment, the presentation control periodic process of the first embodiment of the present invention shown in FIG. 39 is replaced with the process of FIG. 73, so the processes common to FIG. 39 are the same. A reference numeral is assigned to omit the description.

  In the first embodiment of the present invention, as described above, the master IC transmits the next effect control data after receiving the ACK, that is, after confirming that the data has been transmitted normally. It was. For this reason, data is retransmitted when NACK indicating that data cannot be normally received is received instead of ACK.

  On the other hand, in the fourth embodiment of the present invention, the presentation control data is transmitted for each register in the byte mode, instead of transmitting the data in the buffer mode as in the first embodiment. Then, regardless of whether or not the effect control data can be normally transmitted, the process for continuously transmitting the effect control data and retransmitting the effect control data is not executed.

  Referring to FIG. 73, the processing from step 3901 to step 3907 and from step 3909 to step 3911 are the same as those in the first embodiment. In the first embodiment, in order to transmit the effect control data in the buffer mode, “1” is set in the MODE bit of the command register 581 in the processing of Step 3908 and Step 3912. On the other hand, in the fourth embodiment, in order to transmit the effect control data in the byte mode, “0” is set to the MODE bit of the command register 581 in the process of Step 7301 and Step 7302 instead of Step 3908 and Step 3912. Set.

  Therefore, in the fourth embodiment, every time one byte of effect control data (corresponding to 30 data illustrated in FIG. 30) to be transmitted to the slave is transmitted, the update stage number is incremented by one. Therefore, after the update stage number is initialized to 0 and the start condition is output, until the set values are output to all the registers, that is, until the production control data for one slave is transmitted. Has been updated. When the 30 data illustrated in FIG. 30 are transmitted, the maximum value of the update stage number is 29.

  Note that the transmission process continuation determination table for determining continuation of the data transmission resumption process of the first embodiment shown in FIG. 44 is commonly used in the fourth embodiment, but the production control “Update stage number = 1” in the continuation determination 4403 of the data transmission restart process is replaced with “update stage number ≧ 1”.

  Furthermore, in the fourth embodiment, since the presentation control data is not retransmitted, processing related to the retry counter that manages the number of retransmissions is not necessary. Therefore, the process of step 3915 for initializing the retry counter is not executed.

  Further, the processes common to the first embodiment from the step 3913, the step 3914, the step 3916 to the slave output data editing process of the step 3919 are executed, and the error processing after the step 3920 is not executed in the fourth embodiment. It is like that.

  In the first embodiment of the present invention, when the update stage number is 0, the start condition (or restart condition) is immediately after being output, and when the update stage number is 1, data is stored. It shows that it is being sent.

  The above is the procedure of the effect control regular processing according to the fourth embodiment of the present invention. Then, each procedure of the transmission resumption process of the production control data according to the fourth embodiment of the present invention will be described.

  FIG. 74 is a flow chart showing a procedure of resumption transmission processing of effect control data according to the fourth embodiment of the present invention. In the fourth embodiment, the process of resuming the transmission of effect control data according to the first embodiment of the present invention shown in FIG. 43 is replaced with the process of FIG.

  The CPU 551 first determines the value of the update stage number (7401). Then, it is determined whether or not the update stage number is the maximum value (7402). When the update stage number is the maximum value, the values set in all the registers are transmitted as described above, and the transmission of data in slave units is completed.

  When the update stage number is not the maximum value (result of 7402 is “N”), the CPU 551 executes the process of transmitting the untransmitted data because the untransmitted effect control data remains. Specifically, 1 is added to the update stage number (7403), data corresponding to the update stage number added is further extracted from the prepared output data (7404), and the extracted data is stored in the output buffer 572. Set (7405).

  Furthermore, the CPU 551 sets a monitoring timer and starts monitoring for timeout (7406). Finally, STA, STO, and SI of the command REG 581 of the master IC to be processed are set to “0”, and MODE is set to “0” in order to transmit the data set in the output buffer 572 in the byte mode. The setting is made (7407), and the process returns to the calling process.

  On the other hand, when the update stage number reaches the maximum value (result of 7402 is “Y”), the transmission of the effect control data for all the slaves is completed because the transmission of the effect control data for one slave is completed. It is determined whether or not it is completed (7408). If transmission of the effect control data is not completed for all slaves (the result of 7408 is “N”), the next slave is selected (7410), and the update stage number is set to 0 (7411).

  The CPU 551 sets a monitoring timer and starts monitoring for timeout (7412). Finally, the STA of the command REG 581 of the master IC to be processed is set to “1” to output a restart condition, and STO and SI are set to “0”, respectively. Further, in order to transmit the data set in the output buffer 572 in the byte mode, MODE is set to “0” (7413), and the process returns to the calling process.

  When the transmission of the effect control data is completed for all the slaves (the result of 7408 is “Y”), the CPU 551 is left in a state where SI is set to “1”, that is, an interrupt is generated. (7414), the process returns to the calling process. At this time, the signal level of the connection line SCL is set to LOW, and this signal level is maintained.

  In this way, after the production control data is transmitted to all the slaves, the state in which the signal level of the connection line SCL is set to LOW is maintained in the state in which the interrupt is generated, so that the connection line SCL Compared with the case where the signal level is set to HIGH, the data transmission can be restarted immediately, and high-speed communication can be performed.

  Furthermore, by maintaining the signal level of the connection line SCL at LOW while an interrupt is generated, even if the level of the data signal line changes due to noise or the like while the interrupt is generated, each slave is erroneously detected. Therefore, since it is not recognized that the start condition is output, reliable communication can be performed.

  FIG. 75 is a diagram illustrating the structure of data transmitted to each slave according to the fourth embodiment of this invention.

  In the fourth embodiment of the present invention, data is transmitted to all the slaves from the first slave to the last slave in one image update cycle as in the other embodiments. Then, it is a pause time until the next image update cycle starts, that is, until the next VDP interrupt occurs. The configuration of the transmission data is the same as in the other embodiments.

  Further, the fourth embodiment is different from the other embodiments in that a stop condition is not output after the production control data of all slaves is output. However, when initialization is performed by transmitting initialization instruction data to the slave, a stop condition is output after the completion of transmission of the initialization instruction data, as in the first embodiment (step of FIG. 42). 4216).

  FIG. 76 is a diagram for explaining the timing for transmitting and receiving data between the master IC and the slave in the fourth embodiment of the present invention.

  As described above, in the fourth embodiment of the present invention, the presentation control data is transmitted from the master IC to all the slaves within the image update cycle, that is, the VDP interrupt generation interval. At this time, a response signal (ACK) is returned from the slave to the master IC. However, in the fourth embodiment of the present invention, the master IC ignores the returned ACK.

  As described above, the stop condition is not output from the master IC even after the effect control data is transmitted to all the slaves.

  In addition, after the production control data is transmitted to all the slaves, the signal level of the connection line SCL is set to LOW, and when the next production control data is transmitted, the signal level of the connection line SCL is set to LOW. By setting to HIGH and further setting the signal level of the connection line SDA to LOW, a start condition is output.

  Conventionally, since the signal level of the connection line SCL is set to HIGH after the output of the stop condition that is a transmission completion command, if the signal level of the connection line SDA is recognized as being set to LOW due to noise or the like, the slave On the side, there is a risk of erroneous recognition that a start condition, which is a transmission start command, has been output. On the other hand, as in the fourth embodiment of the present invention, after outputting the effect control data to all the slaves, the signal level of the connection line SCL is set to LOW, so that such erroneous recognition is performed. Therefore, more accurate communication can be performed.

  As described above, since the master IC (group overall control means) does not retransmit the data without receiving the response signal (ACK) from the slave (group unit control means), the data transmission time becomes constant, and the master IC It is easy to set the interval for sending data to the slave.

  FIG. 77 illustrates a case in which, when the decoration control device 610 receives data in the fourth embodiment of the present invention, when the ACK is output to the master IC, the received data is reflected in the light emission state of the LED. It is a figure to do.

  As shown in FIG. 77, at the time of ACK output, each slave reflects the effect control data in the output mode of the effect device, thereby controlling the timing of transmitting the effect control data, thereby specifying a specific effect device. It becomes possible to control with.

  As described above, in the fourth embodiment of the present invention, the presentation control data is continuously transmitted, so that no waiting time is required until ACK is received and error processing is necessary. Overhead can be reduced.

  In particular, as shown in FIG. 71, this is particularly effective in the case where it is only necessary to produce a single slave unit instead of a plurality of slaves. In the case where a plurality of master ICs are provided, the effect control process as a whole can be performed by updating the effect mode of the effect device in the stop condition for each master IC or by updating the effect mode of the effect device at the ACK transmission timing. It becomes possible to reduce the load.

Note that in the fourth embodiment of the present invention, all the slaves (I ² CI / O expanders) connected to the master IC cause the connection line SDA to output a response signal 630 (FIG. 18). However, the transistor 630 is not necessarily required. If unidirectional communication is assumed as in the fourth embodiment, it is also possible to use a custom-made slave IC that does not include this transistor.

However, since a general-purpose slave IC generally used in I ² C communication is usually provided with this transistor, there is a network in which custom-made products and general-purpose products are mixed. Preferably it can be configured.

  Since the gaming machine according to the fourth embodiment of the present invention is configured such that the response signal is not confirmed on the master IC side, the slave IC has a function of outputting the response signal to the master IC via the connection line SDA. (For example, a general-purpose product slave IC) and a slave IC that does not have a function of outputting a response signal to the master IC via the connection line SDA (for example, a custom-made product slave IC) may be connected to the master IC. It is possible to operate without.

(Fifth embodiment)
In the first embodiment of the present invention, when the decoration control device 610 (I ² CI / O expander 615) receives transmission data from the master IC (first master IC 570a or second master IC 570b), the response signal The operation was confirmed by sending. However, it is considered that it is not necessary to perform strict control in a production device such as an LED unless it is lit in a manner that causes misunderstandings to the player. Further, when the production process fails, there is a possibility that the load on the production control device 550 increases due to retransmission of production control data.

Therefore, in the fifth embodiment of the present invention, the decoration control device 610 (I ² CI / O expander 615) receives a response signal (ACK) only by receiving presentation control data from the unidirectional communication, that is, the master IC. ) Is not received. By implementing in this way, the procedure of effect control can be simplified, and the structure of the effect control device 550 and the decoration control device 610 can be simplified. The details of each configuration and the processing procedure in the fifth embodiment of the present invention will be specifically described below. Note that the description of the configuration and the processing procedure common to the first embodiment is omitted, and only the differences are described.

  FIG. 78 is a block diagram showing the configuration of the first master IC 570a provided in the effect control device 550 and the effect device provided in the game board 10 according to the fifth embodiment of the present invention.

  In the fifth embodiment, the configuration of the connection line connecting the first master IC 570a and the game board 10 is the same as that of the first embodiment.

  In the fifth embodiment, a gate 584a is provided instead of the transistor 578a. The gate 584a is configured by combining two types of transistors, an nMOS transistor and a pMOS transistor. By disposing the gate 584a on the connection line SDA, it is possible to output a predetermined signal to the connection line SDA while suppressing power consumption. Similarly, the connection line SCL is also provided with a gate 584b, and similarly, a predetermined signal can be output.

  In addition, in the connection line SDA and the connection line SCL, when a low level is output by the controller 574, the pMOS transistor is turned on and a low level signal is output. When the controller 574 outputs a high level, the nMOS transistor is turned on. Thus, a high level signal is output.

  Further, since the first master IC 570a of the fifth embodiment is dedicated to unidirectional communication, that is, for transmission, a configuration for receiving data such as a response signal (ACK) transmitted from the slave is included. Absent. Specifically, the input BUF 571 for temporarily storing the data transmitted from the slave is not included in the first master IC 570a of the fifth embodiment. Therefore, the filters 575a and 575b for removing the noise of the received data are not provided.

  Further, as described above, since the first master IC 570a according to the fifth embodiment is dedicated to transmission and cannot receive the response signal (ACK) and confirm the data transmission result, the transmission status is stored. This status REG 582 is also unnecessary.

  On the other hand, the second master IC 570b may be for unidirectional communication or for bidirectional communication.

The slave (decoration control device 610 (I ² CI / O expander 615)) connected to the first master IC 570a may be a general-purpose product (unidirectional slave) dedicated to reception, and can transmit and receive data. Non-general purpose product (bidirectional slave) may be used. When a bidirectional slave is connected to the first master IC 570a, the reception of the response signal (ACK) is not confirmed, so that the response signal transmitted from the slave is discarded (ignored). For this reason, in the fifth embodiment, the processing procedure is simplified as compared with the first embodiment, but the details will be described later.

  The configuration of the game board 10 according to the fifth embodiment of the present invention is basically the same as that of the game board 10 according to the first embodiment, but a resistor R is disposed on the relay board 600. The resistor R is disposed on the connection line SDA. Details will be described later with reference to FIG.

FIG. 79 is a block diagram illustrating a configuration of the I ² CI / O expander 615 according to the fifth embodiment of this invention.

In the fifth embodiment of the present invention, the gate 642 is arranged on the connection line SDA and the gate 643 is arranged on the connection line SCL. When a signal output from the master IC is received, the signal is output to the filters (631, 633) as it is. To do. Other configurations are the same as the configuration of the I ² CI / O expander 615 of the first embodiment.

FIG. 80 is a diagram illustrating connection between the first master IC 570a and the slave (I ² CI / O expander 615) according to the fifth embodiment of this invention.

As described above, the first master IC 570a of the fifth embodiment is a transmission-only master IC for unidirectional communication. The slave connected to the first master IC 570a includes a unidirectional (reception-only) slave (first slave IC, the I ² CI / O expander 615 shown in FIG. 79), and bidirectional (can transmit and receive). Slaves (second slave IC, I ² CI / O expander 615 shown in FIG. 18 (first embodiment)) are mixed.

  Since the second slave IC is a bidirectional slave, when a predetermined number (for example, 8) of bits is received, a response signal is transmitted to the master IC. However, since the first master IC 570a is dedicated for transmission, it cannot receive a response signal. At this time, when receiving data, the second slave IC sets the signal level of the connection line SDA to LOW by the transistor 630 which is an open drain. At this time, since the first master IC 570a supplies a voltage from the connection line Vcc to set the signal level of the connection line SDA, it is short-circuited to the ground. Therefore, the resistor R is arranged as a current regulating unit on the connection line SDA between the first master IC 570a and the second slave IC so as to limit the current and prevent the short circuit.

  FIG. 81 is a flowchart illustrating a procedure of data transmission processing by the master IC according to the fifth embodiment of this invention. This process corresponds to the procedure of the data transmission process shown in FIG. 45 in the first embodiment, and the same processes are assigned the same reference numerals and the description thereof is omitted.

  The difference between the data transmission process of the first embodiment and the data transmission process of the fifth embodiment is whether or not a transmission interruption interrupt is generated in the middle of data transmission. That is, in the first embodiment, continuation of processing or retransmission is determined based on the response signal, but in the fifth embodiment, data transmission is continued without receiving the response signal. Further, since no response signal is transmitted from the slave, the connection line SDA is not occupied by the slave. Therefore, in the fifth embodiment, it is not necessary to generate a transmission interruption interrupt for transmitting data, and processing may be performed sequentially regardless of whether or not data transmission is successful.

  As described above, in the fifth embodiment, since it is not necessary to manage the state of the master IC at the time of data transmission, it is not necessary to hold the status code in the status REG 582 as described above.

  Further, the start condition process in step 4502, the data transmission process to the slave in step 4505, and the stop condition output process in step 4506 are also simplified because the process based on the status code is not required. Details of these processes will be described later with reference to FIGS. 82, 83, and 84 (FIGS. 84A and 84B).

  FIG. 82 is a flowchart illustrating a procedure of start condition output processing according to the fifth embodiment of the present invention. This process corresponds to the procedure of the start condition output process shown in FIG. 46 in the first embodiment. However, as described above, the process based on the status code is not necessary, so that the process is greatly simplified. ing.

  When the start condition output process is started, the controller 574 first determines whether or not a stop condition is output (8201). That is, it is determined whether it is a start condition or a restart condition.

  When the controller 574 outputs the stop condition (the result of 8201 is “Y”), the signal level of the connection line SCL and the connection line SDA is not always set to HIGH, and therefore the connection line SCL is HIGH. (8202) and the connection line SDA is set to HIGH (8203).

  On the other hand, when the stop condition is output (the result of 8201 is “N”), as described later, the signal levels of the connection line SCL and the connection line SDA are both set to HIGH.

  The controller 574 sets the signal level of the connection line SDA to LOW after completion of the process of step 8203 or after outputting the stop condition (8204). At this time, the start condition is output by changing the signal level of the connection line SDA from HIGH to LOW while maintaining the signal level of the connection line SCL at HIGH.

  Subsequently, the controller 574 sets the signal level of the connection line SCL to LOW (8205). Furthermore, the value of FBF, which is a flag indicating that the start condition has just been established, is set to ON (8206), and this process ends.

  As described above, in the fifth embodiment of the present invention, since the connection line SDA is not occupied by the slave in the communication with the unidirectional slave, the process of outputting the start condition can be simplified.

  FIG. 83 is a flowchart illustrating a procedure of stop condition output processing according to the fifth embodiment of the present invention. This process corresponds to the procedure of the stop condition output process shown in FIG. 50 in the first embodiment, but the process based on the status code is not necessary as described above.

  Since the signal levels of the connection line SCL and the connection line SDA are not specified at the timing of outputting the stop condition, the controller 574 first sets the connection line SCL to LOW (8301), and further sets the connection line SDA to LOW. (8302).

  Subsequently, the controller 574 sets the signal level of the connection line SCL to HIGH (8303). After that, when the signal level of the connection line SDA is set to HIGH (8304), the signal level of the connection line SDA is changed from LOW to HIGH while the signal level of the connection line SCL is maintained HIGH. Is output.

84A and 84B are flowcharts illustrating a procedure of data transmission processing to the slave-side I ² CI / O expander 615 according to the fifth embodiment of this invention. This processing corresponds to the procedure of the data transmission processing to the slave-side I ² CI / O expander 615 shown in FIG. 49 in the first embodiment, but based on the status code as in the other processing. Processing is unnecessary.

First, the controller 574 initializes a variable CTR for storing the number of data transmissions to 0 (8401). Subsequently, it is determined whether or not the transmission destination slave is in the bidirectional mode (8402). In order to determine whether the destination slave is the bidirectional slave or the unidirectional mode, the determination is made with reference to the I ² CI / O expander address table shown in FIG. When the transmission destination slave is in the unidirectional mode (the result of 8402 is “N”), the processing for the unidirectional mode (step 8421 and subsequent steps) described in FIG. 84B is executed.

  When the destination slave is in the bidirectional mode (the result of 8402 is “Y”), the controller 574 sets the signal level of the connection line SCL to LOW by setting the pMOS transistor of the gate 584b to ON ( 8403).

  The controller 574 determines whether or not the value of the variable CTR is 9, that is, whether or not the number of clocks has reached 9 (8404). Eight clocks correspond to data transmission from the master IC to the slave, and the remaining one corresponds to transmission of a response signal (ACK) from the slave to the master IC.

  If the value of the variable CTR is not 9 (the result of 8404 is “N”), the controller 574 outputs data to the slave via the connection line SDA, and adds 1 to CTR (8405). When the value of variable CTR is 8, since ACK is transmitted from the slave, the output data is dummy data (FIG. 87 (b)). Subsequently, the signal level of the connection line SCL is set to HIGH (8406), and data is further output by executing the processing after step 8403.

  On the other hand, when the value of the variable CTR reaches 9 (the result of 8404 is “Y”), the controller 574 sets the signal level of the connection line SCL to HIGH (8407), and then sets the signal level of the connection line SCL to LOW. Set (8408). Further, a condition pre-output change process is executed (8409). In the condition pre-output change process, the signal levels of the connection line SDA and the connection line SCL are set based on whether a start condition is output next or a stop condition is output. In this way, by setting the signal levels of the connection line SDA and the connection line SCL in advance, it becomes possible to minimize the change of the signal level of each connection line, and to quickly start condition output processing and stop condition Output processing can be executed.

  Thereafter, the controller 574 determines whether or not the current data transmission mode is the buffer mode (8410). When the current data transmission mode is the buffer mode (the result of 8410 is “Y”), it is determined whether or not the transmission of the last byte is completed (8411). When transmission of the last byte is not completed and data is further transmitted (result of 8411 is “N”), the value of FBF is set to OFF and the variable CTR is set to 0 (8412). Further, the processing after step 8403 is executed, and transmission of the remaining data is continued.

  On the other hand, if the current data transmission mode is not the buffer mode, that is, the byte mode (the result of 8410 is “N”), or the transmission of the last byte is completed (the result of 8411 is “Y”), it is determined whether or not the FBF is set to ON (8413). If the FBF is set to ON (the result of 8413 is “Y”), the FBF is set to OFF (8414), and the process returns to the caller process. On the other hand, if the FBF is not set to ON (the result of 8413 is “N”), the process returns to the calling process.

  In addition, when the destination slave is in the unidirectional mode (the result of 8402 is “N”), the controller 574 sets the signal level of the connection line SCL to LOW by setting the pMOS transistor of the gate 584b to ON. (Step 8421 in FIG. 84B).

  The controller 574 determines whether or not the value of the variable CTR is 8, that is, whether or not the number of clocks has reached 8 (8422). If the value of the variable CTR is not 8 (the result of 8422 is “N”), data is output to the slave via the connection line SDA, and 1 is added to the CTR (8423). Subsequently, the signal level of the connection line SCL is set to HIGH (8424), and further data is output by executing the processing after step 8421.

  On the other hand, when the value of the variable CTR reaches 8 (the result of 8422 is “Y”), the controller 574 sets the signal level of the connection line SCL to LOW (8425). Further, a condition pre-output change process is executed (8426).

  Thereafter, the controller 574 determines whether or not the current data transmission mode is the buffer mode (8427). When the current data transmission mode is the buffer mode (the result of 8427 is “Y”), it is determined whether or not the transmission of the last byte is completed (8428). When the transmission of the last byte is not completed and data is further transmitted (result of 8428 is “N”), the value of FBF is set to OFF and the variable CTR is set to 0 (8429). Further, the processing after step 8403 is executed, and transmission of the remaining data is continued.

  On the other hand, if the current data transmission mode is not the buffer mode, that is, the byte mode (the result of 8427 is “N”), or the transmission of the last byte is completed (the result of 8428 is the controller 574). “Y”), it is determined whether the FBF is set to ON (8430). If the FBF is set to ON (the result of 8430 is “Y”), the FBF is set to OFF (8431), and the process returns to the caller process. On the other hand, if the FBF is not set to ON (the result of 8430 is “N”), the process returns to the calling process.

FIG. 85 is a diagram illustrating an example of the I ² CI / O expander address table according to the fifth embodiment of this invention.

As described above, 16 addresses from “C0h” to “DEh” can be set in the I ² CI / O expander 615. In the fifth embodiment, since bidirectional slaves and unidirectional slaves coexist, I ² CI / O can be distinguished so that the data transmission destination can be a unidirectional slave or a bidirectional slave. A slave type field has been added to the expander address table.

  The controller 574 of the first master IC 570a refers to the slave type to determine whether the data transmission destination is a bidirectional slave or a unidirectional slave (step 8402 in FIG. 84A).

  Also, for the all-call address and the reset address that are common addresses, it is necessary to set a bidirectional slave and a unidirectional slave respectively (shaded entries in FIG. 85). Therefore, when the bidirectional slave and the unidirectional slave are mixed, four of the 16 addresses cannot be used as unique addresses.

  FIG. 86 is a flowchart illustrating a procedure of condition pre-output change processing according to the fifth embodiment of this invention.

  The condition pre-output changing process is a preparation process when outputting a stop condition or a start condition as described above. That is, the signal levels of the connection line SDA and the connection line SCL are set in advance so that the stop condition output process (FIG. 83) and the start condition output process (FIG. 82) can be easily executed. The procedure will be specifically described below.

  First, the controller 574 determines whether or not the next transmission data is in a stop condition based on the data transmission status or the like (8601). If the next transmission data is a stop condition (the result of 8601 is “Y”), the signal level of the connection line SDA is set to LOW (8602).

  In the stop condition output process, as shown in FIG. 83, the signal levels of the connection line SCL and the connection line SDA are set to LOW, and then the signal level is set to HIGH in the order of the connection line SCL and the connection line SDA. Create a stop condition. The condition pre-output change process is executed in step 8409 in FIG. 84A and step 8426 in FIG. 84B, but the signal level of the connection line SCL is set to LOW in the process immediately before execution. Accordingly, in the stop condition output process, it is possible to output the stop condition without executing the processes of step 8301 and step 8302, and it is possible to output the stop condition faster.

  If the next transmission data is not in the stop condition (the result of 8601 is “N”), the controller 574 determines whether or not the next transmission data is in the start condition (8603). If the next transmission data is not in the start condition (the result of 8603 is “N”), the process returns to the calling process without setting the signal levels of the connection line SDA and the connection line SCL.

  When the next transmission data is in the start condition (the result of 8603 is “Y”), the controller 574 sets the signal level of the connection line SDA to HIGH (8604), and subsequently sets the signal level of the connection line SCL. Set to HIGH (8605).

  In the start condition processing, as shown in FIG. 82, the start condition is set by setting the signal level to LOW in the order of the connection line SDA and the connection line SCL while the signal levels of the connection line SCL and the connection line SDA are HIGH. Establish. Therefore, before executing the start condition output process, the signal levels of the connection line SCL and the connection line SDA are set to HIGH in advance in the processes of steps 8604 and 8605. In this way, in the start condition output process, it is possible to output the start condition without executing the processes of step 8202 and step 8203, and it is possible to output the start condition faster.

  FIG. 87 is a timing chart illustrating a procedure for transmitting data from the first master IC 570a to the slave according to the fifth embodiment of this invention. FIG. 87A is a timing chart when data is transmitted to the unidirectional slave, and FIG. 87B is a timing chart when data is transmitted to the bidirectional slave.

  As shown in FIG. 87A, when transmitting data to the unidirectional slave, the first master IC 570a outputs a start condition and then changes the connection line SCL, which is a timing signal line, eight times. Data is transmitted at the timing of change.

  As described above, in the fifth embodiment, when the production control data for controlling the production device is transmitted, the start condition (restart condition) is outputted without outputting the stop condition, and the next slave is outputted. Send data to. On the other hand, when the initialization instruction data is transmitted, as shown in FIG. 87A, after the start condition is output, the initialization instruction data is transmitted and the stop condition is output.

  As shown in FIG. 87 (B), when transmitting data to the bidirectional slave, the first master IC 570a is a timing signal line after outputting a start condition as in the case of the unidirectional slave. The connection line SCL is changed eight times, data is transmitted in accordance with the change timing, and a dummy pulse not accompanied by data transmission is output to the connection line SCL.

  The dummy pulse is output by setting the signal level of the connection line SCL to HIGH in the process of step 8407 and then setting it to LOW in the process of step 8408 in the data transmission process to the bidirectional slave shown in FIG. 84A. The In response to the output of the dummy pulse, a response signal is output from the bidirectional slave. At this time, the response signal output from the bidirectional slave is discarded. The subsequent processing is the same as in the case of the unidirectional slave. By mounting in this way, it becomes possible to share data output between the general-purpose product (unidirectional slave) and the non-general-purpose product (bidirectional slave), and the processing can be simplified.

  Even when the bidirectional slave occupies the connection line SDA due to the influence of noise or the like, as described in the first embodiment, the master IC has a predetermined number of times (9 times), The occupied state may be canceled by changing the signal level of the connection line SCL.

  As described above, according to the fifth embodiment of the present invention, it is possible to output a predetermined voltage level without requiring a pull-up resistor as in the conventional open drain circuit, so that a high speed can be achieved. Communication can be realized.

  According to the fifth embodiment of the present invention, a general-purpose product (unidirectional slave) and a non-general-purpose product (bidirectional slave) can be mixed and used as slaves. In addition, since the data output of the unidirectional slave and the bidirectional slave is shared, the processing can be simplified.

  According to the fifth embodiment of the present invention, the state where the non-general-purpose product (bidirectional slave) occupies the data line can be released. Further, since no ACK release request is issued to a general-purpose product (unidirectional slave), high-speed communication can be realized.

  According to the fifth embodiment of the present invention, the predetermined voltage levels of the data line (connection line SDA) and the timing line (connection line SCL) are changed prior to transmission of the start condition or stop condition. In addition, a start condition or a stop condition can be transmitted at high speed.

In the fifth embodiment of the present invention, as shown in FIG. 85, information for determining whether the slave is a bidirectional slave or a unidirectional slave is held in the I ² CI / O expander address table. It may be determined whether the slave is a bidirectional slave or a unidirectional slave by setting the address. Hereinafter, a modification in which different addresses are set depending on whether the slave is a bidirectional slave or a unidirectional slave will be described.

  FIG. 88 is an explanatory diagram of the slave address 2200 included in the data output from the presentation control device 550 to the decoration control device 610 according to the modification of the fifth embodiment of the present invention.

  In the first embodiment, the slave address 2200 is composed of a fixed address part 2201 consisting of upper 3 bits and a variable address part 2202 consisting of lower 5 bits. On the other hand, in the modified example of the fifth embodiment, the first 1 bit in the fixed address part consisting of the upper 3 bits is information for identifying the slave to be transmitted. Specifically, “0” is set in the unidirectional mode in which data is transmitted to the unidirectional slave, and “1” is set in the bidirectional mode in which data is transmitted to the bidirectional slave.

Therefore, the value corresponding to the second bit of the fixed address portion 2201 is set to “1”, and the value corresponding to the third bit is set to “0”. In addition, the configuration of the variable address unit 2202 is set in the same manner as in the first embodiment. As described above, since the slave address 2200 is configured, the I ² CI / O expander address table according to the modification of the fifth embodiment is configured as illustrated in FIG.

FIG. 89 is a diagram illustrating an example of an I ² CI / O expander address table according to a modification of the fifth embodiment of this invention.

The I ² CI / O expander address table of the modification of the fifth embodiment of the present invention includes two types of slave addresses for unidirectional mode and bidirectional mode. Specifically, the unidirectional mode addresses are “40h” to “5Eh”, and the bidirectional slave addresses are “C0h” to “DEh”. In addition, since it is possible to identify whether the mode is the unidirectional mode or the bidirectional mode, it is not necessary to include the slave type in the I ² CI / O expander address table.

  Therefore, in the modification of the fifth embodiment of the present invention, it is not necessary to hold the common address for the unidirectional mode and the common address for the bidirectional mode, respectively. Individual management is possible.

  FIG. 90 is a timing chart showing a procedure for transmitting data from the first master IC 570a to the slave according to a modification of the fifth embodiment of the present invention.

  In the modification of the fifth embodiment of the present invention, the first master IC 570a always outputs a dummy pulse at the ninth clock. When data is transmitted to the bidirectional slave address, a response signal (ACK) is output at the timing of the ninth clock. At this time, when the first master IC 570a is configured to be able to receive ACK, it is possible to perform processing according to whether or not the data is correctly transmitted based on whether or not ACK is received. .

  If the slave that receives the data is a unidirectional slave, the data corresponding to the 9th bit pulse may be discarded. For example, hardware settings such as dropping the 9th bit input to ground may be used.

  By implementing in this way, even if the bidirectional slave occupies the connection line SDA to output the response signal (ACK) at the timing when the pulse of the ninth clock is output, the master IC waits during that time. Even in a configuration in which unidirectional slaves and bidirectional slaves coexist, the processing can be continued without occupying the connection line SDA.

  Further, switching between the unidirectional mode and the bidirectional mode of the master IC may be implemented by hardware by providing a mode select setting register (REG). Such a modification will be described with reference to FIGS. 91 and 92. FIG.

  FIG. 91 is a block diagram illustrating a configuration of a first master IC 570a according to another modification of the fifth embodiment of the present invention.

  The first master IC 570a shown in FIG. 91 is different from the first master IC 570a of the fifth embodiment of the present invention in that it includes a mode select setting REG585 and a selection circuit 586.

  The selection circuit 586 includes a MODE SEL terminal configured to select an output circuit by changing the connection destination. Specifically, when the MODE SEL terminal is connected to GND, an output circuit for unidirectional communication is selected, and when connected to a power supply, an output circuit for bidirectional communication is selected.

  When an output circuit for unidirectional communication is selected, a signal output from the controller 574 is supplied to the driver 576c. On the other hand, when an output circuit for bidirectional communication is selected, a signal output from the controller 574 is sent to the driver 576a, and further, the received signal is transmitted to the controller 574 via the filter 575a.

  When the MODE SEL terminal is connected to GND and the output circuit for unidirectional communication is selected, the unidirectional mode in which no ACK request is made or the ACK request is made according to the value set in the mode select setting REG585. One of the bidirectional modes to be performed is selected. Specifically, as shown in FIG. 92, when “00H” is set in the mode select setting REG585, the unidirectional mode is set, and when “01H” is set, the bidirectional mode is set.

  Note that the connection line SCL only outputs a signal from the master IC side in both the unidirectional mode and the bidirectional mode, and therefore does not include a configuration for receiving a signal from the slave side. Absent.

  With the configuration as described above, in another modification of the fifth embodiment of the present invention, it is possible to switch to the unidirectional mode or the bidirectional mode by the selection circuit 586 and the mode select setting REG585.

  Also, as an embodiment, a pachinko machine that generates a special game state corresponding to the result of the variable display game is disclosed, but not limited to the variable display game, the special game corresponding to the result of other auxiliary games Of course, it may be a gaming machine that generates a state.

  For example, when a predetermined condition is satisfied, an entrance of a specific winning device is opened (the movable member of the specified winning device is actuated to open the entrance), and a game ball taken into the winning device is provided inside the winning device. A game in which lottery is selected for which winning area (there is a specific winning area or a general winning area) may be used as an auxiliary game. In this case, a special game state occurs when the game ball taken into the winning device wins a specific winning area.

  Also, as an embodiment, a pachinko machine that generates a special game state corresponding to the result of the special figure variation display game is disclosed, but in response to the result of the general figure fluctuation display game (or It is naturally intended that the present invention can be applied even to a pachinko machine that generates a special gaming state (due to the result of the display game). For example, even a pachinko machine that generates a special game state when the entrance of a specific winning device is opened according to the result of the normal game display game and a game ball taken into the winning device wins a specific winning area. The present invention is applicable.

  Further, as an embodiment, a configuration in which the game control device and the effect control device are separated is disclosed, but the game control device and the effect control device constitute a single control device. Of course, it is intended that the game control device itself may be configured as a group overall control means.

  Furthermore, all the embodiments disclosed in this specification can be applied to other gaming machines such as pachislot machines.

  The embodiment disclosed this time is illustrative in all points and is not restrictive. The scope of the present invention is shown not by the above description of the invention but by the scope of claims, and is intended to include all modifications within the scope and meaning equivalent to the scope of claims.

  As described above, the present invention can be applied to a gaming machine in which an effect control device controls an effect device via a plurality of decoration control devices.

1 gaming machine 2 body frame (outer frame)
3 Front frame (game frame)
9a, 9b Decoration member 10 Game board 12 Auxiliary game device unit 13 1st movable illumination 13a Illumination drive 1st motor (MOT)
14 Second movable illumination 14a Illumination drive second motor (MOT)
15 Reliability notification device 29 Abnormality notification LED
30 Speakers 45 Side lamps 51 Center case 53 Display device 58 Movable effect device 63 First effect unit 64 Second effect unit 70 First effect member 71 The accessory drive first motor (MOT)
80 2nd production member 81 Second article drive second motor (MOT)
500 Game control device 550 Production control device 570a First master IC
570b Second master IC
581 Command register (REG)
582 Status register (REG)
583 Self-address setting register (REG)
584a, 584b Gate 600 Relay board 603 Empty terminal monitor 610 Decoration control device 615 I ² CI / O expander 620 Decoration device 625 Decoration device board 640 Bus monitoring watchdog timer (WDT)
641 Self-occupied watchdog timer (WDT)
1600 Simple relay board 3200, 3300 Abnormality determination table

Claims (7)

When the game ball passes through a predetermined start winning area provided in the game area, a variable display game is displayed in which a plurality of pieces of identification information are displayed in a variable manner. In a gaming machine capable of generating a gaming state,
Game control means for comprehensively controlling games in the game area;
A plurality of directing devices for directing games;
In response to a command from the game control means, an effect control means for controlling the plurality of effect devices,
Dividing each of the systems of the effect devices into a plurality of groups, and providing group unit control means for each group to control the effect devices belonging to the divided group,
The production control means is configured as a group overall control means for comprehensively controlling each of the group unit control means,
A timing signal line for transmitting a timing signal from the group overall control means to the group unit control means;
A data line for transmitting a data signal from the group overall control means to the group unit control means;
By enabling the data transmission from the group overall control means to each group unit control means,
The group overall control means is:
Voltage output means for outputting a predetermined voltage level to the group unit control means via the data line;
The voltage output means includes
By changing the voltage level to be output to the data line corresponding to the data to be transmitted to the group unit control unit, the data is sequentially transmitted to the group unit control unit,
The group unit control means includes:
When receiving the data addressed to itself transmitted by the group overall control means, a bidirectional unit for outputting the response signal to the group overall control means via the data line to which the data is transmitted by the group overall control means A gaming machine comprising control means or unidirectional unit control means that does not output the response signal. The group unit control means includes:
Connecting the group control unit and the bidirectional unit control unit, and connecting the group control unit and the unidirectional unit control unit by the data line;
Current regulating means for regulating a current flowing through the data line when the bidirectional unit control means outputs the response signal to a data line connecting the group overall control means and the bidirectional unit control means. The gaming machine according to claim 1, further comprising: The group unit control means includes
Individual addresses that differ between the group unit control means are pre-assigned,
The group overall control means is:
Based on the individual address, the group unit control means is configured to be able to specify whether it corresponds to either the unidirectional unit control means or the bidirectional unit control means,
When transmitting data to the bidirectional unit control means, a request to release the data line is made each time a predetermined unit of data is transmitted,
3. The gaming machine according to claim 2, wherein when data is transmitted to the unidirectional unit control means, a request for releasing the data line is not made. The bidirectional unit control means includes
Counts the number of times the signal level of the timing signal line changes, and determines whether or not the number of changes in the signal level of the timing signal line has reached a predetermined number in order to determine the response timing for outputting the response signal Response timing determination means for
When the response timing determining means determines that the number of changes in the signal level of the timing signal line has reached the predetermined number, the response signal is output by occupying the data line and changing the signal level. And having a function of releasing the response signal by releasing the data line based on a change in signal level of the timing signal line after outputting the response signal,
The group overall control means is:
And a release request output unit configured to change the signal level of the timing signal line based on the transmission of a predetermined unit of data and to request the bidirectional unit control unit to release the data line. The gaming machine according to claim 2. The group overall control means is:
It is configured to be able to set whether or not to release the data line to each group unit control means,
The unidirectional unit control means includes:
In response to a command from the group overall control unit, the group overall control unit is configured to be able to specify whether or not the data line release request is performed,
If the data line release request is not made, the voltage level of the data line is determined based on the change in the signal level of the timing signal line at the timing when the data line release request is made. Get as
When the data line release request is made, the voltage level of the data line is acquired as received data even if the signal level of the timing signal line changes at the timing when the data line release request is made. The gaming machine according to claim 4, wherein the gaming machine is discarded without any problem. The group overall control means is:
A transmission start command process for changing the signal level of the data line to a second level in a state in which the signal level of the timing signal line is maintained at the first level when data transmission by the transmission unit is started; Configured to run,
Prior to execution of the transmission start command processing, the voltage level of the data line is changed by the voltage output means to change the signal level of the data line to a level different from the first level, and The gaming machine according to any one of claims 2 to 5, further comprising pre-output changing means for changing a signal level of the timing line to a level different from the second level. The group overall control means is:
While the signal level of the timing signal line is maintained at the third level in the middle of data transmission or at the last timing of data transmission, the signal level of the data signal line is different from the second level. Is configured to be able to execute an update command process for changing to a level of 4,
The pre-output changing means is
Prior to execution of the update command process, the voltage level of the data line is changed by the voltage output means to change the signal level of the data line to a level different from the fourth level, and The gaming machine according to claim 6, wherein the signal level of the timing line is changed to a level different from the third level.