JP2012089541A - Multilayer circuit board - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the number of layers in a multilayer circuit board as much as possible, by developing a configuration in which more wiring patterns are led out from lands formed on a surface for mounting a semiconductor device thereon in the multilayer circuit board for mounting the semiconductor device having many electrodes arranged thereon in a lattice form.SOLUTION: There is provided a multilayer circuit board in which, in many lands 6 formed in a lattice form on a surface for mounting a semiconductor device thereon, at intervals of two in an outermost side of the land columns, one land is removed to collectively lead out wiring patterns 5.

Description

  The present invention relates to a multilayer circuit board for mounting a semiconductor device in which a large number of electrodes are arranged in a grid pattern on a mounting surface.

  With the development of electronic devices in recent years, semiconductor devices have become highly functional, and the number of signals that realize functions has increased. Further, the size of semiconductor devices is forced to be reduced due to cost competition, and the mounting density of electrical terminals for transmitting signals is increasing year by year.

  In general, in order to increase the number of electrodes serving as electrical terminals in a small area and increase the mounting density of the electrodes, a semiconductor device in which electrodes are arranged in a grid pattern on the electrode formation surface is used. To mount this semiconductor device on a multilayer circuit board, a connection land is formed on the multilayer circuit board at a portion corresponding to the electrode of the semiconductor device, and a conductor bump is formed between the land and the electrode of the semiconductor device. Make electrical connections.

  However, in a semiconductor device in which electrodes are arranged in a grid pattern, it is difficult to draw a wiring pattern for transmitting a signal out of the lands arranged in a grid pattern on the multilayer circuit board. In particular, since the land at the center cannot be drawn outward on the surface layer, it is drawn from the surface other than the surface layer through the through hole. If the number of signals drawn through the through hole is large, a large number of layers are required as a circuit board.

  When a multilayer circuit board is configured by stacking circuit boards on which high-density circuit patterns are formed, a high-density wiring method such as a build-up method is used, and there are problems in terms of manufacturing cost, reliability, and yield. . When circuit boards are stacked in multiple layers, through holes used for connection between wiring patterns and layers are formed for each layer and stacked, which increases the required manufacturing accuracy. Further, all layers must be free from defects, resulting in poor yield and high cost.

  Therefore, in order to reduce the number of layers of the multilayer circuit board, it is necessary to suppress the required number of layers by increasing the number of wiring patterns drawn on the surface layer.

  For this reason, in order to increase the number of lead-outs on the surface layer, there is a method in which the lands and corresponding semiconductor device electrodes and conductor bumps are deleted, and an internal signal wiring pattern is drawn between them (for example, Patent Documents) 1).

  In addition, regarding the land arrangement, the parameter n is calculated from the land pitch, the land diameter, the pattern width, the space between patterns, and the number of wiring patterns that can be arranged between adjacent lands. There is a method of arranging a land for drawing a wiring pattern on the hypotenuse of an isosceles triangle having a base and a diagonal direction as a hypotenuse, and increasing the number of leads (for example, see Patent Document 2).

JP-A-11-102990 JP 11-186332 A

  However, according to the conventional method, the number of lead wiring patterns can be increased by arranging lands on the hypotenuses of the isosceles triangles and extracting the wiring patterns between the hypotenuse lands. It does not mention the combination when there are multiple, and it cannot be said that the number of drawers is maximized.

  An object of the present invention is to improve the conventional method, and to provide a multilayer circuit board that can draw more signals by considering a combination of land arrangements and can reduce the number of layers even in one layer. To do.

  In order to achieve the above object, a multilayer circuit board according to the present invention has a plurality of lands corresponding to electrodes of a semiconductor device on which a semiconductor device in which a plurality of electrode rows are provided in a grid pattern on the mounting surface from the outside toward the center. In a multilayer circuit board having rows formed in a grid pattern, lands constituting the land rows, lands for mounting other electronic components, and wiring patterns for connecting these lands, The configuration is such that every two outer lands are deleted and one land is deleted, and the wiring pattern connected to the lands in the center side land row is drawn to the portion where the lands are deleted. To do.

  As described above, in the multilayer circuit board of the present invention, every two outermost rows of land rows on the mounting surface of the semiconductor device are deleted, and the space is used for drawing the wiring pattern of the inner land. As a result, the number of wiring pattern leads can be further increased, and a multilayer circuit board having a smaller number of layers can be obtained, so that the reliability can be improved and the cost can be reduced.

The perspective view showing the multilayer circuit board which mounted the semiconductor device and electronic component in embodiment of this invention Disassembled perspective view before mounting the semiconductor device Explanatory drawing which shows the electrode formation surface of the semiconductor device Explanatory drawing of land row and wiring pattern of the part where the semiconductor device is mounted Sectional view of the part where the semiconductor device is mounted Explanatory drawing which shows the surface which forms the land of the multilayer circuit board Explanatory drawing of the land row | line | column and wiring pattern of the part which mounts the semiconductor device as embodiment of this invention Explanatory drawing of the land row | line | column and wiring pattern of the part which mounts the semiconductor device as a comparative example (basic structure of a prior art example) with respect to embodiment of this invention Explanatory drawing which extracted a part of land row in an embodiment of the invention

  In the multilayer circuit board according to the present invention, a plurality of land rows corresponding to the electrodes of a semiconductor device for mounting a semiconductor device in which a plurality of electrode rows are provided in a lattice shape from the outside toward the center on the mounting surface are formed in a lattice shape. In a multilayer circuit board having lands constituting a land row, lands for mounting other electronic components, and wiring patterns for connecting these lands, every two outermost lands of the land row for mounting a semiconductor device are arranged. In this configuration, one land is deleted, and wiring patterns connected to lands in the land row on the central portion side are drawn out to the portion where the land is deleted.

  With this configuration, the number of wiring patterns drawn out on the mounting surface of the semiconductor device can be increased, the number of stacked layers as a multilayer circuit board can be reduced, and the yield, reliability, and manufacturing cost can be reduced. Reduction can be achieved.

(Embodiment)
In the description of the embodiment of the present invention, the configuration of the entire multilayer circuit board will be described first. FIG. 1 is a perspective view showing a multilayer circuit board on which a semiconductor device and electronic components according to an embodiment of the present invention are mounted. A semiconductor device 2 and other electronic components such as a resistor 3 and a capacitor 4 are mounted on the multilayer circuit board 1. FIG. 2 is an exploded perspective view before the semiconductor device is mounted. Signal transmission between the components is electrically performed from the land 6 on which the semiconductor device 2 is mounted as shown in FIG. 2 to the land 6 on which the component is mounted through the wiring pattern 5.

  Next, mounting of the semiconductor device 2 and the multilayer circuit board 1 will be described. An example of the electrode forming surface 8 which is the mounting surface of the semiconductor device 2 is shown in FIG. As shown in FIG. 3, the electrode 9 is divided into an outer side and a central part on the electrode forming surface 8 and arranged in a lattice shape. In addition, an electrode is arranged in a lattice shape only on the outer side, Some are arranged in a lattice pattern. The outer electrode group 9 </ b> A mainly serves as a signal system electrode of the semiconductor device 2, and the central electrode group 9 </ b> B is configured as a power system electrode of the semiconductor device 2. The semiconductor device 2 and the multilayer circuit board 1 are electrically connected by a conductor such as a solder ball 10 between the electrode 9 constituting the electrode row of the semiconductor device 2 and the land 6 constituting the land row on the multilayer circuit substrate 1. Connected to.

  Next, the extraction of the wiring pattern 5 from the land 6 on the multilayer circuit board 1 will be described. FIG. 4 is an explanatory diagram of a land row and a wiring pattern in a portion where the semiconductor device is mounted according to the embodiment of the present invention. In particular, a part of the land row on the multilayer circuit board 1 is extracted. The design rule is that one wiring pattern 5 can be drawn between the lands 6. In this case, the lands 6 in the first and second rows lead out the wiring pattern 5 on the surface layer. Since the land 6 in the third and subsequent rows cannot draw a wiring pattern on the surface layer, a through hole 11 is formed in the vicinity of the land 6 and the wiring pattern is drawn from a layer other than the surface layer.

  FIG. 5 shows a cross-sectional view of a portion where the semiconductor device according to the embodiment of the present invention is mounted. In particular, the state of the cross section of the multilayer circuit board 1 when the wiring pattern 5 is drawn out from the surface layer via the through hole 11 is shown. The through hole 11 serves to electrically connect the layers of the multilayer circuit board 1. As described above, by using the through hole 11 in the multilayer circuit board 1, it is possible to draw the wiring pattern 5 from the land 6 on the center side and transmit the signal. However, if the number of lands 6 that must be drawn out of the surface layer is increased, the number of layers of the multilayer circuit board 1 must be increased, which increases the cost as described above.

  FIG. 6 is an explanatory diagram showing a surface on which a land of the multilayer circuit board in the embodiment of the present invention is formed. As shown in FIG. 6, the multilayer circuit board 1 according to the embodiment of the present invention deletes one land every two outermost lands 6 in order to maximize the number of wiring patterns drawn on the surface layer. The wiring pattern 5 at the center is drawn out in the vacant space. Also, the solder ball 10 is not formed on the electrode of the semiconductor device 2 corresponding to the deleted land. As a specific example of the multilayer circuit board 1, FIG. 7 shows an enlarged view of the main part of FIG. In this wiring rule, it is assumed that one wiring pattern 5 can be passed between the lands 6. In FIG. 7, by using the space of the land deleted portion 7 which is a portion from which the land has been deleted, for the wiring pattern extraction from the land 6 on the center side, the surface layer can be extracted up to the third column, and the number of extraction wiring patterns can be reduced. You can increase.

  Next, it will be described that deleting one land every two can increase the number of wiring pattern extractions most. As a specific example, FIG. 4 shows the case where no land is deleted, FIG. 8 shows the case of a comparative example where every other land is deleted, and FIG. 7 shows the case where every other land is deleted. To do. All of them have the same design rule, and one wiring pattern 5 can be drawn between the lands 6. First, when there is no land deletion portion, 18 wiring patterns 5 can be drawn from the lands 6 in 2 columns and 9 rows. Next, when every other land is deleted, 23 wiring patterns 5 can be drawn from the lands 6 in 3 columns and 9 rows. Finally, when every other land is deleted, 24 wiring patterns 5 can be drawn out from the lands 6 in 3 columns and 9 rows, and there is no land deletion place or one land is deleted every other land. It can be seen that the number of wiring pattern extractions is larger than that in the case of the above.

  Next, the reason why the number of wiring pattern leads increases when every two lands are deleted will be described. FIG. 9 is an explanatory diagram partially extracting a land row in the embodiment of the present invention. When the wiring rule is that one wiring pattern 5 can be passed between adjacent lands 6 and one land is deleted every n rows from the outermost land 6, the land group having the largest number of wiring patterns 5 drawn out. 12 becomes as shown in FIG. If a larger number of land groups 12 that can maximize the number of leads can be arranged, the total number of leads of the wiring pattern 5 can be maximized. Therefore, in order to arrange the land groups 12 as many as possible, it is preferable to delete every other land as shown in FIG. In this case, three land groups 12 can be made from the lands 6 in 3 columns and 9 rows. However, if every other land is deleted as shown in FIG. 8, only two land groups 12 are made. I can't. Similarly, when n> 2 or more, the number of land groups 12 is smaller than when every other land is deleted. Therefore, by deleting one land every two, it is possible to maximize the number of wiring pattern leads.

  Further, as a specific example, a BGA semiconductor device having a size of 27 mm and a number of electrode terminals of 533 is used. When there is no land deletion part, when every other land is deleted, every second land is replaced with one land. In the case of deletion, when comparing the number of lead-out patterns of the surface layer wiring pattern, when there is no land deletion portion, 192 is deleted, every other land is deleted, 240 is every other land, and every other land is When deleted, there are 252 lines. As a result, when every second land is deleted, 60 lands can be drawn on the surface layer compared to when no land is deleted and 60 lands are removed every other land. I found that there are many. The design rule here is that one wiring pattern can be drawn between adjacent lands. When every other land is deleted, 12 wiring patterns are drawn out to the lower multilayer circuit board side through the through holes, and in some cases, it is necessary to increase the number of layers as the multilayer circuit board. Become. For example, in the embodiment of the present invention, a multi-layer circuit board having a four-layer structure can be formed, but in a conventional example (comparative example), a five-layer structure is used. You will have to use the board.

  This is because, as a multilayer circuit board, the reliability of through-hole connection between layers increases as the number of layers increases, cutting due to distortion of thin wiring patterns and changes in conductor resistance due to changes in wiring width, It is possible to obtain a great effect of solving problems such as a reduction in reliability and an increase in manufacturing cost due to an increase in defects.

  As is apparent from the above description, the multilayer circuit board described in the embodiment of the present invention forms a plurality of land rows corresponding to the electrodes of the semiconductor device in a lattice shape, and the land only on the outermost side of the land rows. In which every other land is deleted. According to the multilayer circuit board of this configuration, wiring that can be drawn out on the multilayer circuit board side while securing an electrical path for transmitting power and signals between the semiconductor device and the multilayer circuit board via the electrodes and lands. It is possible to provide the maximum number of patterns per predetermined area.

  If the present invention is used, the number of wiring patterns drawn per predetermined area increases, so the number of electrodes can be reduced and the size of the semiconductor device can be reduced without reducing the number of layers of the multilayer circuit board. As a result, the cost of the semiconductor device can be reduced.

  The multilayer circuit board of the present invention can be effectively used in various electronic devices and electronic control devices on which semiconductor devices are mounted.

DESCRIPTION OF SYMBOLS 1 Multilayer circuit board 2 Semiconductor device 3 Resistance (other electronic components)
4 Capacitors (other electronic components)
5 Wiring pattern 6 Land 7 Land deletion part (the part where the land is deleted)
8 Electrode forming surface (mounting surface)
9 electrode 9A electrode group (electrode)
9B Electrode group (electrode)

Claims (1)

A plurality of land rows corresponding to the electrodes of the semiconductor device for mounting a semiconductor device in which a plurality of electrode rows are provided in a grid shape on the mounting surface from the outside toward the central portion is formed in a grid shape to constitute the land row. In a multilayer circuit board having lands, lands for mounting other electronic components, and wiring patterns for connecting these lands, every two outermost lands in the land row for mounting the semiconductor device, one land A multilayer circuit board having a configuration in which wiring patterns connected to lands in a land row on the central side are drawn together in a portion from which the lands are deleted.

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