JP2012084980A - Semiconductor circuit and semiconductor circuit system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor circuit and a semiconductor circuit system capable of operating with a further appropriate synchronized clock when a plurality of semiconductor circuits need to operate with a synchronized clock.SOLUTION: In a semiconductor circuit system 100, a oscillation capacitor 140a is connected to a oscillation terminal 124a of a semiconductor circuit 10a in semiconductor circuits 10a, 10b, and 10c, and a clock generated by a clock generating circuit unit 12a is input to oscillation terminals 124b and 124c of the semiconductor circuits 10b and 10c.

Description

  The present invention relates to a semiconductor circuit and a semiconductor circuit system, and more particularly, to a semiconductor circuit and a semiconductor circuit system including a charging current source and a discharging current source.

  In various electronic devices and the like, light emitting elements are used. Recently, however, a plurality of light emitting elements are used to produce various light effects. When the number of light emitting elements is small, it is possible to realize various light effects by using one control IC and performing switching control of the light emitting elements. However, when the number of light-emitting elements increases, switching control of the plurality of light-emitting elements with one control IC leads to software complexity. Therefore, when controlling a large number of light emitting elements, switching control using a plurality of control ICs can suppress the complication of software. In this case, the clocks of the plurality of control ICs are synchronized. It is necessary to let

  As a technique related to the present invention, for example, in Patent Document 1, as a light emitting element driving circuit, illuminance information from an illuminance sensor is acquired, brightness is determined, the determination result is output, and brightness change information is also provided. The brightness determination unit to be output, the brightness setting based on the brightness determination result of the brightness determination unit, the brightness setting information that outputs the brightness setting information and the brightness change information, and the brightness setting unit And a light emitting element driving unit that drives the light emitting element with a current having a current value corresponding to the luminance setting information. The light emitting element driving circuit further detects a terminal voltage of one terminal of the light emitting element and compares it with a predetermined voltage, and detects at least one of brightness change information or brightness change information. Based on the output of the comparison unit, a boost determination unit that determines whether or not to boost the terminal voltage of the other side terminal of the light emitting element, and when the boost determination unit determines to boost, the other side terminal of the light emitting element A boosting circuit unit that boosts the terminal voltage and does not boost the terminal voltage of the other terminal of the light emitting element when it is determined by the boosting determination unit that boosting is not performed.

JP 2010-67749 A

  As a method of synchronizing the clocks used in the plurality of control ICs, the plurality of control ICs are assigned to either the master IC or the slave IC, and the clock generated by the master IC is supplied to the slave IC. In this way, the clock can be synchronized. At this time, when the settings related to the master IC and the slave IC are made to the respective control ICs, it is possible to set them using external pins. In this case, the number of pins increases, so the IC package There is a problem that becomes larger. Therefore, when the settings related to the master IC and the slave IC are performed for the respective control ICs, the settings can be made without increasing the number of pins by performing the settings using the control serial control signal. However, when the control serial control signal changes due to noise or the like, the roles of the master IC and slave IC change, and there is a possibility that a plurality of control ICs cannot operate with synchronized clocks.

  An object of the present invention is to provide a semiconductor circuit and a semiconductor circuit system that can operate a plurality of semiconductor circuits with a synchronized clock more appropriately when it is necessary to operate them with a synchronized clock. .

  The semiconductor circuit according to the present invention includes a current source unit including a charging current source, a discharging current source connected in series to the charging current source, and a connection point between the charging current source and the discharging current source. An oscillation terminal that can be connected to a capacitor that is connected and charged / discharged by a charging current source and a discharging current source, and when the capacitor is connected to the oscillation terminal, the voltage of the oscillation terminal is predetermined. A charging current is supplied from the charging current source to the capacitor when the voltage is lower than the first lower limit reference value, and the discharging current source is supplied from the capacitor when the voltage at the oscillation terminal is larger than the predetermined first upper limit reference value. And a clock generation unit capable of generating a signal that is controlled to supply a discharge current as a clock to a terminal for oscillation of another semiconductor circuit having the same configuration as the semiconductor circuit Capacitor Warini characterized in that it comprises a clock terminal for inputting the generated clock by the clock generator of the semiconductor circuit.

  The semiconductor circuit according to the present invention includes a current source unit including a charging current source, a discharging current source connected in series to the charging current source, and a connection point between the charging current source and the discharging current source. An oscillation terminal that can be connected to a capacitor that is connected and charged / discharged by a charging current source and a discharging current source, and when the capacitor is connected to the oscillation terminal, the voltage of the oscillation terminal is predetermined. A charging current is supplied from the charging current source to the capacitor when the voltage is lower than the first lower limit reference value, and the discharging current source is supplied from the capacitor when the voltage at the oscillation terminal is larger than the predetermined first upper limit reference value. And a clock generation unit capable of generating, as a clock, a signal that is controlled to supply a discharge current to the semiconductor circuit, wherein the oscillation terminal has another configuration identical to that of the semiconductor circuit. It is a conde Sa is characterized in that it is a terminal for inputting a clock generated by the clock generator of another semiconductor circuit connected to the oscillation element.

  A semiconductor circuit system according to the present invention includes a current source unit including a charging current source, a discharging current source connected in series to the charging current source, and a connection point between the charging current source and the discharging current source. And an oscillation terminal that can connect a capacitor that is charged and discharged by a charging current source and a discharging current source, and when the capacitor is connected to the oscillation terminal, the voltage of the oscillation terminal is A charging current is supplied from the charging current source to the capacitor when smaller than the predetermined first lower limit reference value, and when the voltage at the oscillation terminal is larger than the predetermined first upper limit reference value, the discharging current is output from the capacitor. A semiconductor circuit system comprising a plurality of semiconductor circuits having a clock generation unit capable of generating, as a clock, a signal that is controlled to supply a discharge current to a source, wherein one half of the plurality of semiconductor circuits Guidance Connect a capacitor to the oscillator terminal of the circuit, characterized by inputting a clock generated by the clock generator of one of a semiconductor circuit to the oscillation pin for the rest of the semiconductor circuit of the plurality of semiconductor circuits.

  According to the semiconductor circuit and the semiconductor circuit system configured as described above, a capacitor is connected to the oscillation terminal of one semiconductor circuit to generate a clock, and the clock is input to the oscillation terminal of another semiconductor circuit. Therefore, one semiconductor circuit and another semiconductor circuit can be operated with a synchronized clock.

In an embodiment concerning the present invention, it is a figure showing a semiconductor circuit system provided with a semiconductor circuit. In an embodiment concerning the present invention, it is a figure showing a clock generation circuit part. In an embodiment concerning the present invention, it is a figure showing a signal etc. outputted by a clock generation circuit part. In an embodiment concerning the present invention, it is a figure showing a clock generation circuit part. In an embodiment concerning the present invention, it is a figure showing a clock etc. inputted into a clock generation circuit part. In an embodiment concerning the present invention, it is a figure showing a clock generation circuit part. In an embodiment concerning the present invention, it is a figure showing a clock etc. inputted into a clock generation circuit part.

  Embodiments according to the present invention will be described below in detail with reference to the drawings. In the following description, in the semiconductor circuit system, one semiconductor circuit is assumed to be a master IC and two semiconductor circuits are assumed to be slave ICs. However, the number may be other than the number of master ICs / slave ICs. For example, the number of slave ICs may be increased to several tens.

  Also, in the following, in all the drawings, the same symbols are attached to the same elements, and the duplicate description is omitted. In the description in the text, the symbols described before are used as necessary.

  FIG. 1 is a diagram illustrating a semiconductor circuit system 100 including semiconductor circuits 10a, 10b, and 10c. The semiconductor circuit system 100 synchronizes the internal logic unit 13a of the semiconductor circuit 10a and the internal logic units 13b and 13c of the semiconductor circuits 10b and 10c that are slave ICs with a clock generated by the semiconductor circuit 10a that is a master IC. Has a function to operate.

  The semiconductor circuit 10a is a circuit set as a master IC by a control serial signal (not shown). In addition, the semiconductor circuit 10a includes a clock generation circuit unit 12a that generates a clock and an internal logic unit 13a that operates with the clock generated by the clock generation circuit unit 12a. The internal logic unit 13a includes a sequential circuit and a combinational circuit.

  FIG. 2 is a diagram illustrating the clock generation circuit unit 12a. The clock generation circuit unit 12a includes a charging current source 121a, a switch circuit 122a, a discharging current source 123a, an oscillation terminal 124a, a first upper limit reference power source 125a, a first lower limit reference power source 126a, An upper limit comparator 127a, a first lower limit comparator 128a, a control circuit 129a, and a clock terminal 130a are included.

  Charging current source 121a is a constant current source having one end connected to input voltage source 1 and the other end connected to one end of switch circuit 122a. The charging current source 121a is a constant current source that supplies a current having a current value of 2I.

  The switch circuit 122a is a switch circuit having one end connected to the other end of the charging current source 121a and the other end connected to one end of the discharging current source 123a. The switch circuit 122a is switching-controlled by the control circuit 129a.

  The discharge current source 123a is a constant current source having one end connected to the other end of the switch circuit 122a and the other end connected to the ground 2 to be grounded. Note that the discharging current source 123a is a constant current source for flowing a current having a current value I.

The first upper limit reference source 125a has a function of outputting a voltage Vh ₁ determined in advance. The positive terminal of the first upper limit reference power supply 125a is connected to the plus input terminal of the first upper limit comparator 127a, and the negative terminal of the first upper limit reference power supply 125a is connected to the ground 2 and grounded. Yes.

The first upper limit comparator 127a has a negative input terminal connected to a connection point between the switch circuit 122a and the discharge current source 123a, a positive input terminal connected to a positive terminal of the first upper limit reference power supply 125a, and an output. This is a comparison circuit whose terminal is connected to the control circuit 129a. The first upper limit comparator 127a is greater than the voltage Vh ₁ voltage input to the negative input terminal is input to the positive input terminal and outputs the High, the voltage inputted to the negative input terminal If the voltage is lower than the voltage Vh ₁ input to the plus side input terminal, Low is output.

The first lower limit reference source 126a has a function of outputting a voltage Vl ₁ determined in advance. The positive terminal of the first lower limit reference power supply 126a is connected to the positive input terminal of the first lower limit comparator 128a, and the negative terminal of the first lower reference power supply 126a is connected to the ground 2 and grounded. Yes.

The first lower limit comparator 128a has a negative input terminal connected to a connection point between the switch circuit 122a and the discharge current source 123a, a positive input terminal connected to the first lower limit reference power supply 126a, and an output terminal as a control circuit. 129a is a comparison circuit connected to 129a. The first lower limit comparator 128a is greater than the voltage Vl ₁ voltage input to the negative input terminal is input to the positive input terminal and outputs the High, the voltage inputted to the negative input terminal If the voltage is smaller than the voltage Vl ₁ input to the plus side input terminal, Low is output.

  The control circuit 129a turns off the switch circuit 122a when the first upper limit comparator 127a changes from Low to High, and turns on the switch circuit 122a when the value of the first lower limit comparator 128a changes from High to Low. The function to switch to. The control circuit 129a generates an output signal as a clock signal that changes the output signal from Low to High when the switch circuit 122a is turned on and changes from High to Low when the switch circuit 122a is turned off. And a function of outputting from the clock terminal (CKO) 130a.

  The oscillation terminal 124a is a terminal connected to the positive terminal of the oscillation capacitor 140a, and is a terminal connected to the connection point between the switch circuit 122a and the discharge current source 123a. The oscillation capacitor 140a is a capacitive element that is grounded with a positive terminal connected to the oscillation terminal 124a and a negative terminal connected to the ground 2.

Here, the operation of the clock generation circuit unit 12a configured as described above will be described. FIG. 3 is a diagram illustrating signals output from the clock generation circuit unit 12a. First, when the voltage of the oscillation pin 124a is smaller than Vl _1, the value of the first lower limit comparator 128a is changed to Low from High, switching on the switch circuit 122a. As a result, a current I (2I-I) flows from the charging current source 121a to the oscillation capacitor 140a to charge the oscillation capacitor 140a, and as shown in the upper diagram of FIG. The voltage of the oscillation terminal 124a increases.

When the voltage of the oscillation pin 124a is greater than Vh _1, the value of the first upper limit comparator 127a is changed to High from Low, switch off the switch circuit 122a. As a result, the electric charge accumulated in the oscillation capacitor 140a flows to the discharge current source 123a with a current value I, and the oscillation capacitor 140a is discharged. As shown in the upper diagram of FIG. The voltage at the oscillation terminal 124a drops.

  Further, as shown in the lower diagram of FIG. 3, the control circuit 129a changes the clock from Low to High when the switch circuit 122a is turned on, and changes from High to Low when the switch circuit 122a is turned off. Form a signal. The clock signal is supplied to the internal logic unit 13a of the semiconductor circuit 10a to operate each logic and is output from the clock terminal 130a.

  The semiconductor circuits 10b and 10c are circuits set as slave ICs by a control serial signal (not shown). The semiconductor circuits 10b and 10c have substantially the same configuration as the semiconductor circuit 10a. The semiconductor circuit 10b includes a clock generation circuit unit 12b and an internal logic unit 13b. The semiconductor circuit 10c includes a clock generation circuit unit 12c and an internal logic unit 13c. Each of the internal logic units 13b and 13c includes a sequential circuit and a combinational circuit. Since the semiconductor circuit 10b and the semiconductor circuit 10c have the same configuration, only the semiconductor circuit 10b will be described below, and the description of the semiconductor circuit 10c will be omitted.

  FIG. 4 is a diagram illustrating the clock generation circuit unit 12b. Since the clock generation circuit unit 12b has substantially the same configuration as the clock generation circuit unit 12a, detailed description thereof is omitted. As shown in FIG. 4, the difference between the clock generation circuit unit 12b and the clock generation circuit unit 12a is that the clock generation circuit unit 12a of the semiconductor circuit 10a is replaced with an oscillation capacitor connected to the oscillation terminal 124b. The clock terminal 130a and the oscillation terminal 124b of the semiconductor circuit 10a are connected to each other in order to supply the clock generated by the above. The difference between the clock generation circuit unit 12b and the clock generation circuit unit 12a is that nothing is connected to the clock terminal 130b and is open.

FIG. 5 is a diagram illustrating a clock and the like input to the clock generation circuit unit 12b. The upper diagram of FIG. 5 shows the state of signal waveforms when the clock generated by the clock generation circuit unit 12a of the semiconductor circuit 10a is input to the oscillation terminal 124b via the clock terminal 130a. The lower diagram of FIG. 5 is a diagram illustrating a signal waveform (clock) output by the clock generation circuit unit 12b. As shown in FIG. 5, when the voltage of the oscillation pin 124b is smaller than Vl _1, the value of the first lower limit comparator 128b is changed to Low from High, turning on the switch circuit 122b Switch. When the voltage of the oscillation pin 124b is greater than Vh _1, the value of the first upper limit comparator 127b is changed to High from Low, switch off the switch circuit 122b. Here, as shown in FIG. 5, the control circuit 129a changes from Low to High when the switch circuit 122a is turned on, and changes from High to Low when the switch circuit 122a is turned off. Is generated. The clock signal is supplied to the internal logic unit 13b of the semiconductor circuit 10b to operate each logic.

  Next, the operation of the semiconductor circuit system 100 including the semiconductor circuits 10a, 10b, and 10c will be described. Further, the semiconductor circuit system 100 is set so that the semiconductor circuit 10a functions as a master IC by a control serial signal including communication information between the semiconductor circuits 10a, 10b, and 10c, and the semiconductor circuits 10b and 10c are set as slave ICs. Set to work. In the semiconductor circuit system 100, the function as a master IC on the side supplying the clock to the semiconductor circuit 10a among the semiconductor circuits 10a, 10b, and 10c is set in advance independently of the control serial signal. In 10b and 10c, a function as a slave IC to which a clock is supplied is set in advance independently of the control serial signal. Specifically, an oscillation capacitor 140a is connected to the oscillation terminal 124a of the semiconductor circuit 10a, and the oscillation terminal 124b of the semiconductor circuit 10b and the oscillation terminal 124c of the semiconductor circuit 10c are respectively connected to the clock terminal 130a of the semiconductor circuit 10a. And wired connection.

  In the clock generation circuit unit 12a of the semiconductor circuit 10a, the clock shown in the lower diagram of FIG. 3 is generated, supplied to the internal logic unit 13a of the semiconductor circuit 10a, and for oscillation of the semiconductor circuit 10b via the clock terminal 130a. The signal is supplied to the terminal 124b and the oscillation terminal 124c of the semiconductor circuit 10c.

  The clock generation circuits 12b and 12c of the semiconductor circuits 10b and 10c receive the clock output from the semiconductor circuit 10a (see the upper diagram of FIG. 5), and the clock generation circuits 12b and 12c display the lower diagram of FIG. The clock shown is generated, and the clock is supplied to the internal logic units 13b and 13c of the semiconductor circuits 10b and 10c, respectively.

  As described above, according to the configuration of the semiconductor circuit system 100, the semiconductor circuit 10a is set to function as a master IC on the clock supply side, independently of the master IC / slave IC setting by the control serial signal. The semiconductor circuits 10b and 10c can be set so as to function as a slave IC to which a clock is supplied from the master IC. Thus, even when noise is superimposed on the control serial signal, the semiconductor circuit 10a functions as a side for supplying a clock to the semiconductor circuits 10b and 10c without being affected by the noise. Since 10b and 10c function as a side to which a clock is supplied from the semiconductor circuit 10a, the internal logic units 13a, 13b and 13c of the semiconductor circuits 10a, 10b and 10c can be operated in synchronization with the same clock.

  Next, the clock generation circuit unit 22 of the semiconductor circuit 20 which is a modification of the clock generation circuit units 12a, 12b, and 12c of the semiconductor circuits 10a, 10b, and 10c will be described. FIG. 6 is a diagram illustrating the clock generation circuit unit 22. The clock generation circuit unit 22 includes a charging current source 221, a switching circuit 222, a discharging current source 223, an oscillation terminal 224, a first upper limit reference power source 225, a first lower limit reference power source 226, and a first An upper limit comparator 227, a first lower limit comparator 228, a control circuit 229, and a clock terminal 230 are included. Since these are the same as the configurations of the clock generation circuit units 12a, 12b, and 12c, detailed description thereof is omitted. In addition to the above configuration, the clock generation circuit unit 22 further includes a second upper limit reference power supply 231, a second lower limit reference power supply 232, a second upper limit comparator 233, a second lower limit comparator 234, and a control circuit. 235.

The second upper reference power 231 has a function of outputting a voltage Vh ₂ predetermined. The positive terminal of the second upper limit reference power source 231 is connected to the positive input terminal of the second upper limit comparator 233, and the negative terminal of the second upper reference power source 231 is connected to the ground 2 and grounded. Yes. Note that the voltage Vh ₂ of the second upper limit reference power supply 231 is a voltage higher than the voltage Vh _{1 of} the first upper limit reference power supply 225.

The second upper limit side comparator 233 has a negative input terminal connected to the connection point between the switch circuit 222 and the discharge current source 223, a positive input terminal connected to the positive terminal of the second upper limit reference power source 231, and an output. A comparison circuit whose terminal is connected to the control circuit 235. The second upper limit comparator 233 outputs High if the voltage input to the negative input terminal is greater than the voltage Vh ₂ input to the positive input terminal, and the voltage input to the negative input terminal is high. If the voltage is smaller than the voltage Vh ₂ input to the plus side input terminal, Low is output.

The second lower limit reference power source 232 has a function of outputting a predetermined voltage Vl ₂ . The positive terminal of the second lower limit reference power source 232 is connected to the plus input terminal of the second lower limit comparator 234, and the negative terminal of the second lower limit reference power source 232 is connected to the ground 2 and grounded. Yes. The voltage Vl ₂ of the second lower limit reference power source 232 is a voltage smaller than the voltage Vl _{1 of} the first lower limit reference power source 226.

The second lower limit comparator 234 has a negative input terminal connected to a connection point between the switch circuit 222 and the discharge current source 223, and a positive input terminal connected to a positive terminal of the second lower limit reference power source 232 for output. A comparison circuit whose terminal is connected to the control circuit 235. The second lower-side comparator 234 is greater than the voltage Vl ₂ voltage inputted to the negative input terminal is input to the positive input terminal and outputs the High, the voltage inputted to the negative input terminal If the voltage is smaller than the voltage Vl ₂ input to the plus side input terminal, Low is output.

  The control circuit 235 has a function of turning off the discharge current source 223 when the output of the second upper limit comparator 233 is High, and turning on the discharge current source 223 when the output of the second upper limit comparator 233 is Low. Have. In addition, the control circuit 235 turns off the charging current source 221 when the output of the second lower limit side comparator 234 is Low, and turns on the charging current source 221 when the output of the second lower limit side comparator 234 is High. It has a function.

The operation of the clock generation circuit unit 22 configured as described above will be described with reference to FIG. FIG. 7 is a diagram illustrating clocks and the like input to the clock generation circuit unit 22. According to the clock generating circuit 22, when the voltage of the oscillation pin 224 is smaller than the voltage Vl ₂ turns off the charging current source 221, when the voltage of the oscillation pin 224 is greater than the voltage Vl ₂ is charging The current source 221 is turned on. Further, according to the clock generating circuit 22, when the voltage of the oscillation pin 224 is greater than the voltage Vh ₂ turns off the discharging current source 223, when the voltage of the oscillation pin 224 is smaller than the voltage Vh ₂ is The discharge current source 223 is turned on. Therefore, when the semiconductor circuit 20 is set as a slave IC and the clock from the master IC is input to the oscillation terminal 224 instead of the oscillation capacitor 240, as shown in FIG. When the voltage of 224 increases from the voltage Vl ₂ toward the voltage Vh ₁ , the switch circuit 222 is on and the charging current source 221 is also on, so that a current flows through the charging current source 221. When the voltage at the oscillation terminal 224 becomes larger than the voltage Vh ₁ , the switch circuit 222 is turned off, and when the discharge current source 223 is also turned on, a current flows through the discharge current source 223. Thereafter, when the voltage at the oscillation terminal 224 becomes higher than the voltage Vh ₂ which is higher than the voltage Vh ₁ , the discharge current source 223 is turned off. That is, unnecessary power consumption is reduced by stopping the discharge current source 223 during a period in which the voltage of the oscillation terminal 224 is higher than the voltage Vh ₂ .

When the semiconductor circuit 20 is set as a slave IC and the clock from the master IC is input to the oscillation terminal 224 instead of the oscillation capacitor 240, as shown in FIG. When the voltage of 224 decreases from the voltage Vh ₂ toward the voltage Vl ₁ , the switch circuit 222 is off and the discharge current source 223 is also on, so that a current flows through the discharge current source 223. When the voltage at the oscillation terminal 224 becomes smaller than the voltage Vl ₁ , the switch circuit 222 is turned on, and a current flows through the charging current source 221. Thereafter, the charging current source 221 is turned off when the voltage at the oscillation terminal 224 becomes smaller than the voltage Vl ₂ smaller than the voltage Vl ₁ . That is, unnecessary power consumption is reduced by stopping the charging current source 221 during a period in which the voltage of the oscillation terminal 224 is smaller than the voltage Vl ₂ .

When the semiconductor circuit 20 is used as a slave IC, power consumption can be reduced as described above. When the semiconductor circuit 20 is used as a master IC, the oscillation capacitor 240 is connected to the oscillation terminal 224 so that the voltage at the oscillation terminal 224 has the same waveform as that shown in FIG. Become. Since the voltage of the waveform does not become larger than the voltage Vh _{2 and} does not become smaller than the voltage Vl ₂ , a clock similar to that of the semiconductor circuit 10a (see the lower diagram in FIG. 3) is generated and clocked. Can be output from the terminal 230. Thus, by using a plurality of semiconductor circuits 20, each semiconductor circuit 20 can be used as both a master IC and a slave IC, and each semiconductor circuit 20 can be operated with a synchronized clock. A system can be provided. When a plurality of semiconductor circuits 20 are used, power consumption can be reduced particularly when the semiconductor circuit 20 is used as a slave IC.

  1 input voltage source, 2 ground, 10a, 10b, 10c semiconductor circuit, 12a, 12b, 12c clock generation circuit unit, 13a, 13b, 13c internal logic unit, 20 semiconductor circuit, 22 clock generation circuit unit, 100 semiconductor circuit system, 121a charging current source, 122a, 122b switch circuit, 123a discharging current source, 124a, 124b, 124c oscillation terminal, 125a first upper limit reference power supply, 126a first lower limit reference power supply, 127a, 127b first upper limit side comparator, 128a, 128b first lower limit comparator, 129a control circuit, 130a, 130b clock terminal, 140a oscillation capacitor, 221 charging current source, 222 switch circuit, 223 discharging current source, 224 oscillation terminal, 225 first upper limit Reference power 226 1st lower limit reference power supply, 227 1st upper limit side comparator, 228 1st lower limit side comparator, 229 control circuit, 230 clock terminal, 231 2nd upper limit reference power supply, 232 2nd lower limit reference power supply, 233 2nd upper limit side Comparator, 234 Second lower limit comparator, 235 Control circuit, 240 Oscillation capacitor.

Claims (5)

A current source unit including a charging current source and a discharging current source connected in series to the charging current source;
An oscillation terminal connected to a connection point between the charging current source and the discharging current source and capable of connecting a capacitor charged and discharged by the charging current source and the discharging current source;
When the capacitor is connected to the oscillation terminal, when the voltage of the oscillation terminal is smaller than a predetermined first lower limit reference value, a charging current is supplied from the charging current source to the capacitor, A clock generator capable of generating, as a clock, a signal that is controlled to supply a discharge current from the capacitor to the discharge current source when the voltage of the oscillation terminal is greater than a predetermined first upper limit reference value. When,
A semiconductor circuit comprising:
A clock terminal for inputting the clock generated by the clock generation unit of the semiconductor circuit instead of the capacitor to the oscillation terminal of another semiconductor circuit having the same configuration as the semiconductor circuit; A featured semiconductor circuit. A current source unit including a charging current source and a discharging current source connected in series to the charging current source;
An oscillation terminal connected to a connection point between the charging current source and the discharging current source and capable of connecting a capacitor charged and discharged by the charging current source and the discharging current source;
When the capacitor is connected to the oscillation terminal, when the voltage of the oscillation terminal is smaller than a predetermined first lower limit reference value, a charging current is supplied from the charging current source to the capacitor, A clock generator capable of generating, as a clock, a signal that is controlled to supply a discharge current from the capacitor to the discharge current source when the voltage of the oscillation terminal is greater than a predetermined first upper limit reference value. When,
A semiconductor circuit comprising:
The oscillation terminal is
Another semiconductor circuit having the same configuration as the semiconductor circuit, the capacitor being a terminal for inputting the clock generated by the clock generation unit of the other semiconductor circuit connected to the oscillation element A semiconductor circuit characterized by the above. The semiconductor circuit according to claim 1 or 2,
The clock generator is
Stopping the supply of the discharge current when the clock is greater than a second upper limit reference value that is greater than the first upper limit reference value;
The semiconductor circuit, wherein the supply of the charging current is stopped when the clock is smaller than a second lower limit reference value smaller than the first lower limit reference value. A current source unit including a charging current source and a discharging current source connected in series to the charging current source;
An oscillation terminal connected to a connection point between the charging current source and the discharging current source and capable of connecting a capacitor charged and discharged by the charging current source and the discharging current source;
When the capacitor is connected to the oscillation terminal, when the voltage of the oscillation terminal is smaller than a predetermined first lower limit reference value, a charging current is supplied from the charging current source to the capacitor, A clock generator capable of generating, as a clock, a signal that is controlled to supply a discharge current from the capacitor to the discharge current source when the voltage of the oscillation terminal is greater than a predetermined first upper limit reference value. When,
A semiconductor circuit system comprising a plurality of semiconductor circuits having
The capacitor is connected to the oscillation terminal of one semiconductor circuit of the plurality of semiconductor circuits, and the clock of the one semiconductor circuit is connected to the oscillation terminal of the remaining semiconductor circuits of the plurality of semiconductor circuits. A semiconductor circuit system, wherein the clock generated by the generation unit is input. The semiconductor circuit system according to claim 4,
The clock generator is
Stopping the supply of the discharge current when the clock is greater than a second upper limit reference value that is greater than the first upper limit reference value;
The semiconductor circuit system, wherein the supply of the charging current is stopped when the clock is smaller than a second lower limit reference value smaller than the first lower limit reference value.

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