JP2012079266A - Information processing apparatus, fault portion discrimination method and fault portion discrimination program - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an information processing apparatus, in multi-processor configuration, which performs startup processing promptly and is capable of accurately discriminating a fault portion even when an interface fault occurs.SOLUTION: When a BIOS 61 operating on e.g., a CPU 11 detects any fault, a fault detection notice comprising an error code based on an analysis result of a status register 21 in the CPU 11 and an investigation request of a CPU 12 of a communication destination of an interface circuit 5 is transmitted to a BMC 3. On the basis of the error code in the received fault detection notice, a BMCFW 7 operating on the BMC 3 determines a ratio indicating a possibility of a fault suspicious portion as a first suspicious ratio and, on the basis of a read result of a status register in the CPU 12 of the communication destination, determines a ratio indicating a possibility of a fault in the fault suspicious portion as a second suspicious ratio. In accordance with predetermined rules, the determined first and second suspicious ratios are merged to determine a final suspicious ratio, thereby discriminating a fault portion.

Description

  The present invention relates to an information processing apparatus, a failure part determination method, and a failure part determination program, and in particular, an information processing apparatus that is applied to a server and can be suitably applied to a field where maintenance work must be performed accurately and quickly. The present invention relates to a failure part determination method and a failure part determination program.

  Recently, in the field of information processing apparatuses applied to servers and the like, in order to improve performance, as represented by RISC (Reduced Instruction Set Computer) and the like, a plurality of components, that is, a CPU (Central Processor Unit), A technique of adopting a multiprocessor configuration in which pipeline connections are made through an interface circuit has been established.

  When a failure is detected in an information processing device with such a multiprocessor configuration, the CPU suspected of failure, that is, a CPU with a high possibility of failure, is identified, and the subsequent failure is performed smoothly by separating the identified failure component from the operational system. It is important to realize a fault handling function that makes it possible. Therefore, in Japanese Patent Laid-Open No. 2006-178557 “Computer System and Error Processing Method” of Patent Document 1 and Japanese Patent Laid-Open No. 2010-026667 “File Sharing Device and File Sharing System” of Patent Document 2, a multiprocessor configuration is used. An effective technique for determining a faulty part in an information processing apparatus has been proposed.

JP 2006-178557 A (pages 10-13) JP 2010-026667 A (page 7-9)

  In an information processing apparatus having a multiprocessor configuration as described above, a failure of the interface circuit between the CPU and the CPU is detected when the basic input / output system (BIOS) is starting up the apparatus. In such a case, the interface failure detection source CPU can access the communication destination component of the interface circuit in which the interface failure (that is, link failure) is detected (that is, a processor having a processing function such as a CPU or a control device). Therefore, in the conventional fault location determination method, in general, despite the interface failure, without using any information regarding the communication destination component (that is, a processor having a processing function such as a CPU or a control device) Interface failure detection source component, that is, CPU The failure information was analyzed using only the information, and the suspected part of the failure was pointed out. For this reason, the reliability with respect to the detected failure is low, a correct failure part cannot be pointed out by a single failure process, and the failure process is repeated a plurality of times.

  On the other hand, in the information processing apparatuses described in Patent Document 1 and Patent Document 2, each component constituting the multiprocessor (that is, a processor having a processing function such as a CPU or a control device) remotely controls the hardware operation. Since it is connected to the baseboard management controller (BMC) with management and monitoring functions via an interface circuit, the baseboard management controller (BMC) is replaced with the basic input / output system (BIOS). It is possible to perform a part startup process.

  Even if an interface failure is detected when the baseboard management controller (BMC) starts up each component (i.e., CPU, control device, etc.) in such a configuration, the baseboard management controller ( BMC) collects status information not only for the interface failure detection source CPU but also for the communication destination components (ie, CPU, control device, etc.) of the interface circuit where the interface failure is detected, and analyzes the failure location. Can do. However, the baseboard management controller (BMC) has a problem that it takes time to start up because the operation of starting up each component (i.e., CPU, control device, etc.) is slower than the basic input / output system (BIOS). is there.

  The conventional problem in the information processing apparatus including the baseboard management controller (BMC) will be further described with reference to FIG. FIG. 9 is a block configuration diagram showing a block configuration in an information processing apparatus of a conventional multiprocessor configuration, and in order to explain the problem of the conventional fault location determination method when a baseboard management controller (BMC) is used. The schematic structure is shown.

  The information processing apparatus of FIG. 9 shows a case of a multiprocessor configuration of two CPUs 11 and 12, and the two CPUs 11 and 12 each include BIOS 61 and 62 as a basic input / output system that performs startup processing. The status registers 21 and 22 holding the states of the CPUs 11 and 12 are provided, and are configured to be able to communicate with each other via the interface circuit 5. Further, a BMC 3 for remotely managing and monitoring the operation states of the CPUs 11 and 12 is connected to the CPUs 11 and 12 via the interface circuits 41 and 42, respectively. The BMC 3 has a built-in BMC FW 7 as firmware for a baseboard management controller that executes a function for remote management monitoring. When a failure occurs, the BMC 3 reads and outputs the states of the CPUs 11 and 12 according to instructions from the maintenance personnel. be able to.

  In a multiprocessor configuration information processing apparatus in which the BIOS 61 and 62 start up the apparatus, when a failure occurs during initialization of the interface circuit 5 between the CPU 11 and the CPU 12, the interface circuit 5 between the CPU 11 and the CPU 12 is used. Since the state becomes impossible, for example, it becomes impossible to directly access the CPU 12 on the other side as the communication destination from the BIOS 61 operating on the CPU 11 that is the detection source of the interface failure. Therefore, in the conventional failure location determination method, the suspected failure location is determined only from the status of the failure detection source CPU 11 without investigating the status of the counterpart CPU 12 as the communication destination. There was a problem that the accuracy of pointing out the suspected part of the subject would deteriorate.

  In the information processing apparatus of FIG. 9, the BMCFW 7 of the baseboard management controller firmware built in the BMC 3 that manages and monitors the entire information processing apparatus by managing the operation states of the CPUs 11 and 12 is stored on the BMC 3. It is working. Here, the BMCFW 7 can access all the components connected to the interface circuits 41 and 42, that is, the CPUs 11 and 12. Therefore, it is possible to perform all of the startup processing of the information processing apparatus by the BMCFW 7 operating on the BMC 3, and even when a failure occurs during startup, the failure part is determined in the BMC FW 7 of the BMC 3. Thus, it is possible to perform failure processing with higher accuracy. However, there is a problem that the startup processing of the information processing apparatus by the BMC FW 7 of the BMC 3 is slower than the case of the BIOS 61 or 62.

  The present invention has been made in order to solve such a problem, and in a multiprocessor information processing apparatus, the start-up process is quickly performed, and even when an interface failure occurs, the failure site is accurately determined. It is an object of the present invention to provide an information processing apparatus, a fault site determination method, and a fault site determination program that can be discriminated automatically.

  In order to solve the above-described problems, the information processing apparatus, the failure part determination method, and the failure part determination program according to the present invention mainly adopt the following characteristic configuration.

  (1) An information processing apparatus according to the present invention has a multiprocessor configuration including a plurality of processors connected to each other via an interface circuit, and each processor is connected to manage and monitor each connected processor. An information processing apparatus including a baseboard management controller (BMC) to be executed, and firmware (BMCFW) that operates on the baseboard management controller (BMC) operates on each processor By cooperating with the basic input / output system (BIOS), it has a fault processing function for determining the fault site and separating the fault site from the active system, and the basic input / output system (BIOS). Failed during the device startup operation When detected, an error code obtained as a result of analyzing an operation state held by a status register included in a processor in which the basic input / output system (BIOS) operates, and a detected failure are a link failure related to the interface circuit. When the determination is made, a failure detection notification consisting of a communication destination processor investigation request for requesting an analysis of the state of the counterpart processor as the communication destination of the interface circuit is transmitted to the baseboard management controller (BMC), and The firmware (BMCFW) operating on the baseboard management controller (BMC) that has received the failure detection notification relates to the error code included in the failure detection notification with respect to the processor connected via the interface circuit. Based on the obstacle The ratio indicating the possibility of the part is determined as the first suspicious ratio, and if the communication destination processor investigation request is included in the failure detection notification, the communication destination of the interface circuit in which the failure is detected is determined. Based on the result of reading and analyzing the operation state held in the status register provided in the processor on the other side, a ratio indicating the possibility of failure of the suspected failure site is determined as a second suspected rate, and the determined first By determining the suspect ratio of 1 and the second suspect ratio in accordance with a predetermined rule to obtain a final suspect ratio, the part having the highest final suspect ratio is determined as a failure part, The failure site is separated from the operational system.

  (2) A failure location determination method according to the present invention is a failure location determination method for determining a failure location in an information processing apparatus having a multiprocessor configuration including a plurality of processors connected between processors via an interface circuit. A baseboard management controller (BMC) that connects processors and executes management and monitoring of each connected processor is provided, and firmware (BMCFW: BMC Firmware) that operates on the baseboard management controller (BMC) By cooperating with a basic input / output system (BIOS) that runs on the processor, it has a fault handling function that identifies the fault location and isolates the fault location from the operational system. The output system (BIOS) When a failure is detected during execution of an operation, an error code obtained as a result of analyzing an operation state held by a status register included in a processor in which the basic input / output system (BIOS) operates, and a detected failure When it is determined that the link fault is related to the interface circuit, a fault detection notification including a communication destination processor investigation request for requesting an analysis of the state of the counterpart processor that is the communication destination of the interface circuit is sent to the baseboard management controller ( The firmware (BMCFW) that is transmitted to the BMC and receives the failure detection notification and that operates on the baseboard management controller (BMC) is included in the failure detection notification regarding the processor connected via the interface circuit. The error code And determining the ratio indicating the possibility of the failure suspected part as the first suspected ratio, and if the communication destination processor investigation request is included in the failure detection notification, the interface where the failure is detected A ratio indicating the possibility of failure of the suspected failure part is determined as the second suspected ratio based on the result of reading and analyzing the operating state held in the status register provided in the processor on the other side of the circuit communication destination The determined first suspect ratio and the second suspect ratio are merged according to a predetermined rule to obtain a final suspect ratio, so that the part having the highest final suspect ratio is determined as a failed part. And the failure part is separated from the operational system.

  (3) The failure site determination program according to the present invention is characterized in that at least the failure site determination method described in (2) is implemented as a program executable by a computer.

  According to the information processing apparatus, the failure part determination method, and the failure part determination program of the present invention, the following effects can be obtained.

  The first effect is that the suspected part of the failure can be pointed out with high accuracy even for a link failure related to the interface circuit detected by the basic input / output system (BIOS) operating on the CPU during startup of the information processing apparatus. It is in. In the present invention, the baseboard management controller (BMC) that has received the failure detection notification from the BIOS directly accesses not only the information on the suspected failure component analyzed by the BIOS but also the communication destination component of the interface circuit in which the link failure has occurred. Since the failure part is analyzed also using information on the suspected failure part obtained from the obtained analysis result of the state of the communication destination part, it is possible to point out the suspected failure part with high accuracy.

  The second effect is that it is possible to grasp the state of a component that cannot be accessed from the basic input / output system (BIOS) during startup of the information processing apparatus. The reason is that the basic input / output system (BIOS) sends a code for notifying the component to be accessed to the baseboard management controller (BMC) in the failure detection notification and sends the failure detection notification to the baseboard management controller (BMC). This is because the received BMC has a mechanism for directly accessing the parts requested for investigation.

  The third effect is that the startup time of the information processing apparatus can be shortened. In the present invention, even when a link failure related to the interface circuit is detected at the time of starting up the information processing apparatus, the baseboard management controller (BMC) can point out the suspected failure site with high accuracy. Therefore, according to the present invention, it is possible to prevent the separation process and the reboot operation from being repeated for the same failure by pointing out the accurate suspected failure portion, so that the startup time of the information processing apparatus can be shortened. .

It is a block block diagram which shows an example of the block configuration of the information processing apparatus by this invention. 3 is a table for explaining an example of an error code table in which the BIOS holds an error code when a failure is detected in the information processing apparatus shown in FIG. 1. 3 is a table for explaining an example of state information held by a status register in the information processing apparatus shown in FIG. 1. 3 is a table for explaining an example of a failure table in which the BMC holds information related to a failure suspected part in the information processing apparatus illustrated in FIG. 1. 3 is a flowchart for explaining an example of an operation of the information processing apparatus illustrated in FIG. 1. 3 is a table illustrating an example of a failure detection notification format transmitted from a BIOS that has detected a failure to the BMC in the information processing apparatus illustrated in FIG. 1. 6 is a table showing another example of a failure detection notification format transmitted from the BIOS that detects a failure to the BMC in the information processing apparatus shown in FIG. 1; It is a block block diagram which shows the other example different from FIG. 1 of the block configuration of the information processing apparatus by this invention. It is a block block diagram which shows the block structure in the information processing apparatus of the conventional multiprocessor structure.

  Hereinafter, preferred embodiments of an information processing apparatus, a failure part determination method, and a failure part determination program according to the present invention will be described with reference to the accompanying drawings. In the following description, the information processing apparatus and the failure part determination method according to the present invention will be described. However, the failure part determination method may be implemented as a failure part determination program executable by a computer, or Needless to say, the failure site determination program may be recorded on a computer-readable recording medium.

(Features of the present invention)
Prior to the description of the embodiments of the present invention, an outline of the features of the present invention will be described first. According to the present invention, a basic input / output system (BIOS: Basic Input / Output System; hereinafter referred to as BIOS) that operates on a processor having a processing function such as a CPU or a control device in an information processing apparatus having a multiprocessor configuration is started up. The present invention relates to a technique for more accurately discriminating a faulty part of a link fault related to the interface circuit even when a fault during initialization of the interface circuit (link fault) is detected.

  In other words, the present invention relates to a baseboard management controller (BMC: Baseboard Management Controller, hereinafter referred to as BMC) for managing and monitoring the operating state of a plurality of components having a multiprocessor configuration (that is, a processor having a processing function such as a CPU and a control device). BMCFW: BMC Firmware (hereinafter referred to as BMCFW) is linked with the BIOS that starts up the information processing apparatus, and the BMCFW identifies the faulty part. By assigning and analyzing the status (state) of the specified part among a plurality of parts (that is, a processor having a processing function such as a CPU or a control device) constituting the information processing apparatus, the failure part can be accurately analyzed Discrimination is the main feature.

  More specifically, according to the present invention, communication between an interface failure detection source component (hereinafter referred to as CPU 11) and a communication destination component of the interface circuit (hereinafter referred to as CPU 12) occurs when a link failure relating to the interface circuit occurs. Even in a situation where the BIOS running on the CPU 11 cannot directly access the communication destination CPU 12, the communication destination CPU 12 requested to investigate from the BIOS of the CPU 11 in the BMCFW responsible for the failure processing function. It is possible to analyze the states of both the CPU 11 and the CPU 12 to accurately determine the failure site, and thus to shorten the startup time of the information processing apparatus. The main feature is to do.

  The failure site determination method according to the present invention will be further described with reference to the block configuration diagram of FIG. 9 described above. When the BIOS 61 operating on the CPU 11 detects a link failure of the interface circuit 5 during startup of the information processing apparatus, access between components (between the CPU 11 and the CPU 12) via the interface circuit 5 is interrupted. For this reason, it is impossible to access the CPU 12 from the BIOS 61 operating on the CPU 11, and in the conventional failure processing, as described above, only the state in the CPU 11 is used to determine the failure part. .

  On the other hand, in the present invention, the BIOS 61 of the failure detection source CPU 11 newly transmits a failure detection notification to the BMC 3 that manages the failure processing function via the interface circuit 41 and transmits the failure detection notification. In this case, a mechanism is provided in which a code indicating the CPU 12 that is the communication destination of the interface circuit 5 in which the link failure has occurred is notified and a request for investigating the state of the communication destination CPU 12 is made.

  Further, the BMC FW 7 which is firmware operating on the BMC 3 reads the contents of the status register 22 of the communication destination CPU 12 that cannot be read from the BIOS 61 of the failure detection source CPU 11 via the interface circuit 42 to detect the failure. It has a function of analyzing a failure part related to a failure detection notification received from the BIOS 61 of the original CPU 11 via the interface circuit 41.

  Further, the BIOS 61 of the CPU 11 of the failure detection source and the BMC FW 7 operating on the BMC 3 merge the suspected proportions of the failed parts obtained by analyzing the respective states of the CPU 11 and the CPU 12 based on a predetermined rule. BMCFW7 has a mechanism to recreate the final suspicion rate.

  By adopting the above-described mechanism, even when a link failure relating to the interface circuit 5 occurs, the state of the CPU 11 and the CPU 12 can be analyzed more accurately. The suspected part can be pointed out.

(Configuration example of embodiment)
Next, an example of the block configuration of the information processing apparatus of the present invention will be described in detail with reference to FIG. FIG. 1 is a block configuration diagram showing an example of a block configuration of an information processing apparatus according to the present invention, which is substantially the same as the block configuration of the conventional information processing apparatus described in FIG. The firmware BMCFW built in the BMC that manages and monitors the state of the processor (that is, a processor having a processing function such as a CPU or a control device) cooperates with the BIOS built in each component (that is, a processor having a processing function such as a CPU or control device) 9 is different from the case of FIG. 9 in that it has a failure processing function for accurately determining the faulty part.

  The information processing apparatus of FIG. 1 is similar to the conventional information processing apparatus of FIG. 9 in that two components connected to each other via the interface circuit 5, such as CPUs 11 and 12, and CPUs 11 and 12, respectively, are interface circuits 41 and 42, respectively. And a baseboard management controller BMC3 connected via the. On the CPUs 11 and 12, the BIOS 61 and 62 operate as basic input / output systems (firmware) that perform startup processing, respectively. On the BMC 3, BMCFW 7 as firmware for a baseboard management controller that performs remote management and monitoring of the CPUs 11 and 12. Works. The CPUs 11 and 12 are respectively provided with status registers 21 and 22 for holding the internal state including the operation state relating to the interface circuit 5.

  The status information held in the status registers 21 and 22 can be read by the BIOS 61 and 62 incorporated in each of the CPUs 11 and 12, and the BMCFW 7 operating on the BMC 3 also has the interface circuits 41 and 42 respectively. Can be read directly through.

  The BIOS 61 operating on the CPU 11 performs link-up of the interface circuit 5 between the CPU 11 and the CPU 12 during startup of the apparatus. The link-up of the interface circuit 5 indicates an operation for enabling the interface called the interface circuit 5. In addition, when the BIOS 61 of the CPU 11 detects a link failure related to the interface circuit 5, failure processing for determining the failure part is started, and is detected as a failure detection notification to the BMCFW 7 of the BMC 3 that manages the failure processing function. An error code indicating the content of the failure and a code indicating the communication destination component (for example, the CPU 12) that was trying to communicate when the failure occurred are notified via the interface circuit 41. Note that the BIOS 61 of the CPU 11 is in the process of starting up, and since the link up of the interface circuit 5 between the CPU 11 and the CPU 12 has not been successful, direct access to the CPU 12 on the other side that is the communication destination of the interface circuit 5 Can not do it.

  Here, the BIOS 61 operating on the CPU 11 and the BIOS 62 operating on the CPU 12 each hold a list of error codes as shown in FIG. FIG. 2 is a table for explaining an example of an error code table in which the BIOS 61, 62 holds an error code at the time of failure detection in the information processing apparatus shown in FIG. This is a table listing components (CPU, control device, etc .; in this embodiment, CPUs 11 and 12) that were processed when an error code and a failure were detected. That is, the error code table shown in FIG. 2 includes at least an error code 81, a processing target component 82, a link failure 83, and a failure suspected component 84.

  In the error code table of FIG. 2, for example, when the error code 81 is “0x0000_0001”, the processing target component 82 indicating the component in which the failure indicated by the error code is detected is the CPU 11, as indicated by the link failure 83. In addition, the failure indicated by the error code is a link failure relating to the interface circuit 5 that has occurred during the link-up, and as shown in the failure suspected component 84, the suspected failure component indicating a component with a high possibility of failure is the CPU 11. It shows that there is.

  When the error code 81 is “0x0000_0002”, the processing target component 82 indicating the component in which the failure indicated by the error code is detected is the CPU 11, and the failure indicated by the error code is indicated by the link failure 83. Is a link failure relating to the interface circuit 5 that occurred during link-up, and as shown in the failure suspected component 84, the suspected failure component indicating a component with a high possibility of failure is the CPU 12.

  When the error code 81 is '0x0000_1001', the processing target component 82 indicating the component that detected the failure indicated by the error code is the CPU 11, but as indicated by the link failure 83, the error code indicates The failure is not a link failure and, as shown in the failure suspected component 84, indicates that the failure suspected component indicating a component with a high possibility of failure is the CPU 11.

  Further, FIG. 3 shows a configuration example of the status registers 21 and 22 of the CPUs 11 and 12, respectively. FIG. 3 is a table for explaining an example of the status information held by the status registers 21 and 22 in the information processing apparatus shown in FIG. 1, and an information part regarding the transmission / reception status of the interface circuit 5 connecting the CPUs 11 and 12. Only take out and show. As shown in the Bit column 91 in FIG. 3, the status registers 21 and 22 are configured with, for example, 16 bits as a register area indicating the transmission / reception state of the interface circuit 5.

  Here, as shown in the Bit column 91 of FIG. 3, one byte is prepared for each of the transmission side and the reception side of the interface circuit 5, and the register area for recording the state of the reception side is the 0th bit. Bits [0: 7] from the first bit to the seventh bit, and the register area for recording the state on the transmitting side is bits [8:15] from the eighth bit to the fifteenth bit. In the present embodiment, the case where the transmission side and the reception side are composed of six stages as communication communication stages of the interface circuit 5 is illustrated.

  As shown in the explanation column 92 and the content column 93, as for the state on the receiving side, the 0th bit [0] indicates the state relating to the presence / absence of reception indicating whether or not the CPU 11 or 12 has received, and “0” indicates A state without reception, “1” indicates a state with reception. The first bit [1] indicates a state relating to the presence / absence of normal termination indicating whether or not the reception processing of the CPUs 11 and 12 has terminated normally, “0” is a normal termination state, and “1” is an abnormal termination. Shows the state. In addition, the second to seventh bits [2: 7] indicate a state regarding the presence / absence of normal termination for each stage indicating whether or not each of the six stages indicating the progress of the reception processing of the CPUs 11 and 12 has been normally completed. '0' indicates a state without abnormality, and '1' indicates a state with abnormality.

  Here, with respect to the second to seventh bits [2: 7] indicating the presence / absence of normal termination by stage, the second bit [2] indicates whether there is a normal termination at the first stage of reception processing, and “0” is abnormal. “No”, “1” indicates an abnormal state, and thereafter, the third to seventh bits [3: 7] sequentially indicate the second, third, fourth, fifth, and sixth stages of the reception process. The presence or absence of normal termination is shown as “0” indicating no abnormality and “1” indicating an abnormality.

  The same applies to the state on the transmission side, and the eighth bit [8] indicates the state relating to the presence / absence of transmission indicating whether or not the CPU 11 or 12 has transmitted, '0' is the state without transmission, and '1' 'Indicates a state with transmission. The ninth bit [9] indicates a state relating to the presence / absence of normal termination indicating whether or not the transmission processing of the CPUs 11 and 12 is normally terminated, “0” is a normal termination state, and “1” is an abnormal termination. Shows the state. In addition, the 10th to 15th bits [10:15] indicate the state regarding the presence / absence of normal termination for each stage indicating whether or not each of the six stages indicating the progress status of the transmission processing of the CPUs 11 and 12 is normally completed. '0' indicates a state without abnormality, and '1' indicates a state with abnormality.

  Here, with respect to the 10th to 15th bits [10:15] indicating the presence / absence of normal termination by stage, the 10th bit [10] indicates whether there is normal termination at the first stage of transmission processing, and “0” is abnormal. No state, “1” indicates an abnormal state, and the 11th to 15th bits [11:15] are the second, third, fourth, fifth, and sixth stages of the transmission process in order. The presence or absence of normal termination is shown as “0” indicating no abnormality and “1” indicating an abnormality.

  The BMCFW 7 which is the firmware for the baseboard management controller operating on the BMC 3 can directly access the status registers 21 and 22 holding the states of the CPUs 11 and 12 via the interface circuits 41 and 42, respectively. . Further, the BMCFW 7 has a failure processing function for performing failure analysis on each of the CPUs 11 and 12 with reference to the status registers 21 and 22, and failure analysis results analyzed by the BIOS 61 and 62 and failure analysis analyzed by the BMCFW 7 itself. It has a function to calculate the failure suspect ratio by merging the results.

  FIG. 4 is a table for explaining an example of a failure table in which the BMC 3 holds information related to a suspected failure component in the information processing apparatus shown in FIG. 1, and the suspected failure determined based on the failure analysis result of the BIOS 61, 62. It is the table | surface which has listed the suspicious ratio of components.

  The failure table shown in FIG. 4 includes at least an error code 101, a suspicious component 1102, a suspicious component 2 103, a suspicious proportion 1 104, and a suspicious proportion 2 105, and the failure detection source CPU 11, For each error code of the error code 101 uniquely determined by the 12 BIOSes 61 and 62, the suspected part 1 102, the suspected part 2 103, the suspected part 1 104, and the suspected part 2 105 suspected of the failure Two percentages are listed. Here, each error code shown in the error code 101 of the failure table of FIG. 4 and the error code 81 of the error code table of FIG. 2 has a one-to-one correspondence.

  That is, in the failure table of FIG. 4, each of the two components (CPUs 11 and 12 in this embodiment) connected via the interface circuit 5 is possible for each error code uniquely determined by the BIOS 61 and 62. The suspicion ratios quantitatively indicating the degree of sex are prepared in advance as a suspicion ratio 1 104 and a suspicion ratio 2 105.

  For example, as described in the error code table of FIG. 2, when the error code 81 is “0x0000 — 0001”, the analysis result of the BIOS 61 and 62 indicates that the suspected failure part with high possibility of failure is the CPU 11. It is estimated that the failure indicated by the error code is a link failure that occurred during link-up. Therefore, in the failure table of FIG. 4, when the error code 101 is “0x0000 — 0001”, as shown in the suspicious component 1102 and the suspicious proportion 1 104, the suspicious rate that the failed suspicious component is the CPU 11 is It is 70%, and as shown in the suspicious part 2 103 and the suspicious ratio 2 105, the suspicious ratio that the failed suspicious part is the CPU 12 is set to 30% in advance.

  Further, as described in the error code table of FIG. 2, when the error code 81 is “0x0000_0002”, the analysis result of the BIOS 61, 62 is estimated that the failure part is the CPU 12, and the error The failure indicated by the code is a link failure that occurred during linkup. Therefore, in the failure table of FIG. 4, when the error code 101 is “0x0000_0002”, as shown in the suspicious component 1 102 and the suspicious proportion 1 104, the suspected rate that the suspected failure component is the CPU 12 is It is 70%, and as shown in the suspicious part 2 103 and the suspicious ratio 2 105, the suspicious ratio that the failed suspicious part is the CPU 11 is set to 30% in advance.

  Further, as described in the error code table of FIG. 2, when the error code 81 is “0x0000_1001”, the analysis result of the BIOS 61, 62 is estimated to be the CPU 11, and the error code indicates Unlike the case where the error code 81 is “0x0000 — 0001”, the failure is not a link failure but a failure inside the CPU 11. Therefore, in the error code table of FIG. 4, when the error code 101 is “0x0000 — 1001”, as shown in the suspected part 1102 and the suspected ratio 1 104, the suspected ratio that the suspected faulty part is the CPU 11 Is 100%, and as shown in the suspicious component 2 103 and the suspicious proportion 2 105, the suspicious proportion that the failure suspicious component is the CPU 12 is set to 0% in advance.

(Description of operation of embodiment)
Next, an example of the operation of the information processing apparatus shown in FIG. 1 will be described with reference to the flowchart of FIG. FIG. 5 is a flowchart for explaining an example of the operation of the information processing apparatus shown in FIG. 1. FIG. 5A is a basic input / output system BIOS 61, 62 that operates on two components, that is, CPUs 11 and 12, respectively. FIG. 5B shows an example of the operation of the baseboard management controller firmware BMCFW 7 operating on the BMC 3. In the following description, in order to make the description easy to understand, the operation when the BIOS 61 operating on the CPU 11 of the two CPUs 11 and 12 detects a failure during the startup of the apparatus will be described. The BIOS 62 that operates on the CPU 12 also has exactly the same operation by simply replacing the BIOS 61 and the BIOS 62.

  First, the BIOS 61 operating on the CPU 11 focuses on the operation when the failure is detected during the initial setting of the interface circuit 5 between the CPU 11 and the CPU 12 as a startup process of the CPU 11. ).

  5A, the BIOS 61 of the CPU 11 is performing the initial setting of the interface circuit 5 between the CPU 11 and the CPU 12 being started up, that is, the link initial setting (link up) of the interface circuit 5 is being performed. When an abnormality such as “no response from the CPU 12 side” or “an unexpected response has been received from the CPU 12 side” is detected in the stage (step A1), failure processing for identifying the faulty part is started, and step A2 Migrate to

  When the failure processing is activated, the BIOS 61 accesses the bits [8:15] of the status register 21 of the CPU 11 having the configuration as shown in FIG. 3, and the transmission operation from the CPU 11 to the CPU 12 side is abnormal. Check if it has occurred. In other words, when the BIOS 61 reads the bits [8:15] of the status register 21, it analyzes whether or not an abnormality has occurred in the transmission operation as the interface circuit 5, that is, the link initial setting operation. Referring to the error code table of FIG. 2, the corresponding error code is specified (step A2).

  That is, in step A2, first, the status of the accessed bit [8] of the status register 21 is checked for “with / without transmission”. If the bit [8] is “0”, the BIOS 61 instructs the transmission operation. Despite this, it is detected that the transmission operation has not been performed due to some abnormality. On the other hand, if bit [8] is “1”, it is confirmed that some transmission operation has been performed to the CPU 12 via the interface circuit 5.

  If any transmission operation has been performed, the status of the bit [9] of the status register 21 is checked for the “presence / absence of normal transmission completion”. If bit [9] is “0”, transmission is performed. On the other hand, if the bit [9] is “1”, the transmission operation cannot be normally performed due to some abnormality, and it is detected that the operation has ended abnormally.

  If the transmission operation has ended abnormally, next, bits [10:15] of the status register 21 are examined. As described above, the bits [10:15] of the status register 21 store the presence / absence of abnormality for each progress stage of the transmission operation for each bit. That is, each of bits [10] to [15] corresponds to the first to sixth stages of the transmission operation, and is “0” when there is no abnormality, but when an abnormality occurs. '1' is stored.

  As described above, if the bit [8] of the status register 21 is “0”, it means that an abnormality that the transmission operation is not performed has occurred, and the bit [8] of the status register 21 is “1”. Even if “,” if “1” exists in bits [9:15], the transmission operation has ended abnormally. On the other hand, if bit [8] of status register 21 is “1” and “1” does not exist in bits [9:15], the transmission operation ends normally, and there is an abnormality other than the transmission operation. It can be determined that it has occurred. Further, the BIOS 61, based on the processing content when the failure is detected, for example, based on whether or not a link initial setting command related to the interface circuit 5 is being transmitted, the link failure related to the interface circuit 5 Or not.

  If it is determined that a link failure has occurred, the BIOS 61 confirms that the transmission operation has been performed normally from the contents of bits [8:15] of the status register 21, and the communication destination of the interface circuit 5 is determined. If the CPU 12 is determined as a suspected faulty part, and if it is confirmed from the contents of bits [8:15] of the status register 21 that some abnormality has occurred in the transmission operation, the CPU 11 itself is determined as the suspected faulty part. .

  Based on the abnormality determination processing result as described above, the BIOS 61 refers to the error code table shown in FIG. 2 and determines the link failure determined from the processing target component on which the BIOS 61 operates and the processing content when the failure is detected. The processing target part 82, the link fault 83, and the fault suspected part 84 are searched by using the presence or absence of the fault and the fault suspected part at the time of the link fault determined from the contents of bits [8:15] of the status register 21, and the corresponding error is searched. The code is extracted from the error code 81. For example, if the processing target component that detected the failure is the CPU 11, and the CPU 11 is a link failure that becomes a suspected failure component, the error code is '0x0000_0001' as shown in the error code table of FIG. . If the processing target component that has detected the failure is the CPU 11 and the CPU 11 is a suspected failure component but is not a link failure, the error code is “0x0000_1001” as shown in the error code table of FIG. become.

  When the failure content analysis process in step A2 in FIG. 5A is performed, next, the BIOS 61 first sets the link initialization related to the interface circuit 5 in order to set information for notifying the BMC 3 of the detection of the failure. It is determined whether a link failure has been detected (step A3).

  If a link failure has been detected (yes in step A3), a failure detection notification with the error code determined in step A2 and a code indicating a communication destination component via the interface circuit 5 is sent to the BMC 3 Transmission is performed via the interface circuit 41 (step A4). For example, if the processing target component that detected the failure is the CPU 11 and the CPU 11 is a link failure that becomes a suspected failure component, as described above, the error code is '0x0000_0001' and the communication destination component The code indicating the CPU 12 is a code indicating the CPU 12, and the BMC 3 to which the failure detection notification is to be transmitted is further investigated in the status register 22 on the CPU 12 side as the communication destination of the interface circuit 5 to analyze the suspected failure portion. I will ask.

  On the other hand, if a link failure is not detected (no in step A3), a failure detection notification consisting only of an error code not including a code indicating a communication destination component is transmitted to the BMC 3 via the interface circuit 41 (step S3). A5). For example, if the processing target component that detected the failure is the CPU 11 and the CPU 11 is a suspected failure component but not a link failure, the error code is “0x0000_1001”, and the code indicating the communication destination component is all A failure detection notification in which “0” (a communication destination component, ie, a code indicating that the investigation of the CPU 12 is not necessary) is set is transmitted, and only the failure detection notification is used to identify the suspected failure site. You will be asked to analyze.

  An example of the format of the failure detection notification transmitted from the BIOS 61 to the BMC 3 is shown in FIG. That is, FIG. 6 is a table showing an example of a failure detection notification format transmitted from the BIOS 61 that has detected a failure to the BMC 3 in the information processing apparatus shown in FIG. Needless to say, even if the BIOS 62 operating on the CPU 12 detects a failure, the BMC 3 can be notified using the same format as in FIG.

  As shown in the Bit column 111 in FIG. 6, the failure detection notification format notified to the BMC 3 is, for example, 48 bits. As shown in the explanation column 112 and the content column 113, the bits [0:31] An error code (that is, a code for specifying a failure) determined as a failure analysis result in the BIOS 61 is set, and a communication destination component code indicating a communication destination component is set in bits [32:47]. Here, the part code of the communication destination is assigned to each part in a one-to-one correspondence. As shown in the content column 113, if a link failure is detected, When a code other than '0x0000' indicating the communication destination component (for example, '0x0002' for CPU 12 and '0x0001' for CPU 11) is set and a fault other than a link fault has been detected. Is set to code “0x0000” of all “0” as a code indicating that the communication destination to be investigated is not designated.

  As another example different from the format of the failure detection notification transmitted from the BIOS 61 to the BMC 3 in order to suppress the traffic through the interface circuit 41, a format as shown in FIG. 7 is used. Also good. FIG. 7 is a table showing another example of a failure detection notification format transmitted from the BIOS 61 that has detected a failure to the BMC 3 in the information processing apparatus shown in FIG. Here, it goes without saying that even if the BIOS 62 operating on the CPU 12 detects a failure, the BMC 3 can be notified using the same format as in FIG.

  As shown in the Bit column 121 of FIG. 7, the failure detection notification format notified to the BMC 3 is composed of, for example, 33 bits, which has a smaller information amount than that of FIG. 6, and as shown in the explanation column 122 and the content column 123, as shown in FIG. As in the case of FIG. 6, an error code is set in bits [0:31]. However, unlike in the case of FIG. If a communication failure investigation request bit is set and a link failure is detected, '1' (investigation request identifier) indicating that a communication destination investigation is requested is set, and a failure other than a link failure is set. If it has been detected, '0' (investigation unnecessary identifier) indicating that no investigation of the communication destination is requested is set.

  However, when the failure detection notification format as shown in FIG. 7 is used, the BMCFW 7 operating on the BMC 3 is set to “1” indicating that the failure detection notification received from the BIOS 61 requests the investigation of the communication destination. Based on the error code included in the failure detection notification, it is assumed that the communication destination list or the like that can identify the communication destination component to be investigated is provided.

  Next, an example of the operation of the base board management controller firmware BMCFW 7 of the BMC 3 that has received the failure detection notification as shown in FIG. 6 or 7 from the BIOS 61 will be described with reference to the flowchart of FIG.

  As shown in FIG. 5 (B), when the BMCFW 7 operating on the BMC 3 receives a failure detection notification from the BIOS 61 via the interface circuit 41 (step B1), failure processing for identifying the failed part is started. The process proceeds to step B2.

  When the failure processing is started, the BMC FW 7 refers to the failure table shown in FIG. 4 based on the error code included in the received failure detection notification, and the failure suspected component and the failure corresponding to the error code. The suspicious ratio is extracted (step B2). For example, when the error code included in the received failure detection notification is “0x0000_0001”, the suspected component 1102, suspected component 2 103, suspected rate 1 104, suspected rate 2 105 in the failure table of FIG. As shown in the figure, it is possible for the failure part that the suspected rate that the suspected failure part indicating the failure part is CPU 11 is 70% and the suspected part that the failure suspect part indicating the failure part is CPU 12 is 30%. Extracted as the first suspicious rate indicating sex.

  Next, the BMCFW 7 refers to information indicating whether or not there is a link failure in the received failure detection notification (for example, bits [32:47] in the case of FIG. 6 and bits [32] in the case of FIG. 7). Then, it is checked whether or not the detected failure is a link failure related to the interface circuit 5, and it is determined whether or not it is necessary to investigate the communication destination component of the interface circuit 5 (step B3). Here, if the failure detection notification has the format shown in FIG. 6, as described above, bits [32:47] include a code other than “0x0000” indicating the communication destination component in the case of a link failure. If it is set and there is no link failure, “0x0000” is set. Further, in the format as shown in FIG. 7, information indicating the presence or absence of a link failure is set in bit [32], which is a survey request bit of the communication destination component.

  If it is determined that the detected failure is not a link failure and it is not necessary to investigate the communication destination component (no in step B3), the failure detection from the BIOS 61 is immediately detected without investigating the communication destination component. Based on only the notification, the process proceeds to step B7 in order to point out and treat the suspected part of the failure.

  On the other hand, when it is determined that the detected failure is a link failure related to the interface circuit 5 and it is necessary to investigate the communication destination component (yes in step B3), the process proceeds to step B4, and the communication destination component. And the state of the communication destination component is analyzed (step B4).

  Here, if the failure detection notification from the BIOS 61 is in the format as shown in FIG. 6, the BMC FW 7 is the communication destination component set in the bits [32:47] of the received failure detection notification as described above. Based on the code, the communication destination component is determined, and if the received failure detection notification is in the format shown in FIG. 7, as described above, based on the error code included in the failure detection notification. By searching the communication destination list and the like, the communication destination parts are determined. Thereafter, the determined communication destination component is accessed to analyze the state of the communication destination component.

  For example, when the format shown in FIG. 6 is used as the failure detection notification in the information processing apparatus shown in FIG. 1, the communication destination included in the failure detection notification from the BIOS 61 of the CPU 11 that detected the link failure related to the interface circuit 5. As the component code, “0x0002” and a code for specifying the CPU 12 are set, and the BMC FW 7 directly accesses the status register 22 of the CPU 12 via the interface circuit 42 as a communication destination component, and the CPU 12 And the transmission / reception state of the CPU 12 with respect to the interface circuit 5 is analyzed.

  Next, the BMCFW 7 extracts the bits [0: 7] of the status register 22 of the CPU 12 configured as shown in FIG. 3, and determines whether or not the CPU 12 is normally performing a reception operation from the partner CPU 11. Check.

  First, the state of “with / without reception” of the bit [0] of the status register 22 of the extracted CPU 12 is checked. If the bit [0] is “0”, a transmission operation is performed from the partner CPU 11. Nevertheless, the CPU 12 detects that the reception operation has not been performed due to some abnormality. On the other hand, if the bit [0] is “1”, it is confirmed that some reception operation from the CPU 11 has been performed via the interface circuit 5.

  If any reception operation has been performed, the status of the bit [1] of the status register 22 is checked for the “presence / absence of normal reception”, and if the bit [1] is “0”, reception is performed. The operation ends normally. On the other hand, if the bit [1] is “1”, it is detected that the reception operation cannot be normally performed due to some abnormality and ends abnormally.

  If the reception operation has ended abnormally, next, bits [2: 7] of the status register 22 are examined. As described above, the bit [2: 7] of the status register 22 stores the presence / absence of an abnormality for each progress stage of the reception operation for each bit. That is, each of bit [2] to bit [7] corresponds to the first stage to the sixth stage of the reception operation, and is “0” when there is no abnormality, but when an abnormality occurs. '1' is stored.

  As described above, if the bit [0] of the status register 22 is “0”, it is determined that the reception operation cannot be performed due to some abnormality despite the transmission operation from the other CPU 11. Even if the bit [0] of the status register 22 is “1”, if “1” exists in the bits [1: 7], the reception operation is abnormally terminated. On the other hand, if the bit [0] of the status register 22 is “1” and “1” does not exist in the bits [1: 7], the reception operation is normally completed, and the communication destination CPU 12 It can be determined that no abnormality has occurred.

  Next, the BMCFW 7 extracts the bits [8:15] of the status register 22 of the CPU 12 and the CPU 12 normally performs the transmission operation to the partner CPU 11 as an operation of returning a response to the transmission from the partner CPU 11. Check if it is.

  First, the state of “with / without transmission” of bit [8] of the status register 22 of the extracted CPU 12 is checked. If bit [8] is “0”, the CPU 12 has instructed a response transmission operation. Nevertheless, it is detected that the transmission operation has not been performed due to some abnormality. On the other hand, if bit [8] is “1”, it is confirmed that some transmission operation has been performed to the CPU 11 via the interface circuit 5.

  If any transmission operation has been performed, then the status of the bit [9] of the status register 22 is checked for the "presence / absence of normal transmission", and if bit [9] is '0', transmission is performed. On the other hand, if the bit [9] is “1”, the transmission operation cannot be normally performed due to some abnormality, and it is detected that the operation has ended abnormally.

  If the transmission operation has ended abnormally, next, bits [10:15] of the status register 22 are examined. In the bits [10:15] of the status register 22, the presence / absence of an abnormality at each progress stage of the transmission operation is stored for each bit as described above. That is, each of bits [10] to [15] corresponds to the first to sixth stages of the transmission operation, and is “0” when there is no abnormality, but when an abnormality occurs. '1' is stored.

  As described above, if the bit [8] of the status register 22 is “0”, it is determined that the transmission operation to the other CPU 11 cannot be performed due to some abnormality, and the bit [8] of the status register 22 is determined. ] Is “1”, if “1” exists in bits [9:15], the transmission operation is abnormally terminated. On the other hand, if bit [8] of status register 22 is “1” and “1” does not exist in bits [9:15], it is determined that the transmission operation is normally completed. Can do.

  Next, based on the analysis result of the transmission / reception state of the CPU 12 that is the communication destination component in Step B4, the BMCFW 7 calculates the suspect ratio of both the failure suspected component of the failure detection source CPU 11 and the failure suspected component of the communication destination CPU 12. Then, it is determined as the second suspected ratio indicating the possibility of the failure part (step B5).

  That is, in step B5, the BMC FW 7 receives, as a failure detection notification from the BIOS 61 of the CPU 11, an error code included in the failure detection notification, for example, “0x0000_0001” and a link failure notification. , The status register 22 of the communication destination CPU 12 is read, and the bits [0] and [8] of the status register 22 are “1”. When the transmission / reception operation is performed and it is recognized that “1” does not exist in bits [1: 7] and bits [9:15] of the status register 22, the communication destination CPU 12 It is determined that the device is operating normally.

  Thus, the BMC FW 7 determines from the analysis result of the transmission / reception state of the communication destination CPU 12 that the suspected faulty component is highly likely to be the CPU 11, and sets the suspected rate that the fault detecting source CPU 11 is the suspected faulty component. On the other hand, the CPU 12 as the communication destination determines that the suspect ratio of the suspected failure part is 20%, for example.

  On the other hand, when the error code included in the failure detection notification from the BIOS 61 of the CPU 11 is, for example, “0x0000_0001” and a link failure has been notified, the bit [0 of the status register 22 of the communication destination CPU 12 ] Or [8] is “0” and the communication destination CPU 12 cannot perform the transmission / reception operation with the CPU 11 on the failure detection side, or the bits [0] and [1] are “1”. Even if the communication destination CPU 12 can perform transmission / reception operation with the CPU 11 on the failure detection side, the bit [1: 7] or the bits [9:15] of the status register 22 are set. If it is recognized that “1” exists, the communication destination CPU 12 determines that it is not operating normally.

  Thus, the BMCFW 7 determines from the analysis result of the transmission / reception state of the communication destination CPU 12 that the suspected faulty component is highly likely to be the CPU 12, and the suspected rate that the communication target CPU 12 is the suspected faulty component is, for example, 70. On the other hand, the CPU 11 as the fault detection source determines the suspect ratio of the suspected fault part as 30%, for example.

  Here, when the failure detection source CPU 11 determines that the component is a suspected failure component, the numerical value of the suspected failure rate of the suspected failure component in step B5 (ie, the numerical value of the second suspected component) is the suspected rate of the suspected failure component in step B2. This is because the following points are taken into consideration as a factor different from the numerical value (that is, the numerical value of the first suspect ratio). That is, in step B2, when the link failure of the interface circuit 5 is detected, “whether or not the transmission operation from the failure detection source CPU 11 to the communication destination CPU 12 via the interface circuit 5 has been correctly performed” is determined. In step B5, when the link fault of the interface circuit 5 is detected, “in the communication destination CPU 12 via the interface circuit 5 with the fault detection source CPU 11”. This is because whether or not the transmission / reception operation has been correctly performed is a result of the BMCFW 7 determining based on the reading result of the status register 22 of the communication destination CPU 12. That is, it is assumed that the analysis result in step B5 is more reliable for failure analysis than the analysis result in step B2.

  After that, in step B2, the suspect ratio of the suspected fault part (that is, the first suspect ratio) determined based on the fault detection notification from the fault detection source CPU 11, and the reading of the status register 22 of the communication destination CPU 12 in step B5. The final suspected ratio is calculated by merging the suspected ratio (that is, the second suspected ratio) of the suspected failure part determined based on the result in accordance with a predetermined rule (step B6). Here, as a predetermined rule for merging, as a simple example, a simple average obtained by adding the suspected ratios of both the analysis result in step B2 and the analysis result in step B5 and dividing by '2'. The value may be the final suspect ratio of the suspected faulty part.

  For example, as a first example, the error code included in the failure detection notification received from the CPU 11 is '0x0000_0001', and a component with a high possibility of failure is both in step B2 and step B5. This is a case where the CPU 11 is the failure detection source. As described above, the suspected rate that the CPU 11 is the suspected failure component is 70% and the suspected rate that the CPU 12 is the suspected failure component is 30% as the analysis result of step B2. On the other hand, if the suspected ratio that the CPU 11 is a suspected fault part is 80% and the suspected percentage that the CPU 12 is a suspected fault part is 20% as an analysis result of the step B5, the CPU 11 of the analysis result of the step B2 is faulty. A simple average of the suspicious ratio 70% that is a suspicious part and the suspicious ratio 80% that the CPU 11 of the analysis result of step B5 is a suspicious part is C The final suspicion rate at which PU11 is a suspicious part is determined to be 75%. Further, the CPU 12 of the analysis result of Step B2 is simply averaged with the suspected ratio 30% that the suspected failure part is 30% and the suspected rate 20% that the CPU 12 of the analysis result of Step B5 is the suspected failure part. A final suspicion rate is determined to be 25%.

  Also, as a second example, the parts having a high possibility of failure are the communication destination CPU 12 in steps B2 and B5, contrary to the case of the CPU 11 described above, and the analysis of step B2 is performed. If both the result and the analysis result of step B5 are 30% of the suspected ratio that the CPU 11 is a suspected fault part and 70% that the suspected part that the CPU 12 is a suspected fault part, the analysis result of the step B2 The CPU 11 is simply the average of the suspected ratio 30%, which is the suspected faulty part, and the CPU11, which is the suspected faulty part 30%, of the analysis result in step B5, and the final suspected percentage 30 is the suspected faulty part of the CPU11. %. Further, the CPU 12 of the analysis result of Step B2 is simply averaged with the suspected ratio 70% that the suspected failure part is 70% and the suspected rate 70% that the CPU 12 of the analysis result of Step B5 is the suspected failure part. A final suspicion rate is determined to be 70%.

  Further, as a third example, a part having a high possibility of failure is different between Step B2 and Step B5, and in both cases, it is determined that the part on which the state is to be analyzed is a failure. The suspected ratio that the CPU 11 of the analysis result is the suspected fault part is 70%, and the suspect ratio that the CPU 12 is the suspected fault part is 30%, while the suspect ratio that the CPU 11 of the analysis result of step B5 is the suspected fault part is 30%. %, If the suspected ratio that the CPU 12 is a suspected fault part is 70%, the CPU 11 of the analysis result of Step B2 is the suspected percentage 70% that the suspected fault part and the CPU 11 of the analysis result of Step B5 is the suspected fault part The CPU 11 determines the final suspected ratio of 50% as a fault suspected part by simply averaging the suspected ratio 30%. Further, the CPU 12 of the analysis result of step B2 is a simple average of the suspected ratio 30% that the suspected failure part is 30% and the CPU 12 that is the analysis result of step B5 is the suspected failure part 70%, and the CPU 12 is the suspected failure part. A final suspicion rate is determined to be 50%.

  Further, as a fourth example, a component having a high possibility of failure is different between Step B2 and Step B5, and in both cases, the other component side that has not been analyzed based on the status registers 21 and 22 has a failure. As a result of the determination, the suspicious ratio in which the CPU 11 of the analysis result in step B2 is a suspected fault part is 30%, and the suspected ratio in which the CPU 12 is a suspected fault part is 70%. If the CPU 11 in the analysis result of step B5 is set to 80%, the suspected ratio that the CPU 12 is the suspected faulty part is 20%, and the suspected ratio that the CPU 12 is a faulty suspected part is set to 20%. The analysis result CPU 11 is a suspected failure part 30% and the step B5 analysis result CPU 11 is a suspected failure part 8 % And by simply averaging, to determine CPU11 is the final suspect ratio is a disorder suspect component and 55%. Further, the CPU 12 of the analysis result of Step B2 is 70% of the suspected failure part, and the CPU 12 of the analysis result of Step B5 is 20% of the suspected failure part. A final suspicion rate is determined to be 45%.

  In other words, as shown in the fourth example, even if the suspicion ratios of both are simply averaged, the setting criteria of the suspicion ratios in step B2 and step B5 are made different so that the reliability of the analysis result is more By setting the suspicion ratio so as to have a large difference in the high step B5, even if both are simply averaged and merged, for example, the suspicion ratio of the CPU 11 is 55% and the suspicion ratio of the CPU 12 is 45%. Then, the result that the CPU 11 that is the analysis result in step B5 has a high possibility of failure can be obtained as the final suspicious ratio after merging.

  In the conventional failure processing technique, even if a link failure relating to the interface circuit 5 is detected, only the state of the failure detection source component, that is, the state of the CPU 11 is detected by the BIOS 61 as shown in step A2 of FIG. As shown in the failure suspected component 84 of FIG. 2, only the failure detection source CPU 11 or the communication destination CPU 12 can be pointed out as a suspected failure component.

  However, in the present embodiment in which the BMC 3 has a failure processing function, the analysis result obtained by analyzing the communication destination component, that is, the state of the CPU 12 in step B5, and the analysis result in step B2 are obtained in step B6. Since the merging process is performed and the final suspicious ratio of the failure is determined, the suspicious part indicating the degree of the possibility of the failure can be pointed out more accurately for both the CPUs 11 and 12.

  Further, as in the fourth example described above, in the analysis result of step B2, even if the CPU 12 is a suspected part of failure, the reliability of step B5 is higher than the analysis result of step B2. By merging with the analysis result, the final suspicion ratio that points out the CPU 11 that has been determined to have a high possibility of failure as the analysis result in step B5 as the suspected component of the failure is increased, and the final suspicion of the CPU 12 The proportion can be reduced.

  Further, by analyzing the states of the CPUs 11 and 12, the suspected part regarding the suspected part can be pointed out with more variations than the suspected ratio of the suspected part that is determined only by the CPU 11 that is the failure detection source. As a result, the reliability and accuracy with respect to the determination of the failure part can be improved.

  Note that the predetermined rule for merging the analysis result of step B2 and the analysis result of step B5 is not limited to the simple averaging as described above. For example, by performing a weighted average of the suspicious ratios of both, a result obtained by weighting the analysis result in step B5 with higher reliability may be obtained.

  Returning to the flowchart of FIG. 5B, finally, the failure part is determined according to the final suspected ratio of the suspected faulty part determined by the merge result of step B6, and the determined faulty part is pointed out. At the same time, a measure is taken for the failed part (step B7). For example, if the final suspected rate that the failure detection source CPU 11 is a suspected failure component is greater than the final suspected rate of the communication destination CPU 12 as a merge result, the CPU 11 is a failed component. The CPU 11 is disconnected from the operational system of the information processing apparatus, and the information processing apparatus is restarted. As a result, the BIOS 61 of the failed CPU 11 does not operate during startup of the information processing apparatus, so that the BIOS 61 does not further detect the failure and the startup operation can proceed smoothly. Become.

  Next, the operation when a failure other than a link failure relating to the interface circuit 5 is detected will be further described. The failure other than the link failure related to the interface circuit 5 is an internal setting of the CPU 11 that is not a scene in which the BIOS 61 performs a transmission / reception operation with the communication destination CPU 12 via the interface circuit 5 even when the CPU 11 is performing an initialization operation. This is the case when an internal failure on the CPU 11 side is detected during operation.

  First, in the flowchart of FIG. 5A, when the BIOS 61 operating on the CPU 11 detects the internal failure on the CPU 11 side during the startup process of the CPU 11, the failure processing is started as described above (step A1), referring to the error code table shown in FIG. 2 and extracting the corresponding error code based on the part that was the object of processing when the fault was detected, whether or not it is a link fault, and the suspected faulty part (Step A2). For example, when the CPU 11 is a component to be processed and an internal failure on the CPU 11 side is detected during internal processing on the CPU 11 side, not a link failure related to a transmission / reception operation with the CPU 12 that is a communication destination via the interface circuit 5, The suspected failure part is the CPU 11, and the corresponding error code is '0x0000_1001' as shown in the error code table of FIG.

  Next, as the failure content analysis processing in step A2 of FIG. 5A, since it is analyzed that it is not a link failure (no in step A3), only an error code that does not include a code indicating a communication destination component is included. A failure detection notification consisting of is transmitted to the BMC 3 via the interface circuit 41 (step A5). For example, if the processing target component that detected the failure is the CPU 11, the CPU 11 is the suspected failure component, and is not a link failure, the error code of bits [0:31] is “0x0000_1001” as described above. In the case of the format of FIG. 6, a failure detection notification in which “0x0000” in which the part code of the communication destination of bits [32:47] is all “0” is set is transmitted, and the suspected failure site is indicated to BMC 3. You will be asked to analyze.

  Next, as shown in FIG. 5B, when the BMCFW 7 operating on the BMC 3 receives the failure detection notification from the BIOS 61 via the interface circuit 41 (step B1), the failure processing for specifying the failure part BMCFW 7 refers to the failure table shown in FIG. 4 based on the error code included in the received failure detection notification, and determines the failure suspected part and failure suspected rate corresponding to the error code. Extract (step B2).

  For example, when the error code included in the received failure detection notification is “0x0000_1001”, the suspected component 1102, suspected component 2 103, suspected rate 1 104, suspected rate 2 105 in the failure table of FIG. As shown in the figure, it is possible for the failure part that the suspected rate that the failure suspected part indicating the failure part is CPU 11 is 100% and the suspected part that the failure suspected part indicating the failure part is CPU 12 is 0%. Extracted as the first suspicious rate indicating sex.

  Next, it is necessary for the BMCFW 7 to check whether or not the detected failure is a link failure by referring to the information indicating whether or not the link failure is in the received failure detection notification, and to investigate the communication destination component. It is determined whether or not there is (step B3). Here, if the failure detection notification has the format as shown in FIG. 6, as described above, bits [32:47] are set to “0x0000” if there is no link failure.

  If it is determined that the detected failure is not a link failure and it is not necessary to investigate the communication destination component (no in step B3), only the failure detection notification from the BIOS 61 is checked without investigating the communication destination component. Based on the above, in order to point out and treat the suspected part of the failure, the process immediately proceeds to step B7, and the part of failure is determined according to the suspected ratio of the failure extracted from the trouble table in step B2. The failed part is pointed out, and a measure for the failed part is performed (step B7).

  In other words, if the error code included in the received failure detection notification is “0x0000_1001”, the CPU 11 indicates that the suspected proportion of the suspected failure component is 100% as the analysis result of step B2. Is a faulty part, the CPU 11 is disconnected from the operational system of the information processing apparatus, and the information processing apparatus is restarted. As a result, the BIOS 61 of the failed CPU 11 does not operate during startup of the information processing apparatus, so that the BIOS 61 does not further detect the failure and the startup operation can proceed smoothly. Become.

(Description of the effect of this embodiment)
As described in detail above, the following effects are obtained in the present embodiment.

  In the conventional technique, when the BIOS 61 of the CPU 11 detects a link failure related to the interface circuit 5 during the startup of the information processing apparatus, communication with the CPU 12 falls into a disconnected state, and therefore, based on only information on the CPU 11 side. I had to do a site analysis.

  On the other hand, in the present embodiment, when the BIOS 61 of the CPU 11 that has detected the link failure notifies the BMC 3 of the failure detection, in addition to notifying an error code indicating the analysis result of the suspected component of the failure, By requesting the investigation of the state of the communication destination CPU 12, the BMC 3 that has received the investigation request accesses the communication destination CPU 12 and the state of the communication destination CPU 12 that could not be accessed from the BIOS 61 of the CPU 11. Therefore, it is possible to further improve the reliability related to the determination result of the suspected faulty part.

  In this embodiment, the BIOS 61 of the failure detection source CPU 11 analyzes the state of the CPU 11 of the self component and the BMC 3 merges appropriately with reference to both the result of analysis of the state of the CPU 12 of the notification destination component. Therefore, the location of the failure can be pointed out with higher reliability than in the conventional technique. Thus, it becomes possible to point out the suspected part in more detail with respect to the detected fault, and the fault indication accuracy can be improved.

  That is, the effects of this embodiment are summarized as follows.

  The first effect is that the suspected part of the failure can be pointed out with high accuracy with respect to the link failure related to the interface circuit 5 detected by the BIOS 61 operating on the CPU 11 during the startup of the information processing apparatus. The reason is that the BMC 3 that has received the failure detection notification from the BIOS 61 directly accesses the communication destination component (for example, the CPU 12) of the interface circuit 5 in which the link failure has occurred, as well as information on the suspected failure component analyzed by the BIOS 61. This is because the failure part can be analyzed using information on the suspected failure part obtained from the analysis result of the state of the communication destination part.

  The second effect is that the state of a component (for example, the CPU 12) that cannot be accessed from the BIOS 61 during startup of the information processing apparatus can be grasped. The reason for this is that the BIOS 61 sends the BMC 3 a code for notifying the component (for example, the CPU 12) to be accessed in the failure detection notification as an investigation request, and the BMC 3 receiving the failure detection notification sends the investigation request. This is because a mechanism for directly accessing the part (for example, the CPU 12) is provided.

  The third effect is that the startup time of the information processing apparatus can be shortened. The reason for this is that even when a link failure related to the interface circuit is detected at the time of starting up the information processing device, the BMC 3 can point out the suspected portion of the failure with high accuracy. This is because the separation process and the reboot operation can be prevented from being repeated.

(Other embodiments of the present invention)
Next, as a configuration of the information processing apparatus according to the present invention, another configuration example different from the above-described embodiment shown in FIG. 1 will be described with reference to FIG. FIG. 8 is a block configuration diagram showing another example of the block configuration of the information processing apparatus according to the present invention which is different from FIG. Unlike the case of FIG. 1, the information processing apparatus shown in FIG. 8 includes not only two CPUs 11 and 12 but also a plurality of (four in the case of FIG. 8) CPUs as components constituting the information processing apparatus. Each component is composed of a plurality (two in the case of FIG. 8) IO Hub (IO device connection control device) and a plurality (two in the case of FIG. 8) NC (Network Controller). However, a configuration example is shown in which the baseboard management controller BMC is directly connected to the status register included in each component by being connected to the baseboard management controller BMC via each interface circuit.

  That is, in the information processing apparatus shown in FIG. 8, the CPU 11 and the CPU 12 are connected by the interface circuit 51, and the CPUs 11 and 12 are connected to the same IO Hub 201 by the interface circuits 221 and 222, respectively. Interface circuits 231 and 232 are connected to the same NC 211. Similarly, the CPU 13 and the CPU 14 are connected by the interface circuit 52, and the CPUs 13 and 14 are connected to the same IO Hub 202 by the interface circuits 223 and 224, respectively, and the same NC 212 by the interface circuits 233 and 234. Connected with.

  The IO Hub 201 and the NC 211 are connected by the interface circuit 53, the IO Hub 202 and the NC 212 are connected by the interface circuit 54, and the NC 211 and NC 212 are connected by the interface circuit 55.

  In addition, BIOS 61, 62, 63, 64 is incorporated in each component of the CPUs 11, 12, 13, 14. Furthermore, status registers 21, 22, 23, 24, 25, 26, 27, and 28 are provided in the CPU 11, 12, 13, 14, IO Hub 201, 202, and NC 211, 212, respectively. Further, the CPU 11, 12, 13, 14, IO Hub 201, 202, and NC 211, 212 are connected to the BMC 3 by interface circuits 41, 42, 43, 44, 45, 46, 47, 48, respectively.

  In the information processing apparatus configured as shown in FIG. 8, for example, the BIOS 61 operating on the CPU 11 links up the interface circuits 51 to 55, 221 to 224, and 231 to 234 during startup of the information processing apparatus. Here, even in the configuration as shown in FIG. 8, when an interface failure occurs during link-up of any of the interface circuits 51 to 55, 221 to 224, 231 to 234, the interface failure has been described above. By performing the same failure processing as in the case of the embodiment, it is possible to determine the fault suspected part and the final suspect ratio, and to specify the faulty part with high accuracy.

  Note that the information processing apparatus according to the present invention includes the case where the information processing apparatus is composed of the two components of the CPUs 11 and 12 in FIG. 1, or the CPUs 11, 12, 13, and 14, the IO Hubs 201 and 202, and the NC 211 in FIG. , 212, the information processing apparatus is not limited to the case where the information processing apparatus is configured by eight components, and an information processing apparatus including any desired number of components can be targeted.

  Further, regarding the configuration of the information processing apparatus, each component such as the CPU 11, 12, 13, 14, IO Hub 201, 202, NC 211, 212 has an interface circuit for connecting to the BMC 3, and the BIOS 61, built in each component, Configuration in which 62, 63, 64, 65, 66, 67, 68 can transmit a failure detection notification as described in the above-described embodiment from each component to the BMC 3 in cooperation with the BMC FW 7 built in the BMC 3. If so, it is not limited to the configuration of FIG. 1 or the configuration of FIG.

  In the above description of the embodiment, the BIOS 61 operating on the CPU 11 starts up the information processing apparatus. However, the information processing apparatus is started up using the BIOS operating on another CPU. It is also possible to do this.

  The configuration of the preferred embodiment of the present invention has been described above. However, it should be noted that such embodiments are merely examples of the present invention and do not limit the present invention in any way. Those skilled in the art will readily understand that various modifications and changes can be made according to a specific application without departing from the gist of the present invention.

3 BMC
5 Interface circuit 7 BMCFW
11 CPU
12 CPU
13 CPU
14 CPU
21 status register 22 status register 23 status register 24 status register 25 status register 26 status register 27 status register 27 status register 28 status register 41 interface circuit 42 interface circuit 43 interface circuit 44 interface circuit 45 interface circuit 46 interface circuit 47 interface circuit 48 interface circuit 51 interface Circuit 52 Interface circuit 53 Interface circuit 54 Interface circuit 55 Interface circuit 61 BIOS
62 BIOS
63 BIOS
64 BIOS
81 Error code 82 Processing target component 83 Link failure 84 Failure suspected component 91 Bit column 92 Description column 93 Contents column 101 Error code 102 Suspected component 1
103 Suspected parts 2
104 Suspicious rate 1
105 Suspicious rate 2
111 Bit field 112 Description field 113 Contents field 121 Bit field 122 Explanation field 123 Contents field 201 IO Hub
202 IO Hub
211 NC
212 NC
221 interface circuit 222 interface circuit 223 interface circuit 224 interface circuit 231 interface circuit 232 interface circuit 233 interface circuit 234 interface circuit

Claims (9)

  A baseboard management controller (BMC: Baseboard Management) that has a multiprocessor configuration composed of a plurality of processors connected to each other via an interface circuit, connects the processors, and manages and monitors each connected processor. A firmware (BMCFW: BMC Firmware) that operates on the baseboard management controller (BMC) is a basic input / output system (BIOS) that operates on each processor. System) has a fault processing function for determining a fault site and separating the fault site from the active system, and the basic input / output system (BIOS) is executing a device startup operation. If a failure is detected, the basic entry / exit An error code obtained as a result of analyzing an operation state held in a status register provided in a processor in which a system (BIOS) operates, and an interface circuit when the detected failure is determined to be a link failure related to the interface circuit The base that has received the fault detection notification is transmitted to the baseboard management controller (BMC), and a fault detection notification including a communication destination processor investigation request for requesting an analysis of the state of the counterpart processor that is the communication destination The firmware (BMCFW) operating on the board management controller (BMC) may be a suspected failure site based on the error code included in the failure detection notification for the processor connected via the interface circuit. The ratio indicating the first covered When the communication destination processor investigation request is included in the failure detection notification, a status register provided in the communication destination partner processor of the interface circuit in which the failure is detected is determined as a ratio. Based on the result of reading and analyzing the operation state to be held, a ratio indicating the possibility of failure of the suspected failure site is determined as a second suspected rate, and the determined first suspected rate and the second suspected rate are determined. Merging according to a predetermined rule to obtain a final suspicion ratio, and determining a part having the highest final suspicion ratio as a faulty part and separating the faulty part from the operational system, Information processing apparatus.   The basic input / output system (BIOS) that detects the failure detects the link failure in the communication destination processor investigation request included in the failure detection notification when the detected failure is determined to be a link failure related to the interface circuit. The firmware (BMCFW) that operates on the baseboard management controller (BMC) that has set the component code for identifying the processor on the other side of the communication destination of the interface circuit and has received the failure detection notification is included in the failure detection notification. Based on the first and second suspect ratios by reading the operating state held by the status register of the processor on the other party of the communication destination specified by the included component code and determining the second suspect ratio The operation of discriminating the failed part was performed, while the failure was detected The basic input / output system (BIOS) determines that the detected failure is not a link failure related to the interface circuit but a failure in the processor in which the basic input / output system (BIOS) operates, and is included in the failure detection notification. A firmware (BMCFW) that operates on the baseboard management controller (BMC) that receives the failure detection notification is set in the communication destination processor investigation request with a code that is different from the component code that identifies the processor. Assuming that there is no request for investigation of the processor on the other side, the operation for determining the faulty part is performed using only the first suspect ratio without performing the operation of reading the status register of the processor on the other party of the communication destination The information processing apparatus according to claim 1.   The basic input / output system (BIOS) that detects the failure sets an identifier indicating the investigation request in the communication destination processor investigation request included in the failure detection notification when the detected failure is determined to be a link failure relating to the interface circuit. Then, the firmware (BMCFW) that operates on the baseboard management controller (BMC) that has received the failure detection notification refers to the communication destination partner processor identified by referring to the communication destination list provided in advance. By reading the operation state held by the status register and determining the second suspect ratio, the operation of discriminating the failed part is performed based on the first and second suspect ratios, while a failure is detected. In the basic input / output system (BIOS), the detected fault is If it is determined that the failure is not a link failure related to the circuit but a failure in the processor in which the basic input / output system (BIOS) operates, an identifier indicating that no investigation is required is set in the communication destination processor investigation request included in the failure detection notification. The firmware (BMCFW) operating on the baseboard management controller (BMC) that has received the failure detection notification assumes that there is no investigation request for the other party processor of the communication destination, and the status of the other party processor of the communication destination 2. The information processing apparatus according to claim 1, wherein the operation of determining the failed part is performed using only the first suspect ratio without performing a register reading operation.   As the rule for merging the first suspicion rate and the second suspicion rate, a simple average of the first suspicion rate and the second suspicion rate is obtained, or the second 4. The information processing apparatus according to claim 1, wherein any one of rules for obtaining a weighted average obtained by assigning a predetermined appropriate weight to the suspect ratio is used.   A failure location determination method for determining a failure location in an information processing apparatus having a multiprocessor configuration including a plurality of processors connected to each other via an interface circuit, wherein each processor is connected and management of each connected processor is performed A baseboard management controller (BMC) that executes monitoring, and firmware (BMCFW) that operates on the baseboard management controller (BMC) is a basic input / output that operates on each processor. By cooperating with a system (BIOS: Basic Input / Output System), it has a fault processing function for determining a faulty part and separating the faulty part from the operational system. The basic input / output system (BIOS) Failure during start-up operation When an error is detected, an error code obtained as a result of analyzing an operation state held by a status register included in a processor in which the basic input / output system (BIOS) operates, and the detected failure is a link failure related to the interface circuit. If it is determined, the failure detection notification consisting of the communication destination processor investigation request for requesting the analysis of the state of the counterpart processor as the communication destination of the interface circuit is transmitted to the baseboard management controller (BMC), The firmware (BMCFW) that operates on the baseboard management controller (BMC) that has received the failure detection notification is related to the error code included in the failure detection notification for the processor connected via the interface circuit. Based on failure When the ratio indicating the possibility of the suspicious part is determined as the first suspected ratio and the communication destination processor investigation request is included in the failure detection notification, the communication destination of the interface circuit in which the failure is detected Based on the result of reading and analyzing the operation state held in the status register provided in the other processor of the other party, the ratio indicating the possibility of failure of the suspected failure part is determined as the second suspected ratio, and the determined By merging the first suspect ratio and the second suspect ratio according to a predetermined rule to obtain a final suspect ratio, the part having the highest final suspect ratio is determined as a failure part. , A failure site determination method characterized in that the failure site is separated from the operational system.   The basic input / output system (BIOS) that detects the failure detects the link failure in the communication destination processor investigation request included in the failure detection notification when the detected failure is determined to be a link failure related to the interface circuit. The firmware (BMCFW) that operates on the baseboard management controller (BMC) that has set the component code for identifying the processor on the other side of the communication destination of the interface circuit and has received the failure detection notification is included in the failure detection notification. Based on the first and second suspect ratios by reading the operating state held by the status register of the processor on the other party of the communication destination specified by the included component code and determining the second suspect ratio The operation of discriminating the failed part was performed, while the failure was detected The basic input / output system (BIOS) determines that the detected failure is not a link failure related to the interface circuit but a failure in the processor in which the basic input / output system (BIOS) operates, and is included in the failure detection notification. A firmware (BMCFW) that operates on the baseboard management controller (BMC) that receives the failure detection notification is set in the communication destination processor investigation request with a code that is different from the component code that identifies the processor. Assuming that there is no request for investigation of the processor on the other side, the operation for determining the faulty part is performed using only the first suspect ratio without performing the operation of reading the status register of the processor on the other party of the communication destination The fault site determination method according to claim 5, wherein:   The basic input / output system (BIOS) that detects the failure sets an identifier indicating the investigation request in the communication destination processor investigation request included in the failure detection notification when the detected failure is determined to be a link failure relating to the interface circuit. Then, the firmware (BMCFW) that operates on the baseboard management controller (BMC) that has received the failure detection notification refers to the communication destination partner processor identified by referring to the communication destination list provided in advance. By reading the operation state held by the status register and determining the second suspect ratio, the operation of discriminating the failed part is performed based on the first and second suspect ratios, while a failure is detected. In the basic input / output system (BIOS), the detected fault is If it is determined that the failure is not a link failure related to the circuit but a failure in the processor in which the basic input / output system (BIOS) operates, an identifier indicating that no investigation is required is set in the communication destination processor investigation request included in the failure detection notification. The firmware (BMCFW) operating on the baseboard management controller (BMC) that has received the failure detection notification assumes that there is no investigation request for the other party processor of the communication destination, and the status of the other party processor of the communication destination 6. The failure part determination method according to claim 5, wherein the operation of determining the failure part is performed using only the first suspect ratio without performing a register reading operation.   As the rule for merging the first suspicion rate and the second suspicion rate, a simple average of the first suspicion rate and the second suspicion rate is obtained, or the second 8. The failure site determination method according to claim 5, wherein any one of rules for obtaining a weighted average obtained by assigning a predetermined appropriate weight to the suspect ratio is used.   9. A failure site determination program, wherein the failure site determination method according to claim 5 is implemented as a program executable by a computer.

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