JP2012078895A - Information processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To eliminate the need for providing to each master a buffer for changing the order of completion data.SOLUTION: When replying and relaying completion data C-A1, C-A2, and C-B1 replied from memories, a relay unit uses transmission relay information and tags to perform the following processing: relaying the replied completion data when completion data that is to be replied to the same master and whose corresponding read request has a prior order is relayed; and holding the replied completion data in a buffer 53 until the completion data having the prior order is relayed when the completion data having the prior order is not relayed.

Description

  The present invention relates to an information processing apparatus in which a plurality of masters can access a plurality of slaves.

  A system (hereinafter referred to as multi-master-multi-slave) in which a plurality of masters (multi-master) can access a plurality of slaves (multi-slave) is provided. The master is a device on the control side and refers to a CPU (Central Processing Unit), a DMA (Direct Memory Access) controller, and the like. A slave is a controlled device, and refers to a memory, an I / O (Input / Output) device, or the like.

  As a multi-master-multi-slave, a system controller in which a plurality of CPUs connected via a shared bus and a plurality of memories or I / O devices are connected via a bus, the CPU issuing a new command; Holding means for holding identification information for identifying the transfer destination of the instruction and the CPU that issued the transfer pending instruction, and transfer of the read instruction and transfer of return data for the read instruction are executed independently. There has been proposed a transfer means and an order control means for controlling the transfer means so that the return data is not switched with the issue order of transfer instructions based on the contents held by the holding means at the time of reading. (For example, refer to Patent Document 1).

JP 2004-126678 A

  As an interface applicable to multi-master-multi-slave, there is PCI Express (Peripheral Component Interconnect Express). PCI Express is a serial transfer interface that improves the shortcomings of parallel interfaces such as PCI and enables high-speed data transfer. The PCI Express can be used as an interface between a plurality of chips and between a chip and a CPU. A system using a PCI Express is effective in terms of extending the life of the chip, reducing development costs, expandability, and versatility.

  In PCI Express, packets are exchanged at the transaction layer. Transactions include memory requests, I / O requests, completions, and the like.

  The memory request is a read / write request for the memory. An I / O request is a read / write request for an I / O device. Completion is a response to a request, and data is included in the case of a read request.

  In multi-master-multi-slave, it is returned according to the order of read requests and read requests due to the difference in the number of chips passing from master to slave, the difference in processing time depending on the request contents, the difference in slave response time, etc. Inevitably, the order of reply data (for example, completion data) is different. A mode in which a buffer is provided in each master and the order of the reply data is correctly arranged is conceivable. However, this mode is inefficient because it is necessary to provide each master with a buffer for rearranging the order.

  An object of the present invention is to provide an information processing apparatus in which it is not necessary to provide each master with a buffer for rearranging the order of reply data returned from a plurality of slaves in response to a read request.

  An information processing apparatus according to one aspect of the present invention that achieves the above object performs transmission relay and reply relay when a plurality of masters, a plurality of slaves, and the plurality of masters access the plurality of slaves. A relay unit, wherein when the relay unit relays the read request transmitted from the plurality of masters, the relay unit transmits the first request identifying the read request and the read request. Storing the second relay information specifying the master, the transmission relay information associated with the third information specifying the order in which the read request is transmitted among the read requests transmitted by the master, In the reply relay, the relay unit reads from the plurality of slaves in the order of read requests transmitted from the plurality of masters. When relaying reply data having the first information sent back in response to a quest, reply data that is reply data that is sent back to the same master and that has the corresponding read request in order is relayed. For example, the reply data that has been returned is relayed, and if the reply data that is in the first order is not relayed, the reply data that has been returned is retained until the reply data that is in the first order is relayed The process is executed in the order of reply data returned from the plurality of slaves based on the transmission relay information.

  According to the present invention, the relay unit relays the reply data that has been sent back if the reply data is reply data that is sent back to the same master and the corresponding read request is in the first order. If the previous reply data is not relayed, a process of holding the reply data returned until the reply data in the first order is relayed is executed. Therefore, if the order of the reply data returned to the same master is different from the order of the read request, the relay unit relays the order of the reply data so that it matches the order of the read request. Therefore, according to the present invention, when the reply data order is different from the read request order, it is not necessary to provide a buffer for rearranging the reply data in the correct order in each master.

  In the present invention, a plurality of masters accessing a plurality of slaves means that at least one of the plurality of masters accesses a plurality of slaves. Therefore, the remaining masters may be accessed for a plurality of slaves or a single slave.

  In the transmission relay configured as described above, the relay unit relays by adding the first information to the transmitted read request, and in the reply relay, the relay unit returns the returned reply data. Using the first information added to the transmission information and the transmission relay information, it is selected whether the returned reply data is held or relayed.

  This configuration is an aspect in which the first information is not included in the read request (for example, packet ID) but is not included in the read request.

  In the above configuration, a plurality of chips (chip sets) are provided, and at least one of the plurality of masters is different in the number of chips (chip sets) that are passed through when accessing the plurality of slaves.

  If the number of chips (chip sets) through which the master accesses the slave is different, the order of the reply data is likely to be different from the order of the read requests. Therefore, the present invention is suitable when at least one of a plurality of masters has a different number of chips (chip sets) through which access is made to a plurality of slaves.

  In the above configuration, the relay unit is provided in a chip (chip set) having a location where reply data returned from the plurality of slaves is diverted to the plurality of masters among the plurality of chips (chip set). ing.

  According to this configuration, since the relay unit is arranged near a plurality of masters, it is possible to reduce the possibility that the order of the reply data changed in the correct order by the relay unit will be changed again.

  In the above configuration, an interface between the plurality of chips (chip sets) is a PCI express.

  According to this configuration, the transfer of the read request and the reply data can be speeded up.

  According to the present invention, it is not necessary to provide each master with a buffer for rearranging the order of reply data returned from a plurality of slaves in response to a read request.

It is a block diagram which shows the structure of the information processing apparatus which concerns on this embodiment. It is a figure which shows the path | route through which a read request and completion data flow. It is a figure explaining the transmission relay of a read request. It is the figure which showed transmission relay information in the table | surface. It is a figure explaining the reply relay of completion data. It is a figure which shows the relationship between the buffer and transmission relay information in a reply relay.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 is a block diagram showing the configuration of the information processing apparatus 1 according to this embodiment. The information processing apparatus 1 can be applied to, for example, an image forming apparatus, and includes three chips 11, 13, and 15 and two memories X and Y. A plurality of masters A and B access a plurality of memories (an example of slaves) X and Y via a plurality of chips 11, 13 and 15.

  The chip 11 includes a CPU 21, a memory controller 23, route complexes 25 and 27, and an internal bus 29 for connecting them. The CPU 21 performs overall control of the entire information processing apparatus 1. The memory controller 23 controls the memory Y. The root complexes 25 and 27 are the highest layers in the hierarchy in PCI Express and function as a host.

  The chip 13 includes an end point 31, two masters A and B, a relay unit 33, and an internal bus 35. The endpoint 31 is a device that is a transaction requester (requesting side) or a completer (completion side) for a device that does not comply with PCI Express. An interface 37 between the end point 31 and the root complex 25, in other words, between the chips 11 and 13, is a PCI express.

  Masters A and B are DMA controllers and are connected to the internal bus 35.

  The relay unit 33 connects the end point 31 and the internal bus 35. When the masters A and B access the memories X and Y, respectively, transmission relay and reply relay are executed. These relays will be described later.

  The chip 15 includes an end point 41, a memory controller 43, and an internal bus 45 connecting them. The end point 41 has the same function as the end point 31. The interface 47 between the end point 41 and the root complex 27, in other words, the chip 11 and 15 is a PCI express. The memory controller 43 controls the memory X.

  Transmission of a read request by the information processing apparatus 1 according to the present embodiment will be described. FIG. 2 is a diagram illustrating a path through which a read request and completion data flow. FIG. 3 is a diagram for explaining read request transmission relay. Completion data is an example of reply data returned in response to a read request.

  Three read requests R-A1, R-A2, and R-B1 will be described as an example. The read request R-A1 is a read request issued from the master A to the memory X. The read request R-A2 is a read request issued from the master A to the memory Y. The read request R-B1 is a read request issued from the master B to the memory Y.

  It is assumed that the relay unit 33 is reached in the order of read requests R-A1, R-A2, and R-B1. When the relay unit 33 relays the read requests R-A1, R-A2, and R-B1 transmitted from the masters A and B, the relay unit 33 transmits the first request for identifying the read request and the read request. A process of storing transmission relay information in association with second information for specifying the master and third information for specifying the order in which the read requests are transmitted among the read requests transmitted by the master, The read requests R-A1, R-A2, and R-B1 transmitted from B are executed in this order.

  This will be specifically described. FIG. 4 is a table showing transmission relay information. The transmission relay information is stored in the storage unit 51 provided in the relay unit 33. The tag is first information that identifies a read request. The tag has a serial number starting from “1” in advance.

  The relay unit 33 assigns the tag “1” to the read request R-A1 that arrives first, stores “A” as the second information for specifying the transmitted master, and reads the read request R- “1” is stored as the third information specifying the order in which the read request R-A1 is transmitted in A1 and R-A2. As shown in FIG. 3, the relay unit 33 adds the tag “1” to the read request R-A1 and relays it. The tag is added to a reserved area provided in the header of the transaction layer packet, for example.

  The relay unit 33 assigns the tag “2” to the read request R-A2 that has arrived next, stores “A” as the second information for specifying the transmitted master, and the read request R− transmitted by the master A. “2” is stored as the third information specifying the order in which the read request R-A2 is transmitted in A1 and R-A2. Then, the relay unit 33 adds the tag “2” to the read request R-A2 and relays it.

  The relay unit 33 assigns the tag “3” to the read request R-B1 that arrives third, stores “B” as the second information for specifying the transmitted master, and the read request R transmitted by the master B. -Stores "1" as the third information specifying the order in which the read request R-B1 is transmitted in B1. Then, the relay unit 33 relays by adding the tag “3” to the read request R-B1.

  Next, reply of completion data (an example of reply data) by the information processing apparatus 1 according to the present embodiment will be described with reference to FIGS. 2, 5, and 6. FIG. 5 is a diagram illustrating reply relay of completion data. FIG. 6 is a diagram showing the relationship between a buffer for reply relay and transmission relay information.

  As shown in FIG. 5, the completion data C-A1 is a response to the read request R-A1, and is returned from the memory X to the master A. The completion data C-A2 is a response to the read request R-A2, and is returned from the memory Y to the master A. The completion data C-B1 is a response to the read request R-B1, and is returned from the memory Y to the master B.

  It is assumed that the completion data C-A2, C-B1, and C-A1 arrive at the route complex 25 in this order, and reach the relay unit 33 in this order. The relay unit 33 includes a buffer 53 that stores completion data.

  When the relay unit 33 relays the completion data C-A2, C-B1, and C-A1 returned from the plurality of memories X and Y, the relay unit 33 reads the corresponding read data corresponding to the same master. If the completion data with the first request is relayed, the returned completion data is relayed. If the completion data with the first order is not relayed, the completion with the first order is completed. Completion data C-A2, C-B1, and C-A1 returned from a plurality of memories X and Y based on the transmission relay information is used to hold the completion data returned until data is relayed. Execute in this order. This will be specifically described.

  The relay unit 33 stores the completion data C-A2 that has arrived first in the buffer 53. As illustrated in FIG. 6A, the relay unit 33 refers to the transmission relay information stored in the storage unit 51, and has the same number as the tag “2” added to the completion data C-A2. In the column, it is determined whether the order is “1”. In the tag “2”, the order is “2”. This indicates that the completion data C-A1 corresponding to “1” has not yet been returned to the master A. The completion data C-A2 is a response to the read request R-A2. The data to be returned to the master A first is completion data C-A1, which is a response to the read request R-A1. Therefore, the relay unit 33 holds the completion data C-A2 in the buffer 53.

  The relay unit 33 stores the completion data C-B1 that has arrived next in the buffer 53. As shown in FIG. 6B, the relay unit 33 refers to the transmission relay information, and in the tag column having the same number as the tag “3” added to the completion data C-B1, the order is “1”. Is determined. In the tag “3”, the order is “1”. This indicates that the data to be relayed without being held in the buffer 53 for the master B. Therefore, the relay unit 33 deletes the tag “3” from the completion data, and executes a relay for returning to the master B.

  The relay unit 33 stores the completion data C-A1 that has reached the third position in the buffer 53. As shown in FIG. 6C, the relay unit 33 refers to the transmission relay information, and in the tag column having the same number as the tag “1” added to the completion data C-A1, the order is “1”. Is determined. In the tag “1”, the order is “1”. This indicates that the data to be relayed without being held in the buffer 53 for the master A. Therefore, the relay unit 33 deletes the tag “1” from the completion data C-A1 and executes a relay for returning to the master A. In addition, the relay unit 33 performs processing for moving up the order of the master A in the transmission relay information. Here, in the column of the tag “2”, the order is increased from “2” to “1”.

  After the completion data C-A1 is relayed, the relay unit 33 refers to the transmission relay information for the completion data C-A2 held in the buffer 53 as shown in FIG. In the tag column with the same number as the tag “2” added to C-A2, it is determined whether the order is “1”. In the tag “2”, the order is “1”. This indicates that the data should be returned to the master A without being held in the buffer 53. Therefore, as shown in FIG. 5, the relay unit 33 deletes the tag “2” from the completion data C-A2 and executes a relay for returning to the master A.

  The main effects of this embodiment will be described. According to the present embodiment, the relay unit 33 creates and stores transmission relay information when relaying the read requests R-A1, R-A2, and R-B1 transmitted from the masters A and B. At the same time, the tags "1", "2", and "3" are added to the read requests R-A1, R-A2, and R-B1 and relayed. When relaying the completion data C-A1, C-A2, and C-B1 returned from the memories X and Y, the relay unit 33 performs the following processing using the transmission relay information and the tag. Completion data that is returned to the same master and that corresponds to the corresponding read request is relayed first. If the completion data that is returned is relayed, the completion data that is returned is relayed. If it is not relayed, the completion data returned until the completion data of the first order is relayed is held in the buffer 53.

  Therefore, if the order of the completion data returned to the same master is different from the order of the read request, the relay unit 33 changes the order of the completion data so as to match the order of the read request and relays. Therefore, when the order of the completion data is different from the order of the read request, it is not necessary to provide a buffer for changing the completion data in the correct order in each of the masters A and B.

  As described above, according to the present embodiment, when a plurality of masters A and B access a plurality of memories X and Y, a buffer for rearranging the order of completion data is provided in each master A and B. There is no need.

  Further, according to the present embodiment, the read latency can be reduced. More specifically, all the completion data returned from the plurality of memories X and Y is stored in the buffer 53 of the relay device 33, the order of the completion data is correctly rearranged, and returned to the memories X and Y. An embodiment is conceivable. However, in this aspect, as a result of storing all the completion data in the buffer 53 once, the masters A and B cannot receive the completion data unless the completion data corresponding to all the read requests are returned. As a result, read latency may increase.

  On the other hand, in the present embodiment, the relay unit 33 executes the process of holding the completion data returned in the reply relay for the completion data returned to the same master. Completion data to be returned is relayed in the order of the returned completion data. Therefore, the read latency can be reduced for the master B.

  Further, according to the present embodiment, the information processing apparatus 1 in which the plurality of masters A and B access the plurality of memories X and Y via the plurality of chips 11, 13 and 15 includes the relay unit 33. At least one of the plurality of masters A and B (master A) has a different number of chips through which the plurality of memories X and Y are accessed. This embodiment is particularly effective because the order of completion data is likely to differ from the order of read requests if the number of chips through which the master accesses the memory is different.

  According to the present embodiment, the relay unit 33 is provided on the chip 13 as shown in FIG. The chip 13 is a chip having a portion (internal bus 35) where the completion data returned from the plurality of memories X and Y is divided into the plurality of masters A and B among the plurality of chips 11, 13, and 15. By providing the relay unit 33 on the chip 13, the relay unit 33 is arranged near the plurality of masters A and B, so that the order of the completion data changed in the correct order by the relay unit 33 is changed again. The possibility can be reduced. Note that the relay unit 33 is between the location where the completion data returned from the plurality of memories X and Y merges (internal bus 29) and the location where the completion data is branched to the plurality of masters A and B (internal bus 35). Can be provided.

  According to this embodiment, the interfaces 37 and 47 between the plurality of chips 11, 13 and 15 are PCI express. Therefore, the transfer of the read request and the completion data can be speeded up.

  In the present embodiment, a mode in which a master A accesses the memories X and Y and a master B accesses the memory Y has been described as a mode in which a plurality of masters access a plurality of slaves. In addition to this, the master A may access the memories X and Y, and the master B may access the memories X and Y.

  In this embodiment, a tag is used as the first information for specifying the read request, and the first information is added to the read request for relaying. However, the transaction packet ID or the like is read as the first information. The request may be specified. This eliminates the need to add the first information to the read request.

  Although described with a plurality of chips, the present embodiment can be applied to a plurality of chipsets.

1 Information processing device 11, 13, 15 Chip 33 Relay unit 51 Storage unit 53 Buffer

Claims (5)

Multiple masters,
With multiple slaves,
A relay unit that performs transmission relay and reply relay when the plurality of masters access the plurality of slaves, and
In the transmission relay, the relay unit includes:
When relaying a read request transmitted from the plurality of masters, first information for identifying the read request, second information for identifying a master that has transmitted the read request, and a read request transmitted by the master The process of storing the transmission relay information associated with the third information specifying the order in which the read requests are transmitted in the order of the read requests transmitted from the plurality of masters,
In the reply relay, the relay unit
When relaying reply data having the first information sent back in response to a read request from the plurality of slaves, reply data to be sent back to the same master and the corresponding read request in order If the data is relayed, the returned reply data is relayed. If the reply data in the order is not relayed, the reply is sent until the reply data in the order is relayed. An information processing apparatus that executes processing for holding the reply data in the order of reply data returned from the plurality of slaves based on the transmission relay information. In the transmission relay, the relay unit includes:
Add the first information to the read request sent and relay it,
In the reply relay, the relay unit
2. The method according to claim 1, wherein whether the reply data returned is retained or relayed is selected using the first information added to the reply data returned and the transmission relay information. Information processing device. With multiple chips,
The information processing apparatus according to claim 1, wherein at least one of the plurality of masters has a different number of chips through which access is made to the plurality of slaves.   4. The information processing apparatus according to claim 3, wherein the relay unit is provided in a chip having a location where reply data returned from the plurality of slaves is diverted to the plurality of masters among the plurality of chips. 5.   The information processing apparatus according to claim 3, wherein an interface between the plurality of chips is a PCI express.

Images