JP2012073755A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device preventing erroneous writing and erroneous erasing of a nonvolatile memory such as a flash memory.SOLUTION: A semiconductor device includes: a memory reset signal generation circuit which has a plurality of registers holding internal reset signals by positive logic and a plurality of registers holding the internal reset signals by negative logic and outputs a memory reset signal that activates when the output signals of the registers and external reset signals are inputted and any one of the signals is in a reset state and deactivates when all of the signals are not in reset states; and a nonvolatile memory in which read/write access and an erasing operation are inhibited when the memory reset signal is inputted and the memory reset signal is activated.

Description

  The present invention relates to a semiconductor device incorporating a nonvolatile memory. In particular, the present invention relates to a semiconductor device incorporating a flash memory.

  In a semiconductor device provided with a non-volatile memory such as a flash memory, it is known that stored data may be rewritten due to noise or a power supply interruption. In order to prevent such erroneous writing, for example, as a memory system such as a USB memory using a nonvolatile memory inside, a write protection switch is provided outside the semiconductor device, and the erroneous writing is prevented by setting the write protection switch. Has also been done. However, these require handling such as providing a security system for preventing erroneous writing outside the semiconductor device or manually operating a write protect switch.

  Patent Document 1 describes a memory control circuit having a function of preventing erroneous writing due to noise or instantaneous power interruption in a semiconductor device having a nonvolatile memory. FIG. 5 is a circuit diagram of an erroneous write prevention circuit for the conventional nonvolatile memory described in Patent Document 1. In FIG. The erroneous write prevention circuit shown in FIG. 5 includes, for example, two latch circuits 911 and 912 and two gates 913 and 914 that constitute a register. A reset signal supplied from a reset generation circuit (not shown) is supplied to the clear terminal CLK of the first latch circuit 911 and the set terminal SET of the second latch circuit 912. Therefore, when the reset signal is asserted, “0” is output from the output terminal Q of the first latch circuit 911, and “1” is output from the output terminal Q of the second latch circuit 912.

  An output signal from the output terminal Q of the first latch circuit 911 is supplied to the input terminal D of the second latch circuit 912. An output signal from the output terminal Q of the second latch circuit 912 is input to the first gate 913. In addition, register setting data supplied from a CPU (not shown) is also input to the first gate 913. The first gate 913 is an AND gate, and its output signal is supplied to the input terminal D of the first latch circuit 911. Therefore, the register setting data is input to the first latch circuit 911 when the output signal of the second latch circuit 912 is “1”. When the output signal of the second latch circuit 912 is “0”, the input signal of the first latch circuit 911 is “0”.

  A write signal supplied from a CPU (not shown) is supplied to the second gate 914. An output signal from the output terminal Q of the first latch circuit 911 is also supplied to the second gate 914. The second gate 914 is a NAND gate and outputs a nonvolatile memory write signal to a nonvolatile memory (not shown). Although not particularly limited, in this conventional example, the write signal and the non-volatile memory write signal are active low and asserted when “0”. Although not particularly limited, other signals in this conventional example are high active.

  Therefore, when the output signal of the first latch circuit 911 is “1”, the nonvolatile memory write signal is asserted or negated according to the assertion or negation of the write signal. When the output signal of the first latch circuit 911 is “0”, the nonvolatile memory write signal is always negated. Further, a register write permission signal supplied from a nonvolatile memory (not shown) in response to a CPU write command (not shown) is supplied to the enable terminals EN of the first latch circuit 911 and the second latch circuit 912. A clock signal supplied from a clock generation circuit (not shown) is supplied to the clock terminals of the first latch circuit 911 and the second latch circuit 912.

  Next, the operation of the conventional erroneous write prevention circuit shown in FIG. 5 will be described. First, when the reset signal is asserted, the output of the first latch circuit 911 is “0”, so the nonvolatile memory write signal is “1”, that is, negated, and the nonvolatile memory has a write signal. Is not supplied. That is, data cannot be written to the nonvolatile memory. Further, the output of the second latch circuit 912 is set to “1” by the reset, and the register setting data is input to the first latch circuit 911 via the first gate 913, so that “0” or “1” is input to the register. "Can be written. Therefore, this state is a write-inhibited state.

  When writing to the register is performed in the write prohibited state, the register setting data is latched by the first latch circuit 911 in synchronization with the register write permission signal. For example, if the register setting data is “1”, “1” is output from the first latch circuit 911. Therefore, when the write signal is asserted, the nonvolatile memory write output from the second gate 914 is performed. The signal is also asserted. That is, data can be written in the nonvolatile memory. Further, “1” is also latched in the second latch circuit 912 and the output of the second latch circuit 912 is “1”, so that the register can be written. Therefore, this state is a write permission state.

  On the other hand, if the register setting data is “0”, “0” is latched in the first latch circuit 911, and “0” is output from the first latch circuit 911. Thereby, even if the write signal is asserted, the nonvolatile memory write signal output from the second gate 914 remains negated. That is, data cannot be written to the nonvolatile memory. In addition, since “0” is latched in the second latch circuit 912 and the output of the second latch circuit 912 becomes “0”, “0” is always input to the first latch circuit 911. That is, until the second latch circuit 912 is set to “1” by reset, the state in which data cannot be written to the register continues, and data cannot be written to the nonvolatile memory. Therefore, this state is an erroneous writing prevention state.

  It should be noted that the state may be shifted from the write-inhibited state to the erroneous write-prevented state through the write-permitted state. Also good.

JP 2004-213103 A

  The following analysis is given by the present invention. In a semiconductor device equipped with a non-volatile memory such as a flash memory, when the power is turned on or off slowly, the state of the control signal for the non-volatile memory becomes unstable, and erroneous data is stored in the non-volatile memory. There is a risk that data written or stored in the nonvolatile memory may be lost. Even if a register for preventing erroneous writing is provided as in Patent Document 1, if the power is turned on or off slowly, the data held in the latch circuit becomes indefinite and the write signal If the state of the control signal becomes indefinite, an erroneous write operation may be performed or an unintended erase operation may be performed.

  A semiconductor device according to one aspect of the present invention outputs a plurality of internal reset signal holding registers each holding an internal reset signal and outputting an internal reset holding signal, and an external reset signal or the plurality of internal reset signal holding registers, respectively. A memory reset signal that is activated when any one of the plurality of internal reset holding signals indicates a reset state, and is deactivated when both the external reset signal and the plurality of internal reset holding signals are in a non-reset state When the memory reset signal is input and the memory reset signal is activated, read / write access and erase operations are prohibited, and the memory reset signal is deactivated Non-volatile that allows read / write access and erase operations Provided Mori and, the.

  According to the present invention, even if the data held in the register becomes indefinite when the power is turned on or off, etc., as long as all the data held in the plurality of internal reset signal holding registers match and the reset is not released. Since an unintended write access and erasing operation are not performed on the nonvolatile memory, it is possible to prevent erroneous writing and erasing on the nonvolatile memory.

1 is a circuit block diagram of a nonvolatile memory and a reset control unit thereof according to an embodiment of the present invention. It is a functional block diagram of the whole semiconductor device by one Example. 4 is a control flowchart for a nonvolatile memory according to an embodiment. It is a circuit block diagram of the reset control part by a reference example. 10 is a circuit diagram of an erroneous write prevention circuit in a conventional memory control circuit described in Patent Document 1. FIG.

  Before describing specific examples of the present invention in detail, an outline of an embodiment of the present invention will be described. In the embodiment of the present invention, a plurality of internal reset signal holding registers for holding internal reset signals are provided. Multiple internal reset signal holding registers are provided when the power supply voltage becomes unstable when the power is turned on or off, and when the power is supplied in an incomplete state. This is to prevent the reset state of the non-volatile memory from being released unless they are matched and reversed in the direction of releasing the reset state.

  When power is supplied in an incomplete state, if the reset signal is canceled and the write signal or erase signal is unstable, there is a risk of erroneous writing or erasing of the nonvolatile memory. . According to the embodiment of the present invention, the nonvolatile memory is in the reset state unless all of the plurality of registers holding the internal reset signal coincide with each other and the reset is released. Further, when the nonvolatile memory is in the reset state, even if a write signal or an erase signal becomes active, access to the nonvolatile memory is prohibited and the nonvolatile memory is held in a stable state. Therefore, even when a situation occurs in which the data held in the internal reset signal holding register becomes indeterminate, by providing a plurality of internal reset signal holding registers, all of them are matched in a probabilistic manner in the direction of reset release. It is possible to prevent data from falling, resetting being released, and erroneous writing and erroneous erasure to the nonvolatile memory.

  In particular, it is preferable to provide a register for holding the internal reset signal with positive logic and a register for holding with negative logic. This is to prevent inversion in the direction of canceling the reset state when the plurality of registers become indefinite.

  Hereinafter, a detailed description will be given in accordance with examples.

[Configuration of Example 1 as a whole]
FIG. 2 is a functional block diagram of the entire semiconductor device according to the first embodiment. The semiconductor device 1 includes a CPU 4 serving as a control unit that controls access to the entire semiconductor device 1 and the flash memory 2. The flash memory 2 is an example of a nonvolatile memory, and is a memory that stores a relatively small amount of data even after the power is shut off. In addition, the semiconductor device 1 includes a built-in RAM 5 that is a volatile memory whose stored contents are lost when the power is turned off, a built-in ROM 6 that is a read-only memory that cannot be rewritten, and peripherals that realize various functions of the semiconductor device. A circuit 7 is provided.

  Further, the CPU 4, the flash memory 2, the RAM 5, the ROM 6, and the peripheral circuit 7 are connected to each other via an internal bus 8. In addition, the external interface unit 9 is connected to an external RAM 11 and an external ROM 12 provided outside the semiconductor device 1. The external interface unit 9 and the external RAM 11 and external ROM 12 are connected by external buses 10-1 and 10-2. For example, the built-in RAM 5 can be an SRAM that can be accessed at a relatively high speed, and the external RAM 11 can be a DRAM that can store a larger capacity. The program of the CPU 4 is stored in a memory such as the internal RAM 5, the internal ROM 6, the external RAM 11, and the external ROM 12. Although not particularly limited, in the first embodiment, the flash memory 2 does not store the program of the CPU 4.

  Further, the semiconductor device 1 is provided with an external reset terminal, and a reset signal for initially setting the entire semiconductor device 1 is input from the outside. In addition to the external reset terminal, the semiconductor device 1 is provided with a clock terminal, a data input / output terminal, a control signal input terminal, and the like, which are not shown in FIG. An external reset signal input from the external reset terminal is connected to the CPU 4 and to the reset control unit 3.

  The reset control unit 3 outputs a memory reset signal to the flash memory 2 and controls the reset state of the flash memory 2 according to the logic level of the memory reset signal. An internal reset signal is connected to the reset control unit 3 from the CPU 4. The CPU 4 can control the reset state of the flash memory 2 by an internal reset signal. When the external reset signal becomes active, the reset control unit 3 unconditionally sets the flash memory to the reset state. Further, when the external reset signal becomes active, the CPU 4 is also reset.

  Further, the CPU 4 can set the flash memory to the reset state by activating the internal reset signal. When the semiconductor device 1 is operating, the reset control unit 3 is always supplied with a system clock, and when either the external reset signal or the internal reset signal becomes active, the flash memory 2 is set to the reset state. Further, when both the external reset signal and the internal reset signal are inactivated (inactive), the reset state of the flash memory is released. When the operation of the semiconductor device 1 is stopped and the system clock is stopped, the reset control unit 3 holds the state of the reset signal.

  When the memory reset signal output from the reset control unit 3 is active, the flash memory 2 is in a stable reset state regardless of the logic level of the control signal for the fresh memory 2 other than the reset signal, and read / write access and erase operations are performed. Is prohibited. Further, when the memory reset signal is inactive, read / write access to the flash memory 2 and erase operation can be performed according to the logic level of other control signals for the flash memory 2.

[Configuration of Reset Control Unit and Nonvolatile Memory of First Embodiment]
FIG. 1 is a more detailed circuit block diagram of the nonvolatile memory (flash memory) 2 and its reset control unit 3 according to the first embodiment. In FIG. 1, an external reset signal EX_RSTB is connected to a data input terminal D of a data flip-flop 34 and a memory reset signal generation circuit (logic AND circuit) 31. The external reset signal EX_RSTB is an active low signal.

  The data output terminal Q of the data flip-flop 34 is connected to the data input terminal D of the data flip-flop 35. Further, the data output terminal Q of the data flip-flop 35 has n first internal reset signal holding registers 32-1 to 32-n and n second internal reset signal holding registers 33-1 to 33-n. Each is connected to a first data input terminal. The data flip-flops 34 and 35 are connected to a system clock signal System_Clock that is supplied as a clock signal when the semiconductor device 1 is operating and is stopped when the operation of the semiconductor device 1 is stopped.

  In FIG. 1, each of the first internal reset signal holding registers 32-1 to 32-n and the second internal reset signal holding registers 33-1 to 33-n is provided with a second data input terminal. An internal reset signal CTRL2 is connected to the second data input terminal. The internal reset signal CTRL2 is a control signal (internal reset signal for the flash memory 2) output from the CPU 4, and is an active low signal. Each of the first internal reset signal holding registers 32-1 to 32-n is a register that holds the reset signal with a positive logic, and each of the second internal reset signal holding registers 33-1 to 33-n is a negative logic of the reset signal. It is a register to hold. The number of first internal reset signal holding registers and second internal reset signal holding registers is n. The larger the number of n, the lower the possibility of erroneous writing. However, the larger the number of n, the larger the circuit scale, so a value of about 5 to 10 is preferable. Details will be described later.

  Each of the first internal reset signal holding registers 32-1 to 32-n and the second internal reset signal holding registers 33-1 to 33-n outputs data output from the data flip-flop 35 connected to the first data input terminal. A logic AND circuit 36 that takes a logical AND of the output signal of the terminal Q and the internal reset signal CTRL2 connected to the second data input terminal, and a data flip-flop circuit 37 that holds the logic of the reset signal are provided.

  In the second internal reset signal holding registers 33-1 to 33-n for holding the logic of the reset signal in the data flip-flop circuit 37 as negative logic, the output signal of the logical AND circuit 36 is the data of the internal data flip-flop circuit 37 as it is. The output signal of the data output terminal Q of the data flip-flop circuit 37 connected to the input terminal D is output as it is as an internal reset holding signal. The first internal reset signal holding registers 32-1 to 32-n that hold the logic of the reset signal in the data flip-flop circuit 37 are inverted by the inverter 38, respectively. Connected to the data input terminal D of the data flip-flop circuit 37, the output signal of the data output terminal Q of the data flip-flop circuit 37 is inverted by the inverter 39 and output as an internal reset holding signal.

  A system clock signal System_Clock is connected as a clock signal to each data flip-flop circuit 37 of the first internal reset signal holding registers 32-1 to 32-n and the second internal reset signal holding registers 33-1 to 33-n. The data is constantly updated in synchronization with the system clock signal System_Clock. However, even when the power is maintained, when the CPU 2 is stopped and the operation of the entire semiconductor device 1 is stopped, the system clock signal System_Clock is also stopped and maintained in the data flip-flop circuit 37. Data is retained.

  The memory reset signal generation circuit 31 is a circuit that takes a logical AND of the external reset signal EX_RSTB, each first internal reset signal holding register, and each internal reset holding signal held by each second internal reset signal holding register. The memory reset signal generation circuit 31 outputs an active-low memory reset signal MRB. That is, the memory reset signal generation circuit 31 outputs at least one of the external reset signal EX_RSTB, the internal reset holding signals held by the first internal reset signal holding registers, and the second internal reset signal holding registers. In this case, the low level is output and the memory reset signal MRB is activated. When the external reset signal EX_RSTB matches each internal reset holding signal and outputs a high level, the high level is output and the memory reset signal MRB is deactivated.

  The memory reset signal MRB becomes an output signal of the entire reset control unit 3 and is connected to the reset terminal RESETB of the flash memory 2. The reset terminal RESETB of the flash memory 2 is an input terminal for an active-low memory reset signal MRB. When a low level is input, the flash memory 2 determines the logic level of other control signals COMMAND, address signal ADR, and data signal DATA. Regardless, data read / write and erasure are prohibited, and the internal data is held in a stable state. On the other hand, when a high level is input to the reset terminal RESETB, external access to the flash memory 2 such as a read / write operation or a batch erase operation is possible depending on the logic levels of other control signals COMMAND, address signal ADR, and data signal DATA. It becomes.

[Comparison between Example 1 and Reference Example 1]
Here, in order to explain the effect of the reset control unit 3 of the first embodiment shown in FIG. 1, the reset control unit 300 of FIG. 4 as a reference example will be described. In the reference example shown in FIG. 4, the same reference numerals as those in the first embodiment are given to portions that are substantially the same as those in the first embodiment shown in FIG. 1, and detailed description thereof is omitted.

  In FIG. 4, the configuration of the flash memory 2 is the same as that of the first embodiment shown in FIG. The first internal reset signal holding registers 32-1 to 32-n and the second internal reset signal holding registers 33-1 to 33-n of the first embodiment shown in FIG. The AND circuit 331 and the data flip-flop 332 are replaced, and the memory reset signal generation circuit 31 in FIG. 1 is replaced with the logical AND circuit 333 in FIG.

  4, the data flip-flop 332 holds a reset signal based on the internal reset signal CTRL2 or the external reset signal EX_RSTB, and takes a logical AND of the reset signal and the external reset signal EX_RSTB. As output.

  As a basic function, the reset control unit 300 of Reference Example 1 in FIG. 4 holds the reset signal by the data flip-flop 332 and resets the flash memory by the internal reset signal or the external reset signal. Therefore, if the data held in the data flip-flop 332 is always correct, the circuit of this reference example does not cause a problem. That is, if the output of the data flip-flop 332 can always be maintained at a low level when the power is turned off or turned on, the flash memory 2 can be maintained in the reset state, so that no problem occurs, but the power is unstable when the power is turned off. If this happens, the data in the data flip-flop 332 may be inverted. In addition, when the power is turned on slowly when the power is turned on and the power-on reset does not work, the data in the data flip-flop 332 is indefinite until an external reset signal is input. Then, the flash memory 2 is released from the reset state, and erroneous writing or erroneous erasure may occur depending on the logic level of other control signals.

  On the other hand, the reset control unit 3 according to the first embodiment illustrated in FIG. 1 holds an internal reset signal by 2n internal reset signal holding registers 32-1 to 32-n and 33-1 to 33-n. Then, the reset signal for the flash memory 2 is canceled only when all of the 2n internal reset signal holding registers are in the reset state and the states coincide with each other. Therefore, when the power is turned on slowly when the power is turned on and the power reset does not work, and the data held in the internal reset signal holding register becomes indefinite, the 2n internal reset signal holding registers match. It is unlikely that reset will be released. Therefore, when the circuit state becomes indefinite, the flash memory is highly likely to be maintained in the reset state, and the possibility of erroneous writing or erroneous erasure can be reduced.

  Here, the number of 2n internal reset signal holding registers provided will be described. The first internal reset signal holding register and the second internal reset signal are set to the same number n of the first internal reset signal holding register holding the internal reset signal with positive logic and the second internal reset signal holding register holding with the negative logic. It is assumed that n holding register pairs are provided.

When the state of the internal circuit becomes indefinite when the power is turned off or the power is turned on, the probability that the data held in the internal reset signal holding register will change to high level (direction in which reset is released) is p (0 ≦ p ≦ Assuming 1), the probability that the value changes in the direction in which a failure occurs for each pair (the direction in which reset is released) is represented by p · (1−p). The probability that all pairs change their values in the failure occurrence direction is represented by {p · (1-p)} ⁿ . Here, the maximum value of p · (1−p) is ¼ (when p = ½) in the range of 0 ≦ p ≦ 1. Therefore, Formula (1) is materialized.

{P · (1-p)} ⁿ ≦ (1/4) ⁿ formula (1)

When it is desired to suppress the probability that all the internal reset signal holding registers fall in the direction in which the malfunction occurs to 1000 ppm (= 10 ⁻³ ) or less, the minimum integer n satisfying (1/4) ⁿ ≦ 10 ⁻³ is obtained. = 5. Therefore, if the number of first internal reset signal holding registers and the number of second internal reset signal holding registers is set to 5 or more, the reset signal is canceled by mistake when all the data held in the holding registers becomes indefinite. It is possible to reduce the probability of being 1000 ppm or less. Even if the reset is released, erroneous writing or erroneous erasure does not always occur, so the probability of actual erroneous writing or erroneous erasure is further reduced.

Further, when it is desired to suppress the probability that all the internal reset signal holding registers fall in the direction in which the malfunction occurs to 1 ppm (= 10 ⁻⁶ ) or less, the minimum integer n satisfying (1/4) ⁿ ≦ 10 ⁻⁶ is obtained. And n = 10. Therefore, if the numbers of the first internal reset signal holding registers and the second internal reset signal holding registers are set to 10 or more, the probability that the reset signal is erroneously canceled can be reduced to 1 ppm or less.

[Operation of Embodiment 1]
Next, the operation of the first embodiment will be described in more detail. FIG. 3 is a control flowchart for the nonvolatile memory 2 according to the first embodiment. In the flowchart of FIG. 3, after power is connected to the semiconductor device 1 and the power is turned on, the entire semiconductor device 1 is initialized by an external reset in step S1. If the system including the semiconductor device 1 has a power-on reset function, this step S1 is performed by a power-on reset. Even if the system is equipped with a power-on reset function, if the power-on reset function does not work properly due to slow power-up, etc., an external reset signal is input again from the external reset terminal. .

  Note that at least one of the plurality of internal reset signal holding registers is in a reset state from when the power supply is connected until the entire semiconductor device 1 is initialized in step S1 except when the power-on reset is activated. The flash memory 2 is held in the reset state. Therefore, it is possible to prevent the flash memory 2 from being erroneously written or erased before the semiconductor device 1 is initialized. Note that step S1 is an operation based on an external reset signal input from the outside of the semiconductor device 1, but all the processes after step S2 are processes executed by the CPU 4 in relation to the flash memory 2.

  In step S2, the CPU starts operation and releases the reset state of the flash memory 2. Note that the reset state of the flash memory 2 is released here because it is necessary to read the data in the flash memory. If access to the flash memory 2 is not required, the reset state for the flash memory may be held.

  In step S3, data is transferred from the flash memory 2 to the volatile memory. Preferably, data of all addresses in the flash memory 2 is transferred in advance to the volatile memory. Here, the data of all addresses of the flash memory is transferred to the volatile memory as described later. After all the data is transferred to the volatile memory, the flash memory is set to the reset state. This is because the access is prohibited and the data transferred from the volatile memory can be read instead of the flash memory. Preferably, the flash memory 2 is a memory having a relatively small data capacity, and all the data stored in the flash memory 2 is transferred to a specific address of the volatile memory. The address to be transferred may be fixed in advance by a circuit, or the CPU may be freely set by a program.

  When the built-in RAM 5 is used as the volatile memory for transferring the data in the flash memory, the built-in RAM 5 is a general-purpose read / write memory that can store data, programs, and the like other than the flash memory required by the CPU 4. Then, it is necessary to determine in advance an address for transferring data in the flash memory. In addition to the built-in RAM 5 (see FIG. 2), a volatile memory dedicated to holding the copy data of the flash memory is provided as the volatile memory, and the copy data of the flash memory is transferred to the volatile memory dedicated to holding the copy data. Also good. The volatile memory may be a memory configured by a flip-flop, a register, or the like in addition to the RAM. Further, the copy data of the flash memory may be transferred to a volatile memory provided outside the semiconductor device 1 such as the external RAM 11 instead of the volatile memory built in the semiconductor device 1.

  Next, in step S4, the CPU 4 activates the internal reset signal and resets the flash memory to the reset state. Here, the flash memory is reset to the reset state in order to protect the data in the flash memory and prevent erroneous writing and erasing. When the flash memory is set in the reset state, external access is prohibited, and the stored data is protected in a stable and stress-free state.

  Next, in step S5, it is checked whether or not there is a read request for data stored in the flash memory. If there is no read request, the process proceeds to step S7, and if there is a read request, the process proceeds to step S6. In step S6, data is not directly read from the flash memory 2, but in step S3, data is read from the data previously transferred from the flash memory 1 to the volatile memory.

  In step S7, it is checked whether or not there is a write request for the flash memory. If there is no write request, the CPU 4 performs other processing and returns to step S5 when the processing is completed. If it is determined in step S7 that there is a write request to the flash memory, the process proceeds to step S9.

  In step S9, the CPU 4 writes to the volatile memory in which a copy of the data in the flash memory is stored before updating the data in the flash memory. Subsequently, in step S10, in order to enable write access to the flash memory 2, the CPU 4 outputs a high level to the internal reset signal CTRL2 to release the reset of the flash memory 2. Subsequently, in step S11, the data in the volatile memory is transferred to the flash memory 2, and the data in the flash memory 2 is updated.

  After updating the data in the flash memory 2 in step S11, the process returns to step S4, and the flash memory 2 is returned to the reset state. By returning the flash memory 2 to the reset state, the data in the flash memory 2 is protected so that erroneous writing or erasing to the flash memory does not occur. After that, it returns to step S5 and performs necessary processing. If there is no other process that needs to be executed by the CPU 4, the process waits until the necessary process occurs.

  In the above embodiment, the flash memory has a relatively small capacity, and the CPU program itself has not been provided in the flash memory. However, for example, only the program shown in FIG. If other programs are installed in the flash memory and the system is reset, the program stored in the flash memory is transferred to the built-in RAM 5 and the program transferred to the built-in RAM 5 is executed by the CPU 4. The present invention can also be applied to a one-chip microcontroller with a built-in flash memory, a one-chip microcomputer, or the like.

  It should be noted that the embodiments and examples can be changed and adjusted within the scope of the entire disclosure (including claims) of the present invention and based on the basic technical concept. Various combinations and selections of various disclosed elements are possible within the scope of the claims of the present invention. That is, the present invention of course includes various variations and modifications that could be made by those skilled in the art according to the entire disclosure including the claims and the technical idea.

1: Semiconductor device 2: Flash memory (nonvolatile memory)
3, 300: Reset control unit 4: CPU (control unit)
5: Built-in RAM (volatile memory)
6: Built-in ROM
7: Peripheral circuit 8: Internal bus 9: External interface unit 10-1, 10-2: External bus 11: External RAM
12: External ROM
31: Memory reset signal generation circuit (logical AND circuit)
32-1 to 32-n: first internal reset signal holding register 33-1 to 33-n: second internal reset signal holding register 34, 35, 37, 332: data flip-flop circuit 36, 331, 333: logical AND Circuits 38 and 39: Inverter 911: First latch circuit 912: Second latch circuit 913: First gate 914: Second gate

Claims (13)

A plurality of internal reset signal holding registers each holding an internal reset signal and outputting an internal reset holding signal;
Activated when either an external reset signal or a plurality of internal reset holding signals output by the plurality of internal reset signal holding registers respectively indicate a reset state, and the external reset signal and the plurality of internal reset holding signals A memory reset signal generation circuit that outputs a memory reset signal that is deactivated when both are in a non-reset state;
When the memory reset signal is input and the memory reset signal is activated, read / write access and erase operations are prohibited. When the memory reset signal is deactivated, read / write access and erase operations are permitted. Non-volatile memory,
A semiconductor device comprising:   2. The semiconductor device according to claim 1, wherein the plurality of internal reset signal holding registers are initialized to a reset state by activation of the external reset signal.   The plurality of internal reset signal holding registers include a plurality of first internal reset signal holding registers that hold the internal reset holding signal with positive logic, and a plurality of second internal reset signals that hold the internal reset holding signal with negative logic. 3. The semiconductor device according to claim 1, further comprising a holding register.   4. The semiconductor device according to claim 3, wherein the number of the plurality of first internal reset signal holding registers is the same as the number of the plurality of second internal reset signal registers.   5. The semiconductor device according to claim 3, wherein the number of the plurality of first internal reset signal holding registers and the number of the plurality of second internal reset signal holding registers are both five or more.   5. The semiconductor device according to claim 3, wherein the number of the plurality of first internal reset signal holding registers and the number of the plurality of second internal reset signal holding registers are both 10 or more.   Each of the plurality of internal reset signal holding registers is a data flip-flop in which a clock signal is always input during operation, and data is constantly updated according to the logic levels of the internal reset signal and the external reset signal. The semiconductor device according to claim 1. A volatile memory for temporarily storing data read from the nonvolatile memory;
A control unit;
Further comprising
The controller is
When reading data from the non-volatile memory,
Deactivating the internal reset signal and setting all the internal reset signal holding registers to a non-reset state to release the reset state of the nonvolatile memory;
After releasing the reset state of the nonvolatile memory, the nonvolatile memory data is transferred to the volatile memory,
After transferring to the volatile memory, the internal reset signal is activated to set the plurality of internal reset signal holding registers to a reset state, thereby prohibiting access to the nonvolatile memory,
8. The semiconductor device according to claim 1, wherein data transferred from the volatile memory to the volatile memory is read instead of reading from the nonvolatile memory. The volatile memory retains data transferred from the non-volatile memory unless the power is turned off,
When the controller next needs to read data from the non-volatile memory, the control unit maintains the reset state of the non-volatile memory, and instead of reading from the non-volatile memory, the control unit reads the data from the volatile memory. 9. The semiconductor device according to claim 8, wherein the transferred data is read out. The controller is
When updating the data in the nonvolatile memory,
Deactivating the internal reset signal and setting all the internal reset signal holding registers to a non-reset state to release the reset state of the nonvolatile memory;
Update the data in the nonvolatile memory after releasing the reset state,
9. The update of the internal reset signal is performed after the update of the data, and all of the plurality of internal reset signal holding registers are set to a reset state to prohibit access to the nonvolatile memory. Or 9. The semiconductor device according to 9.   11. The semiconductor device according to claim 8, wherein the volatile memory is any one of a RAM, a latch circuit, a flip-flop circuit, and a register circuit.   12. The semiconductor according to claim 8, wherein a volatile memory connected to the outside of the semiconductor device is used instead of the volatile memory built in the semiconductor device. apparatus.   The semiconductor device according to claim 1, wherein the nonvolatile memory is a flash memory.

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