JP2012069641A - Solid-state imaging device and method of manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a solid-state imaging device capable of obtaining an image having reduced color mixture and white scratches, and a method of manufacturing the same.SOLUTION: A solid-state imaging device comprises a substrate 101 of a first conductive type and an element isolation insulating film 121 formed in a lattice shape in the substrate. The device further comprises: a plurality of first semiconductor regions 111, 112, and 113 of a first conductive type that are separated by the element isolation insulating film one another; and a second semiconductor region 115 of a first conductive type that is formed on the element isolation insulating film in a lattice shape in the substrate and functions as a pixel isolation region. The device further comprises: a plurality of third semiconductor regions 114 of a second conductive type that are formed on the sides of the second semiconductor region in the substrate, are separated one another by the second semiconductor region, and function as charge storage regions; and a fourth semiconductor region 116 of a first conductive type formed on the second and third semiconductor regions in the substrate. In the device, the sidewall surfaces of the element isolation insulating film are covered with the first and second semiconductor regions.

Description

  Embodiments described herein relate generally to a solid-state imaging device and a manufacturing method thereof, and, for example, to a pixel structure in a solid-state imaging device used for a digital camera, a video camera, or the like.

  In recent years, development of a back-illuminated CMOS image sensor has been promoted in order to increase the optical aperture.

  In general, in a back-illuminated CMOS image sensor, pixel separation is controlled by high acceleration ion implantation from the front surface side of the substrate. In such ion implantation, the longer the flight length of ions, the greater the scattering of ions in the lateral direction. This has the problem that it is difficult to realize ideal pixel separation, and color mixture in an acquired image becomes large.

  On the other hand, a method for realizing pixel separation by digging a deep trench (DT) from the back side of the substrate has been proposed. However, this method has a problem that leakage current is likely to occur from the interface between the deep trench and the substrate, and white scratches are likely to occur in the acquired image.

JP 2009-206356 A

  It is an object of the present invention to provide a solid-state imaging device capable of acquiring an image with less color mixing and white scratches and a method for manufacturing the same.

  The solid-state imaging device according to one aspect of the present invention includes, for example, a first conductivity type substrate having a first surface and a second surface, and element isolation formed in a lattice shape on the second surface in the substrate. And an insulating film. Further, the device includes a plurality of first semiconductor regions of a first conductivity type formed on the side of the element isolation insulating film in the substrate and separated from each other by the element isolation insulating film, and the substrate in the substrate. A first conductivity type second semiconductor region which is formed in a lattice shape on the element isolation insulating film and functions as a pixel isolation region; Further, the device includes a plurality of second semiconductor regions of a second conductivity type that are formed in the substrate at a side of the second semiconductor region, separated from each other by the second semiconductor region, and function as charge storage regions. And a fourth semiconductor region of a first conductivity type formed on the second and third semiconductor regions in the substrate. Furthermore, in the device, the element isolation insulating film has a side wall surface covered with the first and second semiconductor regions.

  In the method of manufacturing a solid-state imaging device according to another aspect of the present invention, for example, a first conductivity type substrate having a first surface and a second surface is prepared, and the first conductivity type first substrate is provided in the substrate. 1 A semiconductor region is formed. Further, in the method, an element isolation insulating film is formed in a lattice shape on the second surface in the substrate, and the first conductivity type first electrode in a lattice shape is formed on the element isolation insulating film in the substrate. Two semiconductor regions are formed. Further, in the method, a plurality of second semiconductor regions of a second conductivity type separated from each other by the second semiconductor region are formed in the substrate at a side of the second semiconductor region, A fourth semiconductor region of the first conductivity type is formed on the second and third semiconductor regions. Furthermore, in the method, the element isolation insulating film is formed so that a side wall surface is covered with the first and second semiconductor regions.

It is a side sectional view showing the structure of the solid-state imaging device of the first embodiment. It is a top view which shows the structure of the solid-state imaging device of 1st Embodiment. It is side sectional drawing which shows the structure of the solid-state imaging device of a 1st comparative example. It is side sectional drawing which shows the structure of the solid-state imaging device of a 2nd comparative example. It is a sectional side view (1/2) which shows the manufacturing method of the solid-state imaging device of 2nd Embodiment. It is a sectional side view (2/2) which shows the manufacturing method of the solid-state imaging device of 2nd Embodiment.

  Embodiments of the present invention will be described with reference to the drawings.

(First embodiment)
FIG. 1 is a side sectional view showing the structure of the solid-state imaging device according to the first embodiment.

FIG. 1 shows a substrate 101 constituting a solid-state imaging device. In FIG. 1, the front surface of the substrate 101 is indicated by S ₁ and the back surface of the substrate 101 is indicated by S ₂ . As shown in FIG. 1, the solid-state imaging device according to the present embodiment is a back-illuminated CMOS image sensor having a light receiving surface on the back surface S ₂ side of the substrate 101. The substrate 101 is a P-type semiconductor substrate, more specifically, a P-type silicon substrate. The P conductivity type is an example of the first conductivity type of the present disclosure. Further, the front surface S ₁ and the back surface S ₂ of the substrate 101 are examples of the first surface and the second surface of the present disclosure, respectively.

  1 further shows a first P + type region 111, a second P + type region 112, a P type region 113, an N type region 114, and a third P + type region 115 formed in the substrate 101. A fourth P + region 116 and a deep trench (DT) insulating film 121 are shown.

Hereinafter, these regions and insulating films will be described with reference to FIGS. FIG. 2 is a plan view showing the structure of the solid-state imaging device according to the first embodiment. 2A shows a cross section of the substrate 101 taken along the arrow A shown in FIG. 1, and FIG. 2B shows a cross section taken along the arrow B shown in FIG. 2A and 2B show an X direction and a Y direction that are parallel to the front surface S ₁ and the back surface S ₂ of the substrate 101 and orthogonal to each other.

In the following description, in the substrate 101, the direction toward the front surface S ₁ of the substrate 101 is referred to as “upward”, and the direction toward the back surface S _{2 of the} substrate 101 is referred to as “downward”.

  First, the structure of the DT insulating film 121 will be described.

As shown in FIG. 1, the DT insulating film 121 is formed on the back surface S ₂ in the substrate 101. The DT insulating film 121 is an example of an element isolation insulating film of the present disclosure. DT insulating film 121 is extend to the surface S ₁ side from the rear surface S ₂ side of the substrate 101, the surface S ₁ of the substrate 101 does not reach. In FIG. 1, the distance between the upper surface of the DT insulating film 121 and the surface S _{1 of the} substrate 101 is indicated by H. In the present embodiment, the distance H is set to 0.2 to 0.4 μm, more specifically 0.3 μm.

In addition, the DT insulating film 121 is formed in a lattice shape as shown in FIG. The DT insulating film 121 has a lattice shape including a plurality of lattice line portions extending in the X direction and a plurality of lattice line portions extending in the Y direction. In FIG. 2A, the width of each lattice line portion constituting the DT insulating film 121 is indicated by W ₁ .

  As shown in FIG. 2A, the substrate 101 is divided into a plurality of regions by a DT insulating film 121. In this embodiment, each of these areas corresponds to one pixel of the solid-state imaging device. The DT insulating film 121 functions as a pixel isolation insulating film that separates pixels from each other.

FIG. 1 shows three regions R _R , R _G , and R _B separated by the DT insulating film 121. Regions R _R , R _G , and R _B correspond to red pixels, green pixels, and blue pixels of the solid-state imaging device, respectively.

In the present embodiment, an insulating film having a refractive index lower than that of the substrate 101 is used as the material of the DT insulating film 121. When the substrate 101 is a silicon substrate, examples of such an insulating film include a silicon oxide film (SiO ₂ ), a silicon nitride film (Si ₃ N ₄ ), a titanium oxide film (TiO), and the like.

  Next, the structures of the first P + type region 111, the second P + type region 112, and the third P + type region 115 will be described.

  The first and second P + type regions 111 and 112 are formed on the side of the DT insulating film 121 as shown in FIG. The first P + type region 111 is formed at the lowermost position in the substrate 101, and the second P + type region 112 is formed on the first P + type region 111. Further, the first P + type regions 111 are separated from each other by the DT insulating film 121, and similarly, the second P + type regions 112 are separated from each other by the DT insulating film 121. The first and second P + type regions 111 and 112 (and a P type region 113 described later) are examples of the first semiconductor region of the present disclosure.

In the present embodiment, the impurity concentration of the P-type impurity in the first P + type region 111 is set to 1.0 × 10 ¹⁹ cm ⁻³ . The impurity concentration of the P-type impurity in the second P + type region 112 is set to 1.0 × 10 ¹⁷ cm ⁻³ .

  As shown in FIG. 1, the third P + type region 115 is formed on the DT insulating film 121 and functions as a pixel isolation region that separates the pixels together with the DT insulating film 121. The third P + type region 115 is an example of the second semiconductor region of the present disclosure. As shown in FIG. 1, the third P + type region 115 is formed not only on the upper surface of the DT insulating film 121 but also on a part of the side wall surface of the DT insulating film 121. The DT insulating film 121 is formed so as not to reach the upper surface of the third P + type region 115.

In the present embodiment, the impurity concentration of the P-type impurity in the third P + type region 115 is set to 1.0 × 10 ¹⁸ cm ⁻³ .

Further, as shown in FIG. 2B, the third P + type region 115 is formed in a lattice shape. The third P + type region 115 has a lattice shape including a plurality of lattice line portions extending in the X direction and a plurality of lattice line portions extending in the Y direction. In FIG. 2B, the width of each lattice line part constituting the third P + type region 115 is indicated by W ₂ .

In this embodiment, as shown in FIGS. 2A and 2B, the width W ₂ of each lattice line portion constituting the third P + type region 115 is equal to each lattice line portion constituting the DT insulating film 121. It is set wider than the width W _1. As a result, the third P + type region 115 is partially formed on the upper surface of the second P + type region 112 in addition to the upper surface of the DT insulating film 121 as shown in FIG. The third P + type region 115 is interposed between the DT insulating film 121 and the N type region 114, and as a result, the DT insulating film 121 and the N type region 114 are not in contact with each other.

  Next, the structures of the P-type region 113, the N-type region 114, and the fourth P + type region 116 will be described.

  The P-type region 113 and the N-type region 114 are formed on the side of the third P + type region 115 as shown in FIG. The P-type region 113 is formed on the second P + type region 112, and the N-type region 114 is formed on the P-type region 113. Further, the P-type regions 113 are separated from each other by the third P + type region 115 and the DT insulating film 121, and similarly, the N-type region 114 is separated from each other by the third P + type region 115.

In the present embodiment, the impurity concentration of the P-type impurity in the P-type region 113 is set to 1.0 × 10 ¹⁶ cm ⁻³ , and the impurity concentration of the N-type impurity in the N-type region 114 is 1.0 × 10 × It is set to 10 ¹⁶ cm ⁻³ . The N-type region 114 functions as a charge accumulation region that accumulates charges generated in the substrate 101. The N conductivity type is an example of the second conductivity type of the present disclosure, and the N type region 114 is an example of the third semiconductor region of the present disclosure.

  As shown in FIG. 1, the fourth P + type region 116 is formed on the third P + type region 115 and the N type region 114. The fourth P + type region 116 is an example of the fourth semiconductor region of the present disclosure. In the present embodiment, the fourth P + type region 116 and the N type region 114 form a diode. Further, in the present embodiment, the DT insulating film 121 does not reach the lower surface of the fourth P + type region 116, and the third P + type region 115 includes the upper surface of the DT insulating film 121 and the fourth P + type region. It is interposed between the lower surface of the region 116.

In the present embodiment, the impurity concentration of the P-type impurity in the fourth P + type region 116 is set to 1.0 × 10 ¹⁹ cm ⁻³ .

Further, as shown in FIG. 1, at the side of the DT insulating film 121, a first P + type region 111, a second P + type region 112 and P-type region 113, the rear surface S ₂ and N-type substrate 101 It is formed between the lower surface of region 114. The impurity concentrations of P-type impurities in the first P + region 111, the second P + region 112, and the P-type region 113 are 1.0 × 10 ¹⁹ cm ⁻³ and 1.0 × 10 ¹⁷ cm, respectively. ⁻³ and 1.0 × 10 ¹⁶ cm ⁻³ .

That is, in the region on the side of the DT insulating film 121, the impurity concentration of the P-type impurity is set so as to decrease from the back surface S _{2 of the} substrate 101 toward the lower surface of the N-type region 114. Thereby, in this embodiment, the charge generated in the region on the side of the DT insulating film 121 easily moves to the N-type region 114.

FIG. 1 further shows a color filter 131 and a microlens 132 that are sequentially formed on the back surface S ₂ of the substrate 101. In the present embodiment, one color filter 131 and one microlens 132 are formed for each pixel partitioned by the DT insulating film 121. In FIG. 1, color filters 131 for red pixels, green pixels, and blue pixels are formed in the regions R _R , R _G , and R _B , respectively.

FIG. 1 further shows a wiring layer 141 formed on the surface S ₁ side of the substrate 101 and an interlayer insulating film 142 in which these wiring layers 141 are embedded.

  In this embodiment, B (boron) is used as the P-type impurity, but other impurities may be used instead. In this embodiment, P (phosphorus) is used as the N-type impurity, but other impurities may be used instead.

  In the present embodiment, as shown in FIG. 1, the sidewall surface of the DT insulating film 121 is covered only with the P-type semiconductor of the P-type semiconductor and the N-type semiconductor. Specifically, the sidewall surface of the DT insulating film 121 is covered with the first P + type region 111, the second P + type region 112, and the third P + type region 115. The advantages of such a configuration will be described later.

  Here, effects of the solid-state imaging device according to the first embodiment will be described with reference to FIGS. 3 and 4. 3 and 4 are side sectional views showing the structures of the solid-state imaging devices of the first comparative example and the second comparative example, respectively.

  In the first comparative example, as shown in FIG. 3, a P + type region 201, a P type region 202, an N− type region 203, an N type region 204, a P type region 205, P A − type region 206 and a P + type region 207 are formed.

In the first comparative example, the P − type region 206 is formed by high acceleration ion implantation from the surface S ₁ side of the substrate 101, thereby realizing pixel separation. However, in this ion implantation, as the flight length of ions increases, the scattering of ions in the lateral direction increases. This has the problem that it is difficult to realize ideal pixel separation, and color mixture in an acquired image becomes large.

FIG. 3 shows a P-type region 205 that has been formed by ion scattering in the lateral direction. Furthermore, the charge in the region R _G are drifted in the region R _R and region R _B, it has been shown how the color mixing occurs.

On the other hand, in this embodiment, pixel separation is realized by forming the DT insulating film 121 from the back surface S ₂ side of the substrate 101 (FIG. 1). Thereby, in the present embodiment, it is possible to realize pixel separation without requiring high acceleration ion implantation, and it is possible to realize a solid-state imaging device capable of acquiring an image with less color mixture.

  In the second comparative example, as shown in FIG. 4, a P + type region 301, a P type region 302, an N− type region 303, an N type region 304, and a P + type region 305 are formed in the substrate 101. A deep trench (DT) insulating film 311 is formed.

In the second comparative example, pixel separation is realized by forming the DT insulating film 311 from the back surface S ₂ side of the substrate 101. However, in the second comparative example, since the N − type region 303 and the N type region 304 are in contact with the side wall surface of the DT insulating film 311, a leak current is generated from the interface between the DT insulating film 311 and these regions. Easy (Figure 4). Therefore, the second comparative example has a problem that white scratches are likely to occur in the acquired image.

  On the other hand, in this embodiment, the side wall surface of the DT insulating film 121 is covered only with the P-type semiconductor (FIG. 1). Specifically, the side wall surface of the DT insulating film 121 is covered with the first to third P + type regions 111, 112, and 115. Thereby, in the present embodiment, the interface state between the substrate 101 and the DT insulating film 121 can be pinned with holes, and the generation of electrons from the interface state can be suppressed. As a result, in the present embodiment, it is possible to suppress the occurrence of leakage current at the interface between the DT insulating film 121 and the substrate 101, and to realize a solid-state imaging device capable of acquiring an image with few white scratches. Become.

  As described above, according to the present embodiment, it is possible to realize a solid-state imaging device capable of acquiring an image with less color mixing and white scratches.

  In the present embodiment, the solid-state imaging device is a back-illuminated CMOS image sensor. However, the present embodiment can also be applied to a solid-state imaging device other than a CMOS image sensor and a front-illuminated solid-state imaging device. is there.

  In the present embodiment, each pixel has a square planar shape, but may have another planar shape (for example, a rectangle).

  In this embodiment, the DT insulating film 121 and the third P + type region 115 are formed in a square lattice shape, but may be formed in other lattice shapes (for example, a staggered lattice shape).

In this embodiment, the distance H between the upper surface of the DT insulating film 121 and the surface S _{1 of the} substrate 101 is set to 0.2 to 0.4 μm, but may be set to other values. . If the distance H is too long, the third P + type region 115 must be formed at a deep position, and scattering of ions in the lateral direction when forming the third P + type region 115 becomes a problem. On the other hand, if the distance H is too short, the trench may penetrate to the surface S _{1 of the} substrate 101 when the trench for the DT insulating film 121 is formed. Therefore, it is desirable to set the distance H to an appropriate value that can avoid these.

In the present embodiment, the third P + type region 115 is formed not only on the upper surface of the DT insulating film 121 but also on a part of the side wall surface of the DT insulating film 121 (FIG. 1). This has the advantage that it is possible to avoid the occurrence of a gap between the DT insulating film 121 and the third P + type region 115 and to prevent the pixel separation from being broken from the gap. The DT insulating film 121 is formed so as not to reach the upper surface of the third P + type region 115 so as not to reach the depletion region of the surface S ₁ of the substrate 101 (FIG. 1).

In the present embodiment, the width W ₂ of each lattice line portion constituting the third P + type region 115 is set larger than the width W ₁ of each lattice line portion constituting the DT insulating film 121. This has the advantage that, for example, the DT insulating film 121 and the N-type region 114 can be reliably brought into non-contact, and the occurrence of leakage current due to the contact between the DT insulating film 121 and the N-type region 114 can be suppressed.

  As described above, in this embodiment, pixel isolation is realized by the DT insulating film 121 and the third P + type region 115, and the side wall surface of the DT insulating film 121 is covered with the P-type semiconductor. Thereby, in this embodiment, it is possible to realize a solid-state imaging device capable of acquiring an image with less color mixing and white scratches.

  Hereinafter, a second embodiment, which is a modification of the first embodiment, will be described focusing on differences from the first embodiment.

(Second Embodiment)
5 and 6 are side cross-sectional views illustrating the method of manufacturing the solid-state imaging device according to the second embodiment. In the method of this embodiment, the solid-state imaging device shown in FIG. 1 is manufactured.

First, a P-type semiconductor substrate is prepared as the substrate 101 (FIG. 5A). Next, by ion implantation from the rear surface S ₂ side of the substrate 101, the substrate 101, to form a first P + type region 111, and a second P + type region 112 (FIG. 5 (A)). As a result, the region other than the first and second P + regions 111 and 112 in the substrate 101 becomes the P region 113 (FIG. 5A).

Thus, the substrate 101, as shown in FIG. 5 (A), a first P + type region 111 are stacked in order from the rear surface S ₂ on the surface S _1, a second P + type region 112, A P-type region 113 is formed.

Next, a DT insulating film 121 is formed in a lattice pattern on the back surface S ₂ in the substrate 101 (FIG. 5B). DT insulating film 121 is, for example, by RIE (Reactive Ion Etching), a trench is formed in a grid pattern on the rear surface S ₂ of the substrate 101, then, by the CVD (Chemical Vapor Deposition) or the like, to embed an insulating film in the trench Formed with.

The RIE is continued even after the trench reaches the lower surface of the P-type region 113, and as a result, a part of the side wall surface of the trench is covered with the P-type region 113. The RIE is performed such that the distance H between the surface S _{1 of the} substrate 101 and the upper surface of the trench is 0.2 to 0.4 μm, more specifically 0.3 μm. In the present embodiment, the timing for stopping the RIE is controlled using the measurement result of the etching time.

Next, a third P + type region 115 is formed on the DT insulating film 121 in the substrate 101 by ion implantation from the surface S ₁ side of the substrate 101 (FIG. 5C). As a result, the P-type region 113 is divided for each pixel. In this embodiment, the irradiation intensity of ions when forming the third P + type region 115 is set to several tens KeV.

Next, an N-type region 114 is selectively formed on each P-type region 113 in the substrate 101 by ion implantation from the surface S ₁ side of the substrate 101 (FIG. 6A). Thus, a plurality of N-type regions 114 are formed on the side of the third P + type region 115 so as to be separated from each other by the third P + type region 115.

Next, by ion implantation from the surface S ₁ side of the substrate 101, on the third P + type region 115 and N-type region 114 of the substrate 101 to form a fourth P + type region 116 (FIG. 6 (B )).

Thereafter, in the present embodiment, as shown in FIG. 6C, the color filter 131 and the micro lens 132 are formed on the back surface S ₂ side of the substrate 101. Further, as shown in FIG. 1, a wiring layer 141 and an interlayer insulating film 142 are formed on the surface S ₁ side of the substrate 101. Thus, the solid-state imaging device shown in FIG. 1 is manufactured.

  Here, the effects of the method of manufacturing the solid-state imaging device according to the second embodiment will be described with reference to FIGS.

In the present embodiment, as shown in FIG. 5B, pixel separation is realized by forming the DT insulating film 121 from the back surface S ₂ side of the substrate 101. Thereby, in the present embodiment, it is possible to realize pixel separation without requiring high acceleration ion implantation, and it is possible to realize a solid-state imaging device capable of acquiring an image with less color mixture.

  In the present embodiment, as shown in FIG. 5B, when the DT insulating film 121 is formed, the side wall surface of the DT insulating film 121 is covered only with the P-type semiconductor. Specifically, when the DT insulating film 121 is formed, the sidewall surface of the DT insulating film 121 is covered with the first P + type region 111, the second P + type region 112, and the P type region 113. .

  Thereafter, as shown in FIG. 5C, the P-type region 113 covering the side wall surface of the DT insulating film 121 is replaced with a third P + -type region 115. However, even when the solid-state imaging device is completed, DT The side wall surface of the insulating film 121 is covered only with the P-type semiconductor (FIG. 1).

  Thus, in this embodiment, the DT insulating film 121 is formed so that the side wall surface is finally covered only with the P-type semiconductor. Thereby, in the present embodiment, the interface state between the substrate 101 and the DT insulating film 121 can be pinned with holes, and the generation of electrons from the interface state can be suppressed. As a result, in the present embodiment, it is possible to suppress the occurrence of leakage current at the interface between the DT insulating film 121 and the substrate 101, and to realize a solid-state imaging device capable of acquiring an image with few white scratches. Become.

  As described above, according to the present embodiment, it is possible to realize a solid-state imaging device capable of acquiring an image with less color mixing and white scratches.

  As described above, in this embodiment, pixel isolation is realized by the DT insulating film 121 and the third P + type region 115, and the side wall surface of the DT insulating film 121 is covered with the P-type semiconductor. Thereby, in this embodiment, it is possible to realize a solid-state imaging device capable of acquiring an image with less color mixing and white scratches.

  As mentioned above, although the example of the specific aspect of this invention was demonstrated by 1st and 2nd embodiment, this invention is not limited to these embodiment.

  101: substrate, 111: first P + type region (first semiconductor region), 112: second P + type region (first semiconductor region), 113: P type region (first semiconductor region), 114: N type Region (third semiconductor region), 115: third P + type region (second semiconductor region), 116: fourth P + type region (fourth semiconductor region), 121: deep trench insulating film (element isolation insulating film) 131: Color filter, 132: Micro lens, 141: Wiring layer, 142: Interlayer insulating film, 201: P + type region, 202: P type region, 203: N− type region, 204: N type region, 205: P Type region, 206: P− type region, 207: P + type region, 301: P + type region, 302: P type region, 303: N− type region, 304: N type region, 305: P + type region, 311: Deep Trench insulation film

Claims (7)

A first conductivity type substrate having a first surface and a second surface;
An element isolation insulating film formed in a lattice pattern on the second surface in the substrate;
A plurality of first semiconductor regions of a first conductivity type formed on the side of the element isolation insulating film in the substrate and separated from each other by the element isolation insulating film;
A second semiconductor region of a first conductivity type formed in a lattice shape on the element isolation insulating film in the substrate and functioning as a pixel isolation region;
A plurality of third semiconductor regions of a second conductivity type formed on the side of the second semiconductor region in the substrate, separated from each other by the second semiconductor region, and functioning as charge storage regions;
A first conductivity type fourth semiconductor region formed on the second and third semiconductor regions in the substrate;
The element isolation insulating film has a sidewall surface covered with the first and second semiconductor regions.   The impurity concentration of the first conductivity type impurity in the first semiconductor region is set to become lower from the second surface of the substrate toward the lower surface of the third semiconductor region. Item 2. The solid-state imaging device according to Item 1.   3. The solid-state imaging device according to claim 1, wherein the second semiconductor region is also formed on a part of the side wall surface of the element isolation insulating film.   4. The solid-state imaging according to claim 1, wherein the second semiconductor region is interposed between an upper surface of the element isolation insulating film and a lower surface of the fourth semiconductor region. apparatus.   5. The distance according to claim 1, wherein a distance between the first surface of the substrate and an upper surface of the element isolation insulating film is 0.2 to 0.4 μm. Solid-state imaging device.   6. The width of each lattice line portion constituting the second semiconductor region is larger than the width of each lattice line portion constituting the element isolation insulating film. 6. Solid-state imaging device. Preparing a first conductivity type substrate having a first surface and a second surface;
Forming a first semiconductor region of a first conductivity type in the substrate;
Forming an element isolation insulating film in a lattice pattern on the second surface of the substrate;
In the substrate, a second semiconductor region of the first conductivity type is formed in a lattice shape on the element isolation insulating film,
Forming a plurality of third semiconductor regions of a second conductivity type separated from each other by the second semiconductor region in the substrate, lateral to the second semiconductor region;
Forming a fourth semiconductor region of a first conductivity type on the second and third semiconductor regions in the substrate;
A method of manufacturing a solid-state imaging device,
The element isolation insulating film is formed so that a side wall surface is covered with the first and second semiconductor regions.

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