JP2012065417A - Power supply interruption device and electric apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To semipermanently stop supply of electric power by automatically and safely shutting down an electric apparatus without troubling a user if the electric apparatus has a voltage failure or an access operation which a user does not intend to do occurs.SOLUTION: A power supply interruption circuit 11 includes a latch relay 6, an Nch_FET 4, and a transistor 7. When a voltage detection circuit 9 and a user definition circuit 10 detect a failure, the transistor 7 is turned on and a switch 6c of the latch relay 6 is also turned on to turn off the Nch_FET 4 and to shut down voltage supply to a secondary main operation circuit 15. The latch relay 6, once the latch relay 6 is turned on, has a characteristic that the state is kept; therefore, power supply interruption can be semipermanently performed. At power supply restoration, the switch 6c of the latch relay 6 is turned off using latch relay control external terminals 16a, 16b.

Description

  The present invention relates to a technique for shutting off a power supply when an abnormality occurs in an electrical device.

  In general, an electric device that uses an AC power supply and supplies power to a secondary circuit in the device using a power supply device that performs AC-DC conversion. In a power supply device that supplies power to an IC or the like in a device, control is performed to stop power supply when the secondary output voltage is abnormal in order to prevent destruction of the IC. For example, in the technique disclosed in Patent Document 1, after the primary side voltage is lowered due to the secondary side voltage fluctuation and the primary side control circuit is stopped, the power supply voltage is automatically supplied via the starting resistor. Supply is being restored.

JP 2009-177990 A

  For electrical equipment that has a power supply unit that inputs AC power and performs AC-DC conversion, protection is performed using some method when the secondary output voltage is abnormal for protection of secondary circuit components and safety of the equipment. It is necessary to do. In the technique described in Patent Document 1, when a voltage abnormality is detected and a device operation is abnormal, the primary side voltage is temporarily reduced to stop the voltage output to the secondary side circuit and via a starting resistor. Thus, it is possible to automatically restore the power supply voltage supply.

  However, since the technique described in Patent Document 1 can automatically restore the power supply voltage supply, another problem may occur. For example, even in the case of a voltage abnormality caused by a physical short circuit between the power supply and the ground in the circuit and IC inside the secondary side substrate, the power supply voltage supply is restored and the voltage supply to the secondary side circuit is performed. Since it continues, there is a possibility that a bad point may be exerted on a part different from the cause of the abnormality.

  In addition, the electric device does not always operate only when the user is nearby. In particular, it is assumed that monitoring equipment is often installed in an unattended ATM or the like and operates for 24 hours 365 days. In such an environment, when a device under unattended operation repeats power recovery due to a voltage abnormality, abnormal heat generation may be repeated by supplying an abnormal voltage to the IC, leading to a worst accident.

  When a semi-permanent power shutdown of an electric device is performed, a fuse is generally used in many cases. However, the circuits of recent electrical equipment are mainly composed of ICs such as LSIs and memories, and the operating voltage of ICs is being lowered in order to save the power consumption of the equipment. As a result, the circuits of recent electrical equipment are easily affected by the influence of the natural environment, for example, the influence of surge voltage inflow due to lightning or the influence of external noise from other equipment. As a result, it is conceivable that a fuse that is not resistant to changes in current value will unintentionally shut off, and it is difficult to keep the reliability of the device high. Further, in the case of a fuse, once it is cut off, it is necessary to replace the part to recover it, and in addition to the part cost, a labor cost is required for the work, leading to an increase in cost.

  On the other hand, monitoring devices, particularly monitoring recording / playback devices, are often installed at important locations such as financial institutions, and the recorded data is very valuable. If an outsider tries to access and browse these data illegally, it is necessary to prohibit the browsing of the data. In addition, in an electrical device provided with a device abnormality detection circuit, when a device abnormality frequently occurs due to an abnormality in an internal circuit, it is necessary to not only restart but also shut off the power.

  In view of such circumstances, an object of the present invention is to appropriately and inexpensively realize power shutoff performed when an abnormality occurs in an electrical device.

According to the present invention, in an electrical apparatus including a power supply device that inputs AC power and performs AC-DC conversion, an output terminal for a secondary voltage applied from the power supply device to a secondary side circuit, and a secondary in the subsequent stage A switching element, a latch relay that controls on / off of the switching element, and an abnormality detection circuit that outputs a control signal indicating an abnormality to the latch relay are provided between the main part of the side circuit. When an abnormality such as a voltage abnormality occurs in the secondary side circuit, the voltage supply to the secondary side circuit is semipermanently stopped by turning on the switching element.
Details will be described later.

  ADVANTAGE OF THE INVENTION According to this invention, the power interruption performed when abnormality arises in an electric equipment can be implement | achieved appropriately and cheaply.

It is a block diagram which shows an example of the electric equipment containing the power cutoff device which concerns on this embodiment. It is a block diagram which shows the specific example of a voltage detection circuit. It is a figure which shows the operation | movement flowchart at the time of a power supply interruption. It is a figure which shows the signal waveform of each part of the power shutdown circuit at the time of a power shutdown. It is a block diagram which shows another example of the electric equipment containing the power cutoff device which concerns on this embodiment.

  Hereinafter, embodiments (hereinafter referred to as “embodiments”) according to the present invention will be specifically described with reference to the drawings.

<< First Embodiment >>
FIG. 1 is a configuration diagram illustrating an example of an electric device including a power shutoff device according to the present embodiment.
The electrical device 1 is, for example, a monitoring recording / playback device that often operates unattended, and mainly includes a power supply device 2, an AC plug 3, a secondary circuit 12, and latch relay control external terminals 16a and 16b.

  The power supply device 2 performs AC-DC conversion on the AC power input from the AC plug 3 of the electrical device 1. The power supply device 2 applies (supplies) a desired secondary voltage V20 from the secondary output terminal 13 to the secondary circuit 12 by the conversion, and supplies power.

The secondary side circuit 12 mainly includes a power cut-off circuit (power cut-off device) 11 and a secondary-side main operation circuit 15, and operates with the power supplied from the power supply device 2.
The secondary side main operation circuit 15 is a main part of the secondary side circuit 12 and is operated by the power supplied from the power supply device 2 to realize the monitoring recording / playback operation processing in ATM or the like. However, in the present embodiment, detailed description regarding the secondary side main operation circuit 15 is omitted.

  The power cut-off circuit 11 mainly includes an Nch_FET 4, a pull-up resistor 5, a latch relay 6, a transistor 7, an OR gate 8, a voltage detection circuit 9, a user-defined circuit 10, a pull-down resistor 14, and a pull-up resistor 20, and an abnormality occurs. The power supplied from the power supply device 2 is shut off.

The Nch_FET 4 is a switching element that controls a current flowing from the power supply device 2 to the secondary main operation circuit 15.
The source of the Nch_FET 4 is connected to a line connected to the secondary output terminal 13. In that line, the secondary voltage V20 is applied.
The drain of the Nch_FET 4 is connected to a line connected to the secondary main operation circuit 15. In that line, the voltage V21 is applied.
The gate of the Nch_FET 4 is connected to a line connected to the latch relay 6. A voltage Vg is applied to the line. Further, the gate of the Nch_FET 4 is connected to a line connected to the secondary output terminal 13 via the pull-up resistor 5.
The pull-up resistor 5 determines the current value of the current flowing through the gate of the Nch_FET 4.

The latch relay 6 mainly includes a coil 6a, a contact 6b, and a switch 6c, and controls the Nch_FET 4 on and off.
One end of the coil 6a is connected to a line connected to the collector of the transistor 7 via the pull-up resistor 20 and to a line connected to the latch relay control external terminal 16b. The other end of the coil 6a is connected to a line connected to the secondary output terminal 13 and to a line connected to the latch relay control external terminal 16a.
One end of the switch 6c is connected to the ground (GND), and the other end of the switch 6c is connected to the contact 6b when a current flows through the coil 6a.
The contact 6 b is a connection destination when the gate of the Nch_FET 4 is connected to the latch relay 6.

The transistor 7 is an element that controls on / off of the operation of the latch relay 6 based on the control signal Vb output from the OR gate 8.
The collector of the transistor 7 is connected to a line connected to the coil 6 a of the latch relay 6 through the pull-up resistor 20. A voltage Vc is applied to the line.
The emitter of transistor 7 is connected to ground.
The base of the transistor 7 is connected to a line connected to the OR gate 8. In that line, a voltage determined from the control signal Vb output from the OR gate 8 is applied. Further, a pull-down resistor 14 connected to the ground is connected to the line.

The pull-up resistor 20 determines a current value that flows between the collector and the emitter when the transistor 7 is in the ON state.
The pull-down resistor 14 fixes the base logic of the transistor 7 so that the power supply is not cut off for an irregular period that occurs in a short time from when the power is turned on to when the secondary power is supplied.

  The OR gate 8 is a logic circuit that outputs the logical sum of the output from the voltage detection circuit 9 and the signal output from the user-defined circuit 10 as a control signal Vb. This control signal Vb determines the level of the voltage applied to the base of the transistor.

The voltage detection circuit 9 and the user-defined circuit 10 are an abnormality detection circuit (abnormality detection unit) that detects an abnormality that has occurred in the secondary circuit 12. The abnormality in the present embodiment is mainly a voltage abnormality in which the voltage applied to the secondary side circuit 12 is too high (more than a predetermined value) or too low (below a predetermined value), or external to the electric device 1. An abnormal operation in which an illegal access from the terminal or an operation that cannot occur in the design of the electric device 1 is performed. The voltage detection circuit 9 detects the voltage abnormality, and the user-defined circuit 10 detects the operation abnormality. It should be noted that the present invention can be applied to abnormalities other than these abnormalities, for example, by providing appropriate abnormality detection circuits.
When the voltage detection circuit 9 and the user-defined circuit 10 detect these abnormalities, they output a signal indicating the abnormalities to the OR gate 8.

The latch relay control external terminal 16 a is an external terminal connected to a line connecting the coil 6 a of the latch relay 6 and the secondary side connection terminal 13 of the power supply device 2.
The latch relay control external terminal 16 b is an external terminal connected to a line connecting the coil 6 a of the latch relay 6 and the collector of the transistor 7.

  During normal times when no abnormality has occurred in the voltage detection circuit 9 and the user-defined circuit 10, the switch 6c of the latch relay 6 is in an OFF state. At this time, since the voltage Vg applied to the gate of the Nch_FET 4 is at a high level, a current flows between the source and drain of the Nch_FET 4. Then, the voltage V21 is supplied to the secondary main operation circuit 15, and the electric device 1 operates.

  In normal operation, the outputs of the voltage detection circuit 9 and the user-defined circuit 10 are both low voltage outputs, and the output of the OR gate 8 that receives the output and performs logical conversion, that is, the control signal Vb is low voltage output. . For this reason, the base of the transistor 7 is not turned on, and no current flows between the collector and the emitter of the transistor 7. As a result, the voltage Vc at the collector of the transistor 7 becomes a high voltage.

  When an abnormality is detected in either the voltage detection circuit 9 or the user-defined circuit 10, a High voltage is output from the circuit that detected the abnormality, and the voltage indicated by the control signal Vb output from the OR gate 8 is a High voltage. As a result, the base of the transistor 7 is turned on, a voltage flows between the collector and the emitter of the transistor 7, and a current flows through the latch relay 6 at the same time. Then, since the switch 6c in the latch relay 6 contacts the contact 6b and the switch 6c is turned on, the secondary output terminal 13 is connected to the ground via the pull-up resistor 5. Become. Therefore, the voltage Vg applied to the gate of the Nch_FET 4 becomes the Low voltage and the Nch_FET 4 is turned off, so that no current flows between the source and the drain of the Nch_FET 4. As a result, the voltage V21 is not supplied to the secondary main operation circuit 15, and the operation of the electric device 1 is stopped. Further, since the latch relay 6 has a characteristic of maintaining the state where the current flows once the current flows, the power supplied from the power supply device 2 is cut off semipermanently.

  As a specific means for realizing the voltage detection circuit 9, for example, as shown in FIG. 2, it can be easily realized. FIG. 2 is a configuration diagram illustrating a specific example of the voltage detection circuit. The voltage detection circuit 9 shown in FIG. 2 mainly includes a low voltage detection circuit 91 and an overvoltage detection circuit 92.

  The low voltage detection circuit 91 detects a voltage abnormality that the voltage applied to the secondary side circuit 12 is too low. In the normal time when the voltage abnormality does not occur, the divided voltage values of various voltages (5.0V, 2.5V, 1.8V) are pulled up to 1.25V or approximately 1.25V, and the comparator 91a It is set to be higher than the voltage value on the + side of. For this reason, no current flows through the diode 91b, and the voltage value on the + side of the comparator 91a is maintained at 1.2V. As a result, the voltage value on the negative side of the comparator 91a is higher than 0.9V, and the output from the comparator 91a becomes High.

  If the voltage abnormality occurs, that is, if any one of the various voltages becomes a low voltage, the current from the positive side of the comparator 91a pulled up to 1.2V through the diode 91b. Flows. For this reason, the voltage value on the + side of the comparator 91a is lower than the voltage value 0.9V on the-side of the comparator 91a, and the output from the comparator 91a changes to Low.

  The overvoltage detection circuit 92 detects a voltage abnormality in which the voltage applied to the secondary side circuit 12 is too high. In normal times when the voltage abnormality does not occur, the divided voltage values of various voltages (5.0V, 2.5V, 1.8V) are pulled up to be 1.25V or approximately 1.25V, and the diode 92b Current flows through. For this reason, when a current flows, the voltage drops by the voltage Vf of the diode 92b, and the voltage value resulting from the voltage drop, that is, approximately 0.75 V becomes the voltage value on the + side of the comparator 92a. As a result, the voltage value of the negative side of the comparator 92a is lower than 0.9V, and the output from the comparator 92a becomes Low.

  If the voltage abnormality occurs, that is, if any one of the various voltages becomes an overvoltage, a current flows through the diode 92b and the voltage drops by the voltage Vf of the diode 92b. The voltage value is higher than the negative voltage value 0.9V of the comparator 92a. For this reason, the voltage value on the + side of the comparator 92a becomes higher than the voltage value 0.9V on the-side of the comparator 92a, and the output from the comparator 92a shifts to High.

  With such a configuration, the voltage detection circuit 9 outputs a signal indicating a normal time or an abnormal time related to the voltage abnormality to the OR gate 8.

  As a concrete means for realizing the user-defined circuit 10, it is easily realized by using an IC (Integrated Circuit) in which a user can freely configure a logic circuit, such as an FPGA (Field Programmable Gate Array). Is possible. Since many of the electric circuits in recent years are equipped with FPGAs, if unused empty terminals are used, they can be realized without incurring component costs.

  When a user intentionally shuts down the power supply, a circuit with a fuse or the like must be intentionally generated with a large current, which is very dangerous and difficult, and damages the internal circuit of the device. there is a possibility. However, the circuit realized in this embodiment has a configuration in which such danger does not occur.

  An example of an event in which the user intentionally shuts off the power using the user-defined circuit 10 is an operation error in which the password locked data is illegally accessed repeatedly and the password is mistaken more than the specified number of times. is there. In addition, in a device provided with a predetermined operation abnormality detection circuit, there is an operation abnormality detected by the operation abnormality detection circuit. If detection of an abnormal operation occurs rarely, the power supply may be restored by using the circuit described in Patent Document 1. However, in the case where the operation abnormality frequently occurs, a failure of the internal circuit of the device can be considered. Therefore, it is conceivable that the power supply is cut off when the operation abnormality occurs more than the specified number of times within a specific time.

  When the power supply is restored from the outside after the power is shut off, the power supply is connected to the latch relay control external terminal 16b, the GND is connected to the latch relay control external terminal 16a, and the latch relay 6 is turned on by supplying current. It may be turned off. Of course, in the case where it is known that there is no abnormality in the internal circuit, even when there is an abnormality in the internal circuit, it is useful to enable power recovery by external control. This is because it is not only very convenient in the analysis work, but also it is possible to save the cost for the part cost and the time spent for the part replacement.

Hereinafter, the operation of the power shutoff device of the present embodiment will be described in detail.
FIG. 3 is a diagram illustrating an operation flowchart when the power is shut off according to the present embodiment.

In the flowchart shown in FIG. 3, first, the process of step S301 is executed. In step S <b> 301, AC power is supplied from the AC plug 3 to the power supply device 2.
Next, in step S <b> 302, the secondary voltage AC-DC converted by the power supply device 2 is supplied to the secondary side circuit 12 and the electric device 1 is activated.

  After startup, in step S303, the voltage detection circuit 9 and the user-defined circuit 10 in the secondary side circuit 12 monitor the voltage level and the presence / absence of an operation contrary to the user's intention. If an abnormality is detected by the monitoring, the OR gate 8 outputs a control signal Vb indicating the abnormality. Step S303 includes Step S304, Step S305, Step S306, and Step S307. After step S302, in step S304, step S305, and step S306, it is determined whether or not an abnormality has been detected.

In step S304, the voltage detection circuit 9 determines whether or not a low voltage lower than the specified level has been detected. When the low voltage is detected (Yes in step S304), the process proceeds to step S307.
In step S305, the voltage detection circuit 9 determines whether or not an overvoltage exceeding a specified level has been detected. When the overvoltage is detected (Yes in step S305), the process proceeds to step S307.
In step S306, the user-defined circuit 10 determines whether or not an operation abnormality has been detected. When the operation abnormality is detected (Yes in step S306), the process proceeds to step S307.

  In step S307, when any abnormality shown in step S304, step S305, or step S306 is detected (Yes), a control signal Vb indicating power-off is output to the base of the transistor 7.

  After the output of the control signal Vb, in step S308, a high level voltage is supplied to the base of the transistor 7 by the control signal Vb, whereby the switching element that controls the latch relay 6, that is, the transistor 7 is turned on and the collector-emitter is turned on. Current flows between them.

  Next, in step S309, in addition to the current flowing between the collector and emitter of the transistor 7 in step S308, the current flows in the coil 6a inside the latch relay 6, and the switch 6c is connected to the contact 6b. The latch relay 6 is turned on.

  Next, in step S310, since the latch relay 6 is turned on, the low-level gate voltage Vg is supplied to the switching element that receives the secondary voltage V20, that is, the gate of the Nch_FET 4, and the Nch_FET 4 is turned off.

Finally, in step S311, because the Nch_FET 4 is turned off, the secondary voltage V21 supplied from the power supply device 2 is not sent to the subsequent stage from the Nch_FET 4, and the secondary voltage V21 is cut off.
This completes the operation when the power is shut off.

  FIG. 4 is a diagram showing signal waveforms at various parts of the power shut-off circuit when the power is shut off. With reference to FIG. 4, the operation timing of each part of the power shutoff circuit will be described. The power-off operation in the power-off circuit 11 proceeds at times t1, t2,..., T6,. In this description, FIG. 3 is referred to as appropriate.

  In FIG. 4A, the signal waveform of the secondary voltage V20 supplied from the power supply device 2 is shown. According to FIG. 4A, it can be seen that the voltage level does not decrease at any timing even when the power shut-off circuit 11 works and the power supply to the secondary main operation circuit 15 stops.

  FIG. 4B shows a signal waveform of the control signal Vb output from the OR gate 8. 4B, since at least one of the voltage detection circuit 9 and the user-defined circuit 10 has detected an abnormality, it can be seen that the control signal Vb changes from the Low level to the High level from time t1 to time t2. . This detection and transition corresponds to step S303 in FIG.

  Further, according to FIG. 4B, since the secondary voltage V21 has transitioned to a low level and lost operating power from time t5 to t6 (see (f)), the control signal Vb is applied after time t6. It can be seen that changes from High level to Low level.

  FIG. 4C shows a signal waveform of the voltage Vc at the collector of the transistor 7. According to FIG. 4C, it can be seen that the collector voltage Vc changes from the high level to the low level from time t2 to time t3 because the transistor 7 is turned on and a current flows between the collector and the emitter. . This transition corresponds to step S308 in FIG.

  Further, according to FIG. 4C, since the secondary voltage V21 has transitioned to the Low level and the operating power has been lost (see (f)), the collector voltage Vc changes from the Low level to the High level after time t6. It turns out that it changes.

  In FIG. 4D, the signal waveform of the operating state of the latch relay 6 is shown. According to FIG. 4D, it can be seen that the current flows through the coil 6a in the latch relay 6 and the state changes from the OFF state to the ON state from time t3 to time t4. This transition corresponds to step S309 in FIG. At this time, the switch 6c is connected to the contact 6b.

  FIG. 4E shows a signal waveform of the gate voltage Vg of the Nch_FET 4. According to FIG. 4E, when the latch relay 6 is turned on and the switch 6c is connected to the contact 6b, the gate voltage Vg changes from the high level to the low level from time t4 to t5. I understand. This transition corresponds to step S310 in FIG.

  In FIG. 4F, the signal waveform of the secondary voltage V21 supplied to the secondary main operation circuit 15 is shown. According to FIG. 4F, the gate voltage Vg is changed to the low level, and the Nch_FET 4 is turned off at the time t5, so that the supply of the secondary voltage V21 is cut off from the time t5 to the time t6. It can be seen that the next voltage V21 changes from the High level to the Low level. This transition corresponds to step S311 in FIG.

  From the above description, according to the present embodiment, it is possible to appropriately and inexpensively realize power shutoff performed when an abnormality occurs in an electrical device. When a voltage abnormality occurs in an electrical device or when an operation unintended by the user occurs, the power supply to the secondary side of the electrical device is stopped semipermanently automatically and safely without any user effort. Can do. Further, since a fuse is not used, it is not unnecessarily blocked by external noise or the like, and the reliability of the device can be kept high.

  Furthermore, since the latch relay control external terminals 16a and 16b are provided and the latch relay 6 can be controlled from the outside of the electric device 1, it is not necessary to spend extra cost or time for parts replacement or opening / closing of the device exterior. It can be easily restored when the breaker circuit is restored.

<< Second Embodiment >>
FIG. 5 is a configuration diagram illustrating another example of an electric device including the power shutoff device according to the present embodiment. Most of the configuration of the present embodiment is the same as that of the first embodiment. Therefore, the components common to the first embodiment are denoted by the same reference numerals, and the description thereof is basically omitted.

  In the present embodiment, there are mainly two differences from the first embodiment. That is, the first point is that the voltage output to the power shutoff circuit 11 is two systems. The power supply device 2 includes secondary side output terminals 13a and 13b. The voltages generated from the power supply device 2 and output to the power cutoff circuit 11 through the secondary output terminals 13a and 13b are V20 and V20 ′, respectively.

  The second point is that a Pch_FET 19 is used instead of the Nch_FET 4 of the first embodiment, and a pull-down resistor 17 and a pull-up resistor 18 are used instead of the pull-up resistor 5. With such a change, the ground connected to the switch 6c in the first embodiment is not used.

Pch_FET 19 is an FET element that is turned on when the gate voltage Vg is at a low level.
The source of the Pch_FET 19 is connected to a line connected to the secondary output terminal 13a. In that line, the secondary voltage V20 is applied.
The drain of the Pch_FET 19 is connected to a line connected to the secondary main operation circuit 15. In that line, the voltage V21 is applied.
The gate of the Pch_FET 19 is connected to a line connected to a contact to which the switch 6c of the latch relay 6 is normally connected. A voltage Vg is applied to the line.

The pull-down resistor 17 fixes the gate logic of the Pch_FET 19 so that the power supply does not shut off during an irregular period that occurs in a short time from when the power is turned on to when the secondary power is supplied.
The pull-up resistor 18 is connected to the contact 6b of the latch relay 6 and the secondary output terminal 13b, and determines the value of the current flowing through the gate of the Pch_FET 19 at the time of abnormality.

  When an abnormality is detected by the voltage detection circuit 9 and the user-defined circuit 10, the latch relay 6 is turned on. As a result, the voltage value divided by the pull-up resistor 18 and the pull-down resistor 17 becomes the gate voltage Vg of the Pch_FET 19. When the switch 6c of the latch relay 6 is turned on, the gate voltage Vg needs to be at a high level in accordance with the specification of the Pch_FET 19 in order for the Pch_FET 19 to be turned off. Therefore, the relationship between the resistance values of the pull-up resistor 18 and the pull-down resistor 17 needs to be determined by calculation.

  For example, when the voltage V20 is 5.7 V and the voltage V20 ′ is 12.0 V, the resistance value of the pull-up resistor 18 is 5.6 kΩ and the resistance value of the pull-down resistor 17 is 10.0 kΩ. That's fine.

  At normal time, since the latch relay 6 is in the OFF state, the gate voltage Vg of the Pch_FET 19 is 0V. At this time, since the source voltage of the Pch_FET 19 is 5.7 V, the Pch_FET 19 is turned on and a current flows through the secondary main operation circuit 15.

  At the time of abnormality, the latch relay 6 is turned on, so that the voltage V20 ′ is divided by the pull-up resistor 18 and the pull-down resistor 17, and the gate voltage Vg of the Pch_FET 19 becomes approximately 7.5V. Therefore, the gate voltage Vg shows a voltage value higher than the source voltage, the Pch_FET 19 is turned off, and no current flows through the secondary side main operation circuit 15.

  In the configuration of the present embodiment, the voltage V20 ′ supplied from the secondary output terminal 13b is supplied at an earlier timing than the voltage V20 supplied from the secondary output terminal 13a. This is because when the switch 6c of the latch relay 6 is turned on, if the voltage level of the contact 6b portion is indefinite, the Pch_FET 19 cannot be immediately turned off, and an abnormal voltage is generated on the secondary side. This is to avoid being supplied to the main operation circuit 15. For example, the power supply apparatus 2 may be provided with a dedicated circuit for setting such timing.

Incidentally, the signal waveform of each part of the power shutdown circuit at the time of power shutdown in this embodiment is the same except for a part of the signal waveform in the first embodiment shown in FIG. 4 is different from the signal waveform of FIG. 4 in that Pch_FET 19 is used instead of Nch_FET 4, and in FIG. 4E, the gate voltage Vg changes from Low level to High level from time t4 to time t5. .
In addition, the signal waveform of the secondary voltage V20 ′ does not decrease at any timing even when the power is shut off, like the signal waveform of the secondary voltage V20 shown in FIG.

  According to the present embodiment, since the Pch_FET is used as the switching element, it is possible to improve the accuracy of the power shutdown control. Therefore, the reliability of the electric device itself can be improved.

≪Others≫
The above embodiment is suitable for carrying out the present invention, but the form of implementation is not limited thereto, and various modifications can be made without departing from the scope of the present invention. It is.

  For example, in this embodiment, control is performed so that the power supply is shut off when an abnormality occurs. However, before an abnormality occurs, it may be determined whether or not there is a possibility that an abnormality will occur, and if there is a possibility, a predetermined warning output may be performed. For example, in the case of a voltage abnormality, a voltage value that may become an undervoltage or an overvoltage is set, and a warning is output when the voltage detection circuit 9 detects the set voltage value. In the case of an abnormal operation, a plurality of conditions that can be regarded as an abnormal operation are determined, and a warning is output when the user-defined circuit 10 determines that a part of the determined conditions is satisfied. For example, there is a method in which a password is output when a wrong password is entered three times, an operation error is considered, and a wrong password is entered twice.

  The warning output includes, for example, a warning display by turning on a screen or lighting, a predetermined warning sound, or notification of a state of fear of abnormality to the management center of the electrical equipment. The power shut-off circuit 11 is provided with a means for outputting a warning.

  In the first embodiment, an Nch_FET is used as a switching element, and in the second embodiment, a Pch_FET is used. However, the circuit design may be changed as necessary, and the Pch_FET may be used in the first embodiment, or the Nch_FET may be used in the second embodiment.

  In addition, the power shut-off device of the present embodiment is designed with a circuit that does not use a fuse. However, the power shut-off device does not exclude a configuration that does not include a fuse, and may be designed so that the power shut-off device includes a fuse for some purpose.

  In addition, it is possible to realize a technique in which various techniques described in this embodiment are appropriately combined.

  In addition, specific configurations such as circuit design and flowcharts can be changed as appropriate without departing from the spirit of the present invention.

DESCRIPTION OF SYMBOLS 1 Electric equipment 2 Power supply device 3 AC plug 4 Nch_FET (switching element)
5 Pull-up resistor 6 Latch relay 6a Coil 6b Contact 6c Switch 7 Transistor 8 OR gate 9 Voltage detection circuit (abnormality detection unit)
10 User-defined circuit (abnormality detection unit)
11 Power-off circuit (power-off device)
12 Secondary circuit (secondary side)
13, 13a, 13b Secondary side output terminal 14 Pull-down resistor 15 Secondary side main operation circuit 16a, 16b Latch relay control external terminal (external terminal)
17 Pull-down resistor 18 Pull-up resistor 19 Pch_FET (switching element)
20 Pull-up resistor

Claims (4)

In a power shut-off device that shuts off the power supplied to the secondary side by the power device,
A switching element connected to the main part of the power supply device and the secondary side;
A latch relay that controls on / off of the switching element;
An abnormality detection unit for detecting an abnormality that has occurred on the secondary side,
When the abnormality is detected, the switching element is turned off. 2. The power shut-off according to claim 1, further comprising: an external terminal connected to a line connected to both sides of a coil inside the latch relay in order to perform the on / off control in the electric device including the power shut-off device. apparatus. The abnormality is either a voltage abnormality in which a voltage value greater than or equal to a predetermined value is detected, or an operation abnormality in which an operation contrary to an operation determined by a circuit using an integrated circuit is detected. The power shut-off device according to claim 1 or 2.   The electric equipment using the power-supply-cutoff apparatus as described in any one of Claims 1-3.

Images