JP2012059950A - Protective device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve the problem that manufacturing processes are complicated and troublesome in a conventional structure and cost reduction of a protective device and versatility are limited, while a bidirectional pn junction diode is used as the protective device of ESD breakdown connected to a signal line between a USB connector and a component to be protected.SOLUTION: A p-type semiconductor layer is laminated on a p semiconductor substrate. A p+-type impurity layer, having a higher concentration than that of the p-type semiconductor layer, is provided on the surface of the p-type semiconductor layer. A first n+-type impurity region and a second n+-type impurity region, separated from each other, are provided on the surface of the p+-type impurity layer. A first electrode which is in contact with the first n+-type impurity region and is electrically connected to an input terminal and a second electrode which is in contact with the second n+-type impurity region and is electrically connected to a ground terminal are provided, and thereby providing a protective device by a horizontal bidirectional pn junction diode. The first n+-type impurity region and the second n+-type impurity region are separated by 140 μm or more, are respectively in a corner-rounded square shape, and are arranged along the diagonal of the p+-type semiconductor substrate.

Description

  The present invention relates to a protective device for electrostatic breakdown protection, and more particularly to a protective device having both high electrostatic breakdown resistance and low capacity.

  In recent years, various interfaces having a so-called hot swap function have been used as interfaces for connecting a host such as a computer and various peripheral devices. A typical example is a USB (Universal Serial Bus). ) Standard connection terminals (hereinafter referred to as USB connectors). The USB connector is often exposed to the outside. For example, when static electricity is applied to the data signal line from the outside via the USB connector, such as contact discharge of a user, a component connected to the signal line (for example, the USB connector) IC that controls the IC may be destroyed. In order to prevent this, a protection device for preventing electrostatic discharge (ESD) breakdown is connected to the signal line between the USB connector and the protected component. The protective device is, for example, a pn junction diode, and can be made to absorb static electricity by connecting it between the signal line and the ground (see, for example, Patent Document 1).

  FIG. 5 is a schematic cross-sectional view showing an example of a protection device using a conventional bidirectional pn junction diode.

  FIG. 5A shows a protection device 100 using a so-called vertical bidirectional pn junction diode in which a plurality of two pn junctions are formed in the thickness direction of the substrate.

  Specifically, a p-type semiconductor layer 102 is stacked on a p + -type semiconductor substrate 101, a p + -type semiconductor region 103 and an n + -type semiconductor region 104 are provided on the surface of the p-type semiconductor layer 102 from below, and the p + -type semiconductor is again formed on the surface. The area 105 is provided. An insulating film 111 covering the substrate surface is opened to expose the p + type semiconductor region 105 on the outermost surface, a first electrode 106 is formed in contact therewith, and a second electrode 107 is provided on the back surface by vapor deposition of metal or the like.

  The first electrode 106 is fixed to a conductive member (for example, lead of a lead frame) 109a by a thin metal wire 108, and the second electrode 107 is fixed to another conductive member (for example, an island of lead frame) 109b. These are integrally covered and supported by the resin layer 110 to form the protective device 100.

  In the protection device 100, the n-type regions of the first diode D11 including the p + -type semiconductor region 105 and the n-type semiconductor region 104 and the second diode D12 including the n-type semiconductor region 104 and the p + -type semiconductor region 103 are connected in series. One end of each of the conductive members 109a and 109b is led out from the resin layer 110 to become an input terminal IN and a ground terminal GND, for example, between a signal line (not shown) from a USB connector (not shown) and the ground. Connected to.

  FIG. 5B shows a bidirectional pn junction diode in which two pn junction diode chips are connected in an assembly process.

  Specifically, an n + type semiconductor region 202a is provided on the surface of the p + type semiconductor substrate 201a, an insulating film 203a covering the substrate surface is opened to expose the n + type semiconductor region 202a, and a first electrode 206a is formed in contact therewith. The second electrode 207a is provided on the back surface to form a chip of the first diode D21. Further, a chip of the second diode D22 is formed by the p + type semiconductor substrate 201b, the n + type semiconductor region 202b, the insulating film 203b, the first electrode 206b, and the second electrode 207b having the same configuration, and these second electrodes 207a are formed. 207b are fixed on different conductive members (for example, lead frame islands) 209a and 209b. The first electrodes 206a and 206b are electrically connected to each other by a thin metal wire 208 or the like, and these are integrally covered and supported by the resin layer 210, whereby the protection device 200 is configured.

  In the protection device 200, the first diode D21 and the second diode D22 have n-type regions connected in series, and one ends of the conductive members 209a and 209b are led out from the resin layer 210 to the input terminal IN and ground, respectively. The terminal GND is connected, for example, between a signal line (not shown) from a USB connector (not shown) and the ground.

JP 2004-112891 A (page 11, FIG. 6)

  When the protection device 100 for measures against ESD destruction is used connected to a signal line, a predetermined ESD destruction tolerance is maintained, and the total capacity (hereinafter referred to as component capacity) of the protection device 100 as a whole is small. Is desired.

  For example, in the case of an interface using a differential signal such as a USB standard interface, if the parasitic capacitance existing in the data signal line such as a component capacity of the protection device 100 is large, the signal waveform of the differential signal is This is because so-called waveform rounding (distortion) occurs in which the pattern is applied to the violation zone. For this reason, the parasitic capacitance existing in the signal line must be reduced to an allowable value, but the allowable value becomes smaller as the data transfer speed is increased.

  As a specific example, in the USB 2.0 standard high speed mode (maximum data transfer rate: 480 Mbps) with a high data transfer rate, the component capacity must be at most 5 pF, preferably about 3 pF or less.

  On the other hand, the ESD breakdown tolerance when employed in the USB standard interface is required to have a resistance of 8 kV in contact discharge based on the standard of IEC (International Electrotechnical Commission).

  Under such restrictions, if the protection device is configured with only one pn junction diode (for example, the first diode D11 in FIG. 5A) and the component capacitance is reduced to about 3 pF, the ESD breakdown tolerance As a result, it is only about 4 kV to 5 kV, and the necessary ESD breakdown tolerance cannot be obtained.

  Therefore, in the protection device 100, the first diode D11 and the second diode D12 having the same pn junction capacitance are connected in series to form a bidirectional pn junction diode. Thereby, for example, as compared with a protection device using only one pn junction diode (first diode D11), the ESD breakdown tolerance is maintained equivalent, and the junction capacitances of the first diode D11 and the second diode D12 are connected in series. By connecting, the component capacity can be halved, and a low capacity and a high ESD breakdown tolerance can be realized. The same applies to the protection device 200 in FIG.

  However, both of the conventional protection devices 100 and 200 have a large number of manufacturing steps and complicated management in the manufacturing process, so that the cost of the protection device does not go down, and the breakdown voltage (reverse breakdown voltage) is controlled. However, there are problems such as difficulty in the use or limitation in versatility of pressure resistance control.

  More specifically, the protection device 100 in FIG. 5A has an impurity concentration above and below the n + -type semiconductor region 104 having a low impurity concentration in order to realize two vertical (depth direction) pn junctions. The p + type semiconductor regions 103 and 105 are high. That is, in this structure, it is particularly difficult to form the n + type semiconductor region 104 and the p + type semiconductor region 103 by impurity diffusion. In other words, the second diffusion region (p + type semiconductor region 103) serving as a base when forming the first diffusion region (n + type semiconductor region 104) is the first diffusion region (n + type semiconductor region 104) to be formed. It is necessary to lower the impurity concentration, and there is a limit to increasing the impurity concentration of the p + type semiconductor region 103 or reducing the impurity concentration of the n + type semiconductor region 104.

  Since the impurity concentration of the n + -type semiconductor region 104 is a factor that determines the breakdown voltage (reverse breakdown voltage VR) of the protection device 100, not only a pn junction is structurally formed but also a desired breakdown voltage can be obtained. It becomes difficult to control the withstand voltage.

  Further, when the p + type semiconductor region 103 is formed by embedding, it is necessary to ion-implant p + type impurities into the surface of the p type semiconductor layer 102 and further stack an n + type semiconductor layer (epitaxial layer) 104, which is costly. Take it.

  Further, since the p + type semiconductor region 103, the n + type semiconductor region 104, and the p + type semiconductor region 105 are sequentially formed on the p type semiconductor layer 102 which is an epitaxial layer, the cost is increased due to an increase in the number of steps and the number of masks.

  Further, the protection device 200 of FIG. 5B requires chips of two separate pn junction diodes (first diode D21 and second diode D22), and both ends of one metal thin wire 208 are connected to the surfaces thereof. It is necessary to wire-bond to the first electrodes 206a and 206b provided on each of the first electrodes 206a and 206b. For this reason, special management is required for the precision and bonding strength of the wire bond for the connection between the surface electrodes, and the manufacturing process becomes complicated. Furthermore, in this structure, p + type semiconductor substrates 201a and 201b corresponding to the respective withstand voltages must be prepared, and there is a problem that is not universal when a plurality of series withstand voltage products are prepared.

  The present invention has been made in view of such problems, and is provided on a one-conductivity-type semiconductor substrate, a one-conductivity-type semiconductor layer provided on one main surface of the one-conductivity-type semiconductor substrate, and the one-conductivity-type semiconductor layer. A one-conductivity type impurity layer having a higher concentration than the one-conductivity type semiconductor layer; a first reverse-conductivity type impurity region and a second reverse-conductivity type impurity region provided on the surface of the one-conductivity type impurity layer so as to be spaced apart from each other; A first electrode in contact with the first reverse conductivity type impurity region and electrically connected to an input terminal; a second electrode in contact with the second reverse conductivity type impurity region and electrically connected to a ground terminal; It solves by having.

  According to the present invention, the following effects can be obtained.

  First, a protection device using a bidirectional pn junction diode that can reduce the component capacity while maintaining a predetermined ESD breakdown tolerance can be realized with a single chip by a small number of manufacturing processes, and the cost of the protection device can be reduced.

  That is, the protection device includes a p-type semiconductor layer and a higher concentration p + -type impurity layer stacked on a p + -type semiconductor substrate, and a high-concentration first n + -type impurity region and second n + -type impurity region on the surface of the p + -type impurity layer. Are arranged side by side to form a lateral bidirectional pn junction diode in which the main current path is formed in the horizontal direction of the substrate. That is, since two pn junctions can be formed with one mask, the number of masks can be reduced as compared with a manufacturing process of a vertical bidirectional pn junction diode in which a plurality of pn junctions are stacked in the thickness direction of the substrate. Further, compared to a configuration in which two diode chips are formed as bidirectional pn junction diodes by connecting the surface electrodes in the assembly process, special management of wire bond accuracy, bonding strength, and the like is not necessary.

  In the present invention, the breakdown voltage (reverse breakdown voltage VR) can be easily controlled by providing a p-type semiconductor layer having a lower concentration below the p + -type impurity layer serving as a current path. The breakdown voltage of the protection device of the present invention is determined by the impurity concentration of the p + -type impurity layer. By forming this with ion implantation into a low-concentration p-type semiconductor layer, the p + -type impurity layer is formed according to the breakdown voltage. The impurity concentration can be appropriately selected.

  Thereby, the freedom degree of a pressure | voltage resistant design spreads. Further, by using a common p + type semiconductor substrate and p type semiconductor layer substrate and changing the impurity concentration of the p + type impurity layer, the first n + type impurity region, and the second n + type impurity region, a plurality of series withstand voltage products can be obtained. Since it can arrange at low cost, versatility improves.

Furthermore, the component capacity and ESD breakdown tolerance of the protective device can be determined by the shape of the first and second n + type impurity regions, that is, the area and shape of the pn junction surface, and in particular, the distance and area of the first and second n + type impurity regions. By appropriately selecting, a desired ESD breakdown tolerance can be obtained. Specifically, the area of the n + -type impurity regions for example, about 5000 .mu.m ^2, and first, the distance between the opposing surfaces of the second n + -type impurity regions spaced over 140 .mu.m. Thereby, the protection device can realize a component capacity of 3 pF or less and an ESD breakdown tolerance of 10 kV or more. The shape of the first and second n + type impurity regions has an advantage that it can be changed only by changing the pattern of one mask.

  Second, by arranging the first and second n + type impurity regions along the diagonal line of the chip, an increase in chip size can be suppressed even when the distance between the two is 140 μm.

  Third, the shape of the first and second n + -type impurity regions in plan view is a quadrangular shape having a curvature at the corner (rounded quadrangular shape), thereby securing an pn junction area and an electric field at the corner. Can be prevented, and can contribute to the improvement of ESD breakdown tolerance. In order to avoid electric field concentration at corners, a circular shape is generally most effective in plan view. However, when a lateral bidirectional pn junction diode is used as a protection device, the first and second n + type impurity regions are used. It has been found that it is desirable to ensure a large area of the opposing surface of the first and second n + type impurity regions as well as the area (pn junction area with the p + type impurity layer). The shape of the first and second n + type impurity regions in plan view is a rounded quadrangular shape, and one side is arranged opposite to each other, so that the area of the opposing surface is reduced compared to the case where the n + type impurity regions are made circular. It can be secured.

It is (A) sectional drawing explaining the protection apparatus of embodiment of this invention, (B) is an equivalent circuit schematic. It is a top view explaining a protection device of an embodiment of the present invention. It is a circuit schematic diagram which shows the example of a connection of the protection apparatus of embodiment of this invention. It is a circuit schematic diagram which shows the example of a connection of the protection apparatus of embodiment of this invention. It is sectional drawing for demonstrating a prior art.

  Embodiments of the present invention will be described with reference to FIGS.

  FIG. 1 is a view for explaining the structure of the protection device 10, FIG. 1A is a cross-sectional view, and FIG. 1B is an equivalent circuit diagram of the protection device 10.

  The protection device 10 includes a p + type semiconductor substrate 1, a p type semiconductor layer 2, a p + type impurity layer 3, a first n + type impurity region 4, a second n + type impurity region 5, a first electrode 6, and a second electrode. And an electrode 7.

Referring to FIG. 1A, a p + type semiconductor substrate 1 forms a chip of a bidirectional pn junction diode Di, for example, silicon having an impurity concentration of about 4E18 cm ^{−3 to} 5E18 cm ⁻³ and a thickness of about 100 μm to 200 μm. It is a semiconductor substrate.

The p-type semiconductor layer 2 is laminated on one main surface of the p + -type semiconductor substrate 1. For example, the p-type semiconductor layer 2 is an epitaxial layer having an impurity concentration of 1E16 cm ^{−3 to} 2E16 cm ⁻³ and a thickness of about 5 μm to 10 μm.

The p + type impurity layer 3 is an impurity ion implantation region provided on the entire surface of the p type semiconductor layer 2 as an example. The impurity concentration of the p + -type impurity layer 3 (e.g. ^5E17cm about ^-3 ~6E17cm -3) is, the breakdown voltage of the bidirectional pn junction diode (reverse breakdown voltage VR), and ESD (Electrostatic Discharge) breakdown voltage, the protection device 10 of the whole This contributes to determining the total capacity (component capacity). In this embodiment, by providing the low-concentration p-type semiconductor layer 2, the impurity concentration of the p + -type impurity layer 3 can be selected as appropriate, so that the breakdown voltage, ESD breakdown tolerance, and component capacity can be easily controlled.

The first n + type impurity region 4 and the second n + type impurity region 5 are provided on the surface of the p + type impurity layer 3 so as to be separated from each other by a distance L (for example, 140 μm or more). Both impurity concentration as an example is formed by ion implantation and diffusion of n-type impurity of high concentration of 7E19cm- ³ ~8E19cm ^-3. A high-concentration n + -type impurity region 9 is also provided at the outer peripheral end of the p + -type impurity layer 3 serving as a chip end.

  An insulating film (for example, an oxide film) 11 is provided on the surface of the p + type impurity layer 3, and the first n + type impurity region 4 and the second n + type impurity region 5 are opened. On the first type impurity region 4 and the second n + type impurity region 5, a first electrode 6 and a second electrode 7 made of, for example, aluminum (Al) or a metal layer mainly composed of aluminum (Al) are provided. The first electrode 6 is provided in a size and shape substantially overlapping with the first n + type impurity region 4 and is in contact with the first n + type impurity region 4. The second electrode 7 is provided in a size and shape substantially overlapping with the second n + type impurity region 5 and is in contact with the second n + type impurity region 5.

  Another insulating film (for example, a nitride film) 12 is provided on the outermost surface, and the first electrode 6 and the second electrode 7 are opened.

  The first n + type impurity region 4 and the p + type impurity layer 3 form a first pn junction J1 and become the first diode D1. Further, the second n + type impurity region 5 and the p + type impurity layer 3 form a second pn junction J2 and become the second diode D2. As a result, the p-type regions are directly connected to each other, and a current path is formed in the horizontal direction from the first n + -type impurity region 4 to the second n + -type impurity region 5 mainly on the main surface of the p + -type impurity layer 3. A lateral bi-directional pn junction diode Di chip is formed.

  The chip of the bidirectional pn junction diode Di is mounted as a chip size package using the support substrate 26, for example.

  The support substrate 26 is an insulating substrate such as a ceramic substrate, and the first conductive pattern 21, the second conductive pattern 22, and the third conductive pattern 23 are formed on one main surface thereof by, for example, printing a conductive paste or sintering a gold plating layer. Is provided. For example, by forming a plating pattern using thick film printing, it is possible to contribute to downsizing of the package as compared with the case where a chip is mounted on a punching frame (lead frame) by stamping. A bi-directional pn junction diode Di is fixed on the third conductive pattern 23 with a fixing material, the first electrode 6 is connected to the first conductive pattern 21 by connection means such as a thin metal wire 24a, and the second electrode 7 is The second conductive pattern 22 is connected by connecting means such as a thin metal wire 24b.

  The support substrate 26 is provided with through holes TH at positions corresponding to the first conductive pattern 21 and the second conductive pattern 22. The through hole TH penetrates the support substrate 26, and the inside is buried with a conductive material such as tungsten.

  External connection electrodes 27 and 28 corresponding to the first conductive pattern 21 and the second conductive pattern 22 are provided on the other main surface of the support substrate 26 in the same manner as the first conductive pattern 21 and the second conductive pattern 22.

  The external connection electrodes 27 and 28 become the input terminal IN and the ground terminal GND, respectively, the first conductive pattern 21 and the external connection electrode 27 are connected through a through hole TH, and the second conductive pattern 22 and the ground terminal GND are a through hole. Connected via TH.

  In addition, the back surface of the bidirectional pn junction diode Di (p + type semiconductor substrate) 1 is fixed to the third conductive pattern 23 with a fixing material, but the back surface of the chip does not function as an electrode, so the fixing material is a conductive fixing material. Even an insulating fixing material may be used.

  The chip of the bidirectional pn junction diode Di, the thin metal wires 24a and 24b, and the support substrate 26 are integrally covered and supported by the resin layer 25 to constitute the protection device 10. The resin layer 25 constitutes the package outer shape. As the material of the resin layer 25, a thermosetting resin formed by transfer molding or a thermoplastic resin formed by injection molding can be employed. The resin layer 25 may be mixed with a particulate or fibrous filler in order to improve heat dissipation. The four peripheral sides of the package are formed by the cut surfaces of the resin layer 25 and the support substrate 26, the upper surface of the package is formed by the flattened surface of the resin layer 25, and the lower surface of the package is formed by the back surface side of the support substrate 26. The

  The package surface side is the entire surface resin layer 25, and the external connection electrodes 27 and 28 of the support substrate 26 on the back surface side are arranged in a left-right (upper and lower) symmetrical pattern, which makes it difficult to determine the polarity of the electrodes. It is preferable to form a mark on the surface side of the resin layer 25, or to print a mark indicating polarity by printing.

  As described above, the protection device 10 is configured by a lateral bidirectional pn junction diode Di in which the first diode D1 and the second diode D2 are connected in series, both of which are formed under the same conditions (FIG. 1B). ).

  In the present embodiment, for example, the component capacity of the protection device 10 can be halved compared to a protection device using only one pn junction diode having the same formation conditions as the first diode D1. That is, the component capacity is the capacity (total capacity) of the entire protection device 10, and the total capacity is C1 × C2 / (C1 + C2) due to the series connection of the junction capacitors C1 and C2 of the first diode D1 and the second diode D2. It becomes. That is, when the junction capacitances C1 and C2 are the same, the total capacitance can be set to a half of the junction capacitance C1 (C2), and the junction area of the first diode D1 (second diode D2). The total capacity can be reduced as compared with.

  On the other hand, the ESD breakdown tolerance is greatly affected by the pn junction area, but even if the protection device 10 has the first pn junction J1 and the second pn junction J2, these are equivalent. For example, the ESD breakdown tolerance is not halved, and the ESD breakdown tolerance of each pn junction can be maintained. Therefore, the protection device 10 can halve the component capacity while maintaining the same ESD breakdown tolerance as compared with the protection device using only one pn junction diode formed under the same conditions as the first diode D1.

  2A and 2B are plan views for explaining an example of the protection device 10 according to the present embodiment. FIG. 2A is an overall plan view, and FIG. 2B is a bidirectional pn junction that constitutes the protection device 10. It is a top view of diode Di. 1A corresponds to a cross section taken along line aa in FIG.

  Referring to FIG. 2A, p + type impurity layer 3 of bidirectional pn junction diode Di is provided on a p type semiconductor layer not shown here. As an example, the p + -type impurity layer 3 is an impurity ion implantation region. Specifically, a p-type impurity having a higher concentration than the p-type semiconductor layer is ion-implanted without providing a mask over the entire surface of the p-type semiconductor layer. It is formed by diffusion.

The first n + type impurity region 4 and the second n + type impurity region 5 are provided on the surface of the p + type impurity layer 3 so as to be separated from each other. Both are formed by ion implantation and diffusion a dose of ^{1E16cm -2 ~2E16cm} -2 as high concentration n-type impurity as an example (for example, phosphorus (P)), the 1n + -type impurity region 4 and the 2n + -type impurity The distance L between the opposite side surfaces (opposing surfaces) of the region 5 is separated by 140 μm or more. A high-concentration n + -type impurity region 9 is also provided at the outer peripheral end of the p + -type impurity layer 3 serving as a chip end.

  Here, an insulating film (not shown) is provided on the surface of the p + -type impurity layer 3, and the first n + -type impurity region 4 and the second n + -type impurity region 5 are opened as indicated by broken lines. On the first type impurity region 4 and the second n + type impurity region 5, the first electrode 6 and the second electrode 7 having a size substantially overlapping with the first type impurity region 4 and the second n + type impurity region 5 are provided. The first electrode 6 and the second electrode 7 are in contact with the first n + type impurity region 4 and the second n + type impurity region 5, respectively.

  The bidirectional pn junction diode Di is mounted on the third conductive pattern 23 provided in the central portion of the support substrate 26, for example. A rectangular first conductive pattern 21 and second conductive pattern 22 are provided along the short side, for example, at both ends on the short side of the support substrate 26 with the bidirectional pn junction diode Di interposed therebetween. The first conductive pattern 21 and the second conductive pattern 22 are electrically connected to the adjacent first electrode 6 and second electrode 7 by connecting means such as metal thin wires 24a and 24a, respectively.

  The resin layer 25 collectively covers the bidirectional pn junction diode Di, the connection means 24a and 24b, and the support substrate 26 to form the package outer shape. The four side surfaces of the resin layer 25 in plan view coincide with the four side surfaces of the support substrate 26.

  The bidirectional pn junction diode Di will be further described with reference to FIG. In FIG. 2B, the first electrode 6 and the second electrode 7 are omitted.

  The first n + type impurity region 4 and the second n + type impurity region 5 are arranged along one diagonal line of a rectangular p + type impurity layer 3 (same as a p + type semiconductor substrate) in plan view, and have a distance L of 140 μm or more. Spaced apart. More specifically, each of the first n + type impurity region 4 and the second n + type impurity region 5 has a shape in which four corners of a regular tetragon are curved with the same curvature in plan view (hereinafter referred to as a rounded quadrangular shape). The p + type impurity layers 3 are arranged along the diagonal lines so that one side (straight line portion e) of the rounded quadrangular shape is substantially parallel and opposed to each other. Then, the distance L between the opposing one sides is separated by 140 μm or more.

  In this way, the protection device 10 ion-implants impurities into the surface of the p + -type impurity layer 3 through one mask in which the pattern of the first n + -type impurity region 4 and the second n + -type impurity region 5 is formed. Two pn junctions can be formed. Therefore, the number of masks can be reduced as compared with the manufacturing process of a vertical bidirectional pn junction diode (FIG. 5A) in which pn junctions are stacked in the thickness direction of the substrate, and the manufacturing process can be shortened. Compared with the configuration in which two diode chips are formed as bidirectional pn junction diodes (FIG. 5B) by connecting the surface electrodes in the assembly process, special management of wire bond accuracy, bonding strength, etc. Is no longer necessary. With these, the product cost of the protection device 10 can be reduced.

  Furthermore, in this embodiment, a low component capacity and a high ESD breakdown tolerance can be obtained by appropriately selecting the impurity concentration and shape of each of the first n + type impurity region 4, the second n + type impurity region 5 and the p + type impurity layer 3. In addition, the breakdown voltage can be easily controlled. This point will be described below with reference to FIGS. 1 (A) and 2 (B).

  Since the component capacity of the protection device 10 is a junction capacity of the first diode D1 and the second diode D2, the first n + type impurity region 4 is set so that the total capacity obtained by directly connecting these diodes has a desired value satisfying the characteristics. And the impurity concentration of the second n + type impurity region 5, the area and depth thereof (pn junction area with the p + type impurity layer 3), and the impurity concentration of the p + type impurity layer 3 are appropriately selected.

The first n + type impurity region 4 is ion-implanted and diffused with an n-type impurity (for example, phosphorus (P)) having a dose amount of 1E16 cm ^{−2 to} 2E16 cm ⁻² to have an area in a plan view of about 5000 μm ² and a depth. It is formed to about 2 μm to 3 μm. The formation conditions (including the shape in plan view) of the second n + type impurity region 5 are the same as those of the first n + type impurity region 4, and the description is omitted.

The p + -type impurity layer 3 is ion-implanted into the entire surface of the p-type semiconductor layer 2 with a p-type impurity (for example, boron (B)) having a dose amount of 3E14 cm ^{−2 to} 5E14 cm ⁻² , for example, about 3 μm to 5 μm. It is formed by diffusing to a depth of.

  Thereby, the total capacitance of the first diode D1 and the second diode D2, that is, the component capacitance of the protection device 10 is about 2 pF to 3 pF.

  Next, the relationship between the ESD breakdown tolerance and the first joint J1 and the second joint J2 will be described. The pn junction area between the first n + -type impurity region 4 and the p + -type impurity layer 3 and the respective impurity concentrations also determine the ESD breakdown tolerance, and these values are as described above.

  In the present embodiment, in addition to this, by appropriately selecting the shape of the first n + type impurity region 4 and the second n + type impurity region 5 in a plan view and the distance L between them, the high ESD breakdown Can withstand the load.

  Specifically, referring to FIG. 2B, the first n + type impurity region 4 (second n + type impurity region 5) has, for example, a corner r having a curvature of about 5 μm to 15 μm and four sides (straight line e). Each of the lengths is a rounded quadrangular shape with a length of about 60 μm to 80 μm, and is disposed so that one side (straight line portion e) is parallel in plan view. A distance L between opposing sides (opposing surfaces) of the first n + type impurity region 4 and the second n + type impurity region 5 is 140 μm or more. By separating the distance L by 140 μm or more, a sufficient ESD breakdown tolerance can be obtained even with a lateral pn junction diode Di in the lateral direction of a shallow pn junction. Specifically, as described above, although the protection device 10 has a low component capacity of about 2 pF to 3 pF, an ESD breakdown tolerance of about 11 kV to 13 kV can be realized.

  According to experiments, it was found that when the distance L between the first n + type impurity region 4 and the second n + type impurity region 5 exceeds 140 μm, the ESD breakdown tolerance becomes almost constant. An increase in the distance L between the first n + type impurity region 4 and the second n + type impurity region 5 directly leads to an increase in chip size. Therefore, if the ESD breakdown tolerance does not change, a minimum distance L of about 140 μm is sufficient.

  Further, in the present embodiment, the first n + type impurity region 4 and the second n + type impurity region 5 are arranged along one diagonal line of the chip in plan view. More specifically, each side (straight line portion e) of the first n + type impurity region 4 and the second n + type impurity region 5 is arranged so as to be substantially parallel to the diagonal of the chip. Thereby, even if the predetermined distance L is secured, an increase in chip size can be avoided.

  In addition, by making the shape of the first n + type impurity region 4 into a rounded quadrangular shape with curved corners r, it is possible to avoid electric field concentration at the corners r and improve ESD breakdown tolerance. In order to avoid electric field concentration at the corner r, a circular shape is generally most effective in plan view, but in the present embodiment, not only the pn junction area but also the first n + type impurity region 4 and the first It has been found that securing a large area of the opposing surface of the 2n + type impurity region 5 is effective in improving the ESD breakdown resistance. The first n + type impurity region 4 and the second n + type impurity region 5 are rounded quadrangular, and one side (straight line portion e) is arranged to face each other, so that both sides have a circular shape, compared to the case where both are made circular. An area can be secured.

  Referring to FIG. 1A again, the first n + type impurity region 4 (second n + type impurity region 5) has an impurity concentration gradient in which the impurity concentration on the surface is the highest and decreases in the depth direction. This can also contribute to the improvement of the ESD breakdown tolerance. As an example, the first n + type impurity region 4 is formed by diffusing with a short heat treatment time (for example, about 90 minutes) after ion implantation of an n type impurity.

  Furthermore, the breakdown voltage (reverse breakdown voltage VR) of the protection device 10 is determined by the impurity concentration of the p + -type impurity layer 3. In the present embodiment, the breakdown voltage can be easily controlled by providing the p-type semiconductor layer 2 having a lower concentration below the p + -type impurity layer 3.

  Since a commercially available general p + type semiconductor substrate 1 has an impurity concentration that is too high as it is, in this embodiment, a low concentration p type semiconductor layer 2 is provided on the p + type semiconductor substrate 1. Then, a p-type impurity layer 3 is provided by implanting and diffusing a p-type impurity having a desired impurity concentration in the p-type semiconductor layer 2.

Impurities above the p-type semiconductor layer 2 are provided by providing the p-type semiconductor layer 2 on the p + -type semiconductor substrate 1 at a sufficiently lower concentration than the p + -type impurity layer 3 (for example, an impurity concentration of about 1E16 cm ^{−3 to} 2E16 cm ⁻³ ) The p + type impurity layer 3 can be formed by freely adjusting the concentration. That is, the allowable range of the impurity concentration that can be selected for the p + -type impurity layer 3 that constitutes the first diode D1 and the second diode D2 and determines the breakdown voltage is expanded. In particular, as compared with the case where a plurality of pn junctions are formed vertically as shown in FIG. 5A, the impurity concentration can be easily controlled, and the degree of freedom in withstand voltage design is increased. Further, the p + type semiconductor substrate 1 and the p type semiconductor layer 2 are used as a common substrate, and the impurity concentration of the p + type impurity layer 3, the first n + type impurity region 4 and the second n + type impurity region 5 is changed to form a series. Since multiple pressure-resistant products can be prepared at low cost, versatility is improved.

  Since the impurity concentration of the p + -type impurity layer 3 affects the ESD breakdown tolerance, it can be said that this control is equally easy.

  In the above-described embodiment, the case where it is mounted on a chip size package using a support substrate has been described as an example. However, the mounting method of the bidirectional pn junction diode is not limited to this, and for example, it may be mounted using a lead frame.

  Explaining this without illustration, a lead frame in which leads and islands are formed is prepared by stamping a conductive material such as copper, and a bidirectional pn junction diode is fixed to the islands. The first electrode and the second electrode are connected to a lead serving as an input terminal and a lead serving as a ground terminal by a thin metal wire, respectively. A part of each lead, island and chip are integrally covered and supported by a resin layer. The other end of the lead is led out from the resin layer. Thereby, a protective device is configured.

  3 and 4 are schematic diagrams showing an example of connection of the protection device 10, and shows a case where the protection device 10 is used by being connected to the signal line of the USB connector 31.

  3A and 3B show the case where the host terminal 35 and the client terminal 36 are both connected via the cable 30 and the USB connector 31, and the USB connector 31 is connected to the USB socket 32 on the host terminal 35 side. The example of a connection of the protection apparatus 10 in the case of connecting is shown. FIG. 3A shows a case where the host terminal 35 is a computer, for example, and the client terminal 36 is a peripheral device such as a printer, an image scanner, or an external hard disk. FIG. 3B shows a case where the device corresponding to the host terminal 35 is a mobile device such as a mobile phone, and the device corresponding to the client terminal 36 is the charger.

  3A and 3B, the USB standard interface includes an IC (hereinafter, USB controller 33) for controlling the USB connector 31 on the host terminal 35 side.

  The USB socket 32 into which the USB connector 31 is inserted and removed is provided, for example, on a motherboard (not shown) of the host terminal 35. A wiring 38 serving as a signal line is provided on the motherboard, and the wiring 38 is connected to a USB controller 33 that controls the USB connector 31.

  Then, in order to prevent static electricity charged to the user when the user contacts the USB connector 31 from being applied to the USB controller 33 via the wiring 38, the data signal between the USB connector 31 and the USB controller 33 is used. The protective device 10 is connected between the signal line (wiring 38) and the ground.

  Specifically, the USB connector 31 has, for example, four pins: a Vbus signal pin for supplying power, a + data (D +) signal pin, a -data (D-) signal pin, and a GND signal pin. The protective device 10 is connected between the wiring 38 connected to the D + signal pin between the USB socket 32 and the USB controller 33 and the ground, and between the wiring 38 connected to the D− signal pin and the ground (or either). Connected).

  The protection device 10 may be connected to the client terminal 36 in FIG. For example, as shown in FIG. 3A, when the USB connector 31 ′ is also provided at the other end of the cable 30 on the client terminal 36 side and the client terminal 36 also has the USB controller 33 ′, the client terminal 36 The protective device 10 is connected between the ground and the wiring 38 ′ connected to the D + signal pin and the D− signal pin between the USB socket 32 ′ (USB connector 31 ′) and the USB controller 33 ′.

  Further, FIG. 4 shows a case where the protection device 10 is connected to the USB memory 40. The USB memory 40 is an external auxiliary storage device (flash memory) having a USB connector 31. Generally, the USB connector 31 is provided directly on a housing 41 in which a flash memory chip is accommodated without using a cable. Say what you are.

  Specifically, the flash memory chip 43, the USB controller 33, and the like are integrated on the mother board 42 and stored in the housing 41. A USB connector 31 is provided at one end of the housing 41, and four pins (Vbus signal pin, D + signal pin, D− signal pin, GND signal pin) of the USB connector 31 are connected to the USB via the wiring 38. Connect to the controller 33.

  The protective device 10 is connected between (or any of) the wiring 38 connected to the D + signal pin and the ground, and between the wiring 38 connected to the D− signal pin and the ground.

  The USB standard interface as shown in FIGS. 3 and 4 uses a differential transmission system in which signals in opposite phases (D + signal, D− signal) are sent to two signal lines forming a pair. The shape of the eye pattern (waveform amplitude and period), which is these signal waveforms, is defined by the standard so as to be a pattern that falls within a predetermined allowable range for each data transfer speed. In other words, if the eye pattern waveform is distorted (rounded) due to an increase in the capacity added to the data signal line, a data transfer error will occur. It is standardized to have an eye pattern waveform that does not reach the zone.

  The violation zone becomes smaller (severe) as the data transfer rate becomes higher, and accordingly, the upper limit of the capacity allowed on the data signal line becomes stricter.

  For the USB standard interface, ESD breakdown tolerance is also defined based on the IEC (International Electrotechnical Commission) standard.

  As described above, when, for example, a pn junction diode is employed as a protection device for the ESD destruction countermeasure of the USB standard interface, this condition is satisfied only by forming an n-type impurity region on the p + type semiconductor substrate and configuring the pn junction diode. You cannot get a protective device. That is, for example, a commercially available p + -type semiconductor substrate has a high impurity concentration, and even if an n-type impurity region is provided in this to form a pn junction diode, the component capacitance cannot be reduced to 5 pF or less, for example. In other words, the (bidirectional) pn junction diode serving as the USB interface protection device must be formed under appropriate conditions so as to satisfy the predetermined conditions required for that purpose.

  In the present embodiment, in a protection device that protects an interface having a so-called hot swap function represented by a USB standard interface from electrostatic breakdown, with the increase in data transfer speed while ensuring a desired ESD breakdown tolerance. Therefore, the required capacity can be reduced.

  That is, the shape of the first n + type impurity region 4 and the second n type impurity region 5 constituting the protection device 10 (bidirectional pn junction diode Di), the distance L separating them, the concentration of these impurities, and the p + type impurity By forming the impurity concentration of the layer 3 under the conditions described in the above embodiment, it is possible to obtain a component capacity and a sufficient ESD breakdown tolerance that are allowed as a protection device for the interface.

  Specifically, in the protection device used in the USB 2.0 high-speed mode (maximum data transfer rate: 480 Mbps), the component capacity is 5 pF or less (preferably 3 pF) or less, and the ESD breakdown tolerance is 8 kV or more. The protection device 10 according to the present embodiment can realize a component capacity of 2 pF to 3 pF and an ESD breakdown tolerance of about 11 kV to 13 kV.

  Further, by forming two pn junctions in the lateral direction, the manufacturing process can be prevented from becoming complicated and complicated, and the cost can be reduced. Since the impurity concentration of the p + -type impurity layer 3 can be easily controlled, the withstand voltage can be controlled. It becomes easy.

  The formation conditions of the bidirectional pn junction diode Di (the shape of the first n + type impurity region 4 and the second n type impurity region 5, the distance L and the impurity concentration separating them, the impurity concentration of the p + type impurity layer 3) are appropriately selected. By doing so, not limited to the above example, low speed mode (maximum data transfer rate: 1.5 Mbps), full speed mode (maximum data transfer rate: 12 Mbps), USB 3.0 standard super speed mode (maximum data transfer rate) : 5 Gbps) or the like.

  Furthermore, although the case where it employ | adopts as an interface of a USB specification was demonstrated to an example, it is not restricted to this, For example, it can employ | adopt also as an interface of other standards, such as HDMI (High Definition Multimedia Interface) standard.

1 p + type semiconductor substrate 2 p type semiconductor layer 3 p + type impurity layer 4 first n + type impurity region 5 second n + type impurity region 6 first electrode 7 second electrode 10 protection device 21 first lead 22 second lead 31 USB connector 33 USB controller

Claims (8)

One conductivity type semiconductor substrate;
A one conductivity type semiconductor layer provided on one main surface of the one conductivity type semiconductor substrate;
One conductivity type impurity layer provided on the one conductivity type semiconductor layer and having a higher concentration than the one conductivity type semiconductor layer;
A first reverse conductivity type impurity region and a second reverse conductivity type impurity region provided on the surface of the one conductivity type impurity layer so as to be spaced apart from each other;
A first electrode in contact with the first opposite conductivity type impurity region and electrically connected to an input terminal;
A second electrode that contacts the second opposite conductivity type impurity region and is electrically connected to a ground terminal;
A protective device comprising:   2. The protection device according to claim 1, wherein the first reverse conductivity type impurity region and the second reverse conductivity type impurity region are disposed along one diagonal line of the one conductivity type semiconductor substrate.   3. The protection device according to claim 1, wherein the first reverse conductivity type impurity region and the second reverse conductivity type impurity region are separated by a distance of 140 μm or more.   4. The plane according to claim 1, wherein the first reverse conductivity type impurity region and the second reverse conductivity type impurity region have a quadrangular shape with curved corners in plan view. 5. Protective device.   5. The protection device according to claim 4, wherein the first reverse conductivity type impurity region and the second reverse conductivity type impurity region are disposed so that one side of the quadrangular shape faces each other.   The first reverse conductivity type impurity region and the second reverse conductivity type impurity region have an impurity concentration gradient in which the impurity concentration on the surface is the highest and decreases along the depth direction. Item 6. The protective device according to any one of Items 5 to 6.   7. The protective device according to claim 1, wherein the one conductivity type impurity layer is an impurity ion implantation region provided on the entire surface of the one conductivity type semiconductor layer.   A first conductive member to which the first electrode is electrically connected, a second conductive member to which the second electrode is electrically connected, and a resin layer that covers and supports them. The protection device according to any one of claims 1 to 7.

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