JP2012059081A - Reference voltage generation circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a circuit which generates a highly accurate reference voltage without being affected by variation of elements.SOLUTION: The circuit includes: means which causes currents having different current densities to flow to semiconductor junctions; means which charges a voltage proportional to a difference voltage to a parallel connection of a plurality of capacities; means which connects the capacities in series to generate a voltage; means which charges a voltages of the semiconductor junctions to the series connection of the plurality of capacities when necessary; means which connects the capacities in parallel to generate a voltage proportional to the voltage of the semiconductor junctions; and means which adds this voltage and the former generated voltage. The difference voltage is a difference between a voltage which is generated by causing a constant current to flow to a parallel connection of a first number of semiconductor junctions or constant current sources out of the plurality of semiconductor junctions or a plurality of constant current sources and a voltage generated by connecting a second number of semiconductor junctions or constant current sources in parallel, and if necessary, a plurality of combinations are successively selected when the first number and the second number are selected.

Description

The present invention relates to a reference voltage generation circuit, and more particularly to a reference voltage generation circuit having a reference voltage proportional to absolute temperature and an arbitrary temperature coefficient including zero using the reference voltage.

Conventionally, a reference voltage generation circuit called a band gap reference is known. This is because, for example, a voltage generated in a silicon semiconductor PN junction (hereinafter referred to as “junction”) has a negative temperature coefficient of about 0.7 V and about −2 mV / ° C. at room temperature, and a pair in which the current density flowing in the junction is changed. In this circuit, the potential difference becomes a positive temperature coefficient proportional to the absolute temperature, and is amplified by a predetermined resistance ratio and added to the junction voltage to cancel the temperature coefficient.

Patent Publication 2002-304224 "Voltage Generation Circuit and Voltage Generation Method" Inventor Mitsutoshi Sugawara Japanese Patent Laid-Open No. 02-015093 “Constant Voltage Circuit” Inventor Mitsutoshi Sugawara USP 6,384,586 "Regulated Low-Voltage Generation Circuit" inventor MitSutoShiSugawara

FIG. 7 shows a conventional CMOS type band gap reference circuit invented by the present inventor described in Patent Document 1, which can be manufactured by a CMOS process and has a temperature coefficient lower than a silicon band gap voltage of about 1.3 V. This is a reference voltage generation circuit capable of generating a substantially zero reference voltage.

The principle and operation will be briefly described below.
The relationship of the voltage VD1 generated at the junction D1 by the current source I1 is I1 = Is × exp (q × VD1 ÷ (k × T))
Given in. Here, Is is a saturation current determined by the size of the process and the junction, q is an electron charge, k is a Boltzmann coefficient, and T is an absolute temperature. Similarly, the voltage VD2 generated at the junction D2 by the current source I2 is I2 = m × Is × exp (q × VD2 ÷ (k × T)).
Given in. Here, Is is almost equal on the integrated circuit, and m is a current density ratio. From these two formulas, VD1−VD2 = (k × T ÷ q) × ln (m × I1 ÷ I2)
Thus, a voltage proportional to the absolute temperature is obtained. For example, assuming that the area of the junction D2 is 10 times that of D1 and I1 = I2, V1−V2≈60 mV at room temperature T = 300 ° K.

By applying negative feedback to the differential amplifier A1 so that the input voltage difference approaches zero, both ends of the resistor R1 become equal to VD1-VD2. Therefore, according to Ohm's law, I2 = (VD1−VD2) ÷ R1
It becomes.
On the other hand, when the voltage VD3 generated at the junction D3 by the bias current source I4 is divided by the resistors R2 and R3 and a current I3 that is n times the current I2 is caused to flow there, the output voltage Vout = VD3 × R3 ÷ by the Thevenin theorem. (R2 + R3) + I3 × (R2 // R3)
Is obtained. Here, // indicates resistance parallel, and R2 // R3≡R2 × R3 ÷ (R2 + R3).
Vout = V3 * R3 / (R2 + R3) + R2 * R3 / (R2 + R3) / R1 * n * k * T * ln (m) / q
It becomes.
The first item has a negative temperature characteristic that is proportional to the temperature characteristic of the junction, and the second item has a positive temperature coefficient that is proportional to the absolute temperature. Therefore, by selecting R1, R2, R3, m appropriately, A voltage having an arbitrary temperature coefficient of zero or positive can be obtained.
Industrially, zero is frequently used and may be used for purposes such as correcting positive and negative temperature coefficients.

For example, if the area of the junction D2 is 10 times that of D1, and I1 = I2 = I3, R2 = R3 = 10 × R1, then m = 10 and n = 1, and the first temperature is T = 300 ° K. The item is half of the junction voltage, which is about 350 mV and becomes -1 mV / ° C, and the second term is about 300 mV and becomes +1 mV / ° C. In total, the temperature coefficient cancels at about 650 mV, and can be made almost zero.

When making this circuit into an integrated circuit, sufficient consideration is given to process variations, but there are slight variations in the saturation current Is and the area ratio m of the junctions D1 and D2, the offset of the differential amplifier, the current ratio of the current source, the resistance ratio, etc. Therefore, even if the 10 mV range was worked out, an error of about mV and temperature fluctuation had to be allowed. In addition, the offset of the differential amplifier has a temperature coefficient, and the resistance is easily affected by stress when encapsulated in a package, so there is a limit to increasing the accuracy of the output voltage and temperature coefficient.
Not only this circuit but almost all band gap reference circuits have similar methods, and thus have similar problems.

By applying the present invention, a desired reference voltage proportional to the absolute temperature can be generated without depending on the resistance ratio, and a desired temperature characteristic including zero can be obtained in combination with a voltage proportional to the voltage generated at the junction. A reference voltage can be generated. It is also possible to reduce the influence of element variation.
As an example of the present invention, a reference voltage generation circuit having a temperature coefficient of zero and an output of about 0.4 V can be realized even with a power supply voltage of only 0.5 V.

The present invention does not use a differential amplifier or a resistance ratio, but instead uses a capacitance ratio with relatively good relative accuracy on an integrated circuit, thereby creating a voltage depending on the current density difference of the junction. If necessary, a voltage proportional to the voltage of the junction is also realized using a capacitance ratio with relatively good relative accuracy.
In the case of higher accuracy, elements that produce a current density difference are sequentially switched and averaged over time to improve accuracy.

When listing the reference voltage generating means of the present invention,
1. A voltage proportional to a difference voltage when currents having different current densities are supplied to the junction is first charged in a parallel connection of a plurality of capacitors, and then a voltage is generated by connecting the capacitors to a series connection.
2. If necessary, the junction voltage is first charged into a series connection of a plurality of capacitors, and then the capacitance is switched to a parallel connection to generate a voltage proportional to the junction voltage. Means for adding to the voltage.
3. First, a first number (for example, 10) of a plurality of junctions are connected in parallel, and a voltage generated by flowing a constant current is charged into a capacitor. Next, there is provided means for creating a differential voltage between a voltage generated by switching the junction to a second number (for example, one) in parallel connection and a voltage charged in the capacitor.
Alternatively, first, among the plurality of constant current sources, a first number (for example, one) is connected in parallel, and a voltage generated by flowing a constant current is charged to the capacitor. Next, there is provided means for creating a differential voltage between a voltage generated by switching the number of constant current sources (for example, 10) and a voltage charged in the capacitor.
4). Further, in the above 3. When selecting at least one of the numbers (for example, one), there may be provided means for preparing a combination of a plurality of different elements with the same number and sequentially switching them to obtain an average value over time.
All or part of the above applies.

FIG. 1 shows a first embodiment of the present invention.
The relationship of the voltage VD1 generated at the junction D0 by the current source I0 is I0 = Is × exp (q × VD1 ÷ (k × T))
Given in. Here, Is is a saturation current determined by the size of the process and the junction, q is an electron charge, k is a Boltzmann coefficient, and T is an absolute temperature. Similarly, the relationship of the voltage VD2 generated in the parallel connection of the junctions D1 to D10 by the current source I1 is I1 = 10 × Is × exp (q × VD2 ÷ (k × T)).
Given in. Here, on the integrated circuit, Is is substantially equal for each junction of the same size. From these two formulas, VD1−VD2 = (k × T ÷ q) × ln (10 × I0 ÷ I1)
Thus, a voltage proportional to the absolute temperature T is obtained.
Here, if the individual junction areas are made equal, and I0 = I1, then V1−V2≈60 mV at room temperature T = 300 ° K. The process up to this point is the same as the conventional example.

Here, the switch means S30a to S39a and S30b to S39b are closed, the capacitors C20 to C29 are connected in parallel, and the difference voltage between the VD1 and VD2 is charged at both ends thereof. Next, the switch means S30a to S39a and S31b to S39b are opened, the switch means S40 to S49 are closed, and the capacitors C20 to C29 are switched to series connection. S30b may remain closed. When the capacitance values of C20 to C29 are equal, a voltage of 10 × (VD1−VD2) appears at both ends of the series connection of C20 to 29 due to the charge conservation law. This voltage is a voltage proportional to the absolute temperature at about 600 mV and having a temperature characteristic of +2 mV / ° C. at room temperature, as in the conventional example. This voltage is added to the voltage VD2 (approximately 0.7 V) generated in parallel connection of the junctions D1 to D10 having a temperature characteristic of about −2 mV / ° C. via S30b, and is output as the reference voltage Vout. At about 1.3 V, the reference voltage has zero temperature characteristics.
It is very common to use a MOS transistor as the switch means.
Further, by changing at least one capacitance value of the capacitors C20 to C29 with another, it is possible to change to a magnification including a fraction other than 10 times. Alternatively, by changing the ratio of the constant current sources I0 and I1, it is possible to change the magnification to include a fraction other than 10 times.

Since this circuit does not use a resistance element, it is not affected by variations in resistance or fluctuations in resistance stress. In general, the variation in capacitance on an integrated circuit is less than that of a resistor and is not affected by stress. Therefore, the circuit of FIG. 1 is a reference voltage circuit with less variation than a conventional bandgap reference circuit using resistors.

FIG. 2 shows a second embodiment of the present invention.
It is widely known that the PNP transistors Q0 to Q8 each have a collector and a base connected to each other and operate as an equivalent diode in which an emitter current corresponding to a forward voltage at the junction between the base and the emitter flows. In addition, a PNP transistor having a P-type substrate as a collector, an N-type well as a base, and a P-type diffusion region as an emitter can be formed without additional steps in a normal MOS process, and this is generally used. However, it is not limited to that.
The relationship of the voltage VD1 generated at the base-emitter junction Q0 by the current source I0 is I0 = Is × exp (q × VD1 ÷ (k × T))
Given in.
Here, Is is a saturation current determined by the size of the process and the junction, q is an electron charge, k is a Boltzmann coefficient, and T is an absolute temperature. Similarly, the relationship between the voltage VD2 generated in parallel connection of the junctions Q1 to Q7 by the current source I1 is I1 = 8 × Is × exp (q × VD2 ÷ (k × T)).
Given in. The voltage VD3 generated in the parallel connection of the junction Q8 by the current source I2 is I2 = Is × exp (q × VD3 ÷ (k × T))
Given in. Here, on the integrated circuit, Is is substantially equal for each junction of the same size. From the first and second expressions, VD1−VD2 = (k × T ÷ q) × ln (8 × I0 ÷ I1)
Thus, a voltage proportional to the absolute temperature T is obtained. Here, if the respective junction areas are made equal, and I0 = I1, the normal temperature T = 300 ° K, and V1−V2≈54 mV.

Here, the switch means S30a to S33a and S30b to S33b are closed, the capacitors C20 to C23 are connected in parallel, and the difference voltage between the VD1 and VD2 is charged at both ends thereof.
Next, the switch means S30a to S33a and S31b to S33b are opened, the switch means S40 to S43 are closed, and the capacitors C20 to C23 are switched to series connection. When the capacitance values of C20 to C23 are equal, 216 mV, which is a voltage of 4 × (VD1−VD2), appears at both ends of the series connection of C20 to 23 due to the charge conservation law. Since this voltage is proportional to the absolute temperature, it is 300 ° K and 0.72 mV / ° C.
On the other hand, it is assumed that the forward voltage of the junction generated by the equivalent diode Q8 and the current source I2 is about 720 mV, for example, and has a temperature characteristic of −2.1 mV / ° C. at room temperature. Here, the switch means S20c, S21c, S22c, and S22b are closed, the capacitors C10, C11, and C12 are connected in series, and the voltage generated in the equivalent diode Q8 is charged at both ends thereof. Next, the switch means S20c, S21c, S22c are opened, the switch means S20a to S22a and S20b to S22b are closed, and the capacitors C10 to C12 are switched to parallel connection. When the capacitance values of C10 to C12 are equal, approximately 240 mV, which is a forward voltage of approximately 720 mV ÷ 3 of the equivalent diode Q8, appears at both ends of the parallel connection of C10 to C12 due to the law of conservation of charge. This temperature coefficient is about -0.7 mV / ° C. When this voltage is added to the voltage at both ends of the series connection of C20 to 23, a very small voltage of 456 mV and a temperature coefficient of 0.02 mV / ° C. can be produced.
By slightly shifting either the current ratio of I0, I1, or I2 or the capacitance ratio of C10 to C12 and C20 to C23, the temperature coefficient can be made just zero.
When the load capacitance Co is repeatedly and repeatedly charged with the added voltage, the Co voltage, that is, the output Vout is eventually charged up to the added voltage and becomes constant at the voltage. That is, almost a DC voltage can be obtained.

Further, in this embodiment, a booster circuit including a capacitor Ci and switch means S01 to S04 is provided. In this operation, first, the switch means S01 and S04 are closed to charge the capacitor Ci to the power supply voltage VDD. Next, the switch means S01 and S04 are opened, the switch means S02 and S03 are closed, and the charging voltage of the capacitor Ci is added to the power supply voltage VDD itself. As a result, the common ends of the constant current sources I0, I1, and I2 become approximately twice the voltage of the power supply voltage VDD. For example, even if VDD = 0.5V, the common end of the current sources I0, I1, and I2 is about 1V from this circuit, which is sufficient to drive an equivalent diode (about 0.7V).
The capacitors C10 to C12 and C20 to C23 are charged when the capacitor Ci is driving the current sources I0, I1, and I2, and the capacitors C10 to C12 and C20 to C23 are charged with the capacitor Co when the capacitor Ci is charged. It is efficient to switch alternately to charge.

Since this circuit does not use a resistance element, it is not affected by variations in resistance or fluctuations in resistance stress. In general, the variation in capacitance on an integrated circuit is less than that of a resistor and is not affected by stress. Therefore, the circuit of FIG. 1 is a reference voltage circuit with less variation than a conventional bandgap reference circuit using resistors.
In particular, in the second embodiment, a constant voltage such as zero temperature coefficient lower than the original band gap regulator value of about 1.3 V can be generated with a power supply of only 0.5 V, and almost a DC voltage can be obtained. There is an effect.

FIG. 3 shows a third embodiment of the present invention.
First, the constant current I0 is closed and the switching means S10 to S19 are closed to flow in the parallel connection of the junctions D0 to D9. At this time, the voltage VD at both ends of the junction is closed and the switching means S20 is closed to charge the relatively large capacitor C10. Next, S20 is opened, and S11 to S19 are opened while the switch means S10 is closed. When D0 to D9 and S10 to S19 are configured with the same size, the current density of the junction D0 becomes 10 times, and the voltage of the junction D0 increases by 60 mV as described above.
The switch means S30a to S39a and S30b to S39b are closed, and the difference voltage between the voltage at the junction D0 and the voltage charged in the capacitor C10 is charged into the parallel connection of the capacitors C20 to C29. Next, S30a to S39a and S31b to S39b are opened, switch means S40 to S49 and switches S20 and S30b are closed, and capacitors C20 to C29 are connected in series. Then, when C20 to C29 are equal, the voltage applied to the series connection of the capacitors C20 to C29 is 10 times the voltage applied to each. The output Vout is the sum of this voltage and the voltage when the constant current I0 flows through the junctions D0 to D9.

When the current flowing out from Vout is negligible, by repeating the above switch operation, the charging voltage of the capacitor C10 converges to the voltage when the constant current I0 flows through the junctions D0 to D9, and the charging voltage of the capacitors C20 to C29. Converges to the voltage when the constant current I0 flows through the junctions D0 to D9, and the output voltage Vout converges to the sum of these voltages when S49 is closed.
The former has a temperature characteristic of about −2 mV / ° C. at about 700 mV at a room temperature of 300 ° K. The latter has a temperature characteristic of about +2 mV / ° C. because it is proportional to the absolute temperature at about 600 mV at a room temperature of 300 ° K. The sum is about 1 .3V cancels temperature coefficient. As a result, it is possible to obtain the same voltage and temperature coefficient output voltage Vout as a circuit called a conventional bandgap reference.
In the above description, the value of the capacitance C10 is assumed to be relatively large, but if it is small, there may be an effect depending on the capacity ratio. However, this effect can be included in the calculation and used.

Since this circuit does not use a resistance element, it is not affected by variations in resistance or resistance stress fluctuations. In general, the variation in capacitance on an integrated circuit is less than that of a resistor and is not affected by stress. Therefore, the circuit of FIG. 1 is a reference voltage circuit with less variation than a conventional bandgap reference circuit using resistors.

In the fourth embodiment of the present invention, the control of each switch means in FIG. 3 is switched according to the table shown in FIG. The horizontal one row in FIG. 4 shows the setting at each clock, and is executed sequentially from 0 to 19 and repeated from 0 again.
Here, the clocks 1 and 2 are exactly the procedures described in the third embodiment. Since all the even clock operations are the same as those in the third embodiment, the description thereof is omitted.
In clock 3, S11 is turned on instead of switch means S10. Then, the capacitors C20 to C29 are charged in parallel with the voltage difference between the voltage of the capacitor C10 storing the voltage generated in the parallel connection of the junctions D0 to D9 charged by the clock 2 and the voltage of the junction D1.
Similarly, S12 is sequentially shifted in the clock 5, S13 is shifted in the clock 7, and so on.
By doing so, the junction selected by the odd-numbered clock sequentially changes. Since the voltage generated at the junctions D0 to D9 slightly changes due to the variation of the elements, the output Vout also varies with each clock accordingly. When a smoothing capacitor is connected to the output Vout (not shown) and repeatedly charged repeatedly, the output voltage converges to the average value of Vout. This is obtained by multiplying the difference voltage between the voltage generated at the parallel connection of the junctions D0 to D9 at the even clock and the average value of the voltages generated at the junctions D0 to D9 at the odd clock by the number of capacitors C20 to C29. This is equivalent to the smoothing voltage of the output voltage Vout.

With this circuit, the smoothing voltage of the output voltage Vout can be obtained with extremely high accuracy without being affected by variations in the individual junctions D0 to D9.

FIG. 5 shows a fifth embodiment of the present invention.
In FIG. 3, since the switch means S10 to S19 are inserted in series with the junctions D0 to D9, the voltage drop caused by the current I0 when the switch means is turned on can be ignored with respect to the voltage generated at the junction. A switch means with low on-resistance was required.
In FIG. 5, the switch means S10a to S16a for supplying the current I0 and the switch means S10b to S16b for charging the capacitance with the voltage generated at the junctions D0 to D6 are separated. By doing so, the influence of the voltage drop generated in the switch means S10a to S16a can be ignored.
The contents described in the first to fourth embodiments will be applied mutatis mutandis. In FIG. 5, the potential difference (kT / q) ln (7) = 50 mV generated at a junction current density ratio of 1: 7 is expressed as parallel / capacitance of capacitors C20 to C25 including switch means S30a to S35a, S30b to S35b, and S40 to S45. About 300 mV multiplied by 6 in the series switching circuit, and the voltage generated in parallel at the junctions D0 to D6 by the switch means S20a, S21a, S20b, S21b, S20c, and S21c is halved by parallel / series switching of the capacitors C10 and C11. About 650 mV, which is the sum of 350 mV, is the output voltage Vout. Since the former is proportional to the absolute temperature, the former is +1 mV / ° C. at a room temperature of 300 ° K. The latter is about −1 mV / ° C., canceling out, and the temperature change of the output voltage Vout becomes zero.
As in the fourth embodiment, the switching means S10a to S16a and S10b to S16b are switched for each clock, and one of the junctions D0 to D6 is sequentially selected and smoothed and averaged by the capacitor Co. This can also reduce the variation.

In this circuit, as in the other embodiments, in addition to being able to accurately generate a voltage with a temperature coefficient lower than the band gap voltage of silicon, the switch means can be reduced in size and the number of junctions and capacitors can be reduced. effective.

FIG. 6 shows a sixth embodiment of the present invention.
In the present embodiment, as means for changing the current density of Q showing the equivalent diode characteristics, the number of constant current sources I00 to I17 is selected from 18 cases and 1 case by switch means S100 to S117. 600 mV obtained by multiplying the potential difference (kT / q) ln (18) = 75 mV generated at the junction Q by a parallel / series switching circuit of capacitors C20 to C27 including switch means S30a to S37a, S30b to S37b, and S40 to S47; About 1.3 V, which is the sum of the voltage generated at the junction Q, is the output voltage Vout.
Since the former is proportional to the absolute temperature, the former is +2 mV / ° C. at a room temperature of 300 ° K. The latter is about −2 mV / ° C., which cancels out and the temperature change of the output voltage Vout becomes zero.
As in the fourth embodiment, the switching means S100 to S117 are switched for each clock so as to select, for example, all parallel when the clock is an even number and one by one when the clock is an odd number, and are connected after the terminal Vout. Variations can be reduced by averaging with a smoothing circuit.
Although not particularly illustrated, consider a case where I17 is set to another 0.8 times for fine adjustment of the temperature characteristics. In this case, I00 to I16 should be switched every odd number of clocks.

In addition to the effects shown in other embodiments, switching of the junction current density is easy and the potential difference is large, so that the circuit is more resistant to variations.

Since each circuit of the present invention can be manufactured by a general CMOS process and does not depend on variations of individual elements, it is useful for the LSI industry that a bandgap regulator with higher accuracy than before can be realized. .
In particular, it should be noted that a bandgap regulator that can operate even with a power supply voltage of only 0.5 V can be realized, and can cope with a power supply voltage drop due to future miniaturization.

In addition, this invention is not limited to what was illustrated as an Example, It is also possible to implement combining arbitrarily.
In each embodiment, the number of junctions and capacitors is selected so that the temperature coefficient that is often used is zero, but by changing these numbers as necessary, a reference voltage having a desired positive or negative temperature coefficient is generated. A circuit can be constructed.

In the first embodiment, a highly accurate reference voltage generation circuit having a temperature coefficient of about 1.3 V and a zero temperature coefficient In the second embodiment, a reference voltage generating circuit having a high accuracy of 456 mV and a temperature coefficient of 0.02 mV / ° C. In the third embodiment, a highly accurate reference voltage generating circuit having a temperature coefficient of about 1.3 V and a zero temperature coefficient. In the fourth embodiment, the operation procedure of the switch means of the circuit of FIG. 3 for further improving the accuracy is described. In the fifth embodiment, a highly accurate reference voltage generation circuit having a temperature coefficient of about 650 mV and a zero temperature coefficient In the sixth embodiment, a highly accurate reference voltage generating circuit having a temperature coefficient of about 1.3 V and a zero temperature coefficient The circuit diagram described in Patent Document 1 in the conventional example

D0 to D10 Semiconductor junction Q, Q0 to Q8 Transistors I0 to I2, I4, I00 to I17 Current sources Ci, C10 to C12, C20 to C29, Co capacitors S01 to S04, S10 to S19, S20 Switch means S10a to S16a, S10b S16b Switch means S20a to S22a, S20b to S22b Switch means S20c to S22c Switch means S30a to S39a, S30b to S39b Switch means S40 to S49, S100 to S117 Switch means R1 to R3 Resistor A1 Differential amplifier VDD Power supply GND Ground Vout Output Terminal

Claims (7)

In a reference voltage generation circuit that uses a voltage proportional to a difference voltage when currents of different current densities are passed through a semiconductor junction as at least part of the reference voltage,
A first capacity group comprising a plurality of capacity;
A first switch means group for connecting the capacitor in parallel with the differential voltage;
And a second switch means group for switching the first capacity group to the serial connection in the previous period,
A reference voltage generating circuit, characterized in that a voltage generated in series connection of the first capacity group in the previous period is said “at least part of output”.
In a reference voltage generation circuit comprising a sum of a voltage proportional to a differential voltage when a current having a different current density flows through a semiconductor junction and a voltage proportional to a forward voltage generated in the semiconductor junction, or
A first capacity group comprising a plurality of capacity;
A first switch means group for connecting the first capacity group in parallel to the differential voltage;
And a second switch means group for switching the first capacity group to the serial connection in the previous period,
A reference voltage generating circuit comprising a sum of a voltage generated in series connection of the first capacity group in the previous period and a "voltage proportional to a voltage generated in the or another semiconductor junction". In the reference voltage generation circuit of the previous section,
A second capacity group consisting of a plurality of capacity;
A third group of switch means for connecting the second group of capacitors in series with a voltage generated at the or another semiconductor junction;
Add a fourth switch means group to switch the second capacity group of the previous period to parallel connection,
A reference voltage generating circuit characterized in that the parallel voltage of the capacitances at both ends of the fourth switch means is the “voltage proportional to the voltage generated at the semiconductor junction” in the preceding paragraph. In the reference voltage generation circuit of the previous three items,
Multiple semiconductor junctions;
In the first constant current source and the first constant current source,
A fifth switch means group for selectively connecting the semiconductor junctions in first and second numbers in parallel;
A third capacity for charging the voltage of the first number of semiconductor junctions via such switch means group;
Switching the fifth switch means group to generate a voltage of the second number of semiconductor junctions;
A differential voltage between the voltage and the voltage of the third capacitor is referred to as “differential voltage when a current having a different current density is passed through the semiconductor junction” in each item.
In a reference voltage generation circuit consisting of a sum of a voltage proportional to a difference voltage when a current having a different current density is passed through a semiconductor junction and a voltage proportional to a voltage generated in the semiconductor junction or in another semiconductor junction,
Multiple semiconductor junctions;
In the first constant current source and the first constant current source,
A fifth switch means group for selectively connecting the semiconductor junctions in first and second numbers in parallel;
A third capacity for charging the voltage of the first number of semiconductor junctions via such switch means group;
Switching the fifth switch means group to generate a voltage of the second number of semiconductor junctions;
A reference voltage generating circuit, wherein a difference voltage between the voltage and the voltage of the third capacitor is referred to as the “difference voltage when a current having a different current density is passed through the semiconductor junction”.
In a reference voltage generation circuit consisting of a sum of a voltage proportional to a difference voltage when a current having a different current density is passed through a semiconductor junction and a voltage proportional to a voltage generated in the semiconductor junction or in another semiconductor junction,
Semiconductor junctions,
A plurality of constant current sources;
A sixth switch means group for selectively connecting a plurality of such constant current sources in parallel to the semiconductor junction in a third and a fourth number;
A fourth capacity for charging the voltage of the semiconductor junction when the third number of constant current sources are applied via the switch means group;
Switching the sixth switch means group to generate a voltage of the semiconductor junction when the fourth number of constant current sources are applied;
A reference voltage generating circuit characterized in that a difference voltage between the voltage and the voltage of the fourth capacitor is referred to as the “difference voltage when a current having a different current density is passed through the semiconductor junction”. In the reference voltage generation circuit of the previous three items,
A reference voltage generation circuit characterized in that at least one of the number selection is prepared by preparing a plurality of types of combinations for selecting different elements with the same number, and selecting them sequentially to average them over time.

Images