JP2012058875A - Storage processing device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a storage processing device that properly suppresses standby power.SOLUTION: An NAS 10, in a hardware configuration, includes a PHY chip 102 for processing a physical layer of an OSI reference model and an SOC 104 for processing a data link layer of the OSI reference model and for processing up to any layer of a network layer or higher of the OSI reference model. If all or a part of the received bit string obtained from a signal received by the PHY chip 102 corresponds to a reference bit string which is the bit string of a packet for interlocking with a PC power in a standby state, power is supplied to other parts of the SOC 104 and the NAS 10 so that the NAS 10 is shifted to the working state.

Description

  The present invention relates to a storage processing apparatus that can be connected to a storage medium and can be connected to another device via a communication network.

  In recent years, a storage processing device called NAS (Network Attached Storage) is becoming widespread. The NAS can connect a plurality of hard disks, and can store various content data such as video and audio on the hard disks. When the NAS receives a request for content data from the terminal device via the network, the NAS transmits the requested content data to the terminal device via the network. In the terminal device, the received content data is reproduced.

  By the way, in recent years, it has been demanded to suppress standby power of various electric devices from the viewpoint of global warming countermeasures. For example, in the European Community, there is a directive on environmentally friendly design called the EuP directive.

  In order to suppress standby power, for example, the data processing device described in Patent Literature 1 is again in a power saving state when the data received after the power saving state is canceled is a predetermined type of data. Migrate to

JP 2006-25212 A

  Since NAS is also an electric device, suppression of standby power is required. However, according to various experiments by the inventors, standby power cannot always be appropriately suppressed with the current NAS circuit configuration.

  In view of the above problems, an object of the present invention is to provide a storage processing device that appropriately suppresses standby power.

  In order to solve the above-described problems, the present invention has the following features.

  A feature of the present invention is that a storage processing device (NAS10) that can be connected to a storage medium (hard disk 122, hard disk 124) and can be connected to another device (personal computer 20) via a communication network (communication network 60). ), The physical layer device (PHY chip 102) for processing the physical layer of the OSI reference model, the data link layer of the OSI reference model, and the OSI reference A communication control device (SOC 104) that performs processing up to one of the layers above the network layer of the model and the power from the power supply device for the communication control according to the configuration of data received by the physical layer device A power control device (power supply) that selectively performs control to be supplied to the device and control not to be supplied And summarized in that a control unit 101).

  In the hardware configuration, such a storage processing device performs processing of the physical layer device of the OSI reference model and the data link layer of the OSI reference model, and more than the network layer of the OSI reference model. A communication control device that performs processing up to any one of the layers is provided separately, and the communication control device is configured according to the configuration of data received by the physical layer device that is supplied with power from the power supply and operates. The standby power can be suppressed by selectively performing the control for supplying power to the control and the control for not supplying power.

  A feature of the present invention is that, while power is supplied to the physical layer device and the power control device does not supply power from the power supply device to the communication control device, The gist of the invention is that, when the data received by the layer device matches the predetermined data, the power control device switches to control for supplying power to the communication control device.

  A feature of the present invention is that, when the received data matches predetermined data, the physical layer device transmits a request signal for requesting power supply to the power control device, and the power control device When the request signal is received, the gist is to switch from control not to supply power from the power supply apparatus to the communication control device to control to supply power to the communication control device.

  A feature of the present invention is that, when the received physical data is data requesting that the power of the storage processing device be interlocked with the power of the other device, the physical layer device supplies data to the power control device. The gist is to transmit a request signal for requesting power supply.

  A feature of the present invention is that the power control device is based on any one of information from an external device and an operation state of a switch device (switch 107-1, switch 107-2) included in the storage processing device. The gist is to determine whether to perform control to supply power from the power supply device to the communication control device and control to not supply according to the configuration of data received by the physical layer device. .

  According to the present invention, standby power can be appropriately suppressed.

1 is an overall schematic configuration diagram of a content distribution system according to an embodiment of the present invention. It is a block diagram of NAS concerning embodiment of this invention. It is a flowchart which shows operation | movement of the power supply control unit which concerns on embodiment of this invention. It is a sequence diagram which shows the 1st operation | movement of NAS which concerns on embodiment of this invention. It is a sequence diagram which shows the 2nd operation | movement of NAS which concerns on embodiment of this invention.

  Next, an embodiment of the present invention will be described with reference to the drawings. Specifically, the configuration of the content distribution system, the configuration of the NAS, the operation of the NAS, the operation / effect, and other embodiments will be described. In the description of the drawings in the following embodiments, the same or similar parts are denoted by the same or similar reference numerals.

(1) Configuration of Content Distribution System FIG. 1 is an overall schematic configuration diagram of a content distribution system. The content distribution system shown in FIG. 1 includes a NAS (Network Attached Storage) 10 as a storage processing device, a personal computer (PC) 20 as another device, and a communication constituted by a LAN cable that connects the NAS 10 and the PC 20. And a network 60.

  In the content distribution system of the present embodiment, the NAS 10 stores content data such as images and sounds, and distributes them to the PC 20 via the communication network 60. The PC 20 reproduces the received content data.

(2) Configuration of NAS FIG. 2 is a configuration diagram of the NAS 10. As shown in FIG. 2, the NAS 10 connects a hard disk 122 and a hard disk 124 that are storage media. The NAS 10 includes a power control unit 101, a PHY chip 102, an SOC (System On a Chip) 104, a main power supply device 106, a switch 107-1, a switch 107-2, and a bus 120. The

  The power supply control unit 101, the PHY chip 102, the SOC 104, the switch 107-1 and the switch 107-2 are connected to the bus 120.

  The power supply control unit 101 is a semiconductor chip that controls the main power supply device 106. The PHY chip 102 is a semiconductor chip that performs processing of the physical layer of the OSI reference model. The PHY chip 102 includes a register 103.

  The SOC 104 is a semiconductor chip that performs processing of the data link layer of the OSI reference model and processing up to any layer above the network layer. In the present embodiment, the SOC 104 performs processing from the data link layer to the application layer. The SOC 104 is obtained by integrating a microprocessor, a memory, a hard disk 122 which is a peripheral device, an interface unit with the hard disk 124, and the like on one semiconductor chip. The SOC 104 connects a hard disk 122 and a hard disk 124 that store content data.

  The switch 107-1 is an operation unit operated by a user to turn on / off the power supply of the NAS 10. The switch 107-2 is an operation unit that is operated by the user to set a power supply determination mode to be described later.

  The power supply control unit 101 is configured by a single semiconductor chip or a plurality of semiconductor chips. The power supply control unit 101 operates by being supplied with power from the main power supply device 106 regardless of whether the NAS 10 is in a standby state or an operating state.

Here, the standby state means that power is supplied to the SOC 104 after a power outlet (not shown) in the NAS 10 is connected to a household power source and the power supply device 108 can supply power to each part in the NAS 10. The operating state means a state after power is supplied to the SOC 104.

  When a power outlet (not shown) in the NAS 10 is connected to a household power source and the NAS 10 enters a standby state, the power control unit 101 can detect the states of the switch 107-1 and the switch 107-2.

  Moreover, the power supply control unit 101 sets a mode (power supply determination mode) for determining whether or not it is necessary to supply power to the SOC 104, in other words, whether or not it is necessary to shift from the standby state to the operating state. Here, the power supply determination mode is a mode in which the PHY chip 102 determines whether or not the received bit string matches the reference bit string (first mode), and the power supply control unit 101 determines whether the switch 107-1 is on or off. Mode (second mode).

  Specifically, the SOC 104 previously receives mode setting information from an external device (for example, a personal computer connected via the Internet) in an operating state. Further, the SOC 104 transmits the received mode setting information to the power supply control unit 101. Upon receiving the mode setting information from the SOC 104, the power supply control unit 101 sets the power supply determination mode to the first mode or the second mode based on the mode setting information, and supplies the information on the set power supply determination mode to the power supply. This is stored in a register (not shown) in the control unit 101.

  After that, when a power outlet (not shown) in the NAS 10 is disconnected from the household power source and connected to the household power source again, and the NAS 10 enters a standby state, the power control unit 101 has set the power supply determination mode. Determine whether or not. Specifically, the power supply control unit 101 determines that the power supply determination mode has been set when information on the power supply determination mode set in the register in the power supply control unit 101 is stored.

  On the other hand, when the power supply determination mode has not been set, the power supply control unit 101 sets the power supply determination mode to the first based on a signal (status signal) transmitted from the switch 107-2 indicating the state of the switch. Set to either mode or second mode. For example, when the switch 107-2 is a changeover switch between the first mode and the second mode, if the switch 107-2 is in a state of setting the first mode, the first mode is set and the second mode is set. Is set to the second mode. For example, when the switch 107-2 is a push button, the first mode is set if the pressing time is less than a predetermined time, and the second mode is set if the pressing time is longer than the predetermined time.

  As described above, after the power supply control unit 101 selects the first mode or the second mode in the standby state of the NAS 10, the following processing is performed.

(Processing in the first mode)
The power supply control unit 101 transmits a signal (first power supply control signal) for supplying power to the PHY chip 102 to the main power supply device 106. The main power supply device 106 supplies power to the PHY chip 102 in response to the first power supply control signal. The PHY chip 102 is operated by electric power supplied from the main power supply device 106.

  Next, the power supply control unit 101 transmits a signal (first mode signal) indicating that the power supply determination mode is the first mode to the PHY chip 102.

  The PHY chip 102 that has received the first mode signal monitors the signal from the PC 20 transmitted via the communication network 60. When the PHY chip 102 receives a signal from the PC 20, the PHY chip 102 performs analog / digital conversion or the like on the signal to obtain a bit string. Further, the PHY chip 102 collates the acquired bit string (received bit string) with the reference bit string stored in the register 103, and determines whether or not all or a part of the received bit string matches the reference bit string. Here, the reference bit string is a bit string of a packet (PC power supply interlocking packet) transmitted from the PC 20 to the NAS 10 in order to turn on / off the power of the NAS 10 in conjunction with the power of the PC 20.

  When all or part of the received bit string matches the reference bit string, it is necessary to link the power supply of the NAS 10 to the power supply of the PC 20 and shift the NAS 10 to the operating state. Therefore, the PHY chip 102 is an interrupt signal that requests the power supply control unit 101 to supply power to the other units of the NAS 10 (components other than the PHY chip 102 and the SOC 104) via the bus 120. A certain power supply request signal is transmitted.

  When receiving the power supply request signal from the PHY chip 102, the power supply control unit 101 performs the following processing. That is, the power supply control unit 101 continues power supply to the PHY chip 102 and causes the SOC 104 and other parts of the NAS 10 to supply power in order to cause the NAS 10 to transition from the standby state to the operating state. (Second power supply control signal) is transmitted to the main power supply device 106. The main power supply device 106 continues power supply to the PHY chip 102 in response to the second power supply control signal, and starts power supply to the SOC 104 and other parts of the NAS 10.

  The other parts of the NAS 10 are operated by power supplied from the main power supply device 106.

(Processing in the second mode)
The power supply control unit 101 transmits a signal (first power supply control signal) for supplying power to the PHY chip 102 to the main power supply device 106. The main power supply device 106 supplies power to the PHY chip 102 in response to the first power supply control signal. The PHY chip 102 is operated by electric power supplied from the main power supply device 106. Unlike the case of the first mode, the PHY chip 102 does not receive the first mode signal thereafter. Therefore, the PHY chip 102 does not perform the process in the first mode described above.

  On the other hand, when receiving a status signal from the switch 107-1, the power supply control unit 101 performs the following processing. That is, the power supply control unit 101 determines whether the switch 107-1 is in an on state or an off state based on the status signal. When the switch 107-1 is in the ON state, the power supply control unit 101 continues to supply power to the PHY chip 102 in order to make the NAS 10 transition from the standby state to the operating state, and the SOC 104 and other parts of the NAS 10 A signal (second power supply control signal) for supplying power to each unit is transmitted to the main power supply device 106. The main power supply device 106 continues power supply to the PHY chip 102 in response to the second power supply control signal, and starts power supply to the SOC 104 and other parts of the NAS 10.

  The other parts of the SOC 104 and the NAS 10 are operated by electric power supplied from the main power supply device 106.

  When the NAS 10 is in an operating state, the PHY chip 102 performs the following processing. That is, the PHY chip 102 receives a signal from the PC 20 via the communication network 60. Next, the PHY chip 102 performs analog / digital conversion or the like on the received signal, and acquires an Ethernet (registered trademark) frame that is a communication frame of the data link layer. The PHY chip 102 transmits the acquired Ethernet (registered trademark) frame to the SOC 104 via the bus 120. The PHY chip 102 receives an Ethernet (registered trademark) frame from the SOC 104 via the bus 120. The PHY chip 102 performs digital / analog conversion or the like on the received Ethernet (registered trademark) frame and acquires a signal. Further, the PHY chip 102 transmits the acquired signal to the PC 20 via the communication network 60.

  Further, when the NAS 10 is in an operating state, the SOC 104 performs the following processing. That is, when the SOC 104 receives an Ethernet (registered trademark) frame from the PHY chip 102, the SOC 104 performs processing beyond the data link layer and acquires content data. Further, the SOC 104 performs processing for storing the acquired content data in the hard disk 122 or the hard disk 124. In addition, when the NAS 10 is in an operating state, the SOC 104 reads content data from the hard disk 122 or the hard disk 124 and performs processing beyond the data link layer to acquire an Ethernet (registered trademark) frame. Further, the SOC 104 transmits the acquired Ethernet (registered trademark) frame to the PHY chip 102 via the bus 120.

(3) NAS Operation FIG. 3 is a flowchart showing an operation of setting the power supply determination mode by the power supply control unit 101.

  In step S11, when the NAS 10 enters a standby state, the power supply control unit 101 determines whether or not the power supply determination mode based on the mode setting information from the external device has been set.

  When the power supply determination mode based on the mode setting information from the external device has already been set, the process proceeds to the operation shown in FIG. 4 or the operation shown in FIG. On the other hand, when the power supply determination mode based on the mode setting information from the external device has not been set, in step S12, the power supply control unit 101 determines the power supply determination mode based on the mode setting operation for the switch 107-2 by the user. Set. Thereafter, the operation proceeds to the operation shown in FIG. 4 or the operation shown in FIG.

  FIG. 4 is a sequence diagram showing the operation of the NAS 10 in the first mode.

  In step S <b> 101 and step S <b> 102, the power supply control unit 101 performs control to supply power to the PHY chip 102 and transmits a first power supply control signal to the main power supply device 106. The main power supply device 106 receives the first power supply control signal.

  In step S103, the main power supply apparatus 106 supplies power to the PHY chip 102 in response to receiving the first power supply control signal. In step S <b> 104, the PHY chip 102 is operated by electric power supplied from the main power supply device 106.

  In step S105, the power supply control unit 101 transmits a first mode signal. The PHY chip 102 receives the first mode signal.

  In step S <b> 106, the PHY chip 102 determines whether a signal from the PC 20 has been received via the communication network 60. When a signal from the PC 20 is received, in step S107, the PHY chip 102 acquires a bit string (received bit string) from the received signal. In step S108, the PHY chip 102 collates the received bit string with the reference bit string, and determines whether all or a part of the received bit string matches the reference bit string.

  If all or part of the received bit string does not match the reference bit string, the operations after step S106 are repeated.

  On the other hand, if all or part of the received bit string matches the reference bit string, in step S109, the PHY chip 102 transmits a signal (power supply request signal) for requesting power to be supplied to the other units of the NAS 10. . The power control unit 101 receives a power supply request signal.

  In step S110 and step S111, the power supply control unit 101 performs control to supply power to the SOC 104 and other units of the NAS 10. The second power supply control signal is transmitted to the main power supply device 106. The main power supply device 106 receives the second power supply control signal.

  In step S <b> 112, the main power supply apparatus 106 supplies power to the SOC 104 and other units of the NAS 10 in response to the reception of the second power supply control signal. In step S <b> 113, the SOC 104 is operated by electric power supplied from the main power supply device 106. Further, the other units of the NAS 10 are also operated by the power supplied from the main power supply device 106. Furthermore, the PHY chip 102 continues to operate.

  FIG. 4 is a sequence diagram showing the operation of the NAS 10 in the second mode.

  In step S201 and step S202, the power supply control unit 101 performs control to supply power to the PHY chip 102, and transmits a first power supply control signal to the main power supply device 106. The main power supply device 106 receives the first power supply control signal.

  In step S203, the main power supply device 106 supplies power to the PHY chip 102 in response to receiving the first power supply control signal. In step S <b> 204, the PHY chip 102 is operated by electric power supplied from the main power supply device 106.

  In step S205, the switch 107-1 transmits a status signal in response to an operation by the user. The power supply control unit 101 receives a status signal.

  In step S206, the power supply control unit 101 determines whether the switch 107-1 is on based on the status signal. When the switch 107-1 is off, the operation after the transmission / reception of the status signal in step S205 is repeated.

  On the other hand, if the switch 107-1 is on, in step S207, the power supply control unit 101 performs control to supply power to the SOC 104 and other units of the NAS 10.

  In step S <b> 208, the power supply control unit 101 transmits a second power supply control signal to the main power supply device 106. The main power supply device 106 receives the second power supply control signal.

  In step S209, the main power supply apparatus 106 supplies power to the SOC 104 and other units of the NAS 10 in response to receiving the second power control signal. In step S <b> 210, the SOC 104 is operated by electric power supplied from the main power supply device 106. Further, the other units of the NAS 10 are also operated by the power supplied from the main power supply device 106. Furthermore, the PHY chip 102 continues to operate.

(4) Operation / Effect In the content distribution system of the present embodiment, the NAS 10 performs processing of the physical layer of the OSI reference model and processing of the data link layer of the OSI reference model in the hardware configuration. In addition, an SOC 104 that performs processing up to any layer above the network layer of the OSI reference model is provided separately.

  Furthermore, in the NAS 10, when the standby state is entered, power is supplied to the PHY chip 102, while power is not supplied to the SOC 104, and only physical layer processing is performed. Accordingly, it is possible to suppress power consumption (standby power) in the standby state.

  In the NAS 10, in the standby state, when the whole or a part of the received bit string obtained from the signal received by the operating PHY chip 102 matches the reference bit string that is the bit string of the PC power supply interlocking packet. In order to shift the NAS 10 to the operating state, power is supplied to the SOC 104 and other parts of the NAS 10. Therefore, the NAS 10 can be appropriately shifted to the operating state by interlocking the power supply of the NAS 10 with the power supply of the PC 20 while suppressing standby power.

  In the NAS 10, when the switch 107-1 is in an on state in the standby state, the PHY chip 102, the SOC 104, and the Power is supplied to the other units of the NAS 10. Therefore, the NAS 10 can appropriately transition to the operating state while suppressing standby power.

(5) Other Embodiments As described above, the present invention has been described according to the embodiment. However, it should not be understood that the description and drawings constituting a part of this disclosure limit the present invention. From this disclosure, various alternative embodiments, examples and operational techniques will be apparent to those skilled in the art.

  In the above-described embodiment, the switch 107-2 is a switch operated for setting the power supply determination mode. However, the switch 107-2 is not provided and the switch 107-1 is set for setting the power supply determination mode. It may be a switch operated for this purpose.

  In FIG. 3, the setting of the power supply determination mode based on the mode setting information has priority over the setting of the power supply determination mode based on the mode setting operation, but the setting of the power supply determination mode based on the mode setting operation is the mode. The setting may be prioritized over the setting of the power supply determination mode based on the setting information.

  In the embodiment described above, a hard disk is connected to the NAS 10, but the storage medium to be connected is not limited to this. For example, a storage medium such as an SSD (Solid State Drive), a flash memory, or an SD card may be connected.

  In the above-described embodiment, the communication network 60 is configured by a LAN cable. However, the communication network 60 may be configured by a wireless LAN, or may be configured by another communication cable such as a USB cable.

  Thus, it should be understood that the present invention includes various embodiments and the like not described herein. Therefore, the present invention is limited only by the invention specifying matters in the scope of claims reasonable from this disclosure.

  DESCRIPTION OF SYMBOLS 10 ... NAS, 20 ... PC, 60 ... Communication network, 101 ... Power supply control unit, 102 ... PHY chip, 103 ... Register, 104 ... SOC, 106 ... Main power supply device, 107-1, 107-2 ... Switch, 120 ... Bus, 122, 124 ... Hard disk

Claims (5)

A storage processing device that can be connected to a storage medium and can be connected to another device via a communication network,
A power supply;
A physical layer device for processing the physical layer of the OSI reference model;
A communication control device that performs processing of the data link layer of the OSI reference model and performs processing up to any one of the layers above the network layer of the OSI reference model;
A power control device that selectively performs control to supply power from the power supply apparatus to the communication control device and control to not supply according to the configuration of data received by the physical layer device;
A storage processing device.   Data received by the physical layer device while power is supplied to the physical layer device and the power control device does not supply power from the power supply device to the communication control device. The storage processing device according to claim 1, wherein the power supply control device switches to control for supplying power to the communication control device when the data and predetermined data match. The physical layer device transmits a request signal for requesting power supply to the power control device when the received data and predetermined data match,
The power supply control device, when receiving the request signal, switches from control not to supply power from the power supply device to the communication control device to control to supply power to the communication control device. The storage processing device described.   The physical layer device is a request for requesting power supply to the power control device when the received data is data requesting to link the power of the storage processing device to the power of the other device. The storage processing device according to claim 3, which transmits a signal.   The power control device is configured to select the power supply according to the configuration of data received by the physical layer device based on either information from an external device or an operation state of a switch device included in the storage processing device. The storage processing device according to claim 1, wherein it is determined whether to perform control to supply power from the device to the communication control device and control to not supply power.

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