JP2012053939A - Semiconductor memory, and method for setting test mode for the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor memory which does not stop operation during a system test by solving the following problems: in a toggle type test mode setting circuit in which a setting code changes in a stepwise fashion each time a pulse is input, a setting code that is not originally designed by the semiconductor memory is sometimes input during the change and the semiconductor memory sometimes stops operation during the system test.SOLUTION: A holding circuit is provided to the test mode setting circuit and, by inputting a start signal from the outside of the semiconductor memory, the output from a counter is held.

Description

  The present invention relates to a semiconductor memory device and a test mode setting method thereof. In particular, the present invention relates to a semiconductor memory device including a toggle type test mode setting circuit.

  The operation mode of the semiconductor memory device can be broadly classified into a normal operation mode for performing a read / write operation on the original memory cell array and a test mode for the purpose of testing the semiconductor memory device. The test mode of the semiconductor memory device is used for various purposes. For example, in the design stage, it is used to check whether the prototyped semiconductor memory device operates as defined in the specification. Alternatively, when the semiconductor memory device is returned as a defective product from the market, it may be used to elucidate the cause of the defect.

  Here, in Patent Document 1, an overvoltage signal is applied to a specific terminal, a flip-flop is provided in a test circuit, and a transition is made to a test mode when an overvoltage signal and a specific logic level condition are met. A technique for preventing switching from the normal operation mode to the test mode is disclosed.

JP-A-5-288806

  The following analysis has been made from the viewpoint of the present invention.

  As described above, the semiconductor memory device has a normal operation mode and a test mode, and the test mode is used in various ways depending on the purpose. For example, in the tester evaluation using the test mode, it is tested what behavior the semiconductor memory device exhibits when operated under specific conditions.

  On the other hand, in the system test using the test mode, it is tested whether the semiconductor memory device operates correctly within a predetermined specification range when operated under actual use conditions.

  In this way, the purpose is different even in the same test mode, so for tester evaluation, the semiconductor memory device may be entered into the test mode and operated after setting to the target test mode. It cannot be operated after presetting to the target test mode. That is, in the system test, it is required to change the internal mode of the semiconductor memory device by changing the test mode while the semiconductor memory device is operating, and to confirm the behavior with respect to the change.

  Here, the control of the operation mode during the normal operation of the semiconductor memory device is performed by decoding a command given from the outside by a combination of a plurality of control signals. In normal operation, the test mode can be set using a test command based on a combination that is not used. Further, when there are many kinds of setting values in the test mode used for the test, it is possible to use a toggle type test mode setting circuit which can be set to another setting value every time a test command is given.

  In a semiconductor memory device equipped with a toggle type test mode setting circuit, the test mode is changed to a test mode, and when a specific code is input to the command decoder, the code is converted into a pulse and output to the test mode setting circuit. . In the toggle type test mode setting circuit, each time this pulse is received, it is converted into a setting code, a different test code is output, and a different setting value is set. The toggle test mode setting circuit is used in a test mode that requires stepwise adjustment, and the connection between the command decoder and the test mode setting circuit can be set in various ways with a single signal. There is an advantage that a wide range of tests can be performed without increasing the number. FIG. 4 shows an example of a toggle type test mode setting circuit.

  In such a toggle test mode setting circuit, the setting code changes step by step each time a pulse is input, but the setting is not intended to be used in the test in the middle of the change. A desired set value may be set via the value. In such a case, the semiconductor memory device cannot operate normally with a setting value that passes along the way, and the operation of the semiconductor memory device may stop during the system test.

  As described above, there are restrictions on the execution of the test mode in the system test of the semiconductor memory device, a test with a high degree of freedom cannot be performed, and it becomes a cause that hinders improvement of the degree of completeness of design and early detection of the cause of failure. Yes.

  As described above, there are problems to be solved in the prior art.

  In one aspect of the present invention, a semiconductor memory device including a toggle type test mode setting circuit that does not output a setting code other than the target in a test mode and a test mode setting method thereof are desired.

  According to a first aspect of the present invention, a memory cell array including a plurality of memory cells that can be read / write accessed from the outside based on a command and an address given from the outside, and the command given from the outside A command control unit that decodes and controls the read / write access; a counter that counts the number of times the command control unit decodes the first test command; and when the command control unit decodes the second test command There is provided a semiconductor memory device comprising: a holding circuit that outputs a test mode setting code based on the count value of the counter.

  According to a second aspect of the present invention, there is provided a synchronous semiconductor memory device that executes a read / write operation based on a command given from outside in synchronization with a clock signal, and decodes the command given from outside. A command control unit that controls the operation inside the semiconductor memory device, a test mode setting circuit, and a test execution circuit that executes a test inside the semiconductor memory device based on a test mode set by the test mode setting circuit. The test mode setting circuit is based on a counter that counts the number of times the command control unit has decoded the first test command, and based on a count value of the counter when the command control unit decodes the second test command. And a holding circuit that outputs a setting code for setting to a predetermined test mode. It is.

  According to the third aspect of the present invention, a read / write operation is controlled based on a command given from the outside, and a counter that counts the number of times the first test command is given as a test mode setting circuit; A test mode setting method for a semiconductor memory device, comprising: a holding circuit that outputs a count value of the counter as a test code when a test command of 2 is given, in accordance with a test mode to be set in advance A first step of giving the first test command to the semiconductor memory device a predetermined number of times and setting the counter to a predetermined count value; and a second step after the first step to the semiconductor memory device. A test mode setting method for a semiconductor memory device is provided in which a test command is given and the semiconductor memory device is set to a predetermined test mode.

  According to each aspect of the present invention, there is provided a semiconductor memory device including a toggle type test mode setting circuit that can be set to a target setting value without passing through a setting value other than the target at the time of setting the test mode.

It is a figure for demonstrating the outline | summary of this invention. 1 is an example of an overall configuration of a semiconductor memory device having a test mode setting circuit according to an embodiment of the present invention. FIG. 3 is a diagram illustrating an example of an internal configuration of the power supply circuit of FIG. 2. 1 is a block diagram showing an internal configuration of a test mode setting circuit according to a first embodiment of the present invention. FIG. 5 is a diagram showing a change in a setting code output from a test mode setting circuit in FIG. 4. FIG. 5 is a diagram illustrating an output level of an internal voltage VDD2 output from a power supply circuit in accordance with a setting code output from a test mode setting circuit of FIG. FIG. 4 is a diagram illustrating an example of an internal configuration of a test mode setting circuit in FIG. 3. It is a figure showing the output level of internal voltage VDD2 output from a power supply circuit according to the setting code output from the test mode setting circuit of FIG. It is a figure which shows the change of the setting code output from the test mode setting circuit in FIG.

  First, the outline of the present invention will be described with reference to FIG. In the toggle test mode setting circuit, test mode information is input using a mode setting signal for designating an operation mode of the semiconductor memory device. The mode setting signal is decoded as a first test command in the command control unit, and a pulse signal is output to the test mode setting circuit. A test command is input a predetermined number of times according to the setting value to be set, the pulse signal output each time is counted by a counter, and the output is used as a setting code to set a desired setting value. Thereafter, the test mode is executed in the test execution circuit connected to the test mode setting circuit.

  However, as described above, in the toggle-type test mode setting circuit, the setting code (test code) changes step by step every time a pulse signal is input. A setting code that has not been set may be output and an unexpected setting value may be set. Therefore, a holding circuit for holding the setting code output from the counter in response to the start signal is provided in the test mode setting circuit. The start signal is output when the command control unit decodes the second test command, and the test mode setting circuit does not output the setting code to the outside until the start signal is activated. In other words, the setting code is not changed only by inputting a pulse signal to the test mode setting circuit, and the setting code is made effective in response to the start signal.

  As a result, it is possible to provide a test mode setting circuit for a semiconductor memory device that does not output a setting code other than the intended one when setting the test mode.

[First Embodiment]
Next, a first embodiment of the present invention will be described in detail with reference to the drawings. First, a basic description of a semiconductor memory device having a test mode setting circuit according to an embodiment of the present invention will be given. FIG. 2 is a block diagram showing the overall configuration of the semiconductor memory device.

  The semiconductor memory device shown in FIG. 2 includes a clock generation circuit 10, a command control unit 20, a memory cell access unit 30, a memory cell array 40, and a power supply circuit 50.

  The clock generation circuit 10 receives the clock signal CK and supplies an internal clock signal to the command control unit 20, the memory cell access unit 30, and the like. Also, the internal clock signal is generated when the externally applied clock enable signal CKE is high level, and the generation of the internal clock signal is stopped when the clock enable signal CKE is low level.

  The command control unit 20 controls the entire operation of the semiconductor memory device such as a read / write operation based on a command signal CMD given from the outside. The command control unit 20 has a command decoder that decodes the command signal CMD, and generates an internal command signal according to the external command. The internal command signal is a read / write operation instruction or the like for the memory cell access unit 30. The command control unit 20 outputs the code setting pulse signal TCMD as one shot pulse when decoding the first test command as a signal for controlling the test mode, and when decoding the second test command. A test mode start signal TST is output as a one-shot pulse signal. The code setting pulse signal TCMD and the test mode start signal TST will be described in detail again when the operation of the test mode setting circuit is described.

  The memory cell access unit 30 performs read / write control on the memory cell array 40 based on data and addresses given from the outside of the semiconductor memory device and the internal command signal decoded by the command control unit 20. During the write operation, data supplied from the data terminals DQ0 to DQn is written to a predetermined memory cell. In a read operation, control is performed to output data held in a predetermined memory cell to the outside of the semiconductor memory device.

  The memory cell array 40 includes a plurality of word lines, a plurality of bit lines, and a plurality of memory cells arranged at intersections thereof. Data supplied from outside is held by the plurality of memory cells.

  The power supply circuit 50 generates a power supply voltage used in each part in the semiconductor memory device from a power supply supplied from the outside.

  Next, a test mode setting circuit of the semiconductor memory device having the above configuration will be described. Since the test mode in the semiconductor memory device is used for various purposes, a test mode setting circuit is arranged in each part of the semiconductor memory device.

  Among them, the toggle type test mode setting circuit is used in the memory cell access unit 30, the power supply circuit 50, and the like. In the memory cell access unit 30, the read / write timing for the memory cell array 40 can be finely changed. Further, in the power supply circuit 50, a test mode setting circuit is arranged so that the voltage of the internal power supply can be finely changed.

  For example, in the power supply circuit 50, as shown in FIG. 3, a test mode setting circuit 52 is connected to a conversion circuit 51 that converts an externally received power supply VDD into an internal power supply VDD2. The test mode setting circuit 52 converts the code setting pulse signal TCMD supplied from the command control unit 20 into a setting code. The conversion circuit 51 changes the voltage value of the internal voltage VDD2 based on the setting code.

  FIG. 4 is a diagram showing an internal configuration of the test mode setting circuit 52. The test mode setting circuit 52 includes four counters 521 to 524 and four D-type flip-flops DFF1 to DFF4, and receives a code setting pulse signal TCMD and a test mode start signal TST. Each counter is connected in cascade, and the connection between each counter and the D-type flip-flop is that the output of the counter 521 is connected to the data terminal of the D-type flip-flop DFF1, and the output of the D-type flip-flop DFF1 is the output of the test mode setting circuit 52. Output from terminal OUT1. The connection between the counters 522 to 524 and the D-type flip-flops DFF2 to DFF4 is the same.

  The code setting pulse signal TCMD is connected to the input of the counter 524, and the counters 521 to 524 sequentially count up the input signals. Further, the test mode start signal TST is connected to the clock terminals of the D-type flip-flops DFF1 to DFF4. With such a configuration, the output values of the counters 521 to 524 are held in the D-type flip-flops DFF1 to DFF4 and output as setting codes. Since the test mode setting circuit 52 of FIG. 4 has four counters, setting corresponding to four bits (16 types) can be performed.

  Next, the operation of the test mode setting circuit 52 will be described with reference to FIG. FIG. 5 shows changes in the code setting pulse signal TCMD and the test mode start signal TST input to the test mode setting circuit 52 and the setting code output from the test mode setting circuit 52. When the test mode is performed, the code setting pulse signal TCMD is sequentially input to the test mode setting circuit 52 while the test mode start signal TST is held at the L level, and predetermined setting codes are set in the counters 521 to 524. . Thereafter, the test mode start signal TST is changed to the H level, and the data input to the counters 521 to 524 is taken in at the rising edge and output. When the test mode start signal TST becomes H level at time t1 in FIG. 5, it can be seen that the setting code is output. The code setting pulse signal TCMD is a signal output as one shot pulse from the command control unit 20 every time the first test command is input from the outside of the semiconductor memory device. The test mode start signal TST is When the second test command is input from the outside of the storage device, the signal is output from the command control unit 20 as one shot pulse. That is, a desired setting code can be output by inputting the first test command from the outside of the semiconductor memory device a required number of times and then inputting the second test command.

  FIG. 6 is a diagram showing the output level of the internal voltage VDD2 output by the conversion circuit 51 when the setting code as shown in FIG. 6 indicates the voltage of the internal voltage VDD2 output from the conversion circuit 51 in accordance with the setting of the test mode setting circuit 52. From FIG. 6, even if the first test command is input before time t1 and the code setting pulse signal TCMD is output, the internal voltage VDD2 maintains the voltage v1, and the second test command is input at time t1. When the test mode start signal TST is output, the count values of the counters 521 to 524 set by the first test command are reflected in the setting code output from the test mode setting circuit, and the conversion circuit 51 operates. It can be seen that the voltage value of the internal voltage VDD2 changes from v1 to v2.

  Here, a case where the D-type flip-flops DFF1 to DFF4 of the test mode setting circuit 52 do not exist will be described. FIG. 7 is a diagram showing an internal configuration of the test mode setting circuit 52a when there are no D-type flip-flops DFF1 to DFF4. In the test mode setting circuit 52a, the outputs of the counters 521 to 524 are output as they are as the output (setting code) of the test mode setting circuit.

  FIG. 8 is a diagram showing the output level of the internal voltage VDD2 output from the conversion circuit 51 of the power supply circuit 50 in accordance with the setting code output from the test mode setting circuit 52a. Since the test mode setting circuit 52a changes the setting according to the number of times the code setting pulse signal TCMD is input, the setting code changes each time the code setting pulse signal TCMD is input, and the setting value is expected in the semiconductor memory device. It may become a value that does not.

  For example, consider a case where the code setting pulse signal TCMD is sequentially input to the test mode setting circuit 52a to change from the setting at time t2 to the setting at time t4. In this case, since the setting code output from the test mode setting circuit 52a must once pass through the setting code at time t3, the voltage v3 is output from the conversion circuit 51. The voltage v3 is a voltage greatly deviating from the voltage v1 output at time t2 and the voltage v2 to be output at time t4, and may be a voltage at which the semiconductor memory device cannot operate. is there. As described above, when the setting value greatly deviates from the setting before and after the transition, depending on the setting content, the semiconductor memory device may not operate and the test itself may not be performed. FIG. 9 shows a change in the setting code output from the test mode setting circuit 52a in this case.

  As described above, in a semiconductor memory device including a command control unit 20 that inputs a command signal or an address signal from the outside of the semiconductor memory device, inputs a test command by a combination of the command signal and the address signal, and decodes the test command. The command control unit 20 decodes the test command and outputs different setting codes based on the count value of the counter when the test mode start signal STS is issued. The mode can be executed. Furthermore, the test mode setting circuit 52 is provided with a holding circuit for holding the setting code output by each counter, and the output of each counter is reflected based on the test mode start signal STS, and a test that could not be performed so far is also executed. And the range of tests during design and analysis of defective products is expanded. In FIG. 2, the command control unit 20 decodes the command signal CMD. However, for decoding the first test command and the second test command, other than the command signal CMD such as the address signals A0 to An. Of course, it can be used for decoding the command of the signal.

  It should be noted that the disclosures of the above patent documents and the like are incorporated herein by reference. Within the scope of the entire disclosure (including claims) of the present invention, the embodiment can be changed and adjusted based on the basic technical concept. Various combinations and selections of various disclosed elements are possible within the scope of the claims of the present invention. That is, the present invention of course includes various variations and modifications that could be made by those skilled in the art according to the entire disclosure including the claims and the technical idea. For example, when the semiconductor memory device includes a plurality of test mode setting circuits, the code setting pulse signal and the test mode start signal are output only to the specific test mode setting circuit, and only the specific test mode setting circuit is independently provided. It is possible to prepare a first test command and a second test command to be operated. Alternatively, the first test command and the second test command for operating the plurality of test mode circuits can be prepared by outputting the code setting pulse signal and the test mode start signal to the plurality of test mode setting circuits. is there.

DESCRIPTION OF SYMBOLS 10 Clock generation circuit 20 Command control part 30 Memory cell access part 40 Memory cell array 50 Power supply circuit 51 Conversion circuit 52, 52a Test mode setting circuit 521-524 Counter DFF1-DFF4 D type flip-flop

Claims (13)

A memory cell array comprising a plurality of memory cells capable of external read / write access based on an externally given command and address;
A command control unit for decoding the command given from the outside and controlling the read / write access;
A counter for counting the number of times the command control unit has decoded the first test command;
A holding circuit that outputs a test mode setting code based on a count value of the counter when the command control unit decodes a second test command;
A semiconductor memory device comprising: The command control unit outputs a pulse signal when the first test command is decoded,
The counter includes counter circuits that are cascaded in n (where n is an integer of 2 or more) stages that output predetermined count values, and the counter circuit in the first stage among the counter circuits that are cascaded in n stages. 2. The semiconductor memory device according to claim 1, wherein a first counter circuit receives the pulse signal and a counter circuit other than the first counter circuit receives the count value of the counter circuit in the previous stage.   The holding circuit is connected to each output of the first to n-th counter circuits, and based on a start signal output when the command control unit decodes the second test command, an output of each counter circuit 3. The semiconductor memory device according to claim 2, further comprising n latch circuits for latching.   The n latch circuits are D-type flip-flops, and the start signal is connected to clock terminals of the first to n-th D-type flip-flops, and outputs of the first to n-th counter circuits are 4. The semiconductor memory device according to claim 3, wherein the semiconductor memory device is connected to data terminals of the first to n-th D-type flip-flops.   The holding circuit outputs different setting codes based on the count value of the counter when the command control unit decodes the second test command, and executes different test modes depending on the value of the setting code 5. The semiconductor memory device according to claim 1, wherein   6. The command control unit inputs an address signal in addition to a command signal from the outside, and decodes the first test command and the second test command by a combination of the command signal and the address signal. The semiconductor memory device according to any one of the above.   7. The power supply circuit according to claim 1, further comprising a power supply circuit that converts an externally supplied power supply voltage into an internal power supply voltage, wherein the power supply circuit has a voltage value of the internal power supply voltage set by the setting code. Semiconductor memory device.   8. The synchronous semiconductor memory device according to claim 1, further comprising a clock input terminal, wherein the semiconductor memory device is a synchronous semiconductor memory device that operates in synchronization with a clock signal supplied from the clock input terminal. Semiconductor memory device. A synchronous semiconductor memory device that executes a read / write operation based on a command given from outside in synchronization with a clock signal,
A command control unit that decodes a command given from the outside and controls the operation inside the semiconductor memory device;
A test mode setting circuit;
A test execution circuit for executing a test inside the semiconductor memory device based on a test mode set by the test mode setting circuit;
Including
The test mode setting circuit includes:
A counter for counting the number of times the command control unit has decoded the first test command;
A holding circuit that outputs a setting code for setting a predetermined test mode based on a count value of the counter when the command control unit decodes a second test command;
A semiconductor memory device comprising:   10. The plurality of test execution circuits are provided corresponding to the plurality of circuits under test in the semiconductor memory device, and the plurality of test mode setting circuits are provided corresponding to the plurality of test execution circuits, respectively. Semiconductor memory device.   The semiconductor memory device according to claim 10, wherein the first test command and the second test command have different decoding results by the command control unit corresponding to each of the plurality of test mode setting circuits. The read / write operation is controlled based on a command given from the outside, and as a test mode setting circuit, a counter for counting the number of times the first test command is given, and a second test command are given, A test mode setting method for a semiconductor memory device, comprising: a holding circuit that outputs a count value of the counter as a test code;
A first step of giving the first test command to the semiconductor memory device a predetermined number of times in accordance with a test mode to be set in advance, and setting the counter to a predetermined count value;
A test mode setting method for a semiconductor memory device, wherein after the first step, a second test command is given to the semiconductor memory device to set the semiconductor memory device to a predetermined test mode.   13. The test mode setting method for a semiconductor memory device according to claim 12, wherein the predetermined test mode is a test mode in which an internal power supply voltage is set based on a count value of the counter.

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