JP2012051422A - Electronic control apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an electronic control apparatus that protects a control circuit from being deadlocked in performing shutoff processing.SOLUTION: In the electronic control apparatus 1, when the voltage of power supply VOM supplied from a regulator 4 starts to fall to stop the operation of a microcomputer 3 and a low voltage detection circuit 10 detects the fall of the power voltage, the microcomputer 3 is reset immediately and a communication start detection circuit 6 is permitted to output a communication start signal.

Description

  The present invention relates to an electronic control device including a control circuit that controls a device to be controlled and a power supply circuit that generates power to be supplied to the control circuit.

  Japanese Patent Application Laid-Open No. 2004-228561 discloses an automobile control device including a microcomputer (microcomputer, control circuit) that performs in-vehicle communication and a power supply IC that supplies power to the microcomputer. In Patent Document 1, as shown in the flowchart of FIG. 7, when the sleep condition is satisfied from the normal control state (step S <b> 1) by, for example, turning off the ignition switch (step S <b> 2: YES), the following is performed. Processing for shutting off the system (cutting off the power supply to the microcomputer) is performed.

  For example, when CAN is adopted as an in-vehicle LAN, after preparing for the microcomputer to wake up when a dominant signal is transmitted on the communication bus and communication is started (re-can-wake-up permission, step S3) The process proceeds to the shut-off process (step S4). Then, when the power supply IC drops off the power supply VOM supplied to the microcomputer by the power supply IC and the microcomputer is reset (low active) (step S5: YES), the microcomputer enters a sleep state in which the microcomputer stops its operation. (Step S6).

Japanese Patent No. 4032955

  However, in the shut-off sequence of Patent Document 1, the microcomputer waits for resetting while repeating an infinite loop in step S5 after instructing the power supply IC to shut off. In this state, as shown in FIG. 8, when any master sends a dominant signal to the communication bus on the in-vehicle communication bus (see (c)), the system starts the wake-up sequence and the power supply IC supplies the signal. The power supply voltage to be turned on again rises (see (a)), but does not change from the state in which the microcomputer is waiting for reset while executing the infinite loop (see (d)), and falls into a deadlock state.

  For example, for an ECU (Electronic Control Unit) for controlling the transmission, for example, when the vehicle door is opened or the driver is seated in the driver's seat, the position of the transmission at that time is displayed on the instrument panel. May be defined. Then, after the ignition is turned off, a signal is sent on the communication bus when the door is opened when the driver tries to go out of the vehicle, so that the deadlock state may occur as described above. In order to solve such a problem, for example, as shown in FIG. 9, while the microcomputer is waiting for reset in step S5 (NO), a dominant signal is sent on the communication bus (CAN Rx = H It is assumed that whether or not is monitored (step S7).

  However, a CAN-compatible communication driver IC detects a dominant signal (for example, about 2V), and a microcomputer recognizes an Rx signal that is an output signal of the communication driver IC (for example, about 3.5V). The set voltage is different. Therefore, there is a possibility that the detection timing is shifted and the wakeup sequence does not proceed normally. In addition, since each of the above determinations is performed during a period when the power supply voltage supplied to the microcomputer fluctuates, there is a high possibility that the detection timing is more shifted and the determination / recognition of the two becomes inconsistent.

  The present invention has been made in view of the above circumstances, and an object thereof is to provide an electronic control device capable of avoiding a control circuit from falling into a deadlock state when performing a shut-off process.

  According to the electronic control device of the first aspect, when the voltage drop of the power supply supplied by the power supply circuit to stop the operation of the control circuit starts to drop, the voltage drop is detected by the voltage drop detection circuit. As soon as the control circuit is reset, the output of the communication start signal by the determination circuit is permitted. Therefore, unlike the conventional case, when the power supply voltage starts to rise again as a result of the communication being started after the power supply voltage starts decreasing, the control circuit enters a deadlock state while waiting for itself to be reset. It will never fall and will be reset once. When the power supply voltage rises and the reset is released, the control circuit can subsequently receive data sent on the communication bus, so that the control target device can be controlled based on the received data. .

  According to the second aspect of the present invention, when the wake-up signal of the control circuit supplied from the outside becomes active, the power supply circuit starts supplying power to the control circuit, and the signal output blocking means is operated by the determination circuit. Block output of communication start signal. That is, in the above case, when the wake-up signal becomes active, the control circuit starts operating, so that unnecessary signal output from the determination circuit can be prevented.

  According to the electronic control device of the third aspect, when the signal of the ignition switch of the vehicle is turned ON, the power supply circuit starts to supply power to the control circuit, and the signal output blocking means receives the communication start signal from the determination circuit. Block output. That is, in the above case, since the control circuit starts operating when the ignition switch signal is turned on, unnecessary signal output from the determination circuit can be prevented as in the second aspect.

  According to the electronic control device of the fourth aspect, since the communication driver, the determination circuit, the latch circuit, and the power supply circuit are configured on the same semiconductor substrate, the number of connection terminals between the semiconductor substrates (between chips) can be reduced. . Further, the communication start signal can be output to the power supply circuit without delay, and the control can be coordinated quickly.

Functional block diagram showing the configuration of the electronic control unit according to the first embodiment Flow chart showing processing contents of microcomputer Timing chart when signal IG-SW indicates OFF 3 equivalent figure The figure which shows the transition of the operation state of (a) microcomputer and (b) power supply IC, and (c) the output timing of reception data Rx FIG. 1 equivalent view showing the second embodiment FIG. 2 equivalent view showing the prior art (part 1) 3 equivalent figure Figure 2 equivalent (part 2)

(First embodiment)
Hereinafter, a first embodiment will be described with reference to FIGS. FIG. 1 is a functional block diagram showing a configuration of an electronic control device, which is configured as an ECU (Electronic Control Unit) mounted on a vehicle, for example. The electronic control unit 1 includes a power supply IC 2 and a microcomputer (microcomputer, control circuit) 3. A regulator (power supply circuit) 4 is mounted on the power supply IC 2, and a battery power supply BATT (for example, 12 V) of the vehicle is applied to the regulator 4. Then, the regulator 4 generates a power supply VOM (for example, 5V) that steps down the power supply BATT and supplies it to the microcomputer 3.

The power supply IC 2 is equipped with a communication driver (and receiver) 5 corresponding to CAN, for example. The communication driver 5 is connected to CANH and CANL which are communication bus lines. When the communication driver 5 receives a differential signal transmitted from another node via the communication bus line, the received data Rx is transmitted to the microcomputer 3. When the microcomputer 3 outputs the transmission data Tx to the communication driver 5, the communication driver 5 outputs a differential signal (dominant, recessive) to the communication bus lines CANH and CANL according to the transmission data Tx.
A communication activation detection circuit (determination circuit) 6 is connected to the communication bus lines CANH and CANL. When detecting that a dominant signal is output to the communication bus lines CANH and CANL, the communication activation detection circuit 6 outputs a communication start signal to the regulator 4 via the latch circuit 7 and the OR gate 8.

  For example, the latch circuit 7 changes the output signal to a high level at the rising edge of the communication start signal and holds the state. In addition, the 3-input OR gate 8 is supplied with a signal IG-SW of the ignition switch of the vehicle and a system shut-off signal (low active) output from the microcomputer 3. Further, the signal IG-SW and the system shut-off signal are given to the input terminal of the OR gate 9, and these OR signals are given as clear signals for the latch circuit 7. The signal IG-SW is also given to the input terminal of the microcomputer 3.

  The regulator 4 operates when the signal supplied via the OR gate 8 is at a high level, supplies the power source VOM to the microcomputer 3, and stops operation when the signal becomes a low level, and the voltage of the power source VOM is set to 0V. To do. A low voltage detection circuit (voltage drop detection circuit) 10 is connected to the output terminal (supply line of the power supply VOM) of the regulator 4, and the low voltage detection circuit 10 has a voltage of the power supply VOM of a predetermined threshold (for example, 4). .5V), a voltage drop detection signal is output to the reset signal generation circuit 11.

The reset signal generation circuit 11 receives the voltage drop detection signal and outputs a reset signal (low active) to the microcomputer 3. The reset signal, the ignition switch signal IG-SW, and the system shutoff signal are given to the input terminal of the three-input OR gate 12, and these OR signals are given as output permission signals for the communication activation detection circuit 6. ing. The communication activation detection circuit 6 outputs a communication start signal to the latch circuit 7 when the signal given through the OR gate 12 is at a high level.
The power supply IC 2 is equipped with a watch dog timer 13. The watch dog timer 13 overflows when a period during which the clear signal from the microcomputer 3 is not given exceeds a predetermined period, and the overflow signal is reset as a reset signal. The signal is output to the generation circuit 11 and the microcomputer 3 is reset.

  Next, the operation of the present embodiment will be described with reference to FIGS. FIG. 2 is a view corresponding to FIG. In steps S11 and S12, the microcomputer 3 waits until a sleep condition is satisfied in the normal control state (for example, the signal IG-SW indicates OFF (low level)) in the same manner as in steps S1 and S2. When the sleep condition is satisfied (step S12: YES), the microcomputer 3 changes the level of the system shutoff signal from high (H) to low (L) (step S13), and shifts to a reset waiting state (step S14). ).

  Thereafter, the reset signal of the microcomputer 3 becomes active due to the action of the hardware side to be described later, and the level of the power supply VOM supplied from the regulator 4 is lowered to shift to the sleep state, and the power supply IC 2 enters the standby state ( Step S15). Since the microcomputer 3 continues to output the clear signal of the watchdog timer 13 while the microcomputer 3 is in a reset waiting state, the watchdog timer 13 does not overflow.

  FIG. 3 corresponds to FIG. (A) When the level of the power supply VOM drops and the low voltage detection circuit 10 outputs a voltage drop detection signal to the reset signal generation circuit 11, the reset signal generation circuit 11 receives the signal and sends a reset signal to the microcomputer 3. Output (e). In FIG. 3D, DATA1 is output on the communication bus before the microcomputer 3 is reset. At this time, the microcomputer 3 is in a reset waiting state in step S14, so DATA1 is not received.

At the same time as the reset signal is output to the microcomputer 3, the communication start detection circuit 6 is allowed to output the communication start signal (c). That is, at the time of “YES” in step S14 in FIG. 2, the “re-can-wake-up permission” state is entered. When DATA 2 is output on the communication bus, the communication activation detection circuit 6 outputs a communication start signal, and this signal is given to the regulator 4 via the latch circuit 7 and the OR gate 8.
Then, since the regulator 4 resumes operation, the level of the power supply VOM starts to rise, and when the level of the power supply VOM becomes equal to or higher than the predetermined level, when the oscillation circuit built in the microcomputer 3 starts operation, the oscillation state changes. After the time until stabilization has elapsed, the reset of the microcomputer 3 is released (e). Therefore, in this case, the microcomputer 3 misses DATA1 to DATA3. However, unlike the conventional case, the microcomputer 3 does not fall into a deadlock state waiting for reset.

  FIG. 4 is a case different from FIG. 3, in which the microcomputer 3 is reset and DATA1 is output on the communication bus after the communication start detection circuit 6 is permitted to output the communication start signal. . In this case, when DATA1 is output, the communication activation detection circuit 6 outputs a communication start signal, and the regulator 4 resumes its operation, so that the level of the power supply VOM starts to rise at an earlier timing than in FIG. Therefore, the microcomputer 3 misses DATA1 and DATA2, but this pattern is the same operation as that of the prior art.

  FIG. 5 shows (a) the transition of the operating state of the microcomputer 3, (b) the power supply IC 2 (regulator 4), and (c) the output timing of the reception data Rx (dominant signal). Even if the reception data Rx is output while the microcomputer 3 outputs the system shut-off signal and is in the reset waiting state, the microcomputer 3 does not accept the data and the regulator 4 is not activated until the reset is applied. . When the reception data Rx is output while the microcomputer 3 is being reset, the communication activation detection circuit 6 outputs a communication start signal, the regulator 4 resumes operation, and the level of the power supply VOM starts to rise. .

  As described above, according to the present embodiment, when the voltage of the power source VOM supplied by the regulator 4 to stop the operation of the microcomputer 3 starts to decrease in the electronic control unit 1, the voltage decrease is detected as a low voltage. When detected by the circuit 10, the microcomputer 3 is immediately reset and the communication start detection circuit 6 is allowed to output a communication start signal. Therefore, unlike the conventional case, when the power supply voltage starts to rise again as a result of the start of communication after the electric voltage starts decreasing, the microcomputer 3 does not fall into a deadlock state while waiting for reset. , Once reset reliably. Then, if the power supply voltage rises and the reset is released, the microcomputer 3 can subsequently receive the data sent on the communication bus, so that the control target device can be controlled based on the received data. .

  Further, since the regulator 4, the communication driver 5, the communication activation detection circuit 6, and the latch circuit 7 are mounted on the power supply IC 2 and are configured on the same chip (semiconductor substrate), the number of connection terminals between the chips is reduced. Can do. Further, the communication start signal can be output to the regulator 4 without delay, and the control can be coordinated quickly.

(Second embodiment)
FIG. 6 shows a second embodiment. The same parts as those in the first embodiment are denoted by the same reference numerals and the description thereof is omitted. Hereinafter, different parts will be described. The electronic control unit 21 of the second embodiment is different from the power supply IC 2 of the first embodiment in the configuration of the power supply IC 22. The electronic control device 21 is provided with a wake-up signal (Wake signal (high active)) of the microcomputer 3 output from an external ECU. The wake signal is passed through the OR gate 23 together with the signal IG-SW. To each of the OR gates 8, 9, and 12. As described above, the external ECU that outputs the Wake signal is, for example, a seating ECU or a door ECU when the electronic control unit 21 is a transmission ECU.

  Further, the communication activation detection circuit (determination circuit) 24 is shown more practically, and a differential amplifier circuit 25 that detects a differential signal of the communication bus lines CANH and CANL and an output signal of the differential amplifier circuit 25 are shown. And an AND gate 26 (signal output blocking means) for outputting the signal to the latch circuit 7. That is, when a dominant signal is output to the communication bus lines CANH and CANL, the differential amplifier circuit 25 outputs a high level signal according to the potential difference between the buses. The output terminal of the OR gate 12 is connected to the other input terminal (negative logic) of the AND gate 26.

Next, the operation of the second embodiment will be described. When a Wake signal is output from the outside, the regulator 4 is activated via the OR gates 23 and 8 as in the case where the signal IG-SW indicates ON, and the voltage of the power supply VOM is increased and supplied to the microcomputer 3. Then, the microcomputer 3 starts (wakes up).
At this time, the high level signal output from the OR gate 23 is also supplied to the OR gates 9 and 12, and the latch circuit 7 is cleared, so that the input terminal on the negative logic side of the AND gate 26 becomes high level. Therefore, even if the differential amplifier circuit 25 of the communication activation detection circuit 24 detects that a dominant signal is output to the communication bus lines CANH and CANL during this period, the communication start signal output to the latch circuit 7 is AND. Blocked by gate 26. The above operation is exactly the same when the signal IG-SW changes to a high level.

  As described above, according to the second embodiment, when the electronic control unit 21 activates the wake-up signal Wake of the microcomputer 3 given from the outside or the signal IG-SW of the ignition switch of the vehicle indicates ON. The regulator 4 starts supplying the power source VOM to the microcomputer 3, and the AND gate 26 prevents the communication start detection circuit 24 from outputting a communication start signal. That is, in the above case, the microcomputer 3 starts operating when the wake-up signal Wake becomes active or the signal IG-SW indicates ON, so that unnecessary signal output from the communication activation detection circuit 24 is prevented. it can.

The present invention is not limited to the embodiments described above or shown in the drawings, and can be modified or expanded as follows.
The power supply IC 2 and the microcomputer 3 do not have to be configured on different chips, but may be configured on the same chip.
In the second embodiment, the signal given from the outside to the electronic control unit 21 may be only one of the wake-up signal Wake and the ignition switch signal IG-SW.
When the microcomputer 3 is reset when the watchdog timer 13 overflows, the output of the communication start signal may be blocked as in the second embodiment.
The watchdog timer 13 may be provided as necessary.
In-vehicle communication is not limited to CAN, but may be LIN, FlexRay (registered trademark), or the like. Moreover, since it is not necessarily limited to what controls an in-vehicle device, it is not necessary to limit to in-vehicle communication.

  In the drawings, 1 is an electronic control device, 2 is a power supply IC, 3 is a microcomputer (control circuit), 4 is a regulator (power supply circuit), 5 is a communication driver, 6 is a communication activation detection circuit (determination circuit), and 7 is a latch. Reference numeral 10 denotes a low voltage detection circuit (voltage drop detection circuit), 21 denotes an electronic control device, 22 denotes a power supply IC, 24 denotes a communication activation detection circuit (determination circuit), and 26 denotes an AND gate (signal output blocking means).

The reset signal generation circuit 11 receives the voltage drop detection signal and outputs a reset signal (low active) to the microcomputer 3. The reset signal, the ignition switch signal IG-SW, and the system shutoff signal are given to the input terminal of the three-input OR gate 12, and these OR signals are given as output permission signals for the communication activation detection circuit 6. ing. Communication start detection circuit 6, the signal applied through the OR gate 12 is in the case of low-level, and outputs a communication start signal to the latch circuit 7.
The power supply IC 2 is equipped with a watch dog timer 13. The watch dog timer 13 overflows when a period during which the clear signal from the microcomputer 3 is not given exceeds a predetermined period, and the overflow signal is reset as a reset signal. The signal is output to the generation circuit 11 and the microcomputer 3 is reset.

At the same time as the reset signal is output to the microcomputer 3, the communication start detection circuit 6 is allowed to output the communication start signal (c). That is, when “YES” is determined in step S14 of FIG. 2, the “re-CAN-Wake-Up permission” state is set. When DATA 2 is output on the communication bus, the communication activation detection circuit 6 outputs a communication start signal, and this signal is given to the regulator 4 via the latch circuit 7 and the OR gate 8.
Then, since the regulator 4 resumes operation, the level of the power supply VOM starts to rise, and when the level of the power supply VOM becomes equal to or higher than the predetermined level, when the oscillation circuit built in the microcomputer 3 starts operation, the oscillation state changes. After the time until stabilization has elapsed, the reset of the microcomputer 3 is released (e). Therefore, in this case, the microcomputer 3 misses DATA1 to DATA3. However, unlike the conventional case, the microcomputer 3 does not fall into a deadlock state waiting for reset.

Claims (4)

A control circuit for controlling the device to be controlled;
A communication driver for the control circuit to communicate via the communication bus;
A determination circuit for determining that communication is started via the communication bus;
A latch circuit that latches a communication start signal output by the determination circuit;
A power supply circuit that generates power to be supplied to the control circuit and whose supply is controlled by a control signal output by the control circuit or a communication start signal given through the latch circuit;
A voltage drop detection circuit for detecting a voltage drop of the power supply,
The electronic control device according to claim 1, wherein the control circuit is reset by a voltage drop detection signal output from the voltage drop detection circuit, and an output of a communication start signal by the determination circuit is permitted. The control circuit wake-up signal is given from the outside,
When the wakeup signal becomes active, the power supply circuit starts supplying power to the control circuit,
2. The electronic control device according to claim 1, further comprising a signal output blocking unit that blocks output of a communication start signal by the determination circuit when the wakeup signal becomes active. It is mounted on the vehicle and given a signal indicating the ignition switch ON / OFF,
When the ignition switch signal is turned ON, the power supply circuit starts supplying power to the control circuit,
3. The electronic control device according to claim 1, further comprising a signal output blocking unit that blocks output of a communication start signal by the determination circuit when the ignition switch signal is turned on.   4. The electronic control device according to claim 1, wherein the communication driver, the determination circuit, the latch circuit, and the power supply circuit are configured on the same semiconductor substrate.

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