JP2012049796A - Amplifying circuit device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To avoid the occurrence of drain current exceeding the standard value by preventing the input of an unintended low-frequency signal, when a J-FET is adopted as an amplifying circuit device.SOLUTION: In a sealing member of a J-FET 1, capacitance is added in series with a gate. The capacitance and a resistor connected between the gate and a source of the J-FET constitute a high-pass filter 5. The setting of the cutoff frequency of the high-pass filter 5 to less than 20 Hz can cut off frequencies lower than the lower limit of the audible frequency band without degrading an audio signal. A p-type semiconductor layer, which becomes a back-gate region, is provided on an n-type semiconductor substrate to form a pn junction. Junction capacitance of the pn junction is capacitance of the high-pass filter 5.

Description

  The present invention relates to an amplifier circuit device, and more particularly to an amplifier circuit device using a junction field effect transistor.

  In order to perform impedance conversion and amplification of an electret condenser microphone (hereinafter referred to as ECM) used in a mobile phone or the like, a junction field effect transistor (hereinafter referred to as J-FET) may be employed. .

  FIG. 7 is a circuit diagram showing an example of the amplifier circuit device 200 using the J-FET 201. The gate G of the J-FET 201 is connected to, for example, one end of an ECM (not shown). The drain D is connected to, for example, a power source (not shown). A resistor 202 and a pn junction diode 203 are connected in parallel between the gate G and the source S of the J-FET 201, respectively. The resistor 202 is a high-resistance body having a resistance value of about 1 GΩ, for example.

  In the amplifier circuit device 200, when the power is turned on, a current flows through the path of the source S, the resistor 202, and the gate G. Therefore, the time from when the power is turned on until the fluctuation of the input voltage (gate potential) is stabilized and the steady state is reached is shortened. And good transient characteristics can be obtained. The pn junction diode 203 can increase the resistance to electrostatic breakdown (see, for example, Patent Document 1).

JP 61-160963 A (page 3, Fig. 1)

  The J-FET 201 employed in the amplifier circuit device is generally used in a steady state after passing a transient state after power-on, that is, in a drain current saturation region.

  In the amplifier circuit device 200 shown in FIG. 7, the gate potential in a transient state immediately after power-on is grounded (absorbed by GND) by appropriately selecting the resistance value of the resistor 202, and the gate potential is stabilized in a short period of time. To achieve a steady state.

  However, even in a steady state, the input voltage may fluctuate due to an external factor from the sealing member (package) of the amplifier circuit device 200, that is, an unintended (not to be amplified) gate potential may vary. For example, the gate potential of the gate terminal led out of the sealing member may fluctuate particularly remarkably in a high humidity environment. Such a change in the gate potential (at most 100 mV) means that a signal having a frequency lower than the audible frequency is input to the gate of the J-FET regardless of the input signal (for example, 10 mV). However, there was a problem that greatly exceeded the standard value.

  The present invention has been made in view of such a problem, and includes one conductivity type semiconductor layer, a reverse conductivity type semiconductor region provided on the one conductivity type semiconductor layer, and a reverse conductivity type provided on the surface of the reverse conductivity type semiconductor region. A source region and a drain region; a gate region of one conductivity type provided on the surface of the reverse conductivity type semiconductor region; and a region of the one conductivity type provided from the surface of the reverse conductivity type semiconductor region provided around the one conductivity type semiconductor layer. A high-concentration one-conductivity type impurity region having a depth reaching the semiconductor layer, a resistor having one end electrically connected to the source region and the other end electrically connected to the one-conductivity type semiconductor layer, and the one-conductivity type The problem is solved by providing a reverse conductivity type semiconductor substrate provided on the other main surface of the semiconductor layer and a conductive member to which the gate potential is applied while being fixed to the reverse conductivity type semiconductor substrate.

  According to the present invention, the following effects can be obtained.

  First, a resistor is connected between the gate and source of the J-FET, a capacitor is connected in series with the gate, and a high-pass filter is configured by the resistor and the capacitor. By setting the cutoff frequency of the high-pass filter near the lower limit of the audible frequency band, the gate potential varies at the gate terminal outside the sealing member due to factors outside the sealing member (package) of the amplifier circuit device (for example, humidity). Even if this occurs, it can be blocked by a high-pass filter in the sealing member, and a low-frequency signal unrelated to the input signal can be prevented from being input to the gate of the J-FET. The input signal to be amplified is an audio signal in the audible frequency band, and is not blocked by a capacitor or high-pass filter, preventing unintended low-frequency signal input and generating a drain current exceeding the standard value. Can be avoided.

  Secondly, the input signal to be amplified is selected by appropriately selecting the capacitance of the capacitor and the resistance value of the resistor, and setting the voltage gain of the high-pass filter expressed using these to 0.9 or more in the audible frequency band. Without lowering the sensitivity of the (audio signal), it is possible to prevent the input of a low-frequency signal below the audible frequency generated regardless of the input signal to the gate.

  Third, a high-pass filter can be configured by using a resistor conventionally provided for stabilizing the gate potential and adding only one capacitor to the resistor. An increase in the outer shape of the stopping member can be suppressed.

  Specifically, a pn junction capacitance is formed by providing a p-type semiconductor layer serving as a back gate region of a J-FET on an n-type semiconductor substrate, and this is used as a capacitance of a high-pass filter. The area) can be maintained equivalent to the conventional one. Moreover, the p-type semiconductor layer can be made thin as long as the required electrostatic capacity can be secured by the depletion layer extending from the pn junction and the desired electrostatic breakdown voltage can be secured. it can.

  Fourth, by providing an n-type impurity region that is exposed on the outermost peripheral surface of the chip (p-type semiconductor layer) and reaches the n-type semiconductor substrate, leakage due to exposure of the pn junction to the outermost peripheral surface of the chip is prevented. it can. The n-type impurity region needs to be formed by ion implantation so as to reach the n-type semiconductor substrate from the chip surface. In the present embodiment, the thickness of the p-type semiconductor layer is set to a minimum thickness if the depletion layer is widened so that the required capacitance C can be obtained and a desired electrostatic breakdown voltage can be secured. Therefore, the distance (depth) from the surface of the chip to the n-type semiconductor substrate can be reduced, and an n-type impurity region for preventing leakage can be provided.

  Fifth, since a capacitor can be formed by providing a p-type semiconductor layer on an n-type semiconductor substrate, the capacitor can be added without increasing the number of components.

It is a figure explaining the amplifier circuit apparatus of this invention, (A) is a circuit diagram which shows the usage example of an amplifier circuit apparatus, (B) is a circuit diagram of an amplifier circuit apparatus, (C) is a high-pass filter. It is a circuit diagram. It is a characteristic view explaining the amplifier circuit apparatus of this invention. It is a characteristic view explaining the amplifier circuit apparatus of this invention. It is a characteristic view explaining the amplifier circuit apparatus of this invention. It is a characteristic view explaining the amplifier circuit apparatus of this invention. It is sectional drawing explaining the amplifier circuit apparatus of this invention. It is a circuit diagram explaining a prior art.

  Embodiments of the present invention will be described with reference to FIGS.

  FIG. 1 is a circuit diagram for explaining an amplifier circuit device 10 of the present embodiment. FIG. 1A is a circuit diagram showing an example of use of the amplifier circuit device 10, and FIG. 1B is an amplifier circuit device. FIG. 1C is a circuit diagram of the high-pass filter 5.

  Referring to FIG. 1A, an amplification circuit device 10 of this embodiment is used by being connected to an electret condenser microphone (hereinafter referred to as ECM) 15, for example.

  The ECM 15 includes a diaphragm (diaphragm) and an electrode facing the diaphragm, and the diaphragm is made of, for example, a polymer material, and the charge is sustained by the electret effect. It is. In the ECM 15, the movement of the diaphragm due to sound is taken out as a change in capacitance between the diaphragm and the electrode, and this is amplified by the amplifier circuit device 10.

  The amplifier circuit device 10 includes a junction field effect transistor (hereinafter referred to as J-FET) 1, a resistor 2, a diode 3, and a capacitor 4.

The J-FET 1 has three terminals: a gate G, a source S, and a drain D. The gate G is connected to one end of the ECM 15. The drain D is connected to the power source 6 through the load resistor _RL. Grounded. The resistance value of the load resistor _RL is, for example, about 1 kΩ to 15 kΩ. The gate G is on the input side, and is used in a state where the gate G is opened in a DC manner. Amplification is mainly performed in a steady state of J-FET 1 (a state where the potential of the gate G is stable, a drain current saturation region). The drain D is on the output side.

Specifically, the capacitance change (voltage change) of the ECM 15 is applied to the gate G of the J-FET 1 as a change of the input voltage Vin (gate G-source S voltage VGS), and the drain current flowing through the J-FET 1 is controlled. . A drain current flowing in the drain D is amplified by the amplifier circuit device 10. The amplified current (current consumption) is converted into a voltage by the load resistance _RL and can be taken out from the drain D of the J-FET 1 as an AC component of the output voltage Vout.

  Referring to FIGS. 1A and 1B, J-FET 1 is, for example, an n-channel depletion type J-FET. That is, it has an n-type channel region, a p-type gate region, a p-type back gate region, and an n-type source region and drain region, respectively.

  The resistor 2 is connected in parallel between the gate G and the source S. The resistor 2 has a resistance value R of, for example, 1 GΩ to 30 GΩ (more preferably 1 GΩ to 3 GΩ), and during the transient state of the J-FET 1 immediately after the power supply 6 is turned on, By flowing a current through the path, the gate potential is connected in a short period of time.

  The diode 3 is connected in parallel between the gate G and the source S. The diode 3 is a pn junction diode, and is connected so as to apply a negative voltage (a reverse bias is applied) to the anode (source S) side, thereby preventing static electricity applied between the gate G and the source S. It discharges to improve the electrostatic breakdown resistance.

  The capacitor 4 is connected in series to the gate G of the J-FET 1. The capacitance of the capacitor 4 is, for example, 1 pF to 50 pF.

  The J-FET 1, the resistor 2, the diode 3, and the capacitor 4 are all housed in a single sealing member 7 and constitute an amplifier circuit device 10. The sealing member 7 is, for example, a sealing resin package, but a metal can package or a ceramic package can also be adopted. As an example, the J-FET 1, the resistor 2, the diode 3, and the capacitor 4 are all integrated on the same semiconductor substrate (chip).

  Referring to FIGS. 1B and 1C, an amplifier circuit device 10 of this embodiment includes a gate G and a capacitor 4 connected in series with one end of a resistor 2, whereby a resistor is connected in series with the gate G. 2 and a high-pass filter 5 having a capacitor 4 are connected.

  The high-pass filter 5 has a cutoff frequency near the lower limit of the audible frequency band (for example, 20 Hz to 20,000 Hz (20 KHz)). Thereby, for example, a signal having a frequency lower than 20 Hz can be cut off. That is, in the steady state of J-FET 1, even if an unintended gate potential change occurs due to external factors such as the usage environment of the amplifier circuit device 10 and is input to the amplifier circuit device 10 as a signal, amplification is performed. The fluctuation (signal) can be reduced before the operation.

  More specifically, the gate potential may fluctuate regardless of changes in the input voltage Vin (input signal or audio signal) to be amplified even in a steady state due to, for example, use in a high humidity environment. The fluctuation of the gate potential in this case is input to the gate G of the J-FET 1 as a signal having a frequency significantly lower than the lower limit (20 Hz) of the audible frequency band. In the present embodiment, even when the gate potential at the point I1 in FIG. 1B varies due to the low-frequency signal, this can be blocked by the high-pass filter 5, thereby reducing the variation in the gate potential at the point I2. it can. On the other hand, a high frequency input signal in the audible frequency band to be amplified can reach the point I2 with almost no loss (decrease).

  The magnitude of the loss of the high frequency input signal to be amplified is calculated by the voltage gain Gain of the high-pass filter 5, and the frequency characteristic of the voltage gain Gain is expressed by the following equation.

ここで、Ｖｉｎ：入力電圧［Ｖ］、Ｖｏｕｔ：出力電圧［Ｖ］、ω：角周波数［ｒａｄ］（＝２πｆ（ｆ：周波数［Ｈｚ］））、Ｃ：静電容量［ｐＦ］、Ｒ：抵抗［Ω］である。

Here, Vin: input voltage [V], Vout: output voltage [V], ω: angular frequency [rad] (= 2πf (f: frequency [Hz])), C: capacitance [pF], R: Resistance [Ω].

  In the present embodiment, the resistance value R of the resistor 2 and the capacitance C of the capacitor 4 are selected so that the voltage gain Gain of the high-pass filter 5 expressed by the above equation is 0.9 or more in the audible frequency band. . As a result, the sensitivity of the input signal (sound signal) to be amplified is hardly lowered, and a low-frequency signal generated regardless of the input signal to be amplified is input to the gate G of the J-FET 1. Can be prevented.

  2 to 5 are characteristic diagrams showing the dependence of the voltage 4 on the voltage gain Gain and the frequency f calculated using the above equations. In any case, the Y-axis is the voltage gain Gain, the X-axis is the frequency f [Hz], and FIGS. 2 to 4 are 6 in which the capacitance C of the capacitor 4 is 0.1 pF, 1 pF, 5 pF, 10 pF, 30 pF, 50 pF, respectively. FIG. 5 shows the dependence of the resistance value R of the resistor 2 on eight cases where the capacitance C of the capacitor 4 is 0.1 pF, 0.5 pF, 1 pF, 2 pF, 5 pF, 10 pF, 30 pF, and 50 pF. Was calculated. 2 shows a resistance value R = 1 GΩ (1.00E09Ω), FIG. 3 shows a resistance value R = 3 GΩ, FIG. 4 shows a resistance value R = 10 GΩ, and FIG. 5 shows a resistance value R = 30 GΩ. In both cases, the broken line indicates the vicinity of the lower limit of the audible frequency band, and the region having a higher frequency (up to about 20,000 Hz) than the broken line indicated by the arrow is the audible frequency band.

  Referring to FIG. 2, when resistance value R of resistor 2 is 1 GΩ, voltage gain Gain is 0.9 or more near the lower limit of the audible frequency band when capacitance C of capacitor 4 is 30 pF or more. The voltage gain Gain is approximately 1 at 50 pF. When the capacitance C is smaller than this, the voltage gain Gain is 0.9 or more at a high frequency, but near the lower limit of the audible frequency band, the voltage gain Gain is less than 0.9, and the low input to the gate G is low. Even if the signal of the frequency can be cut off, the loss of the audible frequency band becomes too large.

  Similarly, referring to FIG. 3, when the resistance value R of the resistor 2 is 3 GΩ, the voltage gain Gain becomes 0.9 or more near the lower limit of the audible frequency band because the capacitance of the capacitor 4 is 5 pF or more. In this case, the voltage gain G is 0.95 or more when the capacitance C is 10 pF or more.

  Further, referring to FIG. 4, when the resistance value R of the resistor 2 is 10 GΩ, if the capacitance C is 5 pF or more, the voltage gain Gain is 0.95 or more and nearly 1 near the lower limit of the audible frequency band. Get closer.

  Further, referring to FIG. 5, when the resistance value R of the resistor 2 is 30 GΩ, the voltage gain Gain is 0.95 or more near the lower limit of the audible frequency band if the capacitance C is 1 pF or more.

  As is apparent from these figures, the larger the resistance value R of the resistor 2, the better the voltage gain Gain is obtained in the audible frequency band with the smaller capacitance C. On the other hand, the resistance value R of the resistor 2 affects the time until the gate potential is stabilized during the transient state, and the larger the resistance value R, the less the current flows between the source S-resistance 2 and the gate G. It takes time for the potential to stabilize. In other words, if the resistance value R suitable for stabilizing the gate potential in the transient state is, for example, 1 GΩ to 3 GΩ, it can be said that the capacitance C is preferably 30 pF or more.

  Further, it can be said that the larger the capacitance C, the smaller the loss can be in a wide range of the audible frequency band. However, when the capacitance C becomes extremely large, it approaches a conventional structure in which the capacitor 4 is not added, that is, the low frequency signal cannot be blocked. . In the present embodiment, the upper limit value of the capacitance C is, for example, about 30 pF to 50 pF. This value is theoretically smaller than the capacitance at which low-frequency signals cannot be cut off, and is limited to the actual size of the capacitance 4.

  That is, as will be described in detail later, the following configuration is conceivable as a specific device of the amplifier circuit device 10 in which the capacitor 4 is connected in series to the gate G. For example, a p-type semiconductor layer serving as a back gate region is provided on an n-type semiconductor substrate constituting the chip of the J-FET 1 and a capacitor 4 by a pn junction capacitance is connected. Further, the capacitor 4 may be an element (chip) different from the J-FET 1 as long as it is accommodated in at least the same sealing member 7.

  In any case, there is a restriction on the chip size of the J-FET 1 or the size of the outer shape of the sealing member 7. For example, when the chip size is about 0.3 mm square, the capacitance 4 such that the capacitance C exceeds 50 pF. It is not realistic to create That is, the upper limit value of the capacitance C of the capacitor 4 of the present embodiment is determined by the outer size of the amplifier circuit device 10 (for example, when the chip size is about 0.3 mm square, the capacitance C is 50 pF). . On the other hand, if the capacitance C is reduced, the voltage gain Gain in the audible frequency band is reduced, and therefore, it is necessary to select an appropriate value for the lower limit. That is, considering the resistance value R of the resistor 2, the lower limit of the capacitor 4 of the present embodiment is preferably about 1 pF.

  Thus, in this embodiment, the capacitance 4 is added in series with the gate G in the sealing member 7 of the J-FET 1, and the capacitance 4 and the resistor 2 connected between the gate and the source of the J-FET 1 are used. A high-pass filter 5 is configured. By setting the cut-off frequency of the high-pass filter 5 to less than 20 Hz, the frequency lower than the lower limit of the audible frequency band can be cut off without lowering the input signal (sound signal) to be amplified. The influence of unintended gate potential fluctuations can be reduced.

  Next, a specific structure of the amplifier circuit device 10 will be described with reference to FIG. FIG. 6 is a cross-sectional view schematically showing the structure of the amplifier circuit device 10 using the n-channel J-FET 1 as an example. The same components as those in the circuit diagram of FIG.

  The amplifier circuit device 10 includes an n-type semiconductor substrate 41, a p-type semiconductor layer 12, n-type semiconductor regions 14a, 14b, and 14c, a source region 15, a drain region 16, a gate region 17, and a high concentration p-type. Impurity region 50, resistor 2, diode 3, and conductive member 42 are provided.

  The n-type semiconductor substrate 41 constitutes a chip of the J-FET 1. As an example, the specific resistance ρ is, for example, 0.015 Ω · cm, and the thickness is about 80 μm. As an example, the amplifier circuit device 10 of the present embodiment partitions a single n-type semiconductor substrate 41 into a plurality of regions, and integrates the J-FET 1, the resistor 2, and the diode 3 thereon. Here, for convenience, the n-type semiconductor substrate 41 is partitioned into a first region r1, a second region r2, and a third region r3, a J-FET 1 is formed above the first region r1, and a resistor is formed above the second region r2. 2 is formed, and the diode 3 is formed above the third region r3. The first region r1, the second region r2, and the third region r3 are not limited to the region where only the n-type semiconductor substrate 41 is partitioned, but various semiconductor layers (semiconductor regions) above the partitioned n-type semiconductor substrate 41. It is a general term for the area including.

  The p-type semiconductor layer 12 is, for example, an epitaxial layer provided on one main surface of the n-type semiconductor substrate 11 and has a specific resistance and a thickness that can obtain a desired electrostatic breakdown resistance. As an example, the specific resistance is about 3 Ω · cm to 4 Ω · cm, and the thickness is about 10 μm, for example. The p-type semiconductor layer 12 becomes a back gate region of the J-FET 1. As described above, the single p-type semiconductor layer 12 is also divided into the first region r1, the second region r2, and the third region r3.

  On the p-type semiconductor layer 12 in the first region r1, an n-type semiconductor region 14a and a high-concentration p-type impurity region 50 surrounding its end are provided. Further, on the p-type semiconductor layer 12 in the second region r2, an n-type semiconductor region 14b and a high-concentration p-type impurity region 50 surrounding its end are provided, and on the p-type semiconductor layer 12 in the third region r3. , An n-type semiconductor region 14c and a high-concentration p-type impurity region 50 surrounding its end are provided. Each of the high-concentration p-type impurity regions 50 is provided deeper than at least the bottom surfaces of the n-type semiconductor regions 14a, 14b, and 14c.

  In the present embodiment, all of the n-type semiconductor regions 14a, 14b, and 14c are impurity diffusion regions provided on the surface of the p-type semiconductor layer 12 by ion implantation and diffusion under the same conditions. Alternatively, the n-type semiconductor regions 14a, 14b, and 14c may be part of the n-type semiconductor layer. That is, a single n-type semiconductor layer is provided on the p-type semiconductor layer 12 by, for example, epitaxial growth, and a plurality of high-concentration p-type impurity regions 50 reaching the p-type semiconductor layer 12 from the surface thereof are provided. 14a, 14b, and 14c may be separated, and the first region r1, the second region r2, and the third region r3 in which the high-concentration p-type impurity region 50 is disposed on the outer periphery may be partitioned.

  In the first region r1, an n + type source region 15 and a drain region 16 and a p + type gate region 17 are provided on the surface of the n type semiconductor region 14a. The n-type semiconductor region 14a becomes a channel region, and the source regions 15 and the drain regions 16 are alternately arranged, and the gate regions 17 are respectively arranged therebetween. The high-concentration p-type impurity region 50 around the first region r <b> 1 has a higher impurity concentration than the gate region 17, and reaches the p-type semiconductor layer 12 partially overlapping with the gate region 17. Thereby, a gate voltage is applied to the gate region 17 through the back gate region (p-type semiconductor layer 12) and the high-concentration p-type impurity region 50.

  A first insulating film (for example, an oxide film) 91 is provided on the n-type semiconductor region 14 a and a contact hole CH is provided on the source region 15 and the drain region 16, but the gate region 17 is covered with the first insulating film 91. Is called. For example, aluminum (Al) or the like is provided with a first source electrode 61 and a first drain electrode 62 in the first layer that are in contact with the source region 15 and the drain region 16 through the contact holes CH, respectively. The first insulating film 91 is covered with a second insulating film (for example, a nitride film (SiN)) 92, and a through hole TH is provided on the first source electrode 61 and the first drain electrode 62. For example, the second source electrode 71 and the second drain electrode 72 of the second layer are provided by aluminum (Al) or the like, which are in contact with the first source electrode 61 and the first drain electrode 62 through the through holes TH, respectively. As a result, the J-FET 1 is formed in the first region r1. The J-FET 1 is a so-called discrete element whose back side (p-type semiconductor layer 12) is a back gate region.

In the second region r2, a first insulating film 91 is provided on the n-type semiconductor region 14b, and a resistor 2 is provided thereon via a third insulating film (for example, a nitride film (Si ₃ N ₄ )) 93. . The resistor 2 is, for example, a conductive layer such as a polysilicon layer into which impurities are introduced. Note that the n-type semiconductor region 14b of the second region r2 may not be provided.

  The resistor 2 has one end T1 electrically connected to the source region 15 of the J-FET 1 and the other end T2 electrically connected to the p-type semiconductor layer 12 in the first region r1 via the p-type semiconductor layer 12 in the second region r2. Connect. More specifically, the first source electrode 61 provided at, for example, the end of the J-FET 1 in the first region r1 is connected to a wiring (for example, a conductive layer such as a metal layer) 63 extending to the second region r2. , Contact one end T1 of the resistor 2. Another wiring 64 connected to the other end T2 of the resistor 2 is provided, and a part of the wiring 64 is p + on the surface of the second region r2 via the contact hole CH provided in the first insulating film 91. Contact with the mold contact region 21. The p + -type contact region 21 is provided on the surface of the high-concentration p-type impurity region 50 that partitions the periphery of the second region r2, so that the other end T2 of the resistor 2 is connected to the p-type semiconductor layer 12 in the second region r2. And is connected to the p-type semiconductor layer 12 in the first region r1 which is the back gate region of the J-FET 1 through this. In this way, the resistor 2 has one end T1 connected to the source S of the J-FET 1 and the other end T2 connected to the gate G (see FIG. 1).

  In the third region r3, an n-type semiconductor region 14c is provided on the p-type semiconductor layer 12, and an n + -type impurity region 31 is provided on the surface thereof. The n + type impurity region 31 is in contact with the wiring 64 through a contact hole CH provided in the first insulating film 91. That is, the n + -type impurity region 31 (n-type semiconductor region 14 c) is electrically connected to the other end T 2 of the resistor 2 through the wiring 64. In addition, a p + -type impurity region 32 is provided on the surface of the n-type semiconductor region 14 c and is in contact with another wiring 65 through a contact hole CH provided in the first insulating film 91.

  The upper side of the resistor 2 and the upper sides of the wirings 63 and 64 connected thereto are covered with a second insulating film 92, and a second-layer wiring 73 extends thereon. The wiring 73 is in contact with the first-layer wiring 65 in the third region r3 through the through hole TH provided in the second insulating film 92, and is also in contact with the first source electrode 61.

  In this manner, the diode 3 having the p + -type impurity region 32 as an anode and the n + -type impurity region 31 (n-type semiconductor region 14c) as a cathode is formed in the third region r3. In the diode 3, the p + -type impurity region 32 is connected to the source region 15 of the J-FET 1 through the wiring 73, and the n + -type impurity region 31 (n-type semiconductor region 14 c) is connected to the wiring 64 and the p-type semiconductor layer of the second region r 2. 12 is connected to the p-type semiconductor layer 12 serving as the back gate region of the J-FET 1. That is, the diode 3 is connected in the reverse direction between the source S and the gate G of the J-FET 1.

  In the present embodiment, the n-type semiconductor substrate 41 is provided on the entire other main surface (back surface) of the p-type semiconductor layer 12. The main surface of the n-type semiconductor substrate 41 exposed as the back surface of the chip is provided with a gate electrode 66 by, for example, nickel-chromium (NiCr) plating and gold (Au) deposition, and the gate electrode 66 is fixed to the conductive member 42. The conductive member 42 is, for example, a lead frame base material made of copper or an alloy material containing copper as a main component, and islands and leads are formed by etching or punching, and the n-type semiconductor substrate 41 is fixed to the islands. One is led out of the sealing member (not shown) and a gate potential is applied. As a result, the capacitance 4 is formed by the pn junction capacitance between the n-type semiconductor substrate 41 and the p-type semiconductor layer 12.

  With the above configuration, the J-FET 1, the resistor 2 and the diode 3 are integrated on a single n-type semiconductor substrate 41, and the resistor 2 and the diode 3 are connected in parallel between the gate G and the source S of the J-FET 1. Thus, an amplifier circuit device 10 in which a capacitor 4 is connected in series to the gate G is configured.

  Furthermore, by appropriately selecting the resistance value of the resistor 2 and the capacitance of the capacitor 4, the high-pass filter 5 is configured, and the amplifier circuit device 10 incorporating the high-pass filter is obtained. Since the relationship between the resistance value and the capacitance is as already described with reference to FIGS. 2 to 4, the description will be omitted, but the pn junction capacitance will be further described.

  In the capacitor 4 by the pn junction, a depletion layer extending to the pn junction has a dielectric property. As described above, the preferred range of the capacitance of the present embodiment is approximately 1 pF to 50 pF. Therefore, the chip size, the n-type semiconductor substrate 41 and the p-type semiconductor layer 12 can be obtained to obtain this capacitance. A pn junction is formed by appropriately selecting a depletion layer formation condition such as impurity concentration. Although the capacitance 4 can be varied depending on the gate potential, the potential fluctuation to be removed by the high-pass filter is 100 mV, which is negligible even if the capacitance 4 is displaced.

  The p-type semiconductor layer 12 needs to ensure a desired electrostatic breakdown voltage. If the required capacitance can be secured by the depletion layer and a desired electrostatic breakdown voltage can be secured, the p-type semiconductor layer 12 can be made thin, and an increase in the thickness of the chip due to the connection of the capacitor 4 can be suppressed. .

  As an example, the n-type semiconductor substrate 41 has a specific resistance ρ of about 0.015 Ω · cm and a thickness of about 80 μm, and the p-type semiconductor layer 12 has a specific resistance ρ of about 3 Ω · cm to 4 Ω · cm and a thickness of about 10 μm.

  Furthermore, in the present embodiment, an n-type impurity region 81 that is exposed on the outermost peripheral side surface of the chip (p-type semiconductor layer 12) and reaches the n-type semiconductor substrate 41 is provided. Since the amplifier circuit device 10 has the p-type semiconductor layer 12 laminated on the n-type semiconductor substrate 41, the pn junction surface is exposed on the end side surface of the chip, but the pn junction surface exposed on the end side surface of the chip. There may be a leak. In the present embodiment, the n-type impurity region 81 is provided on the side surface of the chip end to prevent the exposure of the pn junction on the outermost peripheral side surface of the chip, thereby suppressing leakage.

  Here, the n-type impurity region 81 is formed by ion implantation so as to reach the n-type semiconductor substrate 41 from the chip surface. In the present embodiment, the thickness of the p-type semiconductor layer 12 is set to a minimum thickness as long as the depletion layer expands so that a required capacitance can be obtained and a desired electrostatic breakdown voltage can be secured. Can do. Therefore, the distance (depth) from the surface of the chip to the n-type semiconductor substrate 41 can be reduced, and the n-type impurity region 81 for preventing leakage can be provided by ion implantation and diffusion.

  The chip of the amplifier circuit device 10 in which the J-FET 1, the resistor 2, and the diode 3 are integrated and the capacitor 4 is formed on the back surface is covered and integrally supported by a sealing member (not shown) together with the conductive member 42. The sealing member is, for example, a sealing resin package, but a metal can package or a ceramic package can also be used.

  As described above, according to this embodiment, the p-type semiconductor layer 12 is provided on the n-type semiconductor substrate 41 so that the capacitor 4 is connected in series to the gate of the J-FET 1, and the same n-type semiconductor substrate as the J-FET 1 is used. Since the high-pass filter 5 is composed of the resistor 2 and the capacitor 4 for stabilizing the gate potential integrated in the circuit 41, an increase in chip thickness can be avoided. That is, the high-pass filter 5 can be built in the amplifier circuit device 10 without increasing the chip size (area) or the package outer size.

  Further, if the required capacitance and electrostatic breakdown voltage can be ensured, the p-type semiconductor layer 12 can be made to the minimum thickness. Therefore, an n-type impurity region 81 for preventing the pn junction from being exposed is provided on the side surface of the chip end. And leakage at the end of the chip can be suppressed.

  The p-type semiconductor layer 12 may be a region formed on the n-type semiconductor substrate 41 by ion implantation and diffusion of impurities. In that case, a single n-type semiconductor layer is provided on the p-type semiconductor layer 12, and the n-type semiconductor regions 14a, 14b, and 14c are separated by the high-concentration p-type impurity region 50 reaching the p-type semiconductor layer 12. At the same time, the first region r1, the second region r2, and the third region r3 may be partitioned. Alternatively, a single p-type epitaxial layer or the like may be provided on the p-type semiconductor layer 12, and the n-type semiconductor regions 14a, 14b, and 14c may be individually provided by ion implantation and diffusion.

  In the present embodiment, the p-type semiconductor layer 12 is provided on the n-type semiconductor substrate 41, the capacitor 4 is connected in series to the gate of the J-FET 1, and the capacitor 4 and the J-FET 1 are accommodated in the same sealing member. Thus, the high-pass filter 5 is constituted by the resistor 2 for stabilizing the gate potential.

  Therefore, the configuration is not limited to the configuration shown in FIG. 6, for example, the p-type semiconductor layer 12 is provided on the n-type semiconductor substrate 41 on which the J-FET 1 is formed alone and fixed to the conductive member 42, thereby forming the gate of the J-FET 1. The capacitor 4 may be connected in series, and the resistor 2 and the diode 3 may be provided on a substrate (chip) different from the J-FET 1 and housed in a single sealing member.

  As described above, the n-channel J-FET has been exemplified in the present embodiment, but the same effect can be obtained even with a J-FET having a reversed conductivity type.

1 J-FET
2 Resistance 3 Diode 3
4 capacitance 5 high-pass filter 12 p-type semiconductor layer 14a, 14b, 14c n-type semiconductor region 15 source region 16 drain region 17 gate region 41 n-type semiconductor substrate 42 conductive member 50 high-concentration p-type impurity region 50
61 First source electrode 62 First drain electrode 63, 64, 73 Wiring 71 Second source electrode 72 Second drain electrode 91 First insulating film 92 Second insulating film 93 Third insulating film

Claims (8)

One conductivity type semiconductor layer;
A reverse conductivity type semiconductor region provided on the one conductivity type semiconductor layer;
A reverse conductivity type source region and drain region provided on the surface of the reverse conductivity type semiconductor region;
A gate region of one conductivity type provided on the surface of the reverse conductivity type semiconductor region;
A high concentration one conductivity type impurity region provided around the one conductivity type semiconductor layer and having a depth reaching from the surface of the reverse conductivity type semiconductor region to the one conductivity type semiconductor layer;
A resistor having one end electrically connected to the source region and the other end electrically connected to the one conductivity type semiconductor layer;
A reverse conductivity type semiconductor substrate provided on the other main surface of the one conductivity type semiconductor layer;
A conductive member fixed to the opposite conductivity type semiconductor substrate and applied with a gate potential;
An amplifying circuit device comprising: The reverse conductivity type semiconductor substrate and the one conductivity type semiconductor layer are partitioned into a first region and a second region,
The reverse conductivity type semiconductor region, the source region, the drain region, and the gate region are provided above the first region, and the high concentration one conductivity type impurity region is provided around the first region,
The resistor is provided above the second region, and the other end is electrically connected to the one-conductivity-type semiconductor layer in the first region via the one-conductivity-type semiconductor layer in the second region. The amplifier circuit device according to claim 1, wherein:   3. The amplifier circuit device according to claim 1, wherein a high-pass filter is configured by a junction capacitance of the reverse conductivity type semiconductor substrate and the one conductivity type semiconductor layer and the resistance.   4. The amplifier circuit device according to claim 1, further comprising a reverse conductivity type impurity region exposed on a side surface of the one conductivity type semiconductor layer.   5. The amplifier circuit device according to claim 1, wherein the high-pass filter has a cutoff frequency near a lower limit of an audible frequency band.   6. The voltage gain of the high-pass filter expressed by using the capacitance of the capacitor and the resistance value of the resistor is 0.9 or more in an audible frequency band. The amplifier circuit device according to 1.   The amplifier circuit device according to claim 6, wherein the capacitance is 1 pF to 50 pF.   The reverse-conductivity-type semiconductor substrate and the one-conductivity-type semiconductor layer are partitioned into a third region. Above the third region, another reverse-conductivity-type semiconductor region electrically connected to the other end of the resistor, and the source 8. The amplifier circuit device according to claim 1, further comprising: a diode including one conductivity type impurity region electrically connected to the region.

Images