JP2012049595A - Communication interface device, and semiconductor device having the communication interface device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a multilane communication interface device that synchronizes parallel clock signals across lanes while suppressing an increase in current consumption.SOLUTION: A serial clock signal is supplied to a serial clock line 21. In a lane 1, the serial clock signal is input from the serial clock line and distributed into a first lane, flip-flops (FF) 12 and 13 are cascaded with the serial clock signal as a sampling clock signal and an inverted signal of the output of the FF 13 is fed back into the FF 12 to whereby constitute a frequency division circuit, and the output signal of the FF 13 is distributed as a parallel clock signal into Lane 1. In a lane 2, the serial clock signal is input and distributed into the lane, the output of the FF 12 of the lane 1 is received and sampled by the serial clock signal of the lane 2 in an FF 13, and the output of the FF 13 is distributed as a parallel clock signal into Lane 2 and fed back into the FF 12 of the lane 2.

Description

  The present invention relates to a communication interface apparatus, and more particularly to an apparatus suitable for clock synchronization of a communication interface apparatus having a plurality of lanes.

  In the serial communication interface (SerDes: Serializer / Deserializer), the receiving unit recovers the clock and data from the received data by clock and data recovery (CDR), deserializes (converts serial data to parallel data), and is sent by the transmitting unit. Serial data is serialized and transmitted. In the PCI Express 1.1 standard or the like, the clock frequency requires a 2.5 GHz high-speed clock (serial clock) in order to transmit a data stream of 2.5 Gb / s per lane (transmission path). Incidentally, in the PCI Express 2.0 standard, it is 5 Gb / s and requires a high-speed clock (serial clock) of 5 GHz.

  In the communication interface, a serial clock signal is distributed to each lane, and a divided clock signal obtained by dividing the serial clock signal (which is called a “parallel clock signal” because it is used as a clock signal for driving a parallel signal) is distributed. Is done.

  In the lane, the parallel clock signal is distributed to a sequential circuit or the like that samples parallel data obtained by serial-parallel conversion of serial data. It is necessary to adjust the timing of the parallel clock signal between the lanes (synchronization of the parallel clock signal between the lanes) and adjust the delay between the parallel clock signal and the serial clock signal.

  The inventor of the present application adjusts a delay of a divided clock signal (divided clock signal for serial-parallel conversion) between a plurality of lanes in a semiconductor device having a serial communication interface such as SERDES. A configuration that uses a clock signal is proposed (Patent Document 1).

JP 2006-109426 A

  As described above, in a multi-lane serial communication interface, it is necessary to adjust the timing of a parallel clock signal between a plurality of lanes and adjust the timing with a serial clock signal having a frequency on the order of GHz.

  According to the present invention, in order to solve at least one of the above-described problems, there is no particular limitation.

  According to the present invention, a clock driving circuit is provided for supplying a first clock signal to a first clock signal line to which a plurality of lanes are connected in common, and the plurality of lanes include first and second lanes. The first lane receives the first clock signal from the first clock signal line and distributes the first clock signal in the first lane, and the first clock signal (or a divided signal thereof) is distributed to the first lane. A cascade-connected M-stage flip-flop (where M is an integer of 2 or more) that is commonly input as a sampling clock signal is provided, and an inverted signal of the output of the M-th flip-flop is fed back to the first-stage flip-flop. The output of the M-th flip-flop is distributed as a second clock signal in the first lane, and the second lane is connected to the first clock signal line from the first clock signal line. The clock signal is input and distributed in the second lane, and the output of the (M−1) -th flip-flop input to the M-th flip-flop of the first lane is input to the first lane. And a second flip-flop that receives the first clock signal (or a frequency-divided signal thereof) as a sampling clock and receives the first flip-flop as an input via a second clock signal line between the second lane and the second lane. And a communication interface device in which an output of the first flip-flop is distributed as a second clock signal in the second lane.

In the present invention, the plurality of lanes further include third to S-th (where S is an integer of 3 or more) lanes,
The first lane (where I is an integer not less than 3 and not greater than S) is
Input the first clock signal from the first clock signal line and distribute it in the I-th lane;
The output of the last stage of the cascade-connected (M-1) stage flip-flops that receives the output of the first flip-flop in the adjacent (I-1) th lane at the first stage is taken as the (I-1 ) And the second clock signal line between the first lane and the first lane as an input, and the first clock signal (or a divided signal thereof) in the first lane is used as a sampling clock signal. A first flip-flop that samples the input is provided, and an output of the first flip-flop of the I lane is distributed as a second clock signal in the I lane.

In the present invention, the Jth lane (where J is an integer of 2 or more and S or less) is
Cascaded (M-1) stage flip-flops using the first clock signal (or its frequency-divided signal) as a common sampling clock;
The output of the final flip-flop of the (M-1) flip-flop;
The second clock signal line between the (J-1) th lane and the Jth lane;
Are connected to the first and second inputs,
The output comprises a selector connected to the input of the first flip-flop of the Jth lane, and the inverted output of the first flip-flop of the Jth lane is of the (M-1) stage. It is connected to the input of the first flip-flop of the flip-flop.

  According to the present invention, the timing of the parallel clock signal between the lanes can be matched. Further, according to the present invention, it is possible to adjust the delay between the parallel clock signal and the serial clock signal between the lanes.

It is a figure which shows the structure of the 1st Embodiment of this invention. It is a timing diagram explaining the operation example of the 1st Embodiment of this invention. It is a figure which shows the structure of the 2nd Embodiment of this invention. It is a timing diagram explaining the operation example of the 2nd Embodiment of this invention. It is a timing diagram explaining another operation example of the second embodiment of the present invention. It is a figure which shows the structure of the 3rd Embodiment of this invention. It is a figure which shows the modification 1 of the structure of the 3rd Embodiment of this invention. It is a figure which shows the modification 2 of the structure of the 3rd Embodiment of this invention. It is a timing diagram explaining the operation example of the 3rd Embodiment of this invention. 5 is a diagram showing a configuration of Comparative Example 1. FIG. 6 is a timing chart for explaining the operation of Comparative Example 1. FIG. 10 is a diagram showing a configuration of Comparative Example 2. FIG. 10 is a timing chart for explaining the operation of Comparative Example 2. FIG. 10 is a diagram showing a configuration of Comparative Example 3. FIG. 10 is a timing chart for explaining the operation of Comparative Example 3. FIG.

  Embodiments of the present invention will be described below. The present invention does not employ a method of distributing the parallel clock among the lanes, generates a parallel clock by dividing the serial clock in the first lane, and in the second and subsequent lanes, one clock of the adjacent lane on the younger side. By latching the previous frequency-divided waveform with a clock signal for synchronization timing (serial clock signal in the lane), a parallel clock signal waveform is generated at the same timing between multiple lanes.

  In one aspect (MODES) of the present invention, a clock drive circuit (20) for outputting a first clock signal (serial clock signal) to a first clock signal line (serial clock signal line 21 in FIG. 1) is provided. The first lane (lane 1) receives the first clock signal from the first clock signal line, distributes the first clock signal in the first lane, and uses the first clock signal as a sampling clock signal. Are connected to cascaded M-stage flip-flops (12, 13), where M is an integer greater than or equal to 2, and the inverted signal of the output of the M-th stage flip-flop (13) is the first stage flip-flop (12) is fed back and the output of the M-th flip-flop (13) is input to the first lane as a second clock signal (parallel clock signal). It is arranged. The second lane (lane 2) receives the first clock signal from the first clock signal line and distributes the first clock signal in the second lane, and the M-th flip-flop of the first lane. The output of the (M−1) -th stage flip-flop (12) input to the clock (13) is sent via the second clock signal line (parallel clock signal line 22) between the first and second lanes. And receiving a first flip-flop (13) for sampling the input using the first clock signal in the second lane or its divided signal as a sampling clock signal, The output of the flip-flop (13) is distributed in the second lane as a second clock signal (parallel clock signal).

  Further, third to S-th (where S is an integer of 3 or more) lanes are provided, and the I-th lane (where I is an integer of 3 or more and S or less) is connected to the first clock signal line (21 ) To input the first clock signal and distribute it in the I-th lane. Further, the cascade-connected (M-1) stage provided in the adjacent (I-1) lane and receiving the output of the first flip-flop (13) in the (I-1) lane. The output of the flip-flop (12) is received as an input via the second clock signal line (22) between the (I-1) th lane and the Ith lane, and within the Ith lane. The first flip-flop (13) that samples the input using the first clock signal or the divided signal thereof as a sampling clock signal, and the output of the first flip-flop (13) in the I-th lane Are distributed in the I-th lane as a second clock signal.

  In one aspect (MODES) of the present invention, the J-th lane (where J is an integer of 2 or more and S or less) is the first clock signal or the divided signal of the first clock signal. (M-1) stages (where M is an integer equal to or greater than 2) flip-flops (12). Further, the second clock signal line (22) between the (J-1) th lane and the Jth lane, and the output of the final stage flip-flop (12) of the (M-1) th stage flip-flop. And a selector (14) having first and second inputs connected to each other and an output connected to the input of the first flip-flop (13) of the Jth lane. The inverted output of the first flip-flop (13) is fed back to the input of the first flip-flop (12) of the (M-1) -th flip-flop, and the second transferred from the adjacent lane. The clock signal (parallel clock signal) can be sampled and used as the second clock signal in the lane, or the first clock signal can be divided in the lane to generate the second clock signal. .

  In another aspect of the present invention (MODES), the Jth lane (where J is an integer of 2 or more and S-1 or less) uses the first clock signal as a common sampling clock signal. The first stage is the output of the first flip-flop (13 in FIG. 3) in the Jth lane, and the (N-1) th stage (where N is a predetermined integer equal to or greater than 2) 3), the output of the (N−1) th stage flip-flop of the shift register of the Jth lane is the output of the Jth lane and the (J + 1) th lane. A configuration may be adopted in which the signal is input to the first flip-flop (13) of the (J + 1) th lane via a second clock signal line (22) provided between the lanes.

  In another aspect of the present invention (MODES), the Jth lane (where J is an integer of 2 or more and S or less) inputs the first clock signal as a common sampling clock signal. , Cascade-connected (M−1) -stage flip-flops (12 ′: M = 2 in FIG. 3), and provided between the (J−1) th lane and the Jth lane. First and second inputs to the second clock signal line (22) and the final stage output of the cascaded (M-1) stage flip-flop (12 ') of the Jth lane Are connected to each other, and an output is connected to an input of the first flip-flop (13) of the Jth lane, and an output of the first flip-flop of the Jth lane Before the Jth lane It is feedback input to the cascaded (M-1) stage of the stages of flip-flops (12 '). When the selector (14) selects the second input, the cascaded (M−1) -stage flip-flop (12 ′) of the Jth lane and the first flip-flop of the Jth lane (13) are cascade-connected to form a first frequency dividing circuit composed of M-stage flip-flops. On the other hand, when the selector (14) selects the first input, a signal from the second clock signal line (22) provided between the (J-1) th lane and the Jth lane is received. , And input to the input of the first flip-flop (13) of the Jth lane. For the Jth lane where J is 2 or more and (S-1) or less, the output of the final stage of the (M-1) th flip-flop is provided between the Jth lane and the (J + 1) th lane. The signal is output to the (J + 1) th lane via the second clock signal line.

  In another aspect of the present invention (MODES), in the Jth lane (where J is an integer of 2 or more and S-1 or less), the output of the first flip-flop (13) is output. , Input to the first stage of the shift register comprising the (N−1) th stage flip-flops, and the output of the last stage of the shift register is provided between the Jth lane and the (J + 1) th lane. A configuration may be adopted in which the signal is input to the first flip-flop (13) of the adjacent (J + 1) th lane via the second clock signal line (22). The N corresponds to N when the second clock signal distributed in each lane is obtained by dividing the first clock signal by 2N.

  In yet another aspect of the present invention (MODES), each lane divides the first clock signal input into the lane by a second frequency dividing circuit (FIGS. 6, 7, and 8). 15), the frequency division signal of the first clock signal output from the second frequency divider circuit is distributed in each lane, and the first frequency divider circuit of the first lane The M-stage flip-flops (12 and 13 in FIGS. 6, 7, and 8) are frequency-divided signals of the first clock signal output from the second frequency-dividing circuit in the first lane. Is the common sampling clock signal, and the first flip-flop (13 in FIGS. 6, 7, and 8) in the I-th lane (I is 2 or more and S or less) The frequency-divided signal of the first clock signal output from the second frequency divider circuit is sampled. It may be configured to ring clock signal.

  In yet another aspect of the present invention (MODES), the first stage (FIGS. 7 and 8) of the flip-flops constituting the second frequency divider circuit in the I-th lane (I is not more than 2 S). 16) through a selector (17 in FIGS. 7 and 8), a first divided clock signal line (between the adjacent (I-1) lane and the I lane) ( 23) The frequency-divided signal of the first clock signal from the second frequency-dividing circuit (15) in the (I-1) th lane transferred via (23) may be inputted. The selector (17) includes a first divided clock signal line (23) provided between an adjacent (I-1) lane and the I lane, and the second lane of the I lane. The output of the frequency divider circuit (15) is input to the first and second inputs, one is selected based on the selection signal, and the output of the selector is the flip-flop (15) constituting the second frequency divider circuit. ). Depending on the configuration of the second frequency divider circuit, an inverted signal of the output of the selector is input to the first stage of the flip-flop (15) that constitutes the second frequency divider circuit.

  In still another aspect of the present invention (MODES), the first lane includes one or more stages of flip-flops that use the first clock signal input into the first lane as a sampling clock signal. And the M-stage flip-flop (12, 13) of the first frequency divider circuit of the first lane includes the second frequency divider circuit of (15). The frequency-divided signal of the first clock signal output from the frequency divider 2 is used as a common sampling clock signal. The I-th lane (I is 2 or more and S or less) has K stages (where K is an integer of 1 or more) in which the first clock signal input into the I-lane is the common sampling clock signal. Transfer via a second frequency divider circuit having a flip-flop (15) and a first frequency-divided clock signal line provided between the adjacent (I-1) lane and the I-th lane. The first stage of the frequency-divided signal of the first clock signal in the (I-1) th lane is input to the first stage, and the shift is made up of a 2K-stage flip-flop (16) that is input as a common sampling clock signal. And outputs the output of the second frequency divider circuit (15) and the output of the final stage of the shift register comprising the 2K-stage flip-flop (16) to the first and second inputs. To the second selector (17 The output (17) of the second selector is distributed in the I lane as a divided signal of the first clock signal, and the I lane (I is 2 or more S or less) The first flip-flop in (1) uses the frequency-divided signal of the first clock signal output from the second selector (17) in the I-th lane as a sampling clock signal. Hereinafter, a description will be given according to exemplary embodiments.

<Embodiment 1>
FIG. 1 is a diagram showing the configuration of the first exemplary embodiment of the present invention. The clock driving circuit 20 receives a clock signal (eg, on the order of GHz) from a PLL (phase-locked loop) or the like (not shown), and outputs a serial clock signal to the first clock signal line 21 to which a plurality of lanes are connected in common. To do.

  The first lane (lane 1) 10 includes a receiver 11 that inputs a serial clock signal from the serial clock signal line 21, and the serial clock signal output from the receiver 11 is distributed in the lane 1. Cascade-connected two-stage flip-flops 12 and 13 that commonly input a serial clock signal as a sampling clock signal, and an inverted signal (inverted output) of the output of the second-stage flip-flop 13 is the first-stage flip-flop 12. Is provided with a frequency dividing circuit for feedback input. The output of the second stage flip-flop 13 is distributed in the lane 1 as a parallel clock signal.

  In FIG. 1, ◯ of the input terminal (data terminal) of the flip-flop 12 represents an inverting input (negative logic input). When the output of the flip-flop 13 is 1, 0 is input. When the output is 0, it is equivalent to inputting 1. The flip-flops 12 and 13 usually have an output terminal (normal output terminal) (Q) and an inverted output terminal (QB) that outputs an inverted signal of the output terminal (Q). The inverted output (QB) of the flip-flop 13 is connected in feedback to the data terminal (D) of the flip-flop 12, and the output signal from the output terminal (Q) of the flip-flop 13 is distributed as a parallel clock signal in the lane 1. This indicates that the output terminal (Q) of the flip-flop 12 is connected to the data terminal (D) of the flip-flop 13. In FIG. 1 and subsequent figures, for simplicity, the data terminal of the flip-flop 12 is represented by a negative logic input. However, the flip-flop 12 inputs the inverted output of the flip-flop 13 or the inverted signal of the output signal of the flip-flop to the data terminal. Is equivalent to

  The second lane (lane 2) 10 includes a receiver 11 that inputs a serial clock signal from the serial clock signal line 21, and the serial clock signal output from the receiver 11 is distributed in the second lane. The output of the first-stage flip-flop 12 of the first lane 10 (input to the data terminal of the second-stage flip-flop 13) is connected to the parallel clock signal line 22 between the first and second lanes, and The input is received through the selector 14 of the second lane (lane 2), and the input is sampled by using the serial clock signal distributed in the lane from the receiver 11 of the second lane (lane 2) 10 as the sampling clock signal. The output of the flip-flop 13 is distributed in the second lane as a parallel clock signal.

  The third lane (lane 3) 10 includes a receiver 11 that inputs a serial clock signal from the serial clock signal line 21, and the serial clock signal output from the receiver 11 is distributed in the third lane. The output of the flip-flop 12 of the adjacent second lane is received at the input via the parallel clock signal line 22 between the second lane and the third lane and the selector 14 in the lane 3. A flip-flop 13 that samples the input using a serial clock signal output from the receiver 11 as a sampling clock signal is provided, and an output of the flip-flop 13 is distributed in the third lane as a parallel clock signal.

  Similarly, when the fourth and subsequent lanes are provided, the I-th lane (where I is a predetermined integer equal to or greater than 4) includes the receiver 11 that inputs the serial clock signal from the serial clock signal line 21. The serial clock signal output from 11 is distributed in the I-th lane. The output of the flip-flop 12 of the adjacent (I-1) lane is connected to the second clock signal line 22 between the (I-1) lane and the I lane, and the (I-1) lane. And a flip-flop 13 that samples the input using a serial clock signal output from the receiver 11 as a sampling clock, and the output of the flip-flop 13 serves as the parallel clock signal. Distributed within.

  In the present embodiment, each of the second and subsequent lanes 10 includes a flip-flop 12 that uses a serial clock signal distributed from the receiver 11 in the lane as a sampling clock in common with the flip-flop 13, and the adjacent lane and the lane The first and second inputs are connected to the parallel clock signal line 22 and the output of the flip-flop 12, respectively, and the output includes a selector 14 connected to the input of the flip-flop 13 of the lane. An inverted signal of the output of the flip-flop 13 is feedback-connected to the input of the flip-flop 12. When using the parallel clock signal transferred from the adjacent lane via the parallel clock signal line 22 based on the selection signal sel, the selector 14 selects the first input and selects the parallel clock signal line 22 from the adjacent lane. The parallel clock signal transferred via the signal is supplied to the input of the flip-flop 13.

  In each of the second and subsequent lanes 10, the parallel clock signal is generated by dividing the serial clock signal in the lane without using the parallel clock signal transferred from the adjacent lane via the parallel clock signal line 22. The selector 14 selects the second input and supplies the output of the flip-flop 12 to the input of the flip-flop 13. The flip-flops 12 and 13 function as a divide-by-4 circuit. When the parallel clock signal is generated by dividing the serial clock signal in the lane (when the second input is selected by the selector 14), the delay adjustment of the parallel clock signal is not performed between the lanes, Synchronization of the parallel clock signal is not guaranteed.

  In the configuration shown in FIG. 1, the two-stage cascaded flip-flops 12 and 13 in the first lane form a divide-by-4 circuit. In the present invention, the frequency division number of the parallel clock signal is Of course, is not limited to divide by 4. For example, there are M stages (M is an integer of 2 or more) cascaded, a flip-flop that feeds back the inverted signal of the output of the final stage to the first stage, and an output (M stage) flip-flop of the M-1 stage flip-flop. May be supplied to the input of the flip-flop 13 of the second lane via the parallel clock line 22. In this case, in the second lane, the flip-flop 12 is cascaded in the (M−1) th stage, and the output of the M−1th stage flip-flop and the parallel clock line 22 from the first lane are input to the selector 14. It will be. The same applies to other lanes. Further, the frequency division value is not limited to a multiple of 2, and may be arbitrary.

  FIG. 2 is a timing diagram illustrating the operation of one embodiment of the present invention. 2 shows a serial clock signal (a) distributed to lanes 1, 2, and 3 and a parallel clock signal distributed within each lane in each of lanes 1, 2, and 3 (the output of the flip-flop 13 in each lane). ) Are indicated by solid line waveforms (b), (d), and (f), and are transferred from lane 1 to lane 2 and from lane 2 to lane 3 via parallel clock signal line 22 (flip-flop 12). Are shown by broken line waveforms (c) and (e). In FIG. 2, the parallel clock signal is generated by dividing the serial clock signal by 6. In this divide-by-6 configuration, in FIG. 1, each lane further includes a flip-flop 12 after the flip-flop 12 that inputs the output of the flip-flop 13, and the output of the second flip-flop 12 passes through the selector 14. To the flip-flop 13. The flip-flops 12 and 13 use the serial clock signal from the receiver as a common sampling clock signal.

  As shown in FIG. 2, in each lane after the second lane, the parallel clock signal before one clock (serial clock signal) of the adjacent lane on the younger side passes through the parallel clock line 22 in each lane. The flip-flop 13 samples the transferred parallel clock signal at the rising edge of the next serial clock signal, so that the timing of the parallel clock signal distributed in each lane Can be combined between two or three. Further, each lane is not provided with a clock driving circuit that distributes the parallel clock signal, and delay adjustment of the parallel clock signal and the serial clock signal is facilitated.

<Embodiment 2>
FIG. 3 is a diagram showing a configuration of the second exemplary embodiment of the present invention. The first lane and the third lane in FIG. 3 have the same configuration as in FIG. The second lane includes the receiver 11 that receives the serial clock signal from the serial clock signal line 21 and the output of the flip-flop 12 that is input to the flip-flop 13 of the first lane. A selector 14 that receives a first input via a parallel clock signal line 22 provided therebetween, and a flip-flop 13 (first flip-flop) that receives the output of the selector 14 are provided. The output of the flip-flop 13 is a parallel clock. The signal is distributed in the second lane. Further, the first stage flip-flop 12 receives the output of the flip-flop 13 as an input and the serial clock signal from the receiver 11 in the second lane is commonly received as a sampling clock signal. It has a register. Further, the second lane 10 ′ includes a flip-flop 12 ′ that receives an inverted signal of the output of the flip-flop 13 as an input and receives a serial clock signal from the receiver 11 in the second lane as a sampling clock signal. The output of the flip-flop 12 ′ is connected to the second input of the selector 14.

  In the example of FIG. 3, the parallel clock signal is generated by dividing the serial clock signal by four. In the second lane (lane 2) 10 ′, the three-stage flip-flop 12 constitutes a shift register, and when the first input is selected by the selector 14, the three-stage flip-flop 12 is coupled with the flip-flop 13. A four-stage shift register is formed to adjust the timing of the parallel clock signal. That is, when using the divided clock signal (parallel clock signal) transferred from the adjacent lane 1 via the parallel clock signal line 22, the selector 14 selects the first input based on the selection signal sel, and the flip-flop. The output of the flip-flop 13 is input to the first stage of a shift register including the three-stage flip-flop 12. That is, the divided clock signal (parallel clock signal) transferred from the adjacent lane 1 via the parallel clock signal line 22 is sampled by the flip-flop 13, and the output is sequentially passed through the three-stage flip-flop 12. The parallel clock signal transferred and sampled by the flip-flop 13 of the second lane is delayed by three cycles of the serial clock signal, via the parallel clock signal line 22 and via the selector 14 in the third lane. The signal is input to the flip-flop 13 in the third lane and sampled with a delay of 4 cycles of the serial clock signal (one cycle of the parallel clock signal).

  The output sampled with the serial clock signal by the flip-flop 13 of the second lane is advanced by three cycles of the serial clock signal from the parallel clock signal transferred to the third lane via the parallel clock signal line 22. Yes. Note that the parallel clock signal sampled by the flip-flop 13 in the second lane is distributed in the second lane.

  When a parallel clock signal is generated by dividing the serial clock signal in the lane without using the parallel clock signal transferred from the adjacent lane 1 via the parallel clock signal line 22, the parallel clock signal is generated based on the selection signal sel. The selector 14 selects the second input, supplies the output of the flip-flop 12 'to the input of the flip-flop 13, and the flip-flops 12' and 13 function as a divide-by-4 circuit.

  The third lane (lane 3) (10 ′) outputs the output from the flip-flop 12 at the final stage constituting the three-stage shift register of the adjacent second lane (lane 2), and the second lane and the third lane. A selector 14 that receives the first input via the parallel clock signal line 22 between the lanes is provided, the output of the selector 14 is input to the flip-flop 13, and the inverted signal of the output of the flip-flop 13 is input to the input of the flip-flop 12. Returned. The output of the flip-flop 12 is connected to the second input of the selector 14. The output of the flip-flop 13 is distributed in the third lane as a parallel clock signal. When using the parallel clock signal transferred from the adjacent lane via the parallel clock signal line 22, the selector 14 selects the first input and transfers it from the adjacent lane via the parallel clock signal line 22. The parallel clock signal is supplied to the input of the flip-flop 13. When the parallel clock signal is generated by dividing the serial clock signal in the lane without using the parallel clock signal transferred from the adjacent lane via the parallel clock signal line 22, the selector 14 receives the second input. The output of the flip-flop 12 is selected and supplied to the input of the flip-flop 13, and the flip-flops 12 and 13 function as a divide-by-4 circuit.

  In the case of the S lane configuration (S is an integer of 4 or more), the second to (S-1) lanes have the same configuration as the second lane, and the S lane corresponds to the third lane in FIG. Same configuration as the lane.

  FIG. 4 is a timing chart for explaining the operation of the present embodiment shown in FIG. In FIG. 4, the parallel clock signal is generated by dividing the serial clock signal by 6. In FIG. 3, each lane further includes a flip-flop 12 at the subsequent stage of the flip-flop 12 that inputs an inverted signal of the output of the flip-flop 13, and the output of the second-stage flip-flop 12 passes through the selector 14 to the flip-flop 13. Is input. The flip-flops 12 and 13 use the serial clock signal from the receiver as a common sampling clock signal. The shift register composed of the flip-flops 12 in the second lane (lane 2) is composed of five stages of flip-flops.

  The serial clock signal (a) distributed to the lanes 1, 2, and 3 and the parallel clock signal (output of the flip-flop 13 of each lane) distributed within the lanes in the lanes 1, 2, and 3 are solid line waveforms (b ), (D), (i). A waveform (c) is a parallel clock signal (output of the flip-flop 12) transferred from the lane 1 to the lane 2 via the parallel clock signal line 22. In lane 2, the waveform obtained by sampling the parallel clock signal (waveform (c)) transferred from lane 1 via the parallel clock signal line 22 by the flip-flop 13 is distributed as the parallel clock signal in lane 2 and softened. Feedback is made to the flip-flop 12-1 at the first stage of the register, and the flip-flop 12-1 outputs a waveform (e) delayed by one clock, and the flip-flops at the next stage and later are delayed by one clock cycle from the output of the previous flip-flop. The output (waveform (h)) of the shift register composed of six stages of flip-flops is input to the lane 3 via the parallel clock line 22, and the lane 3 flip-flops are output. Sampled at 13. The output of the flip-flop 13 in lane 3 is distributed in the lane as a parallel clock signal (i) in lane 3.

<Embodiment 2: Modification>
FIG. 5 is a timing chart showing a modified example of the operation of the present embodiment. In FIG. 5, the serial clock signal (a) distributed to lanes 1, 2, and 3 and the parallel clock signal (output of the flip-flop 13 of each lane) distributed within the lanes in lanes 1, 2, and 3 are solid lines. Waveforms (b), (d), and (g) of FIG. A waveform (c) is a parallel clock signal (output of the flip-flop 12 in the lane 1) transferred from the lane 1 to the lane 2 via the parallel clock signal line 22. In lane 2, the waveform (d) obtained by sampling the parallel clock signal (waveform (c)) transferred from lane 1 via the parallel clock signal line 22 by the flip-flop 13 is distributed as the parallel clock signal in lane 2. At the same time, it is fed back to the first flip-flop 12 of the shift register. At that time, the waveform (d) is inverted by the inverter, and the phase is delayed by 180 degrees. The first stage flip-flop outputs a waveform (e) obtained by delaying the inverted signal of the waveform (d) by one clock cycle (60 degrees in phase) of the serial clock signal, and the next stage flip-flop 12 outputs the waveform (e ) Is delayed to one clock cycle (60 degrees in phase) of the serial clock signal, and the waveform (f) is output to the parallel clock line 22. The flip-flop 13 in lane 3 samples the waveform (f) with the serial clock signal in lane 3. The output of the flip-flop 13 in lane 3 is distributed in the lane as a parallel clock signal waveform (h) in lane 3.

  According to the embodiment of FIG. 5, when the parallel clock signal is the serial clock signal divided by 6, the inverted signal of the flip-flop 13 of FIG. 3 is input to the first stage of the shift register. The flip-flops 12 constituting the shift register whose output is connected to the selector 14 need only be two stages.

  On the other hand, in FIG. 4, the flip-flops 12 (flip-flops 12 and 13 in the second lane) constituting the shift register have a five-stage configuration. When the parallel clock signal is a serial clock signal divided by 4, the flip-flop 12 constituting the shift register whose output is connected to the selector 14 needs only one stage. On the other hand, in the embodiment of FIG. 4, the flip-flop 12 constituting the shift register has a two-stage configuration (corresponding to the configuration of FIG. 3).

<Embodiment 3>
FIG. 6 is a diagram showing the configuration of the third exemplary embodiment of the present invention. Referring to FIG. 6, the present embodiment differs from the previous embodiment of FIG. 1 in that the serial clock signal output from the receiver 11 is frequency-divided by two by the flip-flop 15 in the first lane (10 ″). The signal is used as a sampling clock signal for the flip-flops 12 and 13. The output of the flip-flop 12 is output to the second lane via the parallel clock signal line 22, and the output of the flip-flop 13 is the first. Are distributed as parallel clock signals in each lane.

  In each of the second and third lanes (lanes 2 and 3), the serial clock signal input into the second and third lanes is used as a sampling clock signal, and the output is fed back as an inverted signal into the lane. A flip-flop 15 is provided. When the input serial clock is distributed in the lane, the output of the flip-flop 15 is distributed in the second and third lanes as a divided signal of the serial clock signal via the selectors 17 and 18. The output signal of the flip-flop 15 is distributed as a serial clock in the lane via the selector 18, and the inverted signal is input to the data terminal of the flip-flop 15 via the selector 17, and the flip-flop 15 receives the signal of the data terminal. Sample in response to the output of the receiver 11.

  The frequency-divided signal of the serial clock signal output from the flip-flop 15 of the first lane 10 ″ is divided into the second frequency via the serial frequency-divided clock signal line 23 provided between the first lane and the second lane. Lane 10 ″.

  In the second lane, the first stage receives the divided signal of the first clock signal input from the first lane via the serial divided clock signal line 23, and the serial clock signal from the receiver 11 is used as the sampling clock. The shift register includes flip-flops 16 that are cascade-connected in two stages.

  Further, the inverted output is fed back to the input, and the serial clock signal in the second lane is used as the sampling signal, and the output of the flip-flop 15 constituting the divide-by-2 circuit and the serial clock signal in the second lane are used as the sampling signal. A selector 17 is provided for inputting the output of the final stage of the two-stage flip-flop 16 constituting the shift register to the first and second inputs, and the output of the selector 17 is a divided signal of the first clock signal. Are distributed in the second and third lanes. The output of the selector 17 of the second lane is supplied to the third lane via the serial frequency-divided clock signal line 23.

  When the selector 17 selects the second input, the frequency-divided serial clock signal transferred from the adjacent first lane via the serial frequency-divided clock signal line 23 is shifted by a shift register including two stages of flip-flops 16. The timing-adjusted signal is distributed in the second lane and further transferred to the third lane via the serial divided clock signal line 23. When the divided serial clock signal from the adjacent lane is not used, the selector 17 selects the first input, and the output of the divide-by-2 circuit (15) in the second lane is distributed to the second lane. The The same applies to the third lane. However, the third lane does not transfer the serial frequency-divided clock signal to the fourth lane when there is no adjacent lane (fourth lane). Note that when the serial frequency-divided clock signal is used from the adjacent first lane, the operation of the flip-flop 15 may be stopped by performing control such as stopping the supply of the sampling clock signal. Further, when the divided clock signal is generated in the lane (when the flip-flop 15 is operated), the operation of the flip-flop 16 may be stopped.

  In FIG. 6, as a circuit for dividing the serial clock signal, a configuration (one divide-by-2 circuit) including one flip-flop 15 is shown for simplicity, but the present invention is not limited to such a configuration. Of course. That is, instead of the flip-flop 15, a plurality of cascade-connected flip-flops may be provided. When the serial clock signal is divided by N by the flip-flop 15, the flip-flops constituting the shift register 16 are connected in N stages.

<Embodiment 3: Modification 1>
FIG. 7 is a diagram illustrating a configuration of a first modification of the third embodiment. For example, the circuit of FIG. 6 may be configured so that the flip-flop 15 constituting the divide-by-2 circuit is incorporated in a part of the flip-flop 16 constituting the shift register, as shown in FIG. 7, for example. is there. In this case, there is provided a selector 17 having the serial divided clock signal line 23 from the adjacent lane and the output feedback path of the flip-flop 15 as the first and second inputs, and the output of the flip-flop 15 is set as a negative logic input. The flip-flop 16 (negative logic input or inverted output) driven by a common sampling clock with the flip-flop 15 may be provided, and the output of the flip-flop 15 and the output of the flip-flop 16 may be input to the selector 18. . When the selectors 17 and 18 select the first input, a divide-by-2 circuit composed of the flip-flop 15 is used. When the second input is selected by the selectors 17 and 18, the divided clock signal transferred from the adjacent lane via the serial divided clock signal line 23 is shifted by the two-stage flip-flops 15 and 16, and the selector 18 is configured to output.

<Embodiment 3: Modification 2>
FIG. 8 is a diagram illustrating a configuration of a second modification of the third embodiment of the present invention. As shown in FIG. 8, in this modified example, the first lane is the same as the configuration of FIG. 6, and in the second and third lanes, the parallel clock is sent from the adjacent lane via the parallel clock line 22. The configuration of the circuit (flip-flop 12, selector 14, flip-flop 13) distributed in the receiving lane is also the same as that in FIG. In the modification of the present embodiment, the circuit that generates the divided clock from the serial clock in the second and third lanes is composed of the selector 17 and the flip-flop 15. The selector 17 in lane 2 inputs the frequency-divided clock signal from the serial frequency-divided clock line 23 from lane 1 to the first input, and inputs the output of the flip-flop 15 in lane 2 to the second input. One is selected by the selection signal sel, and the inverted signal of the selector 17 is input to the input of the flip-flop 15, and the flip-flop 15 samples the input with the serial clock signal received by the receiver 11. The selector 17 selects the first input (output of the flip-flop 15) when in the local mode, and selects the second input (serial frequency division clock line 23) when synchronizing with the adjacent lane. . The output of the flip-flop 15 is distributed as a serial clock signal in the lane, and is input to the selector 17 of the lane 3 via the serial frequency division clock line 23. The output of the flip-flop 15 (divided by 2 clock) is input as a sampling clock signal of the flip-flops 12 and 13 constituting the parallel clock divide-by-4 circuit.
The selector 17 in lane 3 inputs the frequency-divided clock signal from the serial frequency-divided clock line 23 from lane 2 to the first input, and inputs the output of the flip-flop 15 in lane 2 to the second input. One is selected by the selection signal sel. The inverted signal of the selector 17 is input to the input of the flip-flop 15, and the flip-flop 15 samples the input with the serial clock signal received by the receiver 11. Similar to the second lane, the selector 17 selects the first input (output of the flip-flop 15) when in the local mode, and the second input (serial division) when synchronizing with the adjacent lane. The clock line 23) is selected. The output (divided by 2) of the flip-flop 15 is distributed as a serial clock signal in the lane, and is input as the sampling clock signal of the flip-flops 12 and 13 constituting the parallel clock divide-by-4 circuit.

<Operation of Embodiment 3>
FIG. 9 is a diagram for explaining the operation of the third embodiment of the present invention shown in FIGS. In FIG. 9, the parallel clock signal is a signal obtained by dividing the serial clock signal by 12. In each lane, one flip-flop 12 is provided between the flip-flop 12 and the flip-flop 13. Serial clock signal (a) distributed to lanes 1, 2, and 3 and divided clock signals (b), (e), (i) obtained by dividing the serial clock signal by two in lanes 1, 2, and 3. In addition, solid-line waveforms (c), (f), and (h) are shown for the parallel clock signal (the output of the flip-flop 13 of each lane) distributed in the lanes 1, 2, and 3. Further, the waveform (d) is a waveform of the parallel clock signal (output of the flip-flop 12 in the lane 1) transferred from the lane 1 to the lane 2 via the parallel clock signal line 22.

  In lane 2, the waveform (d) obtained by sampling the parallel clock signal (waveform (c)) transferred from lane 1 via the parallel clock signal line 22 by the flip-flop 13 is distributed as the parallel clock signal in lane 2. At the same time, it is fed back to the first flip-flop 12 of the shift register. At this time, the waveform (d) is inverted, and the flip-flop 12 outputs a waveform (f) delayed by one clock from the inverted signal of the waveform (d), and outputs it to the parallel clock line 22.

  The flip-flop 13 in the lane 3 samples the waveform (f) with the serial clock signal in the lane 3. The output of the flip-flop 13 in lane 3 is distributed in the lane as a parallel clock signal waveform (h) in lane 3.

  As shown in FIG. 9 as “synchronization timing”, the parallel clock signals distributed in lanes 1, 2, and 3 are serially divided clock lines as shown in waveforms (c), (f), and (j), respectively. 23, and is synchronized with the rising edge of the divide-by-2 clock distributed in the lane.

  As a reference example, a comparative example that does not take the configuration of the present invention will be described below.

<Comparative Example 1>
FIG. 10 shows the configuration of Comparative Example 1 of the parallel clock synchronization circuit between multiple lanes. FIG. 10 was created by the present inventors. A serial clock line 21A and a parallel clock line 22A connected to each lane (1, 2, 3) 10A are provided. The clock driving circuit 20-1 receives a clock signal from a PLL (phase locked loop) or the like and outputs a serial clock signal to the serial clock line 21A. Within each lane 10A, the serial clock signal 21A is received by the receiver 11-1 and distributed within each lane. Further, the serial clock signal is frequency-divided by the frequency dividing circuit 30, and the clock driving circuit 20-2 outputs the frequency-divided clock signal (parallel clock) to the parallel clock line 22A. The parallel clock signal on the parallel clock line 22A is received by the receiver 11-2 in each lane 10A and distributed in each lane.

  FIG. 11 shows an example of a timing chart of the configuration of FIG. FIG. 11 shows timing waveforms of the serial clock signal and the parallel clock signal distributed to the lanes 1, 2, and 3. From the clock driving circuit, both the serial clock signal and the parallel clock signal are distributed to each lane.

  In the configuration of FIG. 10, the wiring delay of the parallel clock signal is different in each lane of lanes 1, 2, and 3. In FIG. 10, it is necessary to adjust the delay variation between the lanes by adjusting the delay variation of the serial clock signal and the parallel clock signal.

  However, it is difficult to make the delay times of the parallel clock signal and the serial clock signal equal. The driving capability required for the clock driving circuit for driving the serial clock signal and the parallel clock signal is different. If the clock drive circuits 20-1 and 20-2 for the serial clock signal and the parallel clock signal have the same configuration, it is easy to match the delay time. However, if the drive capability is the same as the serial clock drive, the parallel clock signal drive capability is excessive. As a result, the current consumption increases.

<Comparative example 2>
FIG. 12 is a diagram illustrating a configuration of the second comparative example. FIG. 12 is created by the present inventor. The serial clock signal is collectively driven to the lanes 1, 2, and 3 by the clock driving circuit 20-1. The frequency-divided clock signal obtained by frequency-dividing the serial clock signal by the frequency-dividing circuit 30 is collectively driven to the lanes 1, 2, and 3 by the clock driving circuit 20-2. In each lane 1, 2 and 3, the serial clock signal is received by the receiver 11-1 and distributed in the lane. A flip-flop 12 that inputs a parallel clock signal to the data terminal, samples and outputs it at the rising edge of the serial clock signal, and a flip-flop 13 that receives the output of the flip-flop 12 at the data terminal and samples at the rising edge of the serial clock signal. It has. The flip-flops 12 and 13 constitute a two-stage shift register, and the output of the flip-flop 13 is distributed in the lane.

  FIG. 13 is a timing chart showing an example of the operation of the circuit of FIG. FIG. 12 shows the timing waveform of the serial clock signal and the parallel clock signal distributed to lanes 1, 2, and 3. As shown in FIG. 13, both the serial clock signal and the divided clock signal (parallel clock signal) are distributed from the clock driving circuits 20-1 and 20-2, and the parallel clock distributed to lanes 1, 2, and 3 is distributed. By re-latching the signal with the serial clock signal, the difference between the parallel clock signals distributed to each lane can be eliminated, and the phase can be matched between the lanes. In FIG. 12, waveforms (b), (d), and (f) indicated by broken lines in lanes 1, 2, and 3 represent waveforms of the divided clock signal distributed to each lane from the clock drive circuit. Waveforms (c), (e), and (g) indicated by solid lines in lanes 1, 2, and 3 are parallel clocks that are latched by flip-flops by serial clock signals in each lane and distributed in the lanes. As shown in FIG. 13 as “synchronization timing”, the rising edges of the parallel clock signal indicated by solid lines in each lane are in phase with each other.

  Also in the configuration of FIG. 12, it is difficult to equalize the delay times of the parallel clock signal and the serial clock signal. The required driving ability is different between the serial clock signal and the parallel clock signal. If the serial clock signal, the parallel clock signal, and the clock driving circuit have the same circuit configuration, the delay times can be easily matched. However, the parallel clock signal has excessive driving capability and increases current consumption.

<Comparative Example 3>
FIG. 14 is a diagram illustrating a configuration of Comparative Example 3. In this comparative example 3, the serial clock signal is driven by the clock drive circuit 20-1 and distributed to lanes 1, 2, and 3, and the divided clock signal obtained by dividing the serial clock signal by the divider circuit 30 is used as the clock drive circuit. It is driven by 20-2 and distributed to lanes 1, 2, and 3. In each lane, the serial clock signal received from the serial clock line 20C is divided by two by the frequency dividing circuit (flip-flop 15). In each lane, the parallel clock signal distributed to each lane by the clock drive circuit 20-2 is re-latched with the signal divided by 2 by the frequency dividing circuit 15, thereby the difference between the parallel clock signals distributed to each lane. Is eliminated, and the phase is matched between lanes.

  FIG. 15 is a timing chart showing an example of the operation of the circuit of FIG. In FIG. 15, waveforms (b), (e), and (h) indicated by broken lines in lanes 1, 2, and 3 represent timing waveforms of the divided clock signal distributed from the clock driving circuit 20-2 to each lane. ing. Waveforms (c), (f), and (i) in lanes 1, 2, and 3 represent the serial clock divided by 2 output from the flip-flop 15. Waveforms (d), (g), and (j) indicated by solid lines in lanes 1, 2, and 3 are latched by flip-flops 12 and 13 by the divide-by-2 signal of the serial clock signal in each lane and distributed within the lane. Parallel clock signal. As shown as the synchronization timing, the phase of the parallel clock signal indicated by the solid line is in each lane.

  Also in Comparative Example 3 in FIG. 14, since the clock drive circuits for driving the serial clock signal and the parallel clock signal are different, it is difficult to match the delays of the serial clock signal and the parallel clock signal. When the clock drive circuits 20-1 and 20-2 for the serial clock signal and the parallel clock signal have the same configuration and the delays are matched, the drive capability of the clock drive circuit on the parallel clock signal side becomes excessive and the current consumption increases. To do.

  As described above, each of Comparative Examples 1, 2, and 3 includes the drive circuit that drives the serial clock signal and the parallel clock signal supplied to each lane, and the drive capability of both is the same between the lanes. When adjusting the clock timing, the driving capability of the clock driving circuit on the clock signal side becomes excessive, and the current consumption increases.

  Unlike the comparative example, according to the present embodiment, the parallel clock signal is not collectively driven from the clock driving circuit to each lane, and the real clock and parallel clock driving circuits are configured as the same clock. There is no need to match the delay of the signal and the parallel clock signal. For this reason, the problem that the drive capability of the clock drive circuit on the parallel clock signal side becomes excessive and the current consumption increases is also avoided.

  It should be noted that the disclosures of the above patent documents are incorporated herein by reference. Within the scope of the entire disclosure (including claims) of the present invention, the embodiments and examples can be changed and adjusted based on the basic technical concept. Various combinations and selections of various disclosed elements are possible within the scope of the claims of the present invention. That is, the present invention of course includes various variations and modifications that could be made by those skilled in the art according to the entire disclosure including the claims and the technical idea.

10, 10 ', 10 ", 10A, 10B, 10C lane (transmission path)
11, 11-1, 11-2, 11-3 Receiver 12, 12 ', 12-1, 12-2, 12-3, 13, 15, 31, 32, 33, 34 Flip-flop 14, 16, 17, 18 Selector 20, 20-1, 20-2, 202 Clock drive circuit 21, 21A Serial clock line (serial clock signal)
22, 22A Parallel clock line (parallel clock signal)
23 Serial frequency division clock signal line 30 Frequency division circuit

Claims (14)

A clock driving circuit for outputting a first clock signal to a first clock signal line to which a plurality of lanes are connected in common;
The plurality of lanes include at least first and second lanes,
The first lane is
Inputting the first clock signal from the first clock signal line;
A first frequency divider having a cascade-connected M-stage (where M is an integer of 2 or more) flip-flops using the first clock signal in the first lane as a common sampling clock signal; , The output signal of the M-th flip-flop of the first frequency divider circuit is distributed as a second clock signal in the first lane,
The second lane is
Inputting the first clock signal from the first clock signal line;
The output of the (M−1) th flip-flop of the first lane input to the Mth flip-flop of the first lane is transferred between the first lane and the second lane. A first flip-flop that receives the input through a second clock signal line provided, samples the input using the first clock signal in the second lane as a sampling clock signal, and A communication interface device, wherein an output of the first flip-flop in a second lane is distributed as a second clock signal in the second lane. The plurality of lanes further include third to Sth lanes (where S is an integer of 3 or more),
The first lane (where I is an integer not less than 3 and not greater than S) is
Input the first clock signal from the first clock signal line and distribute it in the I-th lane;
The last of the cascaded (M-1) stage flip-flops provided in the adjacent (I-1) lane and receiving the output of the (I-1) th first flip-flop at the first stage. The output of the stage is received as an input via a second clock signal line between the (I-1) th lane and the Ith lane, and the first clock signal in the Ith lane or A first flip-flop that samples the input using the divided signal as a sampling clock signal is provided, and an output of the first flip-flop of the I lane is input to the I lane as a second clock signal. The communication interface device according to claim 1, wherein the communication interface device is distributed. The plurality of lanes further include third to Sth lanes (where S is an integer of 3 or more);
The Jth lane (where J is an integer of 2 or more and S or less) is
Inputting the first clock signal from the first clock signal line and distributing it in the Jth lane;
A cascade-connected (M−1) -stage flip-flop that uses the first clock signal in the J-th lane as a common sampling clock signal;
A second clock signal line provided between the (J-1) th lane and the Jth lane;
The output of the last stage of the cascaded (M−1) stage flip-flops of the Jth lane;
Are connected to the first and second inputs, respectively,
A selector having an output connected to an input of the first flip-flop of the Jth lane;
The output of the first flip-flop of the Jth lane is fed back to the first stage of the cascaded (M−1) th flip-flop of the Jth lane,
When the selector selects the second input, the cascaded (M−1) -stage flip-flops of the Jth lane and the first flip-flops of the Jth lane are cascaded. Forming a first frequency dividing circuit composed of M-stage flip-flops;
When the first input is selected by the selector, the signal from the second clock signal line provided between the (J-1) th lane and the Jth lane is the signal of the Jth lane. Input to the input of the first flip-flop;
For the Jth lane where J is 2 or more and (S-1) or less, the output of the final stage of the (M-1) th stage flip-flop is between the Jth lane and the (J + 1) th lane. The communication interface device according to claim 2, wherein the communication interface device is supplied to the (J + 1) th lane through a provided second clock signal line. The Jth lane (where J is an integer of 2 or more and S-1 or less) is
Inputting the first clock signal as a common sampling clock signal;
The first stage has an output of the first flip-flop of the Jth lane as an input, and has a shift register including (N-1) stage (where N is a predetermined integer equal to or greater than 2) flip-flops,
The output of the (N−1) th flip-flop of the shift register of the Jth lane is sent via a second clock signal line provided between the Jth lane and the (J + 1) th lane. The communication interface device according to claim 2, input to the first flip-flop of the (J + 1) th lane. The Jth lane (where J is an integer greater than or equal to 2 and less than or equal to S) is
A cascade-connected (M−1) -stage flip-flop using the first clock signal in the J-th lane as a common sampling clock signal;
The second clock signal line provided between the (J-1) th lane and the Jth lane;
The output of the last stage of the cascaded (M−1) stage flip-flops of the Jth lane;
Are connected to the first and second inputs, respectively,
An output comprising a selector connected to an input of the first flip-flop of the Jth lane;
The output of the first flip-flop of the Jth lane is fed back to the first stage of the cascaded (M−1) th flip-flop of the Jth lane,
When the selector selects the second input, the cascaded (M−1) -stage flip-flops of the Jth lane and the first flip-flops of the Jth lane are cascaded, Configure a first frequency divider consisting of M stages of flip-flops,
When the first input is selected by the selector of the Jth lane, a signal from a second clock signal line provided between the (J-1) th lane and the Jth lane is: Input to the input of the first flip-flop of the Jth lane;
For the Jth lane where J is 2 or more and (S-1) or less, the output of the final stage of the (M-1) th stage flip-flop is provided between the Jth lane and the (J + 1) th lane. The communication interface device according to claim 4, wherein the communication interface device is supplied to the (J + 1) th lane via the second clock signal line. In the Jth lane (where J is an integer of 2 or more and S-1 or less),
The output of the first flip-flop is input to the first stage of the shift register composed of the (N−1) -stage flip-flops,
The output of the shift register of the Jth lane is sent to the first of the (J + 1) th lane via a second clock signal line provided between the Jth lane and the (J + 1) th lane. 6. The communication interface device according to claim 4, wherein the communication interface device is an input of a flip-flop.   6. The communication interface device according to claim 4, wherein N corresponds to N in a case where the second clock signal distributed in each lane is obtained by dividing the first clock signal by N. 6. .   7. The communication interface device according to claim 6, wherein N corresponds to N in a case where the second clock signal distributed in each lane is obtained by dividing the first clock signal by 2N. Each of the first to S-th lanes includes a second frequency dividing circuit that divides the first clock signal input into the lane,
Distributing the frequency-divided signal of the first clock signal output from the second frequency-dividing circuit in each lane;
The M-stage flip-flop of the first divider circuit of the first lane is a divided signal of the first clock signal output from the second divider circuit of the first lane. As a common sampling clock signal,
The first flip-flop in the I-th lane (I is an integer not less than 2 and not greater than S) is configured to output the first clock signal output from the second frequency divider circuit in the I-lane. The communication interface device according to claim 2, wherein the divided signal is a sampling clock signal.   In the first stage of the flip-flop constituting the second frequency dividing circuit of the I-th lane (I is an integer equal to or larger than 2 and not larger than S), an adjacent (I-1) -th lane is connected via a selector. The first clock signal from the second frequency divider circuit in the (I-1) th lane transferred via a first frequency-divided clock signal line provided between the I-th lanes. The communication interface device according to claim 9, wherein the frequency division signal is input.   The selector of the I-th lane includes the first frequency-divided clock signal line provided between the adjacent (I-1) -th lane and the I-th lane, and the first lane of the I-th lane. The output of the frequency divider 2 is input to the first and second inputs, one is selected based on the selection signal, and the output of the selector or its inverted signal constitutes the second frequency divider The communication interface device according to claim 10, wherein the communication interface device is input to a first stage of the network. The first lane includes a second frequency dividing circuit including one or a plurality of flip-flops that use the first clock signal input into the first lane as a sampling clock signal.
The M-stage flip-flop constituting the first frequency divider circuit of the first lane is configured to divide the first clock signal output from the second frequency divider circuit of the first lane. The signal is a common sampling clock signal,
The first lane (I is an integer of 2 or more and S or less) is
A second frequency divider circuit comprising one or a plurality of stages of flip-flops using the first clock signal input into the first lane as a common sampling clock signal;
The second in the (I-1) lane transferred via the first frequency-divided clock signal line provided between the adjacent (I-1) lane and the I lane. A shift register composed of a multi-stage flip-flop that receives the frequency-divided signal of the first clock signal from the frequency-dividing circuit at the first stage and inputs it as a common sampling clock signal;
An output of the second divider circuit; and
The output of the last stage of the shift register;
Is provided with a second selector for inputting to the first and second inputs,
An output of the second selector is distributed in the first lane as a divided signal of the first clock signal;
The first flip-flop in the I-th lane (I is 2 or more and S or less) receives the frequency-divided signal of the first clock signal output from the second selector in the I-lane. The communication interface device according to claim 9, wherein the communication interface device is a sampling clock signal.   The communication interface device according to claim 12, wherein, in the I-th lane (I is 2 or more and S or less), the second frequency dividing circuit and the shift register share a flip-flop.   A semiconductor device comprising the communication interface device according to claim 1.

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