JP2012048352A - Data processing device, memory access control method, and memory access control program - Google Patents

Abstract

PROBLEM TO BE SOLVED: To perform overtaking control between arbitrarily grouped instruction groups.SOLUTION: A data processing device comprises a memory access control unit 102 that controls a plurality of memory access instructions accessing a main storage memory which are grouped into a plurality of instruction groups. The memory access control unit 102 performs the overtaking control for the memory access instructions between the instruction groups based on setting information that shows whether the memory access instruction in a predetermined instruction group can overtake the memory access instruction in a precedent other instruction group or not.

Description

  The present invention relates to overtaking control of memory access instructions processed by a data processing device, and more particularly to a data processing device, a memory access control method, and a memory access control program capable of overtaking control between arbitrarily grouped instruction groups.

  Generally, in a memory access instruction control unit of a data processing apparatus, overtaking control between instructions is performed for the purpose of speeding up instruction processing. For example, assume that a load instruction for reading data is executed after a store instruction for writing data to the main memory. If there is no overlap in the main memory area (address area of the main memory) accessed by these two instructions, the load instruction can be executed prior to the store instruction. Thus, by executing the subsequent load instruction first, it is possible to conceal the latency of the load instruction and speed up the instruction processing.

  Techniques relating to such overtaking control are described in Patent Documents 1 to 3, for example. Patent Documents 1 to 3 describe a control circuit that performs an overtaking control by calculating an access area for each instruction by hardware at the time of execution. The control circuit receives a vector store instruction from the instruction issuing unit, performs address area calculation, and holds the result in a register. Next, when a vector load instruction is received, address area calculation is performed in the same manner, and further, a comparison is made with the value held in the register to determine whether there is an overlap in the access area. As a result of this determination, if there is no overlap, the subsequent vector load instruction can be sent as a memory request first. In Patent Documents 1 to 3, such an overtaking control circuit speeds up memory access.

  On the other hand, in Patent Document 4, in addition to the method described in Patent Document 1, a technique related to an apparatus and a method that uses a method of setting whether or not to pass before execution by software is described. Patent Document 4 assumes a case where it is known that the address areas accessed by the preceding store instruction and the subsequent load instruction do not overlap on the program. At this time, a flag for allowing overtaking is provided in the instruction word, and when the software (compiler) generates an instruction word, the value of the flag for allowing overtaking is set in the instruction word. Then, overtaking control is performed using the set flag. Furthermore, by setting a flag that defines the overlap of the memory access address area on the program, it is possible to overtake vector collection / spread instructions (list vector load / store instructions).

  Furthermore, Patent Document 7 describes a method in which a load instruction preferentially sends a store instruction having no address dependency. In Patent Document 7, the compiler determines the address dependency of the main memory address, and specifies a load instruction / store instruction having no address dependency. Then, the store instruction having no address dependency is replaced with a store instruction indicating no address dependency. Based on this added information, a load instruction following the store instruction is preferentially transmitted.

JP 9-231203 JP-A-2005-235135 JP-A-10-269199 JP 2002-366538 A JP2002-297566 JP 2002-32361 A JP2009-026260A

  The technique described in Patent Document 4 is that "the overtaking bit that defines the overlap of the address area of the memory access on the program is set in the instruction word of the preceding store instruction and the subsequent load instruction". It is. Further, the technique described in Patent Document 7 is that “the instruction itself is replaced with an instruction that can be overtaken instead of setting an overtaking bit”. These related technologies have the following problems.

  The first problem is that it is difficult to describe whether overtaking is possible for a plurality of preceding instructions. In other words, the overtaking bit alone can specify only one store-related instruction as a target to be overtaken. Therefore, in order to describe whether overtaking is possible for a plurality of preceding instructions, the number of bits corresponding to the number of preceding instructions is required in the instruction word. As the number of preceding instructions increases, the number of overtaking bits in the instruction word increases accordingly, but the bit width that can be used in the instruction word is limited, and the number of instructions that can be overtaken must be limited. Therefore, when this method is used, the number of overtaking can be limited (Problem 1).

  A second problem is that the determination method when the overtaking bit in the instruction word is not used is unknown. In Patent Document 4, when an overtaking bit in an instruction word is not used, “a determination table is prepared for each instruction word to determine whether overtaking is possible” is described, but there is no description of a setting method of the determination table and the like. Unknown (Problem 2).

  The third problem is that the load of software at the time of command word generation is large. If only the dependency relationship between two instructions (dependency relationship with an instruction executed immediately after a certain instruction, etc.) is analyzed, the software load is relatively small. However, since the dependency relationship is analyzed in units of instructions, when the number of instructions that can be overtaken is increased, the combinations of instructions to be analyzed become enormous. Analyzing such dependence involves problems such as excessive software load and time-consuming instruction word generation (Problem 3).

(Object of invention)
An object of the present invention is to provide a data processing device, a memory access control method, and a memory access control program that can solve the above-described problems and can perform overtaking control between arbitrarily grouped instruction groups.

  A first data processing apparatus of the present invention includes a memory access control unit that controls a plurality of memory access instructions that are grouped into a plurality of instruction groups and that accesses a main storage memory. Based on the setting information indicating whether or not the memory access instruction of the other instruction group preceding the memory access instruction of the instruction group can be executed, overtake control of the memory access instruction between the instruction groups is performed.

  A first memory access control method according to the present invention is a memory access control method for a data processing apparatus including a memory access control unit that controls a plurality of memory access instructions for accessing a main memory, which are grouped into a plurality of instruction groups. And the memory access control unit determines whether the memory between the instruction groups is based on the setting information indicating whether the memory access instruction of the predetermined instruction group can be executed by overtaking the memory access instruction of the other instruction group. Control overtaking of access commands

  The first memory access control program of the present invention operates on a data processing apparatus including a memory access control unit that controls a plurality of memory access instructions that access a main memory, grouped into a plurality of instruction groups, Override memory access instructions between instruction groups based on setting information indicating whether the memory access control unit can execute the memory access instructions of other instruction groups preceding the memory access instruction of a given instruction group. Make control run.

  According to the present invention, overtaking control can be performed between arbitrarily grouped instruction groups.

It is a block diagram which shows the structure of the data processor by the 1st Embodiment of this invention. It is a block diagram which shows the structure of the memory access control part by 1st Embodiment. It is a block diagram which shows the structure of the overtaking setting holding | maintenance part by 1st Embodiment. It is a figure which shows the example of the format of the command word of the overtaking setting command and overtaking setting clear command by 1st Embodiment. It is a block diagram which shows the structure of the overtaking setting register between instruction groups by 1st Embodiment. It is a flowchart which shows operation | movement of the data processor by 1st Embodiment. It is a flowchart which shows operation | movement of the overtaking setting process or overtaking setting clear process by 1st Embodiment. It is a flowchart which shows operation | movement of the data processor by 1st Example of this invention. It is a flowchart which shows operation | movement of the data processor by 2nd Example of this invention. It is a flowchart which shows operation | movement of the data processor by 3rd Example of this invention. It is a flowchart which shows operation | movement of the data processor by the 4th Example of this invention. It is a figure which shows the example of the overtaking control by 5th Example of this invention. It is a figure which shows the operation example of the overtaking control by 1st Example. It is a figure which shows the operation example of the overtaking control by 2nd Example. It is a figure which shows the operation example of the overtaking control by 3rd Example. It is a figure which shows the operation example of the overtaking control by the 4th and 5th Example. It is a block diagram which shows the hardware structural example of the data processor of this invention. It is a figure which shows the example of the overtaking control by background art.

  The data processing device according to the present invention makes it possible to set whether or not the memory access instruction processed by the data processing device can be overtaken by software, and retains overtakeability information between the set memory access instructions in the hardware. This is characterized in that the overtaking control is performed. At this time, the memory access instructions processed by the data processing apparatus are classified into a plurality of types of groups, and whether or not to pass between the respective instruction groups is set. Furthermore, it is characterized in that a range of instruction sequences that can be overtaken is designated, and whether overtaking can be executed between instruction groups in the designated range can be set.

  The present invention solves the problem of determination before execution by software, and performs overtaking control using an overtaking instruction for a specific instruction group.

  First, all instructions that can be executed by the data processing apparatus are classified into an instruction group A, an instruction group B, an instruction group C, an instruction group D,. A user (user) of the data processing apparatus gives an instruction indicating overtaking between instruction groups in the program.

  For example, the instruction group A is classified as a vector store instruction, the instruction group B as a scalar store instruction, the instruction group C as a vector load instruction, and the instruction group D as a scalar load instruction. It can be overtaken between scalar load instructions ”. In response to this instruction, the compiler inserts an “overtaking setting instruction” and an “overtaking setting clear instruction” into the instruction sequence. The overtaking control is performed by the instruction inserted in this way.

  Note that each instruction itself is well known to those skilled in the art of the present invention, and since the method itself is not directly related to the present invention, the details thereof are omitted.

  The memory access control unit of the data processing apparatus has a “register indicating an overtaking setting between instruction groups”, and holds whether or not there is a dependency between instruction groups by turning on / off the register.

  For example, when the memory access control unit of the data processing apparatus detects and executes an “overtaking setting instruction”, the designated “register indicating overtaking setting between instruction groups” in the memory access control unit is turned on. When this register is lit, overtaking control is performed assuming that all dependencies between designated instruction groups have been eliminated. In other words, overtaking between designated instruction groups is allowed unconditionally. Normally, this “register indicating overtaking setting” is turned off, so that the overwriting of the main memory address area is detected by hardware and overtaking control is performed.

  When the memory access control unit of the data processing device detects and executes the “overtake setting instruction”, when the memory access control unit of the data processing device subsequently detects and executes the “overtake setting clear command”, the memory access control unit The “register indicating the overtaking setting between instruction groups” designated by is turned off. With this operation, the designated instruction group is not unconditionally overtaken, and becomes a normal operation. That is, the hardware detection of the overlap of the main memory address area is performed, and the process returns to the overtaking control.

  Regarding the above-described problem 1, in the present invention, since all the instructions between the “overtaking setting instruction” and the “overtaking setting clear instruction” are instructions to be overtaken, the number of overtaking that can be specified is not limited. Further, since the instruction word does not have an overtaking bit, the bit width of the instruction word is not compressed.

  Further, regarding the above-described problem 2, in the present invention, in place of the “determination table” shown in Patent Document 4, “overtaking setting instruction” and “overtaking setting clear instruction” can be controlled by the “between instruction groups”. A register indicating an overtaking setting is used.

  The “register indicating the overtaking setting between instruction groups” is a register that holds whether overtaking between the instruction groups is possible, and all the “registers indicating the overtaking setting” are normally turned off.

  When the “overtaking setting instruction” is executed, the “register indicating overtaking setting” corresponding to the designated instruction group is turned on. The lighting indicates that the unconditional overtaking function is turned on. By maintaining the overtaking setting in this way, overtaking control is performed.

  Further, regarding the above-described problem 3, the present invention does not analyze the dependence between all instructions, but analyzes the dependence of the range specified by the user. A variable or array in a user-specified range (block) is analyzed, and if overtaking is possible, an “overtaking setting command” and an “overtaking setting clear command” are inserted before and after the block. Therefore, even when the number of instructions that can be overtaken is increased, the load on the software (compiler) is small.

  The data processing apparatus according to the present invention includes a central processing unit for HPC (high performance computer) in a preferred embodiment.

  Next, embodiments of the present invention will be described in detail with reference to the drawings. In all the drawings, the same reference numerals are given to the same components, and the description will be omitted as appropriate.

(First embodiment)
First, a first embodiment of the present invention will be described in detail with reference to the drawings. In the following drawings, the configuration of parts not related to the essence of the present invention is omitted and is not shown.

  FIG. 1 is a block diagram showing a configuration of a data processing apparatus 100 according to the present embodiment.

  Referring to FIG. 1, the data processing apparatus 100 includes an instruction control unit 101, a memory access control unit 102, a main storage memory 103, and a calculation unit 104.

  The instruction control unit 101 includes an instruction issuing unit 111 that issues instructions such as a load instruction (an instruction for acquiring memory data), a store instruction, an operation instruction, an overtaking setting instruction, and an overtaking setting clear instruction. Details of the overtaking setting command and the overtaking setting clear command will be described later.

  The instruction issuing unit 111 has a function of issuing an arbitrary instruction to the memory access control unit 102 or the arithmetic unit 104.

  The main memory 103 has a function of storing predetermined data (hereinafter referred to as memory data). The memory data in the main memory 103 is read based on the load command from the command issuing unit 111 and sent to the arithmetic unit 104. Also, predetermined data is stored in the main memory 103 by a store instruction.

  The calculation unit 104 includes a calculation unit 141 that executes a calculation based on a calculation command from the command issuing unit 111. The calculation unit 141 performs a predetermined calculation using the memory data sent from the main memory 103 and returns the calculation result to the instruction control unit 101.

  Next, a block diagram showing a configuration of the memory access control unit 102 according to the present embodiment is shown in FIG.

  Referring to FIG. 2, the memory access control unit 102 includes an instruction receiving unit 121, an access area determination unit 122, an overtaking setting holding unit 123, a preceding instruction state holding table 124 (124-a to 124-c), Instruction holding buffer 125 (125-a to 125-c), dependency check means 126, and memory access instruction output control means 127 are included.

  The command receiving unit 121 has a function of issuing an input command from the command control unit 101 to the access area determining unit 122 and the overtaking setting holding unit 123 and storing it in the command holding buffer 125.

  In addition, when the input instruction from the instruction control unit 101 is a memory access instruction, the instruction receiving unit 121 stores the instruction in a predetermined instruction holding buffer 125. For example, when the input instruction is a memory access instruction of the instruction group A, the instruction receiving unit 121 stores the instruction in the instruction holding buffer 125-A.

  In this embodiment, memory access instructions are arbitrarily classified into three groups (instruction groups A, B, and C), and a plurality of preceding instruction state holding tables 124 and instruction holding buffers 125 are provided for each instruction group. ing. However, the number of instruction groups is not limited to three and can be arbitrarily set, and the numbers of the preceding instruction state holding table 124 and the instruction holding buffer 125 are not limited.

  The access area determination unit 122 depends on the input command from the command receiving unit 121 and the preceding command (hereinafter simply referred to as the preceding command) which is the preceding command of the input command and has not been output to the main memory 103 yet. It has a function to determine the relationship. Here, the dependency relationship means that the address areas of the main memory 103 designated by the instruction overlap.

  The access area determination means 122 displays a flag that can be expressed as “1” when the input instruction and the preceding instruction are in a dependency relationship, and “0” when there is no dependency relationship, as a determination result. To store.

  For example, when the input instruction is a memory access instruction of the instruction group A, the access area determination unit 122 places the input instruction and the preceding instruction in a predetermined location in the preceding instruction state holding table 124-a when there is a dependency relationship. , Flag “1” is stored.

  Further, when an overtaking setting signal (to be described later) is input from the overtaking setting unit 123, the access area determination unit 122, for a set of an input instruction and a preceding instruction between instruction groups corresponding to the overtaking setting signal, It is determined that there is no dependency unconditionally.

  For example, when the overtaking setting signal is a signal indicating that the instruction in the instruction group A can overtake the instruction in the preceding instruction group B, the access area determination unit 122 determines that the input instruction is preceded by an instruction in the group A. If the instruction is an instruction of the instruction group B (or vice versa), it is determined that there is no dependency unconditionally.

  The preceding instruction state holding table 124 has a function of storing a flag indicating a dependency relationship with the preceding instruction for each input instruction of each instruction group. In the preceding instruction state holding table 124, the dependency is expressed by a bitmap using a plurality of bits of flags (in the following description, this bitmap is shown when it is described as a dependency check result).

  The preceding instruction state holding table 124-a stores a flag indicating the dependency between the memory access instruction of the instruction group A and the preceding instruction, and the preceding instruction state holding-table 124-B is the memory of the instruction section group B. A flag indicating the dependency between the access instruction and the preceding instruction is stored, and the preceding instruction state holding-table 124-c stores a flag indicating the dependency between the memory access instruction of the instruction group C and the preceding instruction. .

  The instruction holding buffer 125-a stores the memory access instruction of the instruction group a, the instruction holding buffer 125-b stores the memory access instruction of the instruction group b, and the instruction holding buffer 125-c is the instruction holding buffer 125-c. Stores memory access instructions.

  The dependency check unit 126 checks the dependency relationship of each instruction group with reference to the preceding instruction state holding table 124, and determines an instruction in which the dependency relationship has been canceled (no dependency relationship) as the memory access instruction output control unit 127. It has a function to notify. The check by the dependency relationship check means 126 may be performed periodically or at an arbitrary timing.

  The memory access instruction output control unit 127 has a function of taking out an issuable instruction from the instruction holding buffer 125 of the instruction group based on the notification from the dependency relation checking unit 126 and outputting the instruction to the main memory 103.

  The dependency check unit 126 and the memory access instruction output control unit 127 preferentially acquire and output an instruction having no address dependency from the instruction holding buffer 125.

  The overtaking setting holding unit 123 has a function of holding overtaking settings between instruction groups. Here, a block diagram showing a configuration of the overtaking setting holding unit 123 according to the present embodiment is shown in FIG.

  Referring to FIG. 3, the overtaking setting holding unit 123 includes an instruction identifying unit 1231, a register setting changing unit 1232, an inter-instruction group overtaking setting register 1233, an overtaking setting signal output unit 1234, and an instruction decoding unit 1235. Including.

  The inter-instruction group overtaking setting register 1233 includes a register indicating overtaking setting for each instruction group set. Details of the configuration of the instruction group overtaking setting register 1233 will be described later.

  The command identifying unit 1231 has a function of identifying a command input from the command receiving unit 121.

  When the instruction identifying unit 1231 identifies that the input instruction is an overtaking setting instruction or an overtaking setting clear instruction, the instruction identifying unit 1231 identifies which instruction group the instruction is for, and specifies the instruction type and the instruction group identification result. Is notified to the register setting changing means 1232.

  Further, when the input instruction is a memory access instruction, the instruction identifying unit sends the instruction to the instruction decoding unit 1235.

  The register setting changing unit 1232 has a function of changing the setting of the instruction group overtaking setting register 1233 based on the identification result from the instruction identifying unit 1231.

  The instruction decoding unit 1235 decodes the memory access instruction received from the instruction identifying unit 1231, selects the overtaking setting to be notified based on the decoding result, and notifies the overtaking setting signal output unit 1234 of the selection result.

  The overtaking setting signal output unit 1234 refers to the inter-instruction group overtaking setting register 1233, refers to the overtaking setting register 501 corresponding to the selection result from the instruction decoding unit 1235, and the overtaking setting register 501 is in the “overtaking possible” state. If it is, a signal indicating this (hereinafter referred to as an overtaking setting signal) is output to the access area determination means 122.

  Here, an example of the format of the instruction words of the overtaking setting instruction and the overtaking setting clear instruction is shown in FIG. Referring to FIG. 4, the overtaking setting instruction and the overtaking setting clear instruction include an operation code part 401 or 403 and an instruction group designation part 402 or 404.

  Opcode sections 401 and 403 indicate the type of instruction. The operation code unit 401 stores an identifier indicating that it is an overtaking setting command, and the operation code unit 403 indicates that an identifier indicating that it is an overtaking setting clear command is stored.

  The instruction group designation units 402 and 404 designate between instruction groups for performing overtaking settings or clearing overtaking settings. For example, when the instruction group designations 402 and 404 are “instruction group (AB)”, the overtaking setting or the overtaking setting is cleared for the set of the preceding instruction group A and the subsequent instruction group B.

  Next, the overtaking setting or clearing the overtaking setting will be described in detail with reference to FIG.

  FIG. 5 is a block diagram showing a configuration of the instruction group overtaking setting register 1233 according to this embodiment.

  The inter-instruction group overtaking setting register 1233 includes overtaking setting registers 501-1 to 1234-9 for setting whether overtaking is permitted for each instruction group pair.

  The overtaking setting registers 501-1 to 1234-9 are set / cleared by the register setting changing unit 1232. The register setting changing unit 1232 uniquely designates an instruction group for which the overtaking setting or the setting should be cleared by the instruction group designation units 402 and 404.

  In the example of FIG. 5, the register changing unit 1232 sets a combination of the preceding instruction group A and the succeeding instruction group B because the instruction group specifying unit 402 is “instruction group (AB)” for the overtaking setting instruction. Is set to the overtaking setting register 501-2 corresponding to. Similarly, for the overtaking setting clear instruction, since the instruction group specifying unit 404 is “instruction group (AB)”, the overtaking setting register 501- corresponding to the pair of the preceding instruction group A and the subsequent instruction group B is used. Clear the overtaking setting for 2.

  The overtaking setting means a state indicating that overtaking is possible (overtaking possible state), and clearing the overtaking setting means clearing the overtaking possible state (that is, overtaking is impossible). State).

(Description of the operation of the first embodiment)
Next, the operation of the data processing apparatus 100 according to the present embodiment will be described in detail with reference to the drawings.

  The operation of the data processing apparatus 100 according to this embodiment will be described with reference to the flowchart of FIG.

  First, when an arbitrary command is issued from the command control unit 101 and input to the memory access control unit 102 (step S601), the command receiving unit 121 determines that the input command is an overtaking setting command or an overtaking setting clear command (step S601). S602 “YES”), the input command is issued to the overtaking setting holding unit 123, and overtaking setting processing or overtaking setting clear processing is performed (step S603). The details of this process will be described later, so the description is omitted here.

  On the other hand, when the input command is other than an overtaking setting command or an overtaking setting clear command (ie, a memory access command) (step S602 “NO”), the command receiving unit 121 includes an overtaking setting holding unit 123, an access area determining unit, and the like. It is issued to 122, and the input instruction is stored in a predetermined instruction holding buffer 125 (step S604).

  Next, the instruction identification unit 1231 of the overtaking setting holding unit 123 identifies the input instruction as a memory access instruction, sends the input instruction to the instruction decoding unit 1235, and the instruction decoding unit 1235 decodes the input instruction, and the decoding result Based on the above, the overtaking setting to be notified is selected and the selection result is notified to the overtaking setting signal output means 1234 (step S605).

  Next, the overtaking setting signal output means 1234 refers to the overtaking setting register 501 corresponding to the selection result, and when the overtaking setting register 501 is in the “overtaking possible” state (step S606 “YES”), the corresponding overtaking is performed. A setting signal is output to the access area determination means 122 (step S607).

  Next, the access area determination unit 122 determines the dependency between the input instruction and the preceding instruction of the input instruction, and stores the determination result in the predetermined preceding instruction state holding table 124 (step S608). The access area determination unit 122 stores, as determination results, flags that can be expressed as “1” when the input instruction and the preceding instruction are in a dependency relationship and “0” when there is no dependency relationship.

  At this time, if the overtaking setting signal is input in step S607, the access area determination unit 122 unconditionally determines that there is no dependency between the input instruction and the preceding instruction. When the overtaking setting signal is not input, the dependency is determined by detecting the overlap of the address areas of the main memory 103 by hardware.

  Next, the dependency checking unit 126 checks the dependency result with reference to the preceding instruction state holding table 124, and if there is an instruction that can be issued (an instruction having no dependency) (YES in step S609), the issuance is possible. The memory access instruction output control means 127 is notified of information on a correct instruction, and then the memory access instruction output control means 127 preferentially takes out instructions that can be issued based on the notification from the predetermined instruction holding buffer 125, The selected instruction is output to the main memory 103 (step S610).

  Next, the operation of the overtaking setting process or the overtaking setting clear process in step S603 will be described with reference to the flowchart of FIG.

  First, when a command from the command receiving unit 121 is input (step S701), the command identifying unit 1231 checks the operation code part 401 or 402 of the input command and identifies it as an overtaking setting command or an overtaking setting clear command. (Step S702).

  Next, the instruction identifying unit 1231 checks the instruction group designation unit 402 or 404 of the overtaking setting instruction or the overtaking setting clear instruction, and identifies which instruction group set the overtaking setting instruction or the overtaking setting clear instruction designates. (Step S703).

  Next, the instruction identifying unit 1231 notifies the register changing unit 1232 of the designation of the identified instruction type and instruction group set as an identification result (step S704).

  Next, the register changing unit 1232 changes the setting of the predetermined overtaking setting register 501 in the instruction group overtaking setting register 1233 based on the identification result (step S705).

  Next, the operation of the data processing apparatus according to this embodiment will be described using a specific example. In the following description, instructions A, B, and C are all memory access instructions, and are instructions belonging to instruction groups A, B, and C, respectively.

(Description of configuration)
In the present embodiment, a case will be described in which there is a dependency between an instruction A that is a preceding instruction and an instruction B that is a subsequent instruction, and overtaking control cannot be performed. There are no dependencies other than those described above.

(Description of operation)
The operation of this embodiment will be described in detail with reference to the flowchart of FIG.

  First, when an instruction A is issued from the instruction control unit 101 and input to the memory access control unit 102 (step S801), the instruction receiving unit 121 issues the instruction A to the overtaking setting holding unit 123 and the access area determination unit 122. Further, the instruction A is stored in the instruction holding buffer 125-a (step S802).

  In this embodiment, since no overtaking setting command is issued, any overtaking setting register 501 has an initial value (a state in which overtaking cannot be set), and an overtaking setting signal is output from the overtaking setting holding unit 123. There is nothing. Therefore, the description of the operation of the overtaking setting holding unit 123 is omitted.

  Next, the access area determination unit 122 determines the dependency relationship between the instruction A and the preceding instruction of the instruction A, and stores the determination result in the preceding instruction state holding table 124-a (step S803).

  The access area determination unit 122 displays a flag that can be expressed as “1” when the input instruction and the preceding instruction are in a dependency relationship and “0” when there is no dependency relationship, as a determination result in the preceding instruction state holding table 124. Store in place.

  The instruction A is stored in the instruction holding buffer 125-a in step S802, and then waits in the instruction holding buffer 125-a of the instruction group A for waiting for data necessary for the execution of the instruction A.

  While the instruction A is waiting in the instruction holding buffer 125-a, when the instruction B is issued from the instruction control unit 101 and input to the memory access control unit 102 (step S804), the instruction receiving unit 121 The instruction B is issued to the overtaking setting holding unit 123 and the access area determination unit 122, and the instruction B is stored in the instruction holding buffer 125-b (step S805).

  Next, the access area determination unit 122 determines the dependency between the instruction B and the preceding instruction of the instruction B, and stores the determination result in the preceding instruction state holding table 124-b (step S806).

  At this time, since the instruction B has a dependency relationship with the preceding instruction A, the access area determination unit 122 stores the determination result “1” at a predetermined location in the preceding instruction state holding table 124-b.

  Next, the dependency relationship checking means 126 checks the dependency result of the instruction B with reference to the preceding instruction state holding table 124-b (step S807). Since the instruction B has a dependency relationship with the preceding instruction A, the dependency check unit 126 does not notify the memory access instruction output control unit 127 that the instruction B can be issued, and ends the processing ( Step S808).

  Next, when the data necessary for the execution of the instruction A is available, the dependency relationship checking unit 126 checks the dependency relationship of the instruction A (step S809). In this embodiment, it is assumed that the instruction A has no dependency relationship with the preceding instruction.

  Accordingly, the dependency checking unit 126 determines that the instruction A can be issued, notifies the memory access instruction output control unit 127 of information that the instruction A can be issued, and the memory access instruction output control unit 127 A is selected from the instruction holding buffer 125-a and output to the main memory 103 (step S810).

  When the instruction A is issued from the memory access instruction issuance control unit 209, the dependency relation with the instruction A in the preceding instruction state holding table 204 of the instruction group B is cleared (the flag becomes “0”) ( Step S811). The clearing process may be performed by the access area determination unit 122 or any other unit.

  Next, the dependency relationship checking unit 126 checks the dependency result of the instruction B (step S812).

  Since the dependency relationship between the instruction B and the instruction A has been canceled in step S811, the dependency check unit 126 determines that the instruction B can be issued, and stores information indicating that the instruction B can be issued as a memory access instruction output control unit. 127, the memory access instruction output control means 127 selects the instruction B from the instruction holding buffer 125-b and outputs it to the main memory 103 (step S813).

(Description of configuration)
In the present embodiment, a case will be described in which there is no dependency between the instruction A that is the preceding instruction and the instruction B that is the succeeding instruction, and overtaking control is possible. There are no other dependencies.

(Description of operation)
The operation of this embodiment will be described in detail with reference to the flowchart of FIG.

  First, when an instruction A is issued from the instruction control unit 101 and input to the memory access control unit 102 (step S901), the instruction receiving unit 121 issues the instruction A to the overtaking setting holding unit 123 and the access area determination unit 122. Further, the instruction A is stored in the instruction holding buffer 125-a (step S902).

  Here, in this embodiment, since no overtaking setting command is issued, any overtaking setting register 501 has an initial value (a state in which overtaking setting is not possible), and thus an overtaking setting signal is output from the overtaking setting holding unit 123. Never happen. Therefore, the description of the operation of the overtaking setting holding unit 123 is omitted.

  Next, the access area determination unit 122 determines the dependency relationship between the instruction A and the preceding instruction of the instruction A, and stores the determination result in the preceding instruction state holding table 124-a (step S903).

  The instruction A is stored in the instruction holding buffer 125-a in step S802, and then waits in the instruction holding buffer 125-a of the instruction group A for waiting for data necessary for the execution of the instruction A.

  While the instruction A is waiting in the instruction holding buffer 125-a, when the instruction B is issued from the instruction control unit 101 and input to the memory access control unit 102 (step S904), the instruction receiving unit 121 The instruction B is issued to the overtaking setting holding unit 123 and the access area determination unit 122, and the instruction B is stored in the instruction holding buffer 125-b (step S905).

  Next, the access area determination unit 122 determines the dependency between the instruction B and the preceding instruction of the instruction B, and stores the determination result in the preceding instruction state holding table 124-b (step S906).

  At this time, since the instruction B has no dependency relationship with the preceding instruction A, the access area determination unit 122 stores the determination result “0” in the preceding instruction state holding table 124-b.

  Next, the dependency relationship checking means 126 checks the dependency result of the instruction B with reference to the preceding instruction state holding table 124-b (step S807). Since the instruction B has no dependency relationship with the preceding instruction A, the dependency relationship checking unit 126 determines that the instruction B can be issued, and sends information indicating that the instruction B can be issued to the memory access instruction output control unit 127. The memory access instruction output control means 127 selects the instruction B from the instruction holding buffer 125-b and outputs it to the main memory 103 (step S908).

  Next, when the data necessary for the execution of the instruction A is obtained, the dependency relationship checking unit 126 checks the dependency relationship of the instruction A (step S909). In this embodiment, it is assumed that the instruction A has no dependency relationship with the preceding instruction.

  Accordingly, the dependency checking unit 126 determines that the instruction A can be issued, notifies the memory access instruction output control unit 127 of information that the instruction A can be issued, and the memory access instruction output control unit 127 A is selected from the instruction holding buffer 125-a and output to the main memory 103 (step S910).

  Thus, when overtaking is not set, overtaking between instructions is controlled by normal overtaking control.

(Description of configuration)
In this embodiment, when instructions are issued from the instruction control unit 101 in the order of instruction A, instruction B, and instruction C, there is a dependency relationship between the preceding instruction A and the succeeding instruction B, and the preceding instructions A and B and the succeeding instruction C The case where the dependency relationship is unknown will be described. There are no dependencies other than those described above.

  In this embodiment, since the dependency relationship between the preceding instructions A and B and the subsequent instruction C is unknown, the output of the instruction C to the main storage unit 103 is blocked depending on the dependency relationship between the instruction A and the instruction B. Indicates the state.

(Description of operation)
The operation of this embodiment will be described in detail with reference to the flowchart of FIG.

  First, when an instruction A is issued from the instruction control unit 101 and input to the memory access control unit 102 (step S1001), the instruction receiving unit 121 issues the instruction A to the overtaking setting holding unit 123 and the access area determination unit 122. Further, the instruction A is stored in the instruction holding buffer 125-a (step S1002).

  Here, in this embodiment, since no overtaking setting command is issued, any overtaking setting register 501 has an initial value (a state in which overtaking setting is not possible), and thus an overtaking setting signal is output from the overtaking setting holding unit 123. Never happen. Therefore, the description of the operation of the overtaking setting holding unit 123 is omitted.

  Next, the access area determination unit 122 determines the dependency relationship between the instruction A and the preceding instruction of the instruction A, and stores the determination result in the preceding instruction state holding table 124-a (step S1003).

  The instruction A is stored in the instruction holding buffer 125-a in step S802, and then waits in the instruction holding buffer 125-a of the instruction group A for waiting for data necessary for the execution of the instruction A.

  While the instruction A is waiting in the instruction holding buffer 125-a, when the instruction B is issued from the instruction control unit 101 and input to the memory access control unit 102 (step S1004), the instruction receiving unit 121 The instruction B is issued to the overtaking setting holding unit 123 and the access area determination unit 122, and the instruction B is stored in the instruction holding buffer 125-b (step S1005).

  Next, the access area determination unit 122 determines the dependency between the instruction B and the preceding instruction of the instruction B, and stores the determination result in the preceding instruction state holding table 124-b (step S1006).

  At this time, since the instruction B has a dependency relationship with the preceding instruction A, the access area determination unit 122 stores the determination result “1” at a predetermined location in the preceding instruction state holding table 124-b.

  Next, the dependency relationship checking unit 126 checks the dependency result of the instruction B with reference to the preceding instruction state holding table 124-b (step S1007). Since the instruction B has a dependency relationship with the preceding instruction A, the dependency check unit 126 does not notify the memory access instruction output control unit 127 that the instruction B can be issued, and ends the processing ( Step S1008).

  Next, when the instruction C is issued from the instruction control unit 101 and input to the memory access control unit 102 (step S1009), the instruction receiving unit 121 issues the instruction C to the overtaking setting holding unit 123 and the access area determination unit 122. Further, the instruction C is stored in the instruction holding buffer 125-c (step S1010).

  Next, the access area determination unit 122 determines the dependency relationship between the instruction C and the preceding instruction of the instruction C, and stores the determination result in the preceding instruction state holding table 124-c (step S1011).

  At this time, the instruction C includes the preceding instruction A and the preceding instruction B, and the dependency between the preceding instruction and the instruction C is unknown. Even if there is a dependency between the preceding instruction A or the preceding instruction B and the instruction C, if the instruction C is first output to the main memory 103, the data in the main memory 103 is destroyed. It will end up. Therefore, the instruction C needs to be output to the main memory 103 after the preceding instruction A and the preceding instruction B are output to the main memory 103.

  Accordingly, in step S1011, the access area determination unit 122 stores the determination result “1” at a predetermined location in the preceding instruction state holding table 124-c. The dependency flag is cleared by the access area determination unit 122 or an arbitrary unit after the commands A and B are output in the same flow as in the first embodiment (steps S1012 and S1013).

  Next, the dependency relationship checking unit 126 checks the dependency result of the instruction C (step S1014).

  Since the dependency relationship between the instruction B and the instruction A has been canceled in step S1013, the dependency check unit 126 determines that the instruction C can be issued, and provides information indicating that the instruction C can be issued as a memory access instruction output control unit. 127, the memory access instruction output control means 127 selects the instruction C from the instruction holding buffer 125-c and outputs it to the main memory 103 (step S1015).

(Description of configuration)
In this embodiment, an overtaking operation by an overtaking setting command will be described. Specifically, a case where there is a dependency relationship between the preceding instruction A and the succeeding instruction B when the instructions are issued from the instruction control unit 101 in the order of the overtaking setting instruction, the instruction A, the instruction B, and the instruction C will be described. There are no dependencies other than those described above.

(Description of operation)
The operation of this embodiment will be described in detail with reference to the flowchart of FIG.

  First, when an overtaking setting command is issued from the command control unit 101 and input to the memory access control unit 102 (step S1101), the command receiving unit 121 issues an overtaking setting command to the overtaking setting holding unit 123 (step S1102). ).

  In this embodiment, it is assumed that the overtaking setting instruction indicates a state in which the instruction group C can overtake the instruction groups A and B.

  Next, the overtaking setting holding unit 123 performs a predetermined process, performs a setting of “overtaking possible” indicating that the instruction group C can overtake the instruction groups A and B, and sets the “overtaking possible” state. Hold (step S1103). The details of the above processing are the same as the operation of the overtaking setting holding unit 123 shown in FIG.

  Next, when the instruction A is issued from the instruction control unit 101 and input to the memory access control unit 102 (step S1104), the instruction receiving unit 121 issues the instruction A to the overtaking setting holding unit 123 and the access area determination unit 122. Further, the instruction A is stored in the instruction holding buffer 125-a (step S1105).

  Next, the access area determination unit 122 determines the dependency relationship between the instruction A and the preceding instruction of the instruction A, and stores the determination result in the preceding instruction state holding table 124-a (step S1106). In this embodiment, since the instruction C is a succeeding instruction of the instruction A, no overtaking setting signal is output at this time. Therefore, the access area determination control means 122 determines the dependency by detecting the overlap of the address areas of the main memory 103 by hardware.

  The instruction A is stored in the instruction holding buffer 125-a of the instruction group A in step S1105, and then waits in the instruction holding buffer 125-a of the instruction group A for waiting for data necessary for the execution of the instruction A.

  While the instruction A is waiting in the instruction holding buffer 125-a, when the instruction B is issued from the instruction control unit 101 and input to the memory access control unit 102 (step S1107), the instruction receiving unit 121 The instruction B is issued to the overtaking setting holding unit 123 and the access area determination unit 122, and the instruction B is stored in the instruction holding buffer 125-b (step S1108).

  Next, the access area determination unit 122 determines the dependency between the instruction B and the preceding instruction of the instruction B, and stores the determination result in the preceding instruction state holding table 124-b (step S1109).

  Since the instruction B has a dependency relationship with the preceding instruction A, the access area determination unit 122 stores the determination result “1” in the preceding instruction state holding table 124-b. In this embodiment, since the instruction C is a succeeding instruction of the instruction B, no overtaking setting signal is output at this time. Therefore, the access area determination control means 122 determines the dependency by detecting the overlap of the address areas of the main memory 103 by hardware.

  Next, the dependency relationship checking unit 126 checks the dependency result of the instruction B with reference to the preceding instruction state holding table 124-b (step S1110). Since the instruction B has a dependency relationship with the preceding instruction A, the dependency check unit 126 does not notify the memory access instruction output control unit 127 that the instruction B can be issued, and ends the processing ( Step S1111).

  Next, when the instruction C is issued from the instruction control unit 101 and input to the memory access control unit 102 (step S1112), the instruction receiving unit 121 issues the instruction C to the overtaking setting holding unit 123 and the access area determination unit 122. Further, the instruction C is stored in the instruction holding buffer 125-c (step S1113).

  Next, the access area determination unit 122 determines the dependency relationship between the instruction C and the preceding instruction of the instruction C, and stores the determination result in the preceding instruction state holding table 124-c (step S1114).

  At this time, in the overtaking setting holding unit 123, the overtaking setting between the instruction groups between the instruction group C and the instruction group A or the instruction loop B is set to “overtaking possible”. The overtaking setting signal is output to the access area determination unit 123. The details of this processing are the same as the operations shown in FIG.

  Accordingly, in step S1114, the access area determination unit unconditionally determines that there is no dependency relationship between the instruction C and the instruction A or the instruction B.

  Next, the dependency relationship checking means 126 checks the dependency result of the instruction C (step S1115).

Since the instruction C is unconditionally determined to have no dependency with the instruction A or the instruction B in step S1114, the dependency check unit 126 determines that the instruction C can be issued, and the instruction C can be issued. Is sent to the memory access instruction output control means 127, and the memory access instruction output control means 127 selects the instruction C from the instruction holding buffer 125-c and outputs it to the main memory 103 (step S1116).

  If the data necessary for executing the instruction A is not available at the time of step S1115, the instruction A cannot be executed, and the instruction B depending on the instruction A cannot be executed in the same manner. In this embodiment, the instruction C can be executed even in this state by the overtaking setting instruction. Thereafter, as in the first embodiment, the instructions A and B are issued in this order (step S1117).

(Description of configuration)
In this embodiment, an operation of clearing the overtaking setting by the overtaking setting clear command in a state where the overtaking setting is set by the overtaking setting command will be described.

  Specifically, when the overtaking setting clear instruction, the instruction A, the instruction B, and the instruction C are issued from the instruction control unit 101 in this order, the preceding instruction A and the succeeding instruction B have a dependency relationship, and the preceding instructions A and B A case where the subsequent instruction C has no dependency will be described. There are no dependencies other than those described above.

  The operation after the overtaking setting is cleared by the overtaking setting clear command is the same as that of the third embodiment, and the operation of the third embodiment can be applied by analogy by replacing the overtaking setting command in the third embodiment with the overtaking setting command. The description about the operation | movement using a flowchart as shown in Example 3 is abbreviate | omitted.

(Description of operation)
The operation of this embodiment will be described in detail with reference to FIGS. FIG. 20 is a diagram illustrating an example of overtaking control according to the background art, and FIG. 12 is a diagram illustrating an example of overtaking control in the present embodiment.

  Referring to FIG. 18, in the overtaking control according to the background art, the instruction sequence before passing 708 and the instruction sequence after passing 709 execute instructions according to the execution order 730.

  In the overtaking control according to the background art, the address load overlap is checked, and when there is no overlap, overtaking is performed. In the example of FIG. 18, the vector load instruction 703 and the vector load instruction 705 depend on other vector store instructions. Since there is no relationship, overtaking is possible.

  On the other hand, since the vector load instruction 704 and the vector store instruction 707 are in a dependency relationship, the vector load instruction 704 cannot be overtaken.

  In addition, since the dependency relationship between the vector load instruction 704 and the scalar store instruction 701 is not specified, whether overtaking is possible is unknown. Therefore, the scalar store instruction 701 cannot be overtaken.

  As a result, in the post-overtaking instruction string 609, the vector load instruction 704, the vector store instruction 706, and the vector store instruction 707 are in the order in which the scalar store instruction 501 and the scalar load instruction 502 cannot be overtaken.

  Next, referring to FIG. 12, in the overtaking control according to the present invention, the overtaking setting instruction 610 unconditionally permits overtaking between a vector instruction (VST, VLD) and a scalar instruction (SST, SLD). If there is, the overtaking between the vector instruction (VST, VLD) and the scalar instruction (SST, SLD) is unconditionally permitted until the overtaking setting clear instruction 620 is executed after the overtaking setting instruction 610 is executed. Is done.

  Therefore, the vector instructions 604 to 607 can pass the scalar store instruction 501 and the scalar load instruction 502. As a result, in the post-overtaking instruction string 609, the vector load instruction 604, the vector store instruction 606, and the vector store instruction 607 are in the order of instructions overtaking the scalar store instruction 501 and the scalar load instruction 502.

  Examples of the operations of the first to fifth embodiments are shown in FIGS.

(Effects of the first embodiment)
Next, the effect of this embodiment will be described.

  According to the present embodiment, there is an effect of speeding up the program processing. The reason is that it is possible to set a preceding instruction that can only be handled as being overtaken by the background technology method as being overtaken, thereby issuing a subsequent memory access instruction that could not be issued by overtaking in the background art. Because it can.

  In addition, according to the present embodiment, the overtaking setting command can be set as to whether overtaking can be set by the designation of the user (user), and therefore can be applied to the purpose of controlling the order of issuing memory access commands.

  Next, a hardware configuration example of the data processing apparatus 100 of the present invention will be described with reference to FIG. FIG. 17 is a block diagram illustrating a hardware configuration example of the data processing apparatus 100.

  Referring to FIG. 17, the data processing device 100 has a hardware configuration similar to that of a general computer device, and includes a data work area including a memory such as a CPU (Central Processing Unit) 801 and a RAM (Random Access Memory). And a main storage unit 802 used for a temporary data saving area, a communication unit 803 that transmits and receives data via a network, an input / output interface that transmits and receives data by connecting to the input device 805, the output device 806, and the storage device 807 A unit 804 and a system bus 808 for interconnecting the above components. The storage device 807 is realized by, for example, a hard disk device including a non-volatile memory such as a ROM (Read Only Memory), a magnetic disk, and a semiconductor memory.

  The instruction control unit 101, the memory access control unit 102, and the calculation unit 104 of the data processing apparatus 100 of the present invention are implemented by mounting circuit components that are hardware components such as LSI (Large Scale Integration) incorporating a program. In addition to realizing the operation in hardware, a program that provides the function is stored in the storage device 807, and the program is loaded into the main storage unit 802 and executed by the CPU 801. It can also be realized.

  Although the present invention has been described with reference to the preferred embodiments, the present invention is not necessarily limited to the above embodiments, and various modifications can be made within the scope of the technical idea. .

  It should be noted that any combination of the above-described constituent elements and a conversion of the expression of the present invention between a method, an apparatus, a system, a recording medium, a computer program, etc. are also effective as an aspect of the present invention.

  The various components of the present invention do not necessarily have to be independent of each other. A plurality of components are formed as a single member, and a single component is formed of a plurality of members. It may be that a certain component is a part of another component, a part of a certain component overlaps with a part of another component, or the like.

  Moreover, although the several procedure is described in order in the method and computer program of this invention, the order of the description does not limit the order which performs a several procedure. For this reason, when implementing the method and computer program of this invention, the order of the several procedure can be changed in the range which does not interfere in content.

  The plurality of procedures of the method and the computer program of the present invention are not limited to being executed at different timings. For this reason, another procedure may occur during the execution of a certain procedure, or some or all of the execution timing of a certain procedure and the execution timing of another procedure may overlap.

  Further, a part or all of the above-described embodiment can be described as in the following supplementary notes, but is not limited thereto.

(Appendix 1)
A memory access control unit that controls a plurality of memory access instructions for accessing the main memory, divided into a plurality of instruction groups,
The memory access control unit is
Overtaking of the memory access instruction between the instruction groups based on setting information indicating whether the memory access instruction of the predetermined instruction group can be executed by overtaking the memory access instruction of the other instruction group preceding A data processing apparatus characterized by performing control.

(Appendix 2)
Command issuing means for issuing to the memory access control unit, the memory access instruction, an overtaking setting instruction for setting overtaking in the setting information, and an overtaking setting clear instruction for setting overtaking impossible in the setting information;
The memory access control unit is
An overtaking setting holding unit for holding the setting information;
The overtaking setting holding unit
An instruction group passing setting register for storing the contents of the setting information;
The data processing apparatus according to claim 1, further comprising: a register changing unit that changes setting information of the overtaking setting register between the instruction groups based on the overtaking setting instruction or the overtaking setting clear instruction.

(Appendix 3)
The data processing apparatus according to appendix 2, wherein the overtaking setting command and the overtaking setting clear command include information for specifying an instruction group for performing setting for overtaking or setting for non-overtaking.

(Appendix 4)
The memory access control unit is
Access area determination means for determining address dependency between the memory access instruction and the other preceding memory access instruction;
The overtaking setting holding unit
An overtaking setting signal output means for outputting an overtaking setting signal for specifying between instruction groups in an overtaking enabled state to the access area determining means based on the setting information of the overtaking setting register between the instruction groups;
The access area determination means includes:
Supplementary note 2 or Supplementary note 3, wherein address dependency between the memory access instruction between the instruction groups specified by the overtaking setting signal and the preceding other memory access instruction is determined unconditionally as being independent. The data processing apparatus described in 1.

(Appendix 5)
The overtaking setting holding unit
Decoding means for decoding the memory access instruction when the memory access instruction is input, and selecting a set of instruction groups to output the overtaking setting signal based on the decoding result;
The overtaking setting signal output means includes
The inter-instruction group overtaking setting register corresponding to the instruction group selected by the decoding means is referred to, and when the setting information is in an overtaking possible state, the overtaking setting output signal indicating that is output. The data processing device according to appendix 4

(Appendix 6)
The memory access control unit is
A preceding instruction state holding table that holds information on presence / absence of address dependency between the memory access instruction and the preceding other memory access instruction;
The access area determination means includes:
6. The data processing device according to any one of appendix 2 to appendix 5, wherein the determination result is stored in the preceding instruction state holding table.

(Appendix 7)
The preceding instruction state holding table is
The data processing according to appendix 6, wherein for each instruction group, the memory access instruction is represented by a bit map that represents a dependency result of all the preceding other memory access instructions with a flag. apparatus.

(Appendix 8)
The memory access control unit is
An instruction holding buffer for holding the memory access instruction until it is output to the main memory;
Dependency check means for checking the presence or absence of the dependency with reference to the preceding instruction state holding table;
Memory access instruction output control means for preferentially acquiring the memory access instruction having no address dependency from the instruction holding buffer based on a check result of the dependency check means and outputting the memory access instruction to the main memory. 8. The data processing device according to appendix 6 or appendix 7, which is a feature.

(Appendix 9)
A memory access control method for a data processing apparatus including a memory access control unit that controls a plurality of memory access instructions that are grouped into a plurality of instruction groups and accesses a main memory.
The memory access control unit is
Overtaking of the memory access instruction between the instruction groups based on setting information indicating whether the memory access instruction of the predetermined instruction group can be executed by overtaking the memory access instruction of the other instruction group preceding A memory access control method characterized by performing control.

(Appendix 10)
The overtaking setting holding unit of the memory access control unit,
Store the contents of the setting information in the overtaking setting register between instruction groups,
The setting information of the overtaking setting register between the instruction groups is changed based on an overtaking setting instruction that sets overtaking permission in the setting information and an overtaking setting clear instruction that sets overtaking impossible in the setting information. 10. The memory access control method according to 9.

(Appendix 11)
11. The memory access control method according to appendix 10, wherein the overtaking setting command and the overtaking setting clear command include information for specifying an instruction group for performing setting for overtaking or setting for non-overtaking.

(Appendix 12)
In the access area determination means of the memory access control unit,
Determining an address dependency between the memory access instruction and another preceding memory access instruction;
In the overtaking setting signal output means of the memory access control unit,
Based on the setting information in the inter-instruction group overtaking setting register, an overtaking setting signal for specifying an instruction group in an overtaking enabled state is output to the access area determination unit,
The access area determination means includes:
Supplementary note 10 or Supplementary note 11, wherein address dependency between the memory access instruction between instruction groups specified by the overtaking setting signal and the preceding other memory access instruction is unconditionally determined to be independent. The memory access control method described in 1.

(Appendix 13)
The overtaking setting holding unit of the memory access control unit,
Decode the input memory access instruction, select a set of instruction groups to output the overtaking setting signal based on the decoding result,
The overtaking setting signal output means is
Item 13. The additional setting output signal indicating that when the setting information is in an overtaking enabled state with reference to an instruction group overtaking setting register corresponding to the selected instruction group, the overtaking setting output signal is output. Memory access control method.

(Appendix 14)
The access area determination means includes:
The determination result is stored in a preceding instruction state holding table that holds information on presence / absence of address dependency between the memory access instruction and the other preceding memory access instruction. The memory access control method according to any one of the above.

(Appendix 15)
The preceding instruction state holding table is
15. The memory access according to appendix 14, wherein for each instruction group, the memory access instruction is represented by a bit map representing a dependency result of all the preceding other memory access instructions with a flag. Control method.

(Appendix 16)
The memory access control unit is
Until it is output to the main memory, the memory access instruction is held in the instruction holding buffer,
Referring to the preceding instruction state holding table, the presence or absence of the dependency is checked,
The supplementary note 14 or the supplementary note 15, wherein the memory access instruction having no address dependency is preferentially acquired from the instruction holding buffer based on the check result of the dependency relation and output to the main memory. Memory access control method.

(Appendix 17)
Operated on a data processing device having a memory access control unit that controls a plurality of memory access instructions that are grouped into a plurality of instruction groups and that accesses a main memory,
In the memory access control unit,
Overtaking of the memory access instruction between the instruction groups based on setting information indicating whether the memory access instruction of the predetermined instruction group can be executed by overtaking the memory access instruction of the other instruction group preceding A memory access control program for executing control.

(Appendix 18)
Store the contents of the setting information in the overtaking setting register between instruction groups,
Based on an overtaking setting instruction that sets overtaking allowed in the setting information and an overtaking setting clear instruction that sets overtaking impossible in the setting information, a process of changing setting information in the overtaking setting register between the instruction groups is executed. 18. The memory access control program according to appendix 17, which is characterized by

(Appendix 19)
19. The memory access control program according to appendix 18, wherein the overtaking setting instruction and the overtaking setting clear instruction include information for specifying an instruction group that performs setting for overtaking or setting for non-overtaking.

(Appendix 20)
A process for determining an address dependency between the memory access instruction and the other preceding memory access instruction;
Based on the setting information in the instruction group overtaking setting register, and a process of outputting an overtaking setting signal that identifies between instruction groups in an overtaking possible state,
In the determination process,
Supplementary note 10 or Supplementary note 11, wherein address dependency between the memory access instruction between instruction groups specified by the overtaking setting signal and the preceding other memory access instruction is unconditionally determined to be independent. Memory access control program described in 1.

(Appendix 21)
Decode the input memory access instruction, select a set of instruction groups to output the overtaking setting signal based on the decoding result,
Item 13. The additional setting output signal indicating that when the setting information is in an overtaking enabled state with reference to an instruction group overtaking setting register corresponding to the selected instruction group, the overtaking setting output signal is output. Memory access control program.

(Appendix 22)
The determination result is stored in a preceding instruction state holding table that holds information on presence / absence of address dependency between the memory access instruction and the other preceding memory access instruction. The memory access control program according to any one of the above.

(Appendix 23)
The preceding instruction state holding table is
15. The memory access according to appendix 14, wherein for each instruction group, the memory access instruction is represented by a bit map representing a dependency result of all the preceding other memory access instructions with a flag. Control program.

(Appendix 24)
Until it is output to the main memory, the memory access instruction is held in the instruction holding buffer,
Referring to the preceding instruction state holding table, the presence or absence of the dependency is checked,
The supplementary note 14 or the supplementary note 15, wherein the memory access instruction having no address dependency is preferentially acquired from the instruction holding buffer based on the check result of the dependency relation and output to the main memory. Memory access control program.

DESCRIPTION OF SYMBOLS 100: Data processing apparatus 101: Instruction control part 102: Memory access control part 103: Main memory 104: Arithmetic part 111: Instruction issuing means 121: Instruction receiving means 122: Access area determination means 123: Overtaking setting holding part 1231: Instruction Identification means 1232: Register setting changing means 1233: Overtaking setting register between instruction groups 1234: Overtaking setting signal output means 1235: Instruction decoding means 124: Preceding instruction state holding table 124-a: Preceding instruction state holding table of instruction group A 124- b: Preceeding instruction state holding table of instruction group B 124-c: Preceding instruction state holding table of instruction group C 125: Instruction holding buffer 125-a: Instruction holding buffer of instruction group A 125-b: Instruction holding of instruction group A Buffer 25-c: Instruction holding buffer for instruction group A 126: Dependency check means 127: Memory access instruction output control means 141: Operation means 401: Operation code part 402: Instruction group specification part 403: Operation code part 404: Instruction group specification part 501 (501-1 to 501-6): Overtaking setting register 601: SST
602: SLD
603: VLD
604: VLD
605: VLD
606: VST
607: VST
608: Instruction sequence before overtaking 609: Overtaking instruction sequence 610: Overtaking setting instruction 620: Overtaking setting clear instruction 630: Execution order 701: SST
702: SLD
703: VLD
704: VLD
705: VLD
706: VST
707: VST
708: Instruction sequence before passing 709: Passing instruction sequence 730: Execution order 801: CPU
802: Main storage unit 803: Communication unit 804: Input / output interface unit 805: Input device 806: Output device 807: Storage device 808: System bus

Claims (10)

A memory access control unit that controls a plurality of memory access instructions for accessing the main memory, divided into a plurality of instruction groups,
The memory access control unit is
Overtaking of the memory access instruction between the instruction groups based on setting information indicating whether the memory access instruction of the predetermined instruction group can be executed by overtaking the memory access instruction of the other instruction group preceding A data processing apparatus characterized by performing control. Command issuing means for issuing to the memory access control unit, the memory access instruction, an overtaking setting instruction for setting overtaking in the setting information, and an overtaking setting clear instruction for setting overtaking impossible in the setting information;
The memory access control unit is
An overtaking setting holding unit for holding the setting information;
The overtaking setting holding unit
An instruction group passing setting register for storing the contents of the setting information;
The data processing apparatus according to claim 1, further comprising: a register changing unit that changes setting information of the overtaking setting register between the instruction groups based on the overtaking setting instruction or the overtaking setting clear instruction.   The data processing apparatus according to claim 2, wherein the overtaking setting command and the overtaking setting clear command include information for specifying an instruction group that performs setting for overtaking or setting for non-overtaking. The memory access control unit is
Access area determination means for determining address dependency between the memory access instruction and the other preceding memory access instruction;
The overtaking setting holding unit
An overtaking setting signal output means for outputting an overtaking setting signal for specifying between instruction groups in an overtaking enabled state to the access area determining means based on the setting information of the overtaking setting register between the instruction groups;
The access area determination means includes:
3. The address dependency between the memory access instruction between instruction groups specified by the overtaking setting signal and the preceding other memory access instruction is determined unconditionally as being independent. Item 4. The data processing device according to item 3. The overtaking setting holding unit
Decoding means for decoding the memory access instruction when the memory access instruction is input, and selecting a set of instruction groups to output the overtaking setting signal based on the decoding result;
The overtaking setting signal output means includes
The inter-instruction group overtaking setting register corresponding to the instruction group selected by the decoding means is referred to, and when the setting information is in an overtaking possible state, the overtaking setting output signal indicating that is output. The data processing apparatus according to claim 4 The memory access control unit is
A preceding instruction state holding table that holds information on presence / absence of address dependency between the memory access instruction and the preceding other memory access instruction;
The access area determination means includes:
6. The data processing apparatus according to claim 2, wherein the result of the determination is stored in the preceding instruction state holding table. The preceding instruction state holding table is
7. The data according to claim 6, wherein, for each instruction group, the memory access instruction is represented by a bit map that represents a dependency result of all the preceding other memory access instructions with a flag. Processing equipment. The memory access control unit is
An instruction holding buffer for holding the memory access instruction until it is output to the main memory;
Dependency check means for checking the presence or absence of the dependency with reference to the preceding instruction state holding table;
Memory access instruction output control means for preferentially acquiring the memory access instruction having no address dependency from the instruction holding buffer based on a check result of the dependency check means and outputting the memory access instruction to the main memory. 8. The data processing apparatus according to claim 6, wherein the data processing apparatus is characterized in that: A memory access control method for a data processing apparatus including a memory access control unit that controls a plurality of memory access instructions that are grouped into a plurality of instruction groups and accesses a main memory.
The memory access control unit is
Overtaking of the memory access instruction between the instruction groups based on setting information indicating whether the memory access instruction of the predetermined instruction group can be executed by overtaking the memory access instruction of the other instruction group preceding A memory access control method characterized by performing control. Operated on a data processing device having a memory access control unit that controls a plurality of memory access instructions that are grouped into a plurality of instruction groups and that accesses a main memory,
In the memory access control unit,
Overtaking of the memory access instruction between the instruction groups based on setting information indicating whether the memory access instruction of the predetermined instruction group can be executed by overtaking the memory access instruction of the other instruction group preceding A memory access control program for executing control.

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