JP2012048153A - Driving circuit of display device and control method therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce current consumption when all gradation data in one line is of the same gradation.SOLUTION: A driving circuit of a display device of the present invention comprises: a determination circuit for determining whether multiple digital gradation data input for respective pixels is the same among all pixels in one line; a stop circuit for stopping control for respective pixels in one line based on the multiple digital gradation data when the sameness is determined by the determination circuit; and a gradation output circuit for outputting one gradation determined as the same, for all pixels in one line, when the sameness is determined by the determination circuit.

Description

  The present invention relates to the field of semiconductor integrated circuits, and more particularly to the field of drive circuits for display devices and control methods thereof.

  In recent years, in mobile devices equipped with liquid crystal display devices such as mobile phones, it has become necessary to reduce the power consumption of the display control circuit itself in accordance with the demand for long-time operation by battery drive. In particular, in a liquid crystal display control circuit, a large amount of current is generated when display image data is transferred, and there is a strong demand for reduction in reducing power consumption.

  Patent Document 1 discloses a technique related to a liquid crystal driving circuit that can reduce current consumption. FIG. 5 is a block diagram showing a configuration of a liquid crystal driving circuit 900 according to Patent Document 1. As shown in FIG. In the liquid crystal drive circuit 900, digital gradation data S3 is input, and the gradation data use determination circuit 23 determines which gradation is used in one line, and the determination result is used as the amplifier enable circuit 25. Is input. The amplifier enable circuit 25 stops the unnecessary gradation amplifier 6 using the determination result of the gradation data use determination circuit 23. That is, unnecessary gradation amplifiers are stopped by determining one line of digital gradation data input from a CPU (Central Processing Unit), thereby reducing current consumption.

JP 2002-108301 A

  However, the liquid crystal driving circuit 900 according to Patent Document 1 has a problem that wasteful current is generated when all the lines have the same gradation. The reason is that in the liquid crystal driving circuit according to Patent Document 1, the operation from the load latch circuit 3 to the decoder 21 is always performed regardless of the number of gradations. That is, the liquid crystal driving circuit 900 according to Patent Document 1 latches input digital gradation data from the data latch circuit 2 to the load latch circuit 3 and performs an operation from the level shifter 4 to the decoder 21. Therefore, even if all the lines have the same gradation, the operations of the load latch circuit 3, the level shifter 4 and the decoder 21 cannot be stopped.

  The drive circuit of the display device according to the first aspect of the present invention includes a determination circuit that determines whether or not a plurality of digital gradation data input for each pixel is the same among all the pixels in one line. When the determination circuit determines that they are the same, the determination circuit determines that they are the same as the stop circuit that stops the control for each pixel in the one line based on the plurality of digital gradation data. A gradation output circuit that outputs one gradation determined to be the same to all pixels of the one line.

  The control method of the drive circuit of the display device according to the second aspect of the present invention determines whether or not a plurality of digital gradation data inputted for each pixel is the same among all the pixels in one line. If it is determined that they are the same, the control for each pixel in the one line based on the plurality of digital gradation data is stopped, and the one gradation determined to be the same is all of the one line. Output to the pixel.

  For example, when the above-described first and second aspects of the present invention are applied to FIG. 5, when all the gradation data of one line input from the CPU is the same gradation, which gradation is used is which one gradation. The operation from the load latch circuit 3 to the decoder 21 is not required because the gradation is determined and the gradation is output from the output selection circuit 22. Therefore, current consumption can be reduced by stopping the load latch circuit 3 to the decoder 21.

  According to the present invention, it is possible to provide a display device driver circuit and a control method thereof for reducing current consumption when gradation data of one line are all the same gradation.

1 is a block diagram showing a configuration of a drive circuit of a display device according to a first exemplary embodiment of the present invention. 1 is a block diagram showing a configuration of a one gradation determination circuit according to a first exemplary embodiment of the present invention; 1 is a block diagram showing a configuration of an amplifier control circuit according to a first exemplary embodiment of the present invention. 3 is a timing chart of the one gradation determination circuit according to the first exemplary embodiment of the present invention. It is a block diagram which shows the structure of the liquid crystal drive circuit concerning related technology.

  Hereinafter, specific embodiments to which the present invention is applied will be described in detail with reference to the drawings. In the drawings, the same elements are denoted by the same reference numerals, and redundant description will be omitted as necessary for the sake of clarity.

<Embodiment 1 of the Invention>
FIG. 1 is a block diagram showing a configuration of a drive circuit 100 of a display device according to Embodiment 1 of the present invention. Here, the shift pulse S1, the transfer clock S2, the digital gradation data S3 and the load signal S4 according to FIG. 1, the shift register 1, the data latch circuit 2, the load latch circuit 3, the level shifter 4, the decoder 21, and the output Various circuits such as the selection circuit 22, the gradation voltage generation circuit 7, and the gradation amplifier 6 may be equivalent to those disclosed in Patent Document 1 or FIG. Therefore, in the following description, it demonstrates centering on the component and operation | movement peculiar to Embodiment 1 of this invention, and abbreviate | omits description about another component and operation | movement suitably.

  Compared with the liquid crystal drive circuit 900, the drive circuit 100 includes a 1 gradation determination circuit 131, a gradation output short circuit 132, and an amplifier control circuit 133. The one gradation determination circuit 131 is a circuit that determines whether or not a plurality of digital gradation data input for each pixel is the same among all the pixels in one line. Further, when it is determined that the digital gradation data S3 is the same among all the pixels in one line, the one gradation determination circuit 131 performs control for each pixel in one line based on the digital gradation data S3. It can be said that it is a stop circuit for stopping. Further, the gradation output short circuit 132 and the amplifier control circuit 133 determine that the digital gradation data S3 is the same between all the pixels in one line when the one gradation determination circuit 131 determines that all the pixels in one line are the same. It can be said that this is a gradation output circuit that outputs one gradation to all pixels in one line. Thereby, the current consumption can be reduced when the gradation data of one line are all the same gradation. The control for each pixel in one line may be at least one of various processes from the load latch circuit 3 to the level shifter 4 and the decoder 21, for example. That is, the one gradation determination circuit 131 may be controlled not to output the processing result based on the data latched by the data latch circuit 2 to the output selection circuit 22.

  Below, each structure is demonstrated concretely. The 1 gradation determination circuit 131 receives the input of the transfer clock S2, the digital gradation data S3, the load signal S4, the 1 line start pulse S5, and the 1 line end pulse S6. The 1-line start pulse S5 is a horizontal reference signal. The 1-line end pulse S6 is a signal indicating the end of data transfer for one line. The 1-line end pulse S6 can be easily generated by using, for example, counters for the number of data transferred using the 1-line start pulse S5 as a trigger. The digital gradation data S3 is 6 bits or 8 bits, which is the number of bits of RGB in the case of RGB division transfer, and 18 bits or 24 bits in the case of RGB batch transfer. Here, in the first embodiment of the present invention, it is assumed that RGB transfer is performed. In the case of RGB batch transfer, one gradation determination circuit 131 is provided separately for each RGB.

  Then, the 1 gradation determination circuit 131 determines whether or not the digital gradation data S3 from the 1 line start pulse S5 to the 1 line end pulse S6 is 1 gradation. Here, when it is determined that the gradation is one gradation, the one gradation determination circuit 131 outputs a signal for stopping the latch operation of the load latch circuit 3 to the load latch circuit 3. The load latch circuit 3 is a circuit that performs latch control for each pixel in one line based on a plurality of digital gradation data. When the one gradation determination circuit 131 determines that the gradation is one gradation, the latch control in the load latch circuit 3 is stopped. As a result, the load latch circuit 3 to the decoder 21 are stopped, and current consumption can be reduced.

  Further, the one gradation determination circuit 131 outputs the ONE_DATA [n−1: 0] signal S8 and the ONE_JUDGE signal S9 to the amplifier control circuit 133 for the digital gradation data S3 in one line. Further, the 1 gradation determination circuit 131 outputs the ONE_JUDGE signal S9 to the gradation output short circuit 132 for the digital gradation data S3 in one line. The ONE_DATA [n-1: 0] signal S8 is data per pixel in the digital gradation data S3 in the case of RGB batch transfer. In particular, when one line has one gradation, the ONE_DATA [n-1: 0] signal S8 continues to be output with the same value. The ONE_JUDGE signal S9 is a signal indicating a determination result of whether or not the digital gradation data S3 in one line in the one gradation determination circuit 131 is one gradation.

  FIG. 2 is a block diagram showing a configuration of the one gradation determination circuit 131 according to the first embodiment of the present invention. FIG. 2 shows an example of the 1 gradation determination circuit 131, and the configuration of the 1 gradation determination circuit 131 according to the first embodiment of the present invention is not limited to this.

  The one gradation determination circuit 131 includes n mismatch circuits 140, OR 33, SR 34, FF 35, FF 36, and AND 37. Each of the mismatch circuits 140 processes the input digital gradation data S3 in units of bits, and determines whether there is a change from the bit in the digital gradation data S3 input immediately before. The mismatch circuit 140 can sequentially perform comparison with the previous data using, for example, the FF 31 and the EXOR 32 as shown in FIG. The OR 33 is a circuit that takes a logical sum of outputs from the n mismatch circuits 140. SR34 outputs SR_OUT signal S7 based on the output of one line start pulse S5 and OR33. The SR_OUT signal S7 is a signal indicating whether or not the digital gradation data S3 after the one-line start pulse S5 is input is one gradation. Here, it is assumed that the SR_OUT signal S7 is set to L when H is set as an initial value and multi-gradation is detected by the outputs of the mismatch circuit 140 and the OR 33. The FF 35 receives the digital gradation data S3 and the 1-line end pulse S6, and outputs it as a ONE_DATA [n-1: 0] signal S8. The FF 36 receives the SR_OUT signal S7 and the 1-line end pulse S6, and outputs it as a ONE_JUDGE signal S9. The AND 37 receives the ONE_JUDGE signal S9 and the load signal S4, and outputs a signal indicating whether or not the load is executed to the load latch circuit 3.

Returning to FIG. 1, the amplifier control circuit 133 is a circuit that controls the gradation amplifier 6 based on the ONE_DATA [n−1: 0] signal S8 and the ONE_JUDGE signal S9 input from the one gradation determination circuit 131. Here, the gradation amplifier 6 exists corresponding to the number of gradations that can be displayed by the display device to which the drive circuit 100 belongs. Here, the driving circuit 100 includes 2 ⁿ gradation amplifiers 6. When the one gradation determination circuit 131 determines that one line has one gradation, the amplifier control circuit 133 sets one gradation determined as one gradation among the plurality of gradation amplifiers 6. The corresponding gradation amplifier is selected, and the gradation corresponding to the selected gradation amplifier is output via the other gradation amplifier that has not been selected. More specifically, the amplifier control circuit 133 stops the gradation amplifiers other than the gradation amplifier corresponding to one gradation determined as one gradation among the plurality of gradation amplifiers 6.

  The gradation output short circuit 132 is a circuit that selects the output of the gradation amplifier 6 based on the ONE_JUDGE signal S 9 input from the one gradation determination circuit 131 and outputs the selected output to the output selection circuit 22. More specifically, the gradation output short circuit 132 shorts all outputs of the plurality of gradation amplifiers 6 when it is determined that one gradation is in one line.

  As a result, since the amplifier control circuit 133 has selected, the output line of the gradation amplifier 6 to which only the voltage is supplied and the output lines of the other gradation amplifiers 6 that do not share the voltage are connected, and all of them are connected. The same voltage is supplied to the output line of the gradation amplifier 6. Therefore, even if the control signal for each pixel is not sent from the decoder 21 in the output selection circuit 22, the output selection circuit 22 outputs one gradation for all pixels based on the voltage supplied from the gradation output short circuit 132. be able to. At this time, since the operation from the load latch circuit 3 to the decoder 21 is stopped by the control from the one gradation determination circuit 131, the power consumption can be reduced.

FIG. 3 is a block diagram showing a configuration of the amplifier control circuit 133 according to the first embodiment of the present invention. The amplifier control circuit 133 includes 2 ⁿ NANDs 38 and AND 39. The amplifier control circuit 133 receives the ONE_DATA [n-1: 0] signal S8 and the ONE_JUDGE signal S9, decodes them using the NAND 38 and the AND 39, and outputs AMP_STOP_0 to AMP_STOP_2 ⁿ⁻¹ to the corresponding gradation amplifier 6.

  FIG. 4 is a timing chart of the 1 gradation determination circuit 131 according to the first embodiment of the present invention. First, when the one-line start pulse S5 becomes H (timing T1), SR34 which is an SR latch in the one-gradation determination circuit 131 is set, and the SR_OUT signal S7 which is a determination result is initialized to H.

  Next, from the state in which the determination result is initialized, it is determined whether or not each bit has changed in one line using the mismatch circuit 140 for the input digital gradation data S3 (timing T1 to T2). ).

  If any bit of the digital gradation data does not change in one line, the mismatch circuit 140 that inputs each bit of the digital gradation data S3 continues to output L. Since the output of the OR 33 also outputs L, the SR 34 is not reset, and the initialization state at the timing T1 is maintained. Therefore, the 1 gradation determination circuit 131 determines that 1 line is 1 gradation (timing T2).

  The SR_OUT signal S7 determined to have one gradation in one line is held in the FF 36 as the ONE_JUDGE signal S9 at the rising edge of the one-line end pulse S6. Further, which gradation is the same gradation at the same timing is held in the FF 35 as a ONE_DATA [n-1: 0] signal S8 (timing T3).

  When one line has one gradation, the ONE_JUDGE signal S9 held in the FF 36 becomes H, and the AND 37 invalidates the load signal S4, so that the one gradation determination circuit 131 performs the latch operation of the load latch circuit 3. Stop.

The amplifier control circuit 133 stops the unnecessary gradation amplifier 6 based on the results of the ONE_JUDGE signal S9 and the ONE_DATA [n-1: 0] signal S8. When the ONE_JUDGE signal S9 is H, since one line has one gradation, the amplifier control circuit 133 generates a decode value of the ONE_DATA [n-1: 0] signal S8 by the NAND 38. As a result, any ^one of AMP_STOP_0 to ^2n-1 becomes L, and only one gradation amplifier 6 operates.

  The gradation output short circuit 132 shorts all the outputs of the gradation amplifier 6 when the ONE_JUDGE signal S9 is H (timing T3 to T4).

  By the operation from timings T1 to T4, it is possible to realize one gradation output from the output terminal in a state where the operation after the load latch circuit 3 is stopped on the next line.

  From timing T4, the 1 gradation determination circuit 131 receives H of the 1 line start pulse S5 again, the SR_OUT signal S7 as the determination result is initialized, and the determination in 1 line is performed.

  When any bit of the digital gradation data changes in one line, the mismatch circuit 140 that inputs the changed bit of the digital gradation data outputs H, the output of OR33 becomes H, and SR34 is reset. To do. Thereby, the 1 gradation determination circuit 131 determines that 1 line is not 1 gradation (timing T5).

  The SR_OUT signal S7 determined not to have one gradation in one line is held in the FF 36 as the ONE_JUDGE signal S9 at the rise of the one-line end pulse S6 (timing T6).

When one line is not one gradation, the ONE_JUDGE signal S9 held in the FF 36 becomes L, and the latch operation of the load latch circuit 3 operates normally. In addition, since the ONE_JUDGE signal S9 input to the AND 39 is also L in the amplifier control circuit 133, all the signals of AMP_STOP_0 to ²ⁿ⁻¹ are L, and the gradation amplifier 6 is not stopped. The gradation output short circuit 132 also receives L of the ONE_JUDGE signal S9 and does not perform all output shorts (timing T6 to T7).

  By the operation from timing T4 to T7, the next line is a multi-tone output from the output terminal in the normal operation.

  From the above, there is a reduction in current consumption as an effect in the first embodiment of the present invention. The reason is that when all the lines have one gradation, the operation of the load latch circuit 3, the level shifter 4 and the decoder 21 can be stopped by stopping the load latch circuit 3.

  Further, the drive circuit of the display device according to the present invention determines from the input digital gradation data that the gradation used in one line is only one gradation, and based on the determination result, the load latch circuit. One gradation determination circuit for controlling, an amplifier control circuit controlled by the determination result of the one gradation determination circuit, and a gradation output short circuit for selecting one gradation output based on the determination result of the one gradation determination circuit Circuit. If all the lines have the same gradation, the load latch circuit is stopped according to the determination result of the one gradation determination circuit, so that the current consumption can be reduced by not operating the load latch circuit, the level shifter, and the decoder. Become.

  Note that the present invention is not limited to the above-described embodiment, and can be changed as appropriate without departing from the spirit of the present invention.

DESCRIPTION OF SYMBOLS 100 Drive circuit 1 Shift register 2 Data latch circuit 3 Load latch circuit 4 Level shifter 6 Gradation amplifier 7 Gradation voltage generation circuit 21 Decoder 22 Output selection circuit 23 Gradation data use judgment circuit 25 Amplifier enable circuit 131 1 Gradation judgment circuit 132 Gradation output short circuit 133 Amplifier control circuit S1 Shift pulse S2 Transfer clock S3 Digital gradation data S4 Load signal S5 One line start pulse S6 One line end pulse S7 SR_OUT signal S8 ONE_DATA [n-1: 0] signal S9 ONE_JUDGE signal 140 Mismatch circuit 31 FF
32 EXOR
33 OR
34 SR
35 FF
36 FF
37 AND
38 NAND
39 AND
900 Liquid crystal drive circuit T1 timing T2 timing T3 timing T4 timing T5 timing T6 timing T7 timing

Claims (8)

A determination circuit for determining whether or not a plurality of digital gradation data inputted for each pixel is the same among all the pixels in one line;
A stop circuit for stopping the control for each pixel in the one line based on the plurality of digital gradation data when the determination circuit determines that they are the same;
A gradation output circuit that outputs the one gradation determined to be the same to all the pixels of the one line when the determination circuit determines that they are the same;
A display device drive circuit comprising: The drive circuit of the display device further includes a load latch circuit that performs latch control for each pixel in the one line based on the plurality of digital gradation data,
The display device driving circuit according to claim 1, wherein the stop circuit stops latch control in the load latch circuit when it is determined by the determination circuit that they are the same. The display device drive circuit comprises:
A plurality of gradation amplifiers corresponding to the number of gradations that can be displayed by the display device;
The gradation output circuit includes:
When the determination circuit determines that they are the same, a gradation amplifier corresponding to the one gradation determined to be the same among the plurality of gradation amplifiers is selected, and the gradation amplifier corresponding to the selected gradation amplifier is selected. The display device driving circuit according to claim 1, wherein the gradation is output through the other gradation amplifier not selected. The gradation output circuit includes:
The gradation amplifiers other than the gradation amplifier corresponding to one gradation determined to be the same among the plurality of gradation amplifiers are stopped, and all outputs of the plurality of gradation amplifiers are short-circuited. A drive circuit for a display device according to claim 3. Determining whether or not a plurality of digital gradation data inputted for each pixel is the same among all the pixels in one line;
When it is determined that they are the same, the control for each pixel in the one line based on the plurality of digital gradation data is stopped,
If it is determined that the same, the one gradation determined to be the same is output to all pixels of the one line;
A method for controlling a driving circuit of a display device. The drive circuit of the display device further includes a load latch circuit that performs latch control for each pixel in the one line based on the plurality of digital gradation data,
The control method according to claim 5, wherein when it is determined that they are the same, the latch control in the load latch circuit is stopped. The driving circuit of the display device further includes a plurality of gradation amplifiers corresponding to the number of gradations that can be displayed on the display device,
If it is determined that they are the same, select a gradation amplifier corresponding to one gradation determined to be the same among the plurality of gradation amplifiers;
7. The control method according to claim 5, wherein a gradation corresponding to the selected gradation amplifier is output via another gradation amplifier that is not selected. Stop gradation amplifiers other than the gradation amplifier corresponding to one gradation determined as the same among the plurality of gradation amplifiers,
The control method according to claim 7, wherein all outputs of the plurality of gradation amplifiers are short-circuited.

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