JP2012044406A - Semiconductor integrated circuit and method of testing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit in which an influence of phase noise of a sampling clock on transfer characteristics of a DAC and an ADC can be detected and the quality of a loop-back test can be improved, and to provide a method of testing the same.SOLUTION: A semiconductor integrated circuit comprises: a DAC that operates synchronously with a sampling clock and converts a digital signal into an analog signal; an ADC that operates synchronously with the sampling clock and converts an analog signal into a digital signal; a sampling clock generating circuit for generating first and second sampling clocks having different phase noise characteristics based on a reference clock; and a sampling clock switching circuit for supplying the first sampling clock to one of the DAC and the ADC and for supplying the second sampling clock to the other of the DAC and the ADC during a loop-back test in which the analog signal from the DAC is inputted to the ADC or the digital signal from the ADC is inputted to the DAC.

Description

  The present invention relates to a semiconductor integrated circuit equipped with both a DAC (Digital to Analog Converter) and an ADC (Analog to Digital Converter) and a test method thereof.

  In a semiconductor integrated circuit equipped with both a DAC and an ADC, for example, in a DAC test, a digital signal (digital data for testing) is input from the outside of the semiconductor integrated circuit, and is output from the DAC to the outside of the semiconductor integrated circuit. This is done by sampling an analog signal with an LSI tester. On the other hand, the ADC test is performed by inputting an analog signal (analog data for testing) from the outside of the semiconductor integrated circuit and measuring a digital signal output from the ADC to the outside of the semiconductor integrated circuit with an LSI tester.

  In recent years, DACs and ADCs have been increased in bit speed and speed, and performance has been increasing. In particular, communication devices tend to be mounted with, for example, digital signals having a resolution of 10 bits or more and a sampling clock operating speed of 100 MHz or more. In order to perform such high-performance DAC and ADC tests, high-bit high-speed digital data and high-frequency analog data are input to the semiconductor integrated circuit and output from the semiconductor integrated circuit. Therefore, a high-performance measuring instrument or LSI tester capable of testing high-speed digital data and high-frequency analog data with high bits is required.

  However, when testing a semiconductor integrated circuit equipped with both a DAC and an ADC, the problem is the function and high accuracy required for an LSI tester, and the purpose is to solve this problem. Conventionally, various methods have been proposed.

  As a conventional test method, for example, a method using an external test apparatus (BOST) in which a test signal is supplied to a DAC and ADC to be tested, or a circuit for processing an output signal is incorporated (see Patent Document 1) , A method that allows external test equipment to have multiple functions and enables processing with an inexpensive tester (see Patent Document 2), and further, test signal generation and signal correction inside a DUT (Device Under Test) There is a method of performing a functional test of DAC and ADC by incorporating an integrated circuit having a function (see Patent Documents 3 and 4).

JP 2002-236151 A US Pat. No. 7,327,153 JP 2008-252235 A JP 2009-17359 A

  A tester maker provides a mixed signal tester which is a dedicated test device for testing a semiconductor integrated circuit equipped with a DAC and an ADC. However, this semiconductor integrated circuit test device is extremely expensive. There is a point.

  On the other hand, an analog signal output from the DAC to the outside of the semiconductor integrated circuit is looped back and input to the ADC inside the semiconductor integrated circuit, or a digital signal output from the ADC is input to the DAC. (Loopback test) is known. This test method eliminates the need for a high-performance and expensive mixed signal tester, and is an effective method for reducing test costs.

  Hereinafter, a conventional semiconductor integrated circuit on which a DAC and an ADC are mounted and a test method of the loopback method will be described.

  FIG. 4 is a conceptual block diagram illustrating an example of a configuration of a conventional semiconductor integrated circuit. The semiconductor integrated circuit 50 shown in FIG. 1 includes a DAC 54, an output amplifier (PGA) 56, an input amplifier (PGA) 58, an ADC 60, and a sampling clock generation circuit 64. The sampling clock generation circuit 64 is configured by a PLL circuit (PLL 2x) 68.

  During the test operation, a 62.5 MHz reference clock and a 12-bit digital signal (digital data for testing) synchronized with the reference clock are input to the semiconductor integrated circuit 50 from the semiconductor automatic test apparatus (ATE) 72.

  In the semiconductor integrated circuit 50, the 62.5 MHz reference clock input from the semiconductor automatic test apparatus 72 is multiplied by 2 by the PLL circuit 68 of the sampling clock generation circuit 64 to generate an internal clock of 125 MHz, and both the DAC 54 and the ADC 60 are generated. Are input in common.

  On the other hand, the 12-bit (12b) digital signal input from the semiconductor automatic test apparatus 72 is converted into an analog signal (differential) by the DAC 54 in synchronization with the 125 MHz sampling clock input from the sampling clock generation circuit 64. After the gain adjustment is performed by the output amplifier 56, the gain is output to the outside of the semiconductor integrated circuit 50.

  The analog signal (differential) output to the outside of the semiconductor integrated circuit 50 is looped back to the inside of the semiconductor integrated circuit 50, gain adjustment is performed by the input amplifier 58, and then input to the ADC 60. Then, the ADC 60 converts it into a 12-bit (12b) digital signal in synchronization with the 125 MHz sampling clock input from the sampling clock generation circuit 64, and outputs it to the outside of the semiconductor integrated circuit 50.

  The semiconductor automatic test apparatus 72 compares the 12-bit digital signal input to the semiconductor integrated circuit 50 with the 12-bit digital signal output from the semiconductor integrated circuit 50, and detects a match or mismatch between the two. Done. In order to avoid an increase in chip area, one sampling clock is usually arranged for the test chip, and a common clock is supplied to the DAC and ADC. Further, even when the operating frequencies of the DAC and the ADC are different, a frequency divider can be added to the output of the PLL, and the frequency required for both can be realized with one sampling clock.

  As described above, in the conventional loopback test, the same sampling clock is input to both the DAC 54 and the ADC 60. However, in this test method, since the DAC 54 and the ADC 60 are simultaneously operated with the same sampling clock, the verification of the individual functional blocks is insufficient as compared with the case of individually testing, and the test quality is low. It became clear that there was a problem of lowering.

  That is, the phase noise characteristic (jitter characteristic) of the PLL circuit 68 affects the conversion characteristics of the DAC 54 and the ADC 60. For example, it is a well-known fact that the S / N ratio of the digital signal output from the ADC 60 decreases according to the phase noise characteristics of the PLL circuit 68. In the function test of the semiconductor integrated circuit 50, the conversion characteristics are evaluated, Judgment is required.

  However, when the same sampling clock is input to both the DAC 54 and the ADC 60 during the loopback test as in the semiconductor integrated circuit 50, the influence of the phase noise characteristics of the PLL circuit 68 on the conversion characteristics of the DAC 54 and the ADC 60. Therefore, it is difficult to detect the influence of the phase noise characteristics of the PLL circuit 68 on the conversion characteristics of the DAC 54 and the ADC 60.

  As shown in FIG. 5, at the time of the loopback test, the input signal cos (ωt) is input to the DAC, and the output signal y (t) is output from the DAC, which is looped back and the input signal y (t) is transferred to the ADC. Assume that an output signal ylb ′ (t) is output from the ADC.

  In the DAC, the phase noise component φcj (dac) of the sampling clock is combined with the phase noise component φij (dac) of the input signal cos (ωt). That is, the output signal y (t) from the DAC includes the phase noise component φcj (dac) of the sampling clock input to the DAC.

  Also in the ADC, the phase noise component φcj (adc) of the sampling clock is combined with the phase noise component φij (adc) of the input signal y (t), and the output signal ylb ′ (t) from the ADC is input to the ADC. A phase noise component φcj (adc) of the sampling clock. However, when the same sampling clock is input to both the DAC and the ADC, the phase noise component φcj (dac) of the sampling clock input to the DAC included in the input signal φij (adc) to the ADC and the ADC are input. The sampling clock phase noise component φcj (adc) cancels each other out, and the phase noise component of the sampling clock is removed from the ADC output signal ylb ′ (t).

  FIG. 6 is a graph obtained by fast Fourier transform (FFT) of a digital signal output from the semiconductor integrated circuit shown in FIG. The vertical axis of the graph is the amplitude spectrum (dBm) of the digital signal, and the horizontal axis is the frequency (Hz). As shown in this graph, when the same sampling clock is input to both the DAC 54 and the ADC 60, the amplitude spectrum of the digital signal is almost uniform over all frequencies, and the phase noise characteristic of the sampling clock is detected. I can't understand.

  FIG. 6 shows the values of SNR, SINAD, and SFDR. SNR is the S / N ratio of only the basic component of the sampling clock included in the digital signal output from the semiconductor integrated circuit 50 during the loopback test, and SINAD is the S / N ratio when the basic component and the high frequency component are included. , SFDR represents the S / N ratio when only the fundamental component and the next highest signal component are included. SNR = 55.37 dB, SINAD = 55.37 dB, and SFDR = 67.84 dB.

  An object of the present invention is to provide a semiconductor integrated circuit capable of detecting the influence of phase noise of a sampling clock on the conversion characteristics of a DAC and an ADC and improving the test quality of a loopback test, and a test method therefor. There is.

To achieve the above object, the present invention operates in synchronization with a sampling clock and converts a digital signal into an analog signal;
An ADC that operates in synchronization with a sampling clock and converts an analog signal into a digital signal;
A sampling clock generation circuit for generating first and second sampling clocks having different phase noise characteristics based on a reference clock;
In a loopback test in which an analog signal output from the DAC is input to the ADC or a digital signal output from the ADC is input to the DAC, one of the DAC and the ADC receives the first sampling clock. And a sampling clock switching circuit for supplying the second sampling clock to the other. A semiconductor integrated circuit is provided.

  Here, it is preferable that the sampling clock generation circuit includes a PLL circuit that generates the second sampling clock from the reference clock, and further outputs the reference clock as the first sampling clock. .

  The sampling clock generation circuit preferably includes two PLL circuits that generate the first and second sampling clocks from the reference clock.

  Further, the sampling clock switching circuit further supplies one of the first and second sampling clocks to both the DAC and the ADC at the time of evaluating the characteristics of the DAC and the ADC. Is preferred.

The present invention also provides a semiconductor integrated circuit comprising a DAC that operates in synchronization with a sampling clock and converts a digital signal into an analog signal, and an ADC that operates in synchronization with the sampling clock and converts an analog signal into a digital signal. In the loopback test method, an analog signal output from the DAC is input to the ADC, or a digital signal output from the ADC is input to the DAC.
A sampling clock generation circuit generates first and second sampling clocks having different phase noise characteristics based on the reference clock,
A testing method for a semiconductor integrated circuit, wherein a sampling clock switching circuit supplies the first sampling clock to one of the DAC and the ADC and supplies the second sampling clock to the other. I will provide a.

  Here, it is preferable that the sampling clock generation circuit generates the second sampling clock from the reference clock by a PLL circuit and outputs the reference clock as the first sampling clock signal.

  Preferably, the sampling clock generation circuit generates the first and second sampling clocks from the reference clock by two PLL circuits.

  Further, it is preferable that the sampling clock switching circuit further supplies one of the first and second sampling clocks in common to both the DAC and the ADC when evaluating the characteristics of the DAC and the ADC.

  According to the present invention, phase noise characteristics can be detected in a loopback test that is easy to test. Therefore, the test quality of the loopback test can be improved without increasing the test cost.

1 is a block conceptual diagram of a first embodiment illustrating a configuration of a semiconductor integrated circuit of the present invention. 2 is a graph obtained by fast Fourier transform (FFT) of a digital signal output from the semiconductor integrated circuit shown in FIG. It is a block conceptual diagram of 2nd Embodiment showing the structure of the semiconductor integrated circuit of this invention. It is an example block conceptual diagram showing the structure of the conventional semiconductor integrated circuit. It is a conceptual diagram showing the influence of a phase noise at the time of inputting the same sampling clock into DAC and ADC at the time of a loopback test. 5 is a graph obtained by performing a fast Fourier transform (FFT) on a digital signal output from the semiconductor integrated circuit shown in FIG.

  Hereinafter, a semiconductor integrated circuit and a test method thereof according to the present invention will be described in detail based on preferred embodiments shown in the accompanying drawings.

  FIG. 1 is a block conceptual diagram of the first embodiment showing the configuration of the semiconductor integrated circuit of the present invention. The semiconductor integrated circuit 10 shown in FIG. 1 includes a DAC 14, an output amplifier (PGA) 16, an input amplifier (PGA) 18, an ADC 20, a sampling clock generation circuit 24, and a sampling clock switching circuit 26. . FIG. 2 also shows a semiconductor automatic test apparatus (ATE) 32 that automatically tests the semiconductor integrated circuit 10.

  The sampling clock generation circuit 24 generates first and second sampling clocks based on a 125 MHz reference clock input from the semiconductor automatic test apparatus 32, and is configured by a PLL circuit (PLL 1x) 28. Yes. The sampling clock generation circuit 24 outputs the 125 MHz reference clock as it is as the first sampling clock SC1, and also multiplies the reference clock by 1 by the PLL circuit 28, and outputs this internal clock as the second sampling clock SC2.

  Here, the first and second sampling clocks SC <b> 1 and SC <b> 2 are sampling clocks of the same frequency supplied to either the DAC 14 or the ADC 20. Since the first and second sampling clocks SC1 and SC2 have different clock generation sources, their phase noise characteristics (jitter characteristics) are also different. While eliminating the jitter of the reference clock, the jitter characteristics of the PLL are added. The PLL characteristics can be confirmed by supplying a clock with reduced jitter during the test.

  The sampling clock switching circuit 26 receives the first and second sampling clocks SC1 and SC2 from the sampling clock generation circuit 24. The sampling clock switching circuit 26 loops back the analog signal (differential) output from the DAC 14 to the ADC 20 inside the semiconductor integrated circuit 10 and inputs it to the ADC 20 inside the semiconductor integrated circuit 10. The first sampling clock SC1 is supplied to one side, and the second sampling clock SC2 is supplied to the other side.

  Although not shown, the sampling clock switching circuit 26 receives a test signal for switching between normal operation and test operation. In accordance with this test signal, switching between normal operation and test operation and switching of the supply state of the sampling clock can be performed. In the example of FIG. 1, in order to eliminate the jitter of the sampling clock and check the characteristics of the DAC and ADC in the normal operation according to the test signal, the DAC 14 and the second sampling clock SC2 are used as a common clock. During the test operation, the first sampling clock SC1 is input to the ADC 20, and the second sampling clock SC2 is input to the DAC 14.

  Further, in accordance with the test signal, the first sampling clock SC1 may be input to the DAC 14 and the second sampling clock SC2 may be input to the ADC 20 during the test operation. Further, according to the test signal, during the test operation, the supply state of the first and second sampling clocks SC1 and SC2 shown in FIG. 1 and the supply state of the first and second sampling clocks SC1 and SC2 are changed. You may enable it to switch.

  The DAC 14 operates in synchronization with the 125 MHz second sampling clock SC2 input from the sampling clock switching circuit 26 during the test operation, and converts the 12-bit digital signal into an analog signal (differential).

  Here, the analog signal (differential) output from the DAC 14 is output to the outside of the semiconductor integrated circuit 10 after gain adjustment is performed by the output amplifier 16. During the test operation, an analog signal (differential) output from the DAC 14 to the outside of the semiconductor integrated circuit 10 is looped back to the inside of the semiconductor integrated circuit 10, gain adjustment is performed by the input amplifier 18, and then input to the ADC 20. The

  The ADC 20 operates in synchronization with the 125 MHz first sampling clock SC1 input from the sampling clock switching circuit 26 during the test operation, and the analog signal (differential) input from the input amplifier 18 is 12 bits (12b). Converted to a digital signal and output.

  During the test operation, the semiconductor automatic test apparatus 32 inputs a 125 MHz reference clock and a 12-bit digital signal to the semiconductor integrated circuit 10, and outputs a 125 HMz sampling clock output from the semiconductor integrated circuit 10 and a 12-bit digital signal. receive. Then, a 12-bit digital signal input to the semiconductor integrated circuit 10 is compared with a 12-bit digital signal output from the semiconductor integrated circuit 10, and a test is performed to detect a match or mismatch between them.

  The specific circuit configurations of the sampling clock generation circuit 24 and the sampling clock switching circuit 26 are not limited at all. These components include first and second sampling clocks having a predetermined frequency used by the DAC 14 and the ADC 20 according to the frequency of the reference clock input from the semiconductor automatic test apparatus 32 and having different phase noise characteristics. The circuit configuration is not limited as long as it can be generated and supplied to the DAC 14 and the ADC 20.

  The semiconductor automatic test apparatus 32 compares the 12-bit digital signal input to the semiconductor integrated circuit 10 with the 12-bit digital signal output from the semiconductor integrated circuit 10 to detect a match or mismatch between them. Done.

  FIG. 2 is a graph obtained by fast Fourier transform (FFT) of a digital signal output from the semiconductor integrated circuit shown in FIG. The vertical axis of the graph is the amplitude spectrum (dBm) of the digital signal, and the horizontal axis is the frequency (Hz). As indicated by the oval in this graph, the sampling clock generation circuit 24 of the semiconductor integrated circuit 10 has a second sampling clock in which the amplitude spectrum of the digital signal fluctuates in the vicinity of the frequency of 2.00E + 07 (Hz). It is thought that the influence by the phase noise characteristic of SC2 is represented.

  Further, FIG. 2 shows values of SNR, SINAD, and SFDR. As shown in FIG. 2, in the semiconductor integrated circuit 10, SNR = 52.22 dB, SINAD = 52.21 dB, SFDR = 59.56 dB, and SNR = 55.37 dB in the conventional semiconductor integrated circuit 50 shown in FIG. Compared to SINAD = 55.37 dB and SFDR = 67.84 dB, the S / N ratio is small for all of SNR, SINAD, and SFDR, that is, the influence of the phase noise characteristic of the PLL circuit 28 appears. It is done.

  As described above, the second sampling clock SC2 input to the DAC 14 and the first sampling clock SC1 input to the ADC 20 have different clock noise sources, and therefore have different phase noise characteristics. For this reason, in the loopback test, the effects of the phase noise characteristics of the first and second sampling clocks SC1 and SC2 on the conversion characteristics of the DAC 54 and the ADC 60 are not offset each other. It is possible to detect the effect.

  As described above, in the semiconductor integrated circuit 10 that performs the loopback test by applying the test method of the present invention, it is possible to detect the phase noise characteristic in the loopback test that is excellent in the testability, thereby increasing the test cost. The quality of the loopback test can be improved without doing so. Further, a test can be performed even with a low-function LSI tester, and the test cost can be reduced. Furthermore, it is possible to perform DAC and ADC function tests in a short time, and to detect defects efficiently.

  Next, a semiconductor integrated circuit according to a second embodiment of the present invention will be described.

  FIG. 3 is a block conceptual diagram of the second embodiment showing the configuration of the semiconductor integrated circuit of the present invention. The only difference between the semiconductor integrated circuit 40 shown in FIG. 1 and the semiconductor integrated circuit 10 shown in FIG. 1 is the configuration of the sampling clock generation circuit 42 and the sampling clock switching circuit 46. Are denoted by the same reference numerals, detailed description thereof is omitted, and the sampling clock generation circuit 42 and the sampling clock switching circuit 46 will be mainly described.

  The sampling clock generation circuit 42 generates the first and second sampling clocks SC1 and SC2 based on the 62.5 MHz reference clock input from the semiconductor automatic test apparatus 32, and includes two PLL circuits (PLL 2x) 44a and 44b. The sampling clock generation circuit 42 doubles the 62.5 MHz reference clock by the PLL circuit 44a, and outputs this first internal clock as the first sampling clock SC1. Similarly, the sampling clock generation circuit 42 doubles the 62.5 MHz reference clock by the PLL circuit 44b, and outputs this second internal clock as the second sampling clock SC2. Further, the frequency of the sampling clock can be appropriately changed according to the multiplication number in the PLL circuit 28 as in the case of the conventional semiconductor integrated circuit 50.

  Here, as in the case of the semiconductor integrated circuit 10, the first and second sampling clocks SC1 and SC2 have different clock noise sources, and therefore have different phase noise characteristics (jitter characteristics).

  Note that the test signal is also input to the sampling clock switching circuit 46 of the semiconductor integrated circuit 40, and switching between the normal operation and the test operation and the switching state of the sampling clock are performed in accordance with the test signal. In the example of FIG. 3, during the test operation, the first sampling clock SC1 is input to the ADC 20 and the second sampling clock SC2 is input to the DAC 14. However, the supply states of the first and second sampling clocks may be reversed. However, these two supply states may be switched. During normal operation (characteristic evaluation), one sampling clock of the first and second sampling clocks is supplied to the DAC 14 and ADC 20.

  In the semiconductor integrated circuit 40, during the test operation, the 62.5 MHz reference clock input from the sampling clock generation circuit 42 from the semiconductor automatic test apparatus 32 is doubled by the PLL circuit 42a, and the 125 MHz first internal clock is Output as the first sampling clock SC1. Further, the reference clock is doubled by the PLL circuit 42b, and the second internal clock of 125 MHz is output as the second sampling clock SC2.

  As in the case of the semiconductor integrated circuit 10, the sampling clock switching circuit 46 inputs the first sampling clock SC 1 output from the sampling clock generation circuit 24 to the ADC 20, and the second sampling clock SC 2 is input to the DAC 14. Is done. The subsequent operation is the same as that of the semiconductor integrated circuit 10.

  Also in the semiconductor integrated circuit 40, the second sampling clock SC2 input to the DAC 14 and the first sampling clock SC1 input to the ADC 20 have different clock noise sources, and therefore have different phase noise characteristics. Therefore, the effects of the phase noise characteristics of the first and second sampling clocks on the conversion characteristics of the DAC 54 and the ADC 60 are not canceled out from each other, and the effects on the conversion characteristics of the DAC 54 and the ADC 60 can be detected. .

  Further, according to the present invention, the frequency is made variable by a sampling clock generation circuit including a reference clock, so that not only the phase noise characteristic of the sampling clock but also the characteristics of the DAC and ADC (bit width, variable rate, etc.) are met. Various test conditions can be set, and both the first and second embodiments can facilitate testing. This is because in the present invention, by providing a sampling clock switching circuit, variations in the frequency of the supplied clock can be increased more easily than in the prior art.

The present invention is basically as described above.
Although the present invention has been described in detail above, the present invention is not limited to the above-described embodiment, and it is needless to say that various improvements and modifications may be made without departing from the gist of the present invention.

10, 40, 50 Semiconductor integrated circuit 14, 54 DAC
16,56 output amplifier (IAMP)
18,58 Input amplifier (PGA)
20,60 ADC
24, 42, 64 Sampling clock generation circuit 26, 46 Sampling clock switching circuit 28, 44a, 44b, 68 PLL circuit 32, 72 Semiconductor automatic test equipment (ATE)

Claims (8)

A DAC that operates in synchronization with a sampling clock and converts a digital signal into an analog signal;
An ADC that operates in synchronization with a sampling clock and converts an analog signal into a digital signal;
A sampling clock generation circuit for generating first and second sampling clocks having different phase noise characteristics based on a reference clock;
In a loopback test in which an analog signal output from the DAC is input to the ADC or a digital signal output from the ADC is input to the DAC, one of the DAC and the ADC receives the first sampling clock. And a sampling clock switching circuit for supplying the second sampling clock to the other.   The sampling clock generation circuit includes a PLL circuit that generates the second sampling clock from the reference clock, and further outputs the reference clock as the first sampling clock. Semiconductor integrated circuit.   2. The semiconductor integrated circuit according to claim 1, wherein the sampling clock generation circuit includes two PLL circuits that generate the first and second sampling clocks from the reference clock.   2. The sampling clock switching circuit further supplies one of the first and second sampling clocks in common to both the DAC and the ADC when evaluating characteristics of the DAC and the ADC. A semiconductor integrated circuit according to 1. In a semiconductor integrated circuit including a DAC that operates in synchronization with a sampling clock and converts a digital signal into an analog signal, and an ADC that operates in synchronization with the sampling clock and converts an analog signal into a digital signal, output from the DAC An analog signal to be input to the ADC, or a digital signal output from the ADC to the DAC.
A sampling clock generation circuit generates first and second sampling clocks having different phase noise characteristics based on the reference clock,
A testing method for a semiconductor integrated circuit, wherein a sampling clock switching circuit supplies the first sampling clock to one of the DAC and the ADC and supplies the second sampling clock to the other. .   6. The test of a semiconductor integrated circuit according to claim 5, wherein the sampling clock generation circuit generates the second sampling clock from the reference clock by a PLL circuit and outputs the reference clock as the first sampling clock signal. Method.   6. The method of testing a semiconductor integrated circuit according to claim 5, wherein the sampling clock generation circuit generates the first and second sampling clocks from the reference clock by two PLL circuits.   The sampling clock switching circuit further supplies one of the first and second sampling clocks in common to both the DAC and the ADC when evaluating characteristics of the DAC and the ADC. A method for testing a semiconductor integrated circuit.