JP2012043888A - Semiconductor device, and method of manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device that can be downsized.SOLUTION: A semiconductor device 10 has: a substrate 17 having an opening 12 provided so as to penetrate from one surface to the other surface 11b, a wire 19 connected with an external electrode 28, and an inner lead 7 having one end connected with the wire 19 and the other end exposed into the opening 12; and a semiconductor chip 16 mounted on one side of the substrate 17. The semiconductor chip 16 has an electrode pad group 15 including two or more electrode pads 5 that are arranged so as to be exposed from the opening 12, and that have the same potential. The two or more electrode pads 5 with the same potential are connected to one inner lead 7.

Description

  The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device.

  As an example of a conventional semiconductor device, there is, for example, a semiconductor package such as a BGA (Ball Grid Array) type or a CSP (Chip Size Package) type. Such a semiconductor package has a structure in which a semiconductor chip is mounted on a substrate and the semiconductor chip and the substrate are connected by wire bonding or the like.

  As a BGA type semiconductor device, a semiconductor chip has a chip pad, a package substrate has an opening for facing the chip pad outward, and a bonding pad is provided at one end of a package wiring arranged on the package substrate. In some cases, solder balls are provided at the other end, and the chip pads and bonding pads are electrically connected via bonding wires (see, for example, Patent Document 1).

  Moreover, as a conventional semiconductor device, for example, in Patent Document 2, a plurality of electrode pads are aligned on one main surface of a semiconductor pellet, and electrode pads are also provided at positions separated from this electrode pad group row. A main bonding hole is opened in the tape body of the TAB tape, and a sub-bonding hole is opened beside the main bonding hole, and a plurality of inner wires laid on the tape body are arranged. It is described that the leading end portion of the lead is gang-bonded to each of the electrode pads in the main bonding hole and the sub-bonding hole.

  Moreover, as a conventional semiconductor device, for example, in Patent Document 3, a plurality of TAB film leads electrically connected to a semiconductor chip are formed on a connection pad of a lead frame. The semiconductor integrated circuit device connected in parallel is described.

JP 2008-198841 A JP 2003-059980 A Japanese Patent Laid-Open No. 06-268152

However, in the conventional semiconductor device, it may be difficult to route the package wiring on the package substrate, or the circuit wiring may become a long-distance wiring, and it is necessary to secure a wide wiring space. It was difficult to cope with downsizing.
Specifically, for example, in the technique described in Patent Document 1, in addition to the restriction on the number of solder balls, the number of package wirings arranged between solder balls is reduced because only one wiring layer is included in the package wiring. Therefore, it is difficult to route the package wiring on the package substrate, and it is easy to make a long-distance wiring.

The present inventor has intensively studied to solve the above problems.
As a result, a substrate having an inner lead having one end connected to the wiring and the other end exposed in the opening, and having the same potential among the plurality of electrode pads of the semiconductor chip arranged to be exposed from the opening By assuming that two or more electrode pads are connected to one of the inner leads, the number of wirings arranged on the substrate with respect to the number of electrode pads can be reduced, and the wiring arrangement on the substrate is free. It has been found that a semiconductor device suitable for miniaturization of a semiconductor device can be obtained, and the semiconductor device and the method for manufacturing the semiconductor device of the present invention have been conceived.

  The semiconductor device according to the present invention includes an opening provided from one surface to the other surface, a wiring connected to an external electrode, an inner end connected to the wiring and the other end exposed in the opening. An electrode pad group comprising a substrate having leads and a semiconductor chip mounted on one surface of the substrate, wherein the semiconductor chip is disposed so as to be exposed from the opening. The two or more electrode pads having the same potential are connected to one of the inner leads.

  The semiconductor device according to the present invention includes an opening provided from one surface to the other surface, a wiring connected to an external electrode, an inner end connected to the wiring and the other end exposed in the opening. An electrode pad group comprising a substrate having leads and a semiconductor chip mounted on one surface of the substrate, wherein the semiconductor chip is disposed so as to be exposed from the opening. Since the two or more electrode pads having the same potential are connected to one of the inner leads, the number of wirings arranged on the substrate with respect to the number of electrode pads can be reduced. As a result, the degree of freedom of wiring arrangement on the substrate can be improved, and the semiconductor device is suitable for downsizing.

FIG. 1 is a diagram for explaining the semiconductor device according to the first embodiment which is an example of the semiconductor device of the present invention, and is a plan view of the semiconductor device viewed from the lower surface side. FIG. 2 is a view for explaining the semiconductor device according to the first embodiment which is an example of the semiconductor device of the present invention, and is a cross-sectional view corresponding to the line A-A ′ of FIG. 1. FIG. 3A is a view for explaining the semiconductor device manufacturing method of the first embodiment as an example of the semiconductor device manufacturing method of the present invention, and is a cross-sectional view corresponding to the line AA ′ of FIG. . FIG. 3B is a diagram for explaining the semiconductor device manufacturing method of the first embodiment as an example of the semiconductor device manufacturing method of the present invention, and is a cross-sectional view corresponding to the line AA ′ of FIG. 1. . FIG. 3C is a view for explaining the semiconductor device manufacturing method of the first embodiment as an example of the semiconductor device manufacturing method of the present invention, and is a cross-sectional view corresponding to the line AA ′ of FIG. 1. . FIG. 3D is a view for explaining the semiconductor device manufacturing method of the first embodiment as an example of the semiconductor device manufacturing method of the present invention, and is a cross-sectional view corresponding to the line AA ′ of FIG. 1. . FIG. 3E is a view for explaining the semiconductor device manufacturing method of the first embodiment as an example of the semiconductor device manufacturing method of the present invention, and is a cross-sectional view corresponding to the line AA ′ of FIG. 1. . FIG. 3F is a view for explaining the semiconductor device manufacturing method of the first embodiment as an example of the semiconductor device manufacturing method of the present invention, and is a cross-sectional view corresponding to the line AA ′ of FIG. 1. . 4A is a diagram for explaining the process shown in FIG. 3C and is a cross-sectional view corresponding to the line A-A ′ of FIG. 1. 4B is a view for explaining the step shown in FIG. 3C and is a cross-sectional view corresponding to the line A-A ′ of FIG. 1. FIG. 4C is a view for explaining the step shown in FIG. 3C and is a cross-sectional view corresponding to the line A-A ′ of FIG. 1. FIG. 5 is a view for explaining the semiconductor device of the second embodiment, which is another example of the semiconductor device of the present invention, and is an enlarged plan view of a part of the semiconductor device as viewed from the lower surface side. FIG. 6 is a view for explaining the semiconductor device of the third embodiment, which is another example of the semiconductor device of the present invention, and is an enlarged plan view of a part of the semiconductor device as viewed from the lower surface side. FIG. 7 is a view for explaining the semiconductor device of the fourth embodiment, which is another example of the semiconductor device of the present invention, and is an enlarged plan view of a part of the semiconductor device as seen from the lower surface side.

Embodiments to which the present invention is applied will be described below in detail with reference to the drawings. The present invention is not limited to the following embodiment, and the drawings used in the following description are for explaining the configuration of the embodiment of the present invention. The dimensions and the like may differ from the actual dimensional relationship of the semiconductor device.

(First embodiment)
FIG. 1 and FIG. 2 are diagrams for explaining the semiconductor device of the first embodiment which is an example of the semiconductor device of the present invention. FIG. 1 is a plan view of the semiconductor device viewed from the lower surface side, and FIG. 2 is a cross-sectional view corresponding to the line AA ′ in FIG.
The semiconductor device 10 of this embodiment is a BGA type semiconductor device, and includes a wiring substrate 17 (substrate) and a semiconductor chip 16 as shown in FIG.

The wiring board 17 is, for example, a flexible wiring board provided with an insulating substrate 11 made of a polyimide base material having a substantially rectangular shape in plan view. The insulating substrate 11 is not limited to one made of a polyimide base material, and may be a glass epoxy substrate, for example.
A plurality of wirings 19 made of a conductive material such as Cu are formed in a predetermined shape on the surface of the insulating substrate 11 on the semiconductor chip 16 side (the upper surface in FIG. 2).

  The wiring board 17 is divided into two regions by the opening 12 on the first side wall 12 a side and the second side wall 12 b side of the opening 12. As shown in FIG. 1, solder that is an external electrode is provided in each region on the first side wall 12a side and the second side wall 12b side of the other surface 11b (the lower surface in FIG. 2) of the wiring board 17. Balls 28 are arranged in a grid pattern. As shown in FIG. 2, the solder balls 28 are electrically connected to lands (external connection terminals) 29 in which one end of each wiring 19 is exposed to the other surface 11 b of the wiring substrate 17 through a hole formed in the insulating substrate 11. It is connected to the. Thereby, each wiring 19 and the solder ball 28 are electrically connected.

  Further, as shown in FIGS. 1 and 2, the wiring board 17 has an opening 12 having a substantially rectangular shape in plan view, provided so as to penetrate from the one surface 11 a to the other surface 11 b. The opening 12 is provided in the center of the wiring board 17 in plan view, and has a first side wall 12a and a second side wall 12b facing the first side wall 12a.

Further, the wiring board 17 has an inner lead having a plurality of multiple connection inner leads 7 (inner leads), a plurality of single connection inner leads 73, and a plurality of dummy leads D7. The multi-connection inner lead 7 and the single connection inner lead 73 are linear in a plan view made of a conductive material such as Au or Cu, and one end is connected to the wiring 19 and the other end is exposed in the opening 12. It is what. Each dummy lead D7 has a linear shape in plan view made of the same conductive material as the multi-connection inner lead 7, and is insulated from other conductive members. As shown in FIGS. 1 and 2, each dummy lead D <b> 7 is disposed opposite to the multiple connection inner lead 7 in the opening 12, and the wiring 19 extends in the same layer as the multiple connection inner lead 7. It is formed along the direction.
In the present embodiment, as shown in FIG. 1, two or more electrode pads 5 having the same potential described later are connected to the multi-connection inner lead 7 exposed in the opening 12 and exposed in the opening 12. One electrode pad 5 is connected to the single connection inner lead 73 that is formed.

As shown in FIG. 2, the semiconductor chip 16 is mounted on one surface 11 a of the wiring board 17 via an adhesive member 31 made of DAF (Die Attached Film), elastomer (elastic body), or the like. The adhesive member 31 covers a region where the wiring 19 of the wiring substrate 17 is formed, and is provided in a region excluding the opening 12.
The semiconductor chip 16 has a substantially rectangular plate shape. For example, a memory circuit (not shown) and the semiconductor chip 16 are electrically connected to the outside on the lower surface 16b (one surface) of the semiconductor chip 16 in FIGS. An electrode pad group 15 including a plurality of electrode pads 5 is formed.
A passivation film (not shown) is formed on the lower surface 16b of the semiconductor chip 16 except for the region where the electrode pads 5 constituting the electrode pad group 15 are formed, and the surface on which the memory circuit is formed is protected. ing.

  As shown in FIGS. 1 and 2, the semiconductor chip 16 is arranged with the electrode pad group 15 side (the lower surface 16 b side) facing the wiring substrate 17. Further, as shown in FIGS. 1 and 2, the semiconductor chip 16 is disposed so that the electrode pad group 15 is exposed from the opening 12 of the wiring substrate 17. In the present embodiment, as shown in FIGS. 1 and 2, the electrode pad group 15 is composed of a plurality of electrode pads 5 arranged in two rows in the center of the semiconductor chip 16.

More specifically, as shown in FIG. 1, the electrode pad group 15 includes a first electrode pad 5 including a plurality of first electrode pads 5 disposed in the vicinity of the first side wall 12 a along the first side wall 12 a of the opening 12. It consists of two rows of a row of one electrode pad 13 and a row of second electrode pads 14 made up of a plurality of first electrode pads 5 arranged close to the second side wall 12b along the second side wall 12b. ing.
Further, in the semiconductor device 10 shown in FIGS. 1 and 2, the electrode pad group 15 includes two or more electrode pads 5 having the same potential. Of the electrode pads 5 included in the electrode pad group 15, the number of electrode pads 5 having the same potential may be two or more, and is not particularly limited.

  In the present embodiment, as shown in FIGS. 1 and 2, the first electrode pad 13 disposed third from the bottom in FIG. 1, which is the two electrode pads 5 having the same potential, and the first electrode pad 13. A second electrode pad 14 disposed adjacent to is connected to one of the multiple connection inner leads 7. Further, in FIG. 1, which are two electrode pads 5 having the same potential, the first electrode pad 13 arranged fourth from the bottom, and the second electrode pad 14 arranged adjacent to the first electrode pad 13 are provided. , Connected to one of the multiple connection inner leads 7.

  In the semiconductor device 10 shown in FIGS. 1 and 2, the first electrode pad 13 and the second electrode pad 14 of the same potential connected to each of the multiple connection inner leads 7 are set as a power source or a ground. The electrode pad 5 connected by the multi-connection inner lead 7 is preferably a power source or a ground. However, the electrode pad 5 may be at the same potential so that it can be connected by the multi-connection inner lead 7. It doesn't have to be ground.

Further, as shown in FIG. 1, the electrode pad 5 arranged at the end of the multi-connection inner lead 7 is compared with the other electrode pads 5 connected to the multi-connection inner lead 7. The distance to the wiring 19 connected to is long.
For example, the first electrode pad 13 arranged third from the bottom in FIG. 1 is connected to the multi-connection inner lead 7 as compared with the second electrode pad 14 arranged third from the bottom in FIG. The distance from the wiring 19 is far.
Further, the second electrode pad 14 arranged fourth from the bottom in FIG. 1 is connected to the multi-connection inner lead 7 as compared with the first electrode pad 13 arranged fourth from the bottom in FIG. The distance from the wiring 19 is far.

Further, among the electrode pads 5 shown in FIG. 1, the electrode pads 5 that are not connected to the multiple connection inner leads 7 are electrically connected to the corresponding single connection inner leads 73 that are closest to each other.
As shown in FIGS. 1 and 2, the solder ball 28 provided on the wiring board 17 and the semiconductor chip are connected by connecting the multi-connection inner lead 7 and the single connection inner lead 73 and the electrode pad 5. 16 is electrically connected.

  Further, in the semiconductor device 10 shown in FIGS. 1 and 2, the sealing body 32 made of the sealing resin is formed in the opening 12 and in the vicinity of the opening 12, so that the multiple connection inner lead 7 and the single connection inner lead are formed. 73 is sealed with a sealing resin. Thereby, in the semiconductor device 10 shown in FIGS. 1 and 2, the connection portion between the semiconductor chip 16 and the wiring board 17 using the multi-connection inner lead 7 and the single connection inner lead 73 is protected from the outside. It has become.

A region of the semiconductor chip 16 that is not opposed to the wiring substrate 17 is covered with a sealing body 33 made of a sealing resin. In the semiconductor device 10 shown in FIGS. 1 and 2, the semiconductor chip 16 is protected from the outside world by forming the sealing body 33.
In addition, as sealing resin used for the sealing bodies 32 and 33, thermosetting resins, such as an epoxy resin, etc. can be used, for example.

"Production method"
3A to 3F are views for explaining the semiconductor device manufacturing method according to the first embodiment as an example of the semiconductor device manufacturing method of the present invention, and a cross section corresponding to the line AA ′ in FIG. FIG. 4A to 4C are diagrams for explaining the process shown in FIG. 3C and are cross-sectional views corresponding to the line AA ′ in FIG. 1. 3A to 3F and FIGS. 4A to 4C, the same components as those of the semiconductor device 10 of the first embodiment are denoted by the same reference numerals.

  In order to manufacture the semiconductor device 10 shown in FIGS. 1 and 2, first, a substrate to be the wiring board 17 is prepared. As shown in FIG. 3A, the product forming portions 43 arranged in a matrix form each surface from the surface 11a. An opening 12 provided through the other surface 11b, a plurality of wirings 19 connected to one external electrode (the solder ball 28 shown in FIGS. 1 and 2), and one end connected to the wiring 19 The other end is insulated and a plurality of inner lead materials A7 separated into the multi-connection inner lead 7 and the dummy lead D7 by being cut in a later process, and one end is wired by being cut in a later process 19 and a plurality of lead materials (not shown) separated into two single connection inner leads 73 (not shown in FIG. 3A, see FIG. 1), the other ends of which are exposed in the opening 12. Wiring mother board 41 Wiring board 17) to form a.

The wiring mother board 41 used in the present embodiment is processed by a MAP (Mold Array Process) method, and a plurality of product forming portions 43 are arranged in a matrix. As shown in FIG. 3A, an adhesive member 31 is mounted on each product forming portion 43 of the wiring mother board 41.
Each product forming portion 43 is a portion that becomes the wiring substrate 17 of the semiconductor device 10 shown in FIGS. 1 and 2 by cutting and separating the wiring mother substrate 41 in the subsequent process. Therefore, a dicing line is disposed between adjacent product forming portions 43 of the wiring mother board 41.

Further, as shown in FIG. 3A, the inner lead material A7 and the lead material to be the single connection inner lead 73 are in a predetermined shape in which both end portions are integrated with the wiring board 17, and the product forming portion of the wiring mother board 41 is formed. It is formed so as to extend over the opening 12 provided in each of 43.
In this embodiment, in the step of forming the wiring mother board 41 (wiring board 17), as shown in FIG. 3A, one end of each wiring 19 is formed on the insulating substrate 11 on the wiring mother board 41 (wiring board 17). A land 29 exposed to the other surface 11b is formed by the formed hole.

  Next, as shown in FIG. 3B, an electrode pad group 15 including two or more electrode pads 5 having the same potential on one surface 11a of each of the product forming portions 43 (wiring board 17) of the wiring mother board 41 (see FIG. 1). ) And the electrode pad group 15 is disposed so as to be exposed from the opening 12. The semiconductor chip 16 is bonded and fixed with the electrode pad group 15 of the semiconductor chip 16 facing the wiring substrate 17 side through an adhesive member 31 such as DAF.

  FIG. 3B shows the first electrode pad 13 and the second electrode pad 14 arranged in a cross section corresponding to the A-A ′ line in FIG. 1 among the plurality of first electrode pads 5. By mounting the semiconductor chip 16 on the wiring mother board 41, the inner lead material A7 (multiple connection inner lead 7) and the lead material to be the single connection inner lead 73 are connected in the opening 12 respectively. The electrode pad 5 is disposed opposite to the electrode pad 5.

Next, as shown in FIG. 3C, the electrode material 5 is connected to the lead material that becomes the inner lead material A7 (multiple connection inner lead 7) and the single connection inner lead 73. At this time, two or more electrode pads 5 having the same potential are connected to one of the multiple connection inner leads 7 (inner leads) (connection process).
In the present embodiment, as shown in FIG. 4A, the lead material to be the inner lead material A7 (multiple connection inner lead 7) and the single connection inner lead 73 is cut in the opening 12 before the connection process is performed. . As a result, the inner lead material A7 is separated into the double connection inner lead 7 and the dummy lead D7, and the lead material is separated into two single connection inner leads 73.

As a method of cutting the lead material that becomes the inner lead material A7 and the single connection inner lead 73, for example, as shown in FIGS. 4A and 4B, it is connected to the electrode pad 5 using a bonding tool 70 of an inner lead bonding apparatus. A method of cutting the lead material that becomes the inner lead material A7 or the single connection inner lead 73 using the bonding tool 70 can be used. In this case, after cutting the lead material to be the inner lead material A7 or the single connection inner lead 73, the work of connecting the multiple connection inner lead 7 or the single connection inner lead 73 to the electrode pad 5 can be performed smoothly, and the efficiency It can be manufactured well and is preferable.
Further, at the predetermined positions of the lead material to be the inner lead material A7 (multiple connection inner lead 7) and the single connection inner lead 73, an easy-to-cut portion (not shown) such as a notch portion is provided before the connection process. It is preferable to provide it. In this case, when cutting the lead material to be the inner lead material A7 and the single connection inner lead 73, it can be easily and efficiently cut at a predetermined position with high accuracy.

  Next, a connection process is performed. As shown in FIG. 3C, the connecting step is preferably performed by arranging the semiconductor chip 16 so that the surface on the wiring board 17 side is on the upper side. Further, in the connecting step, as a method of connecting the electrode pad 5 and the multi-connection inner lead 7 or the single connection inner lead 73, for example, a bonding tool 70 of the inner lead bonding apparatus shown in FIGS. 4A to 4C is used. For example, a method of ultrasonic thermocompression bonding can be used.

  Here, first, the connection between the first electrode pad 13 and the second electrode pad 14 arranged third from the bottom in FIG. 1 and the multi-connection inner lead 7 will be described. In addition, about the connection of the 1st electrode pad 13 and the 2nd electrode pad 14 which are arrange | positioned 4th from the bottom in FIG. 1, and the multiple connection inner lead 7, connection of the 1st electrode pad 13 and the multiple connection inner lead 7 is shown. The second electrode pad 14 and the multi-connection inner lead 7 are the same except that the connection is made in the reverse order, and the description thereof is omitted.

  In the connection step of connecting the first electrode pad 13 and the second electrode pad 14 arranged third from the bottom in FIG. 1 and the multi-connection inner lead 7, two or more electrode pads 5 (first electrode) having the same potential are connected. Of the pad 13 and the second electrode pad 14), the electrode pad 5 (the first electrode pad 13 in FIG. 3C) that is farthest from the wiring 19 connected to the multi-connection inner lead 7 is the multi-connection inner lead 7. Connect to be placed at the end.

In the connection process of this embodiment, as shown in FIG. 4B and FIG. 4C, of the two or more electrode pads 5 having the same potential, an electrode having a short distance from the wiring 19 connected to the multiple connection inner lead 7. The pads 5 (second electrode pads 14 in FIG. 3C) are connected to the multi-connection inner leads 7 in order.
Specifically, first, as shown in FIG. 4B, the multi-connection inner lead 7 and the second electrode pad 14 are electrically connected. That is, the bonding tool 70 shown in FIG. 4A used for cutting the multi-connection inner lead 7 connected to the electrode pad 5 is moved to the position on the second electrode pad 14 as shown in FIG. 7 is connected to the second electrode pad 14 by ultrasonic thermocompression bonding.

Next, as shown in FIG. 4C, the bonding tool 70 shown in FIG. 4B is arranged such that the distance between the first electrode pad 13 and the second electrode pad 14 and the wiring 19 (see FIG. 1) is long. It moves to the upper position, and the bonding part which is the cut end of the multi-connection inner lead 7 is connected to the first electrode pad 13 by ultrasonic thermocompression bonding.
Accordingly, in the present embodiment, as shown in FIGS. 1 and 4C, the first electrode pad 13 and the second electrode pad 14 having the same potential are the electrode pads 5 that are far from the wiring 19. One electrode pad 13 is disposed at the end of the multi-connection inner lead 7.

  Next, the connection between the electrode pad 5 not connected to the multiple connection inner lead 7 and the single connection inner lead 73 will be described. When connecting the electrode pad 5 that is not connected to the multiple connection inner lead 7 and the single connection inner lead 73, the bonding tool 70 used for cutting the single connection inner lead 73 is positioned on the electrode pad 5 to be connected. Among the two or more electrode pads 5 having the same potential, the single connection inner lead 73 is connected to the electrode pad 5 in the same manner as the connection between the electrode pad 5 having the longest distance to the wiring 19 and the multiple connection inner lead 7. The bonding part which is the cutting end of is connected by ultrasonic thermocompression bonding.

Subsequently, as shown in FIG. 3D, a sealing body 32 made of a sealing resin is formed in the opening 12 and in the vicinity of the opening 12 to seal the multiple connection inner lead 7 and the single connection inner lead 73. Then, a sealing body 33 made of a sealing resin is formed so as to cover a region of the semiconductor chip 16 that does not face the wiring substrate 17.
Although it does not specifically limit as a method of forming the sealing body 32 and the sealing body 33, For example, it is preferable to use the method shown below.

  First, a molding die comprising an upper mold and a lower mold of a transfer mold apparatus is prepared, and the wiring mother board 41 is closed. At this time, the wiring mother board 41 can be disposed in the cavity of the molding die so that the long side of the opening 12 formed in the product formation region 43 is disposed along the injection direction of the sealing resin. preferable. As a result, the multiple connection inner lead 7 and the single connection inner lead 73 can be prevented from hindering the flow of the sealing resin in the molding die, and the flow of the sealing resin in the molding die can be made smooth. be able to.

  Next, molten sealing resin is injected into the cavity of the molding die from the gate provided in the molding die, and the inside of the cavity is filled with the sealing resin. Next, the sealing resin is cured by heat treatment (curing) at a predetermined temperature of about 180 ° C., for example. Thereafter, by removing the wiring mother board 41 from the molding die, the wiring mother board 41 collectively covered with the sealing body 32 and the sealing body 33 as shown in FIG. 3D is obtained.

  Thereafter, as shown in FIG. 3E, solder balls 28 electrically connected to lands 29 formed by exposing one end of each wiring 19 are formed. When forming the solder ball 28, for example, it is preferable to use a method using a ball mount tool in which a plurality of suction holes are formed in accordance with the arrangement of the lands 29. Specifically, the solder ball 28 is held in the suction hole of the ball mount tool, a flux is transferred and formed on the held solder ball 28, and the solder ball 28 is collectively mounted on the land 29 and then reflowed at a predetermined temperature. A method of fixing 28 can be used.

Thereafter, the wiring mother board 41 is cut by vertical and horizontal dicing lines with a dicing blade, and is cut and separated for each product forming portion 43 to be divided into the respective wiring boards 17, thereby obtaining the semiconductor device 10 shown in FIGS. 1 and 2. It is done.
When cutting the wiring mother board 41, as shown in FIG. 3F, the dicing tape 48 is bonded to the sealing body 33 covering the semiconductor chip 16, and the wiring mother board 41 is supported by the dicing tape 48 for cutting. It is preferable to do.

  The semiconductor device 10 of the present embodiment includes an opening 12 provided so as to penetrate from one surface 11a to the other surface 11b, wiring connected to the solder ball 28, one end connected to the wiring 19, and the other end opened. 12 includes a wiring board 17 having a multi-connection inner lead 7 exposed in 12 and two or more electrode pads 5 mounted on one surface of wiring board 17 and arranged to be exposed from opening 12. Since the semiconductor chip 16 having the electrode pad group 15 and two or more electrode pads 5 having the same potential are connected to one of the multiple connection inner leads 7, the wiring board 17 corresponding to the number of the electrode pads 5 is provided. It is possible to reduce the number of wirings 19 arranged in the. As a result, a wiring space on the wiring board 17 can be secured, the degree of freedom of arrangement of the wiring 19 on the wiring board 17 can be improved, and the semiconductor device 10 is suitable for downsizing.

  Further, in the semiconductor device 10 of the present embodiment, the electrode pad 5 arranged at the end of the multi-connection inner lead 7 is compared with the other electrode pads 5 connected to the multi-connection inner lead 7. Since the distance from the wiring 19 connected to the lead 7 is long, the electrode pad 5 connected to the end of the multi-connection inner lead 7 is connected to another electrode pad connected to the multi-connection inner lead 7. Compared to the case where the distance from the wiring 19 is short, the length of the multi-connection inner lead 7 can be shortened, and the plane area required for arranging the multi-connection inner lead 7 is small. It can be easily manufactured.

  In addition, since the wiring 19 of the wiring board 17 is a single-layer wiring, the semiconductor device 10 of the present embodiment can be easily manufactured as compared with the case where the wiring 19 is a multilayer wiring, and the productivity of the semiconductor device 10 can be improved. It can be improved and the cost can be reduced.

  In the semiconductor device 10 of this embodiment, the opening 12 has the first side wall 12a and the second side wall 12b facing the first side wall 12a, and the electrode pad group 15 extends along the first side wall 12a. A plurality of first electrode pads 13 arranged close to the first side wall, and a plurality of second electrode pads 14 arranged close to the second side wall 12a along the second side wall 12a. The electrode pads 5 having two or more potentials include the first electrode pad 13 and the second electrode pad 14 adjacent to each other, and the multi-connection inner lead 7 is linear in a plan view. The flat area required for the arrangement is small, and it is suitable for miniaturization, and the connection between the multi-connection inner lead 7 and the first electrode pad 13 and the second electrode pad 14 is easy and excellent in productivity. It will be.

Further, in the semiconductor device 10 of the present embodiment, since two or more electrode pads 5 having the same potential are used as a power source or a ground, for example, when two or more electrode pads 5 having the same potential are not a power source or a ground. In comparison, two or more electrode pads 5 having the same potential can be easily provided.
Further, in the semiconductor device 10 of this embodiment, since one end of the wiring 19 is exposed to the other surface 11 b of the wiring substrate 17, the land 29 can be easily formed, and the solder ball 28 is formed on the land 29. Thus, the wiring 19 and the solder ball 28 can be easily connected.

  Further, in the method of manufacturing the semiconductor device 10 according to the present embodiment, since the connection step of connecting one of the multiple connection inner leads 7 and two or more electrode pads 5 having the same potential is provided, the number of electrode pads 5 is reduced. Therefore, the number of wirings 19 can be reduced, and the degree of freedom of arrangement of the wirings 19 on the wiring board 17 can be improved.

  Further, in the method of manufacturing the semiconductor device 10 of the present embodiment, in the step of forming the wiring substrate 17, the inner lead material A7 that becomes the multiple connection inner lead 7 and the dummy lead D7 extending across the opening 12, Since the lead material to be the single connection inner lead 73 is formed and the connection step is performed, the method includes the step of cutting the inner lead material A7 and the lead material to be the single connection inner lead 73 in the opening 12. When the semiconductor chip 16 is mounted, the inner lead material A7 (multiple connection inner lead 7) and the lead material serving as the single connection inner lead 73 function as a reinforcing material, so that the semiconductor chip 16 can be easily raised to a predetermined position. In addition to being able to be mounted with accuracy, workability when mounting the semiconductor chip 16 can be improved.

  Further, in the method of manufacturing the semiconductor device 10 according to the present embodiment, in the connecting step, among the two or more electrode pads 5 having the same potential, from the electrode pad 5 having a short distance to the wiring 19 connected to the multi-connection inner lead 7. Since it is a method of connecting to the multi-connection inner lead 7 in order, the connection is compared with the case of connecting to the multi-connection inner lead 7 in order from the electrode pad 5 which is far from the wiring 19 connected to the multi-connection inner lead 7. Two or more electrode pads 5 having the same potential can be connected to the multi-connection inner lead 7 efficiently and with high accuracy.

  Further, in the manufacturing method of the semiconductor device 10 according to the present embodiment, each process until the solder ball 28 is formed using the wiring mother board 41 is separated into individual product formation regions 43, so that FIG. And it can manufacture efficiently compared with the case where the semiconductor device shown in FIG. 2 is manufactured separately.

(Second Embodiment)
In the first embodiment shown in FIGS. 1 and 2, two electrode pads 5 having the same potential including the first electrode pad 13 and the second electrode pad 14 are connected to one of the multiple connection inner leads 7. In the present invention, for example, three or more electrode pads having the same potential may be connected to one of the multiple connection inner leads.

FIG. 5 is a view for explaining the semiconductor device of the second embodiment, which is another example of the semiconductor device of the present invention, and is an enlarged plan view of a part of the semiconductor device as viewed from the lower surface side.
The semiconductor device 20 shown in FIG. 5 is different from the semiconductor device 10 shown in FIG. 1 in that two or more electrode pads 5 having the same potential are adjacent to two first electrode pads 13a and 13b and one second electrode. The only difference is that the three electrode pads 5 are adjacent to each other, and that the multi-connection inner lead 7a is L-shaped in plan view.

  Therefore, the same members as those of the semiconductor device 10 shown in FIG. Further, the semiconductor device 20 shown in FIG. 5 can be manufactured in the same manner as the semiconductor device 10 shown in FIG. That is, the multi-connection inner lead 7a is connected to both ends and the center of the three electrode pads 5 in the process of forming the wiring board 17, in the same manner as the multi-connection inner lead 7 constituting the semiconductor device 10 shown in FIG. The electrode pad 5 (the first electrode pad 13a in FIG. 5) connected to the vicinity of the portion connected to the wiring substrate 17 has a predetermined shape and extends across the opening 12. Before the inner lead material is formed and the connecting step is performed, the inner lead material is cut in the opening 12 and separated from the dummy lead D7.

  Since the semiconductor device 20 shown in FIG. 5 has two or more electrode pads 5 having the same potential connected to one of the multiple connection inner leads 7a, like the semiconductor device 10 shown in FIG. The number of wirings 19 with respect to the number of 5 can be reduced, and the same effect as the semiconductor device 10 shown in FIG. 1 can be obtained.

(Third embodiment)
FIG. 6 is a view for explaining the semiconductor device of the third embodiment, which is another example of the semiconductor device of the present invention, and is an enlarged plan view of a part of the semiconductor device as viewed from the lower surface side.
The semiconductor device 30 shown in FIG. 6 is different from the semiconductor device 10 shown in FIG. 1 in that two or more electrode pads 5 having the same potential are second from one second electrode pad 14 and the second electrode pad 14. And a bent portion in which the double-connected inner lead 7b extends obliquely in a plan view with respect to the first side wall 12a and the second side wall 12b. It is only a point which has.

  Therefore, the same members as those of the semiconductor device 10 shown in FIG. 6 can be manufactured in the same manner as the semiconductor device 10 shown in FIG. That is, the multi-connection inner lead 7b is formed in a predetermined manner in which both ends thereof are integrated with the wiring substrate 17 in the step of forming the wiring substrate 17 in the same manner as the multi-connection inner lead 7 constituting the semiconductor device 10 shown in FIG. The inner lead material is formed so as to extend over the opening 12 in a shape, and formed by a method of cutting the inner lead material within the opening 12 and separating it from the dummy lead D7 before performing the connecting step. It has been done.

The semiconductor device 30 shown in FIG. 6 is similar to the semiconductor device 10 shown in FIG. 1 in that two or more electrode pads 5 having the same potential are connected to one of the multi-connection inner leads 7b. The number of wirings 19 relative to the number of 5 can be reduced, and the same effect as the semiconductor device 10 shown in FIG.
Further, in the semiconductor device 30 shown in FIG. 6, the multiple connection inner lead 7b has a bent portion extending obliquely in plan view with respect to the first side wall 12a and the second side wall 12b. When the two or more electrode pads 5 are two electrode pads 5 including one second electrode pad 14 and the first electrode pad 13 closest to the second electrode pad 14, the two electrodes The pad 5 is a multi-connection inner lead 7b connected at the shortest distance.

  In the semiconductor device 30 shown in FIG. 6, two or more electrode pads 5 having the same potential include one second electrode pad 14 and a first electrode pad 13 that is second closest to the second electrode pad 14. The case of two electrode pads 5 has been described as an example, but two or more electrode pads 5 having the same potential may be connected by a multi-connection inner lead having a bent portion. For example, one electrode pad and its electrode pad It may be the third or fourth nearest electrode pad from the electrode pad.

(Fourth embodiment)
FIG. 7 is a view for explaining the semiconductor device of the fourth embodiment, which is another example of the semiconductor device of the present invention, and is an enlarged plan view of a part of the semiconductor device as seen from the lower surface side.
The semiconductor device 40 shown in FIG. 7 is different from the semiconductor device 10 shown in FIG. 1 in that two or more electrode pads 5 having the same potential are adjacent to two first electrode pads 13c and 13d and two adjacent second electrodes. The point that the electrode pads 14c and 14d are adjacent four electrode pads 5, and the double connection inner lead 7c is at least a part of the two adjacent first electrode pads 13c and 13d and the two adjacent second electrodes. The two adjacent pads 14c and 14d have a band-like shape that overlaps at least a part of the pads 14c and 14d in plan view, the width of the multi-connection inner lead 7c, and the width of the wiring 19a connected to the multi-connection inner lead 7c. It is only a point that is longer than the distance between the first electrode pads 13c and 13d and the distance between the two adjacent second electrode pads 14c and 14d.

  Therefore, the same members as those of the semiconductor device 10 shown in FIG. 7 can be manufactured in the same manner as the semiconductor device 10 shown in FIG. That is, a predetermined shape in which both ends are integrated with the wiring board 17 in the step of forming the wiring board 17 in the same manner as the multiple connecting inner lead 7c and the multiple connecting inner lead 7 constituting the semiconductor device 10 shown in FIG. Thus, the inner lead material is formed so as to extend over the opening 12, and the inner lead material is cut in the opening 12 and separated from the dummy lead D7 before performing the connecting step. It is a thing.

The semiconductor device 40 shown in FIG. 7 is similar to the semiconductor device 10 shown in FIG. 1 in that two or more electrode pads 5 having the same potential are connected to one of the multiple connection inner leads 7c. The number of wires with respect to the number of 5 can be reduced, and the same effect as the semiconductor device 10 shown in FIG.
Further, in the semiconductor device 40 shown in FIG. 7, the width of the multi-connection inner lead 7c and the width of the wiring 19a connected to the multi-connection inner lead 7c are the same as the distance between the two adjacent first electrode pads 13c and 13d. Since the distance is longer than the distance between the two second electrode pads 14c and 14d, the power supply can be strengthened as compared with the case where the width of the wiring is narrower than the width of the electrode pad 5, for example.

  In the semiconductor device 40 shown in FIG. 7, two or more electrode pads 5 having the same potential are adjacent to each other including two adjacent first electrode pads 13c and 13d and two adjacent second electrode pads 14c and 14d. The case of four electrode pads 5 has been described as an example, but two or more electrode pads 5 having the same potential can be, for example, five or more electrode pads 5 adjacent to each other. The planar shape of the inner lead can be a shape that overlaps at least a part of all the electrode pads 5 constituting two or more electrode pads 5 having the same potential in a plan view.

  As mentioned above, although the invention made | formed by this inventor was demonstrated based on embodiment, it cannot be overemphasized that this invention can be variously changed in the range which is not limited to said embodiment and does not deviate from the summary.

For example, in the above-described embodiment, the semiconductor device in which one semiconductor chip 16 is mounted on the wiring substrate 17 has been described as an example. However, the present invention enables an increase in capacity and functionality of the semiconductor device. In addition, the present invention may be applied to a semiconductor device in which a plurality of semiconductor chips are mounted on the wiring board 17.
Further, in the above-described embodiment, the semiconductor device using the one-layer wiring having the wiring 19 only on the one surface 11a of the insulating substrate 11 as the wiring substrate 17 has been described. In order to enable high functionality, the present invention may be applied to a semiconductor device using a multilayer wiring board having two or more wirings as a wiring board.

In the above-described embodiment, the semiconductor device including the wiring substrate having the opening 12 disposed in the center has been described. However, the position of the opening may not be the center, and the wiring substrate may be formed by the opening. You may use what was isolate | separated into two completely.
In the above-described embodiments, the case where the present invention is applied to a BGA type semiconductor device has been described. However, the present invention may also be applied to an LGA (Land Grid Array) type semiconductor device.

  5 ... Electrode pads, 7, 7a, 7b, 7c ... Multiple connection inner leads (inner leads) 10, 20, 30, 40 ... Semiconductor device, 11 ... Insulating substrate, 11a ... One side, 11b ... Other side, 12 ... Opening Part, 12a ... first side wall, 12b ... second side wall, 13, 13a, 13b, 13c, 13d ... first electrode pad, 14, 14c, 14d ... second electrode pad, 15 ... electrode pad group, 16 ... semiconductor chip , 17 ... Wiring board (board), 19, 19a ... Wiring, 28 ... Solder ball (external electrode), 29 ... Land, 31 ... Adhesive member, 32, 33 ... Sealed body, 41 ... Wiring mother board, 43 ... Product Formation part 48 ... Dicing tape 70 ... Bonding tool 73 ... Single connection inner lead.

Claims (13)

A substrate having an opening provided penetrating from one surface to the other surface, a wiring connected to an external electrode, and an inner lead having one end connected to the wiring and the other end exposed in the opening;
A semiconductor chip mounted on one surface of the substrate,
The semiconductor chip has an electrode pad group including two or more electrode pads of the same potential disposed so as to be exposed from the opening;
2. A semiconductor device, wherein two or more electrode pads having the same potential are connected to one of the inner leads.   The electrode pad connected to the end portion of the inner lead is farther away from the wiring connected to the inner lead than the other electrode pads connected to the inner lead. 2. The semiconductor device according to 1. The opening has a first side wall and a second side wall facing the first side wall;
The electrode pad group is disposed in proximity to the second sidewall along the second sidewall and a plurality of first electrode pads disposed in proximity to the first sidewall along the first sidewall. A plurality of second electrode pads;
3. The semiconductor device according to claim 1, wherein the two or more electrode pads having the same potential include the first electrode pad and the second electrode pad. 4.   4. The semiconductor device according to claim 3, wherein the two or more electrode pads having the same potential are the first electrode pad and the second electrode pad adjacent to each other.   The semiconductor device according to claim 4, wherein the inner lead is linear in a plan view.   4. The semiconductor device according to claim 3, wherein the inner lead has a bent portion extending obliquely in a plan view with respect to the first side wall and the second side wall.   4. The semiconductor device according to claim 3, wherein the two or more electrode pads having the same potential include two adjacent first electrode pads or two adjacent second electrode pads.   The semiconductor device according to claim 7, wherein the inner lead is L-shaped in plan view. The two or more electrode pads having the same potential include two or more adjacent first electrode pads and two or more adjacent second electrode pads;
The inner lead has a belt-like shape overlapping with at least a part of two or more adjacent first electrode pads and at least a part of two or more adjacent second electrode pads in plan view. The semiconductor device according to claim 3. Forming a substrate having an opening provided penetrating from one surface to the other surface, wiring connected to an external electrode, and an inner lead having one end connected to the wiring and the other end exposed in the opening And a process of
Mounting a semiconductor chip having an electrode pad group including two or more electrode pads of the same potential on one surface of the substrate, and disposing the electrode pad group so as to be exposed from the opening;
A method of manufacturing a semiconductor device, comprising: a connection step of connecting one of the inner leads to two or more electrode pads having the same potential. In the step of forming the substrate, an inner lead extending across the opening is formed,
The method of manufacturing a semiconductor device according to claim 10, further comprising a step of cutting the inner lead in the opening before performing the connecting step.   In the connecting step, among the two or more electrode pads having the same potential, the electrode pad that is farthest from the wiring connected to the inner lead is connected so that the electrode pad is disposed at the end of the inner lead. 12. The method of manufacturing a semiconductor device according to claim 10, wherein the method is a semiconductor device manufacturing method.   The said connection process WHEREIN: It connects to the said inner lead in an order from the electrode pad with the short distance with the wiring connected to the said inner lead among the two or more electrode pads of the said same electric potential. Item 13. A method for manufacturing a semiconductor device according to any one of Items 12 to 12.

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