JP2012043867A - Laminated layer-type optical element package - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a laminated layer-type optical element package in which an optical element having a large chip size, i.e. a large light-reception area, can be arranged on the top layer.SOLUTION: A laminated layer-type optical element package includes: a first element 1; a second element 2 provided on a top face of the first element 1; an interposer 6 provided on the top face of the first element 1; a third element 3 provided on a top face of the interposer 6; fourth elements 4a and 4b provided on a top face of the third element 3; an interposer 7 provided on the top face of the third element 3; and a fifth element 5 provided on a top face of the interposer 7. The fifth element 5 includes an Si substrate 51, a dustproof cap glass 52, a bonding layer 53, and a light-emission/light-reception part 54. The cap glass 52 is fixed on the fifth element 5 via the bonding layer 53. The material of the cap glass 52 must have excellent transmissivity for a wavelength in use, without deteriorating the optical characteristics of the fifth element 5.

Description

  The present invention relates to a laminated optical element package, and more particularly to a laminated optical element package applied to a light receiving device such as an image sensor and a light emitting device such as a light emitting diode.

  For light receiving devices such as image sensors and light emitting devices such as light emitting diodes, a hollow chip size package structure is proposed by combining capping technology using transparent materials such as glass and through wiring technology to the device side. ing. This structure is also applied to packages such as a pressure sensor and an acceleration sensor. In that case, the cap substrate is not limited by transparency, and various materials are used. Further, the through wiring is rewired on the back surface of the device, and is flip-chip mounted on the substrate via the solder terminal.

  For these optical devices, a method of mounting on a mounting substrate after being stacked with a driving integrated circuit has been proposed. Regarding the stacking method, when flip chip mounting is adopted as a mounting form, a structure in which devices are connected by through wirings is becoming mainstream. In addition, as a method for realizing the structure, each element is packaged by a wafer level packaging method, and then stacked one by one vertically through micro bumps, and the stacked structure is complicated and rewiring layout is difficult. In some cases, there are methods for inserting an interposer between devices.

  However, since the above-described conventional laminated structure is a structure in which each element is stacked one by one in the vertical direction, it is difficult to make the height of the laminated body equal to or less than the thickness of each element. In addition, when the dimensions of the elements to be stacked are different, the order of stacking is also limited, and it has been required to stack the elements in order from a large area. Therefore, when the dimensional difference between the elements to be connected is large, another element is sandwiched between them, resulting in problems that the connection becomes complicated and the wiring becomes long.

  As a method for solving these problems, an element embedding structure on a mounting board was first proposed. However, in this structure, elements are arranged at various locations on the mounting board, and thus occupy a large area on the mounting board. It was a problem. Moreover, it was a problem that repair at the time of mounting failure was difficult, and it was difficult to radiate the embedded element.

Therefore, the next proposed structure is a structure in which a cavity is provided in a substrate and an element is mounted in the cavity (see, for example, Patent Document 1).
This structure has the following effects.
First, lamination of different dimensions is facilitated. This is because the conventional technology has an order restriction that the elements must be stacked in order from the larger dimension. In the above proposal, even if a smaller dimension element is mounted on the lower layer, the substrate on which the cavity is formed. This is because the element mounting area of the upper layer can be freely changed.

Next, the overall height of the element stack can be reduced. This is because the previous technology only allowed stacking in the vertical direction except for the uppermost layer. In the above proposal, after using a substrate on which a cavity was formed, This is because a larger element can be mounted on a substrate in which these elements are accommodated by a cavity. By adopting a substrate in which a cavity is formed, the height of the stacked body is increased, but the effect is manifested when the effect of reducing the number of stacked layers in the vertical direction by the planar arrangement of the above-described small-sized elements is exceeded. .
Furthermore, the structural freedom of the semiconductor element stacked structure increases. Specifically, since there is no restriction on the stacking order with respect to the element dimensions, the connection can be simplified and the wiring length can be shortened.

  However, in the above-mentioned proposal, including Patent Document 1, there is no disclosure about a configuration in which an optical device (optical element) is arranged in the uppermost layer and its effect.

JP 2007-19454 A

  The present invention has been made for the above-mentioned circumstances, and an object of the present invention is to provide a stacked optical element package in which an optical element having a large chip size, that is, a large light receiving area can be arranged in the uppermost layer. It is to provide.

In order to achieve the above object, a stacked optical element package of the present invention is defined by a first semiconductor element, a substrate disposed on a main surface of the semiconductor element, and a main surface of the semiconductor element and the substrate. And a second semiconductor element disposed in the gap, and an optical element is further provided on the uppermost stage of the stacked structure.
Preferably, the substrate is a glass substrate.
Preferably, a through wiring is formed on the substrate.
Suitably, the said board | substrate has a ventilation hole which connects the said space | gap and external air.

According to the present invention, a large-sized optical element can be laminated on a small-sized second semiconductor element. Moreover, since an optical element having a large light receiving area can be used, a stacked optical element package having excellent light receiving performance can be provided.
Further, if the through wiring is formed on the substrate, the first semiconductor element and the optical element can be connected without using the wire wiring.
Furthermore, if a vent is provided in the substrate, the heat generated from the second semiconductor element in the gap can be released to the outside.

Sectional drawing of one Embodiment of the laminated | stacked optical element package of this invention. The plane direction sectional view of the interposer which has a vent hole. Sectional drawing of other embodiment of the laminated | stacked optical element package of this invention. Sectional drawing of other embodiment of the laminated | stacked optical element package of this invention. Sectional drawing of other embodiment of the laminated | stacked optical element package of this invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
FIG. 1 is a cross-sectional view of an embodiment of a stacked optical element package of the present invention. The stacked optical element package shown in FIG. 1 includes a first element 1, a second element 2 mounted on the upper surface of the first element 1, an interposer 6 mounted on the upper surface of the first element 1, and an interposer. The third element 3 mounted on the upper surface of the sixth element, the fourth elements 4a and 4b mounted on the upper surface of the third element 3, the interposer 7 mounted on the upper surface of the third element 3, and the interposer 7 The fifth element 5 mounted on the upper surface is included.

The first element 1 includes a silicon (Si) substrate 11, a first insulating layer 12, a second insulating layer 13, a first conductor layer 14, a second conductor layer 15, and a third conductor layer 16. It consists of.
Here, the Si substrate 11 is employed for manufacturing each element. However, in the present invention, the Si substrate 11 is not limited to a silicon device, and may be a substrate made of some compound semiconductor. The first insulating layer 12 is formed on the element surface and the back surface of the Si substrate 11 on which rewiring is formed, and generally silicon oxide (SiO ₂ ), silicon nitride (SiN), or the like is used. However, the material is not a limitation of the configuration of the present invention. The second insulating layer 13 is a protective layer on the surface of the rewiring and corresponds to what is called a cover lay or an overcoat. Although it is common to use a resin material, the material does not become a restriction | limiting of the structure of this invention like the 1st insulating layer 12. FIG. The first conductor layer 14 is formed as a wiring and a pad in the manufacture of the element, and generally uses aluminum (Al), aluminum silicide (AlSi), or the like. The second conductor layer 15 corresponds to a rewiring formed on the surface of the second insulating layer 13, and copper (Cu) or nickel (Ni) is mainly used as a material. The third conductor layer 16 corresponds to what is generally called a solder bump, and is formed to electrically connect each element or between the element and the mounting substrate. Similarly, the materials of the first conductor layer 14, the second conductor layer 15, and the third conductor layer 16 do not limit the configuration of the present invention.
The first element 1 is the lowermost element, and a rewiring is formed on the back surface of the substrate using a through wiring. This rewiring is used for electrical connection with a mounting substrate via solder bumps.

  The second element 2 is mounted on the surface of the first element 1 via the solder bump 91. With this structure, the first element 1 and the second element 2 are electrically connected. The second element 2 needs to have a smaller outer diameter than the first element 1.

  The interposer 6 is a first glass substrate mounted on the upper surface of the first element 1. Here, the material is limited to glass, but a commonly used silicon material may be used. Since it is a linear expansion coefficient equivalent to the 1st element 1 and the 2nd element 9 if it is glass and a silicon | silicone material, the stress in the junction part at the time of thermally deforming can be reduced. Therefore, the bonding reliability between the interposer 6 and the first element 1 or the second element 9 can be ensured. An advantage of using an insulating material such as glass is that the insulation treatment between rewirings can be omitted.

  The interposer 6 is formed with a cavity 81 in which the second element 2 is accommodated. The planar dimension of the cavity 81 needs to be equal to or larger than the planar dimension of the second element 2, and the height dimension thereof needs to be equal to or larger than the height dimension of the second element 2. The planar dimension of the interposer 6 itself is preferably equal to or smaller than the planar dimension of the first element 1, but even larger than that is not related to the configuration of the present invention. Further, it is desirable that the height dimension of the interposer 6 itself be as thin as possible within the limits of the height dimension of the cavity 81 described above.

  The interposer 6 forms a substantially sealed space that houses the second element 2 together with the first element 1. Moreover, you may fill with nitrogen as needed. However, the circulation of gas molecules between the cavity 81 and the outside air is delayed due to the sealing property. In order to avoid this, as will be described later, a through hole for ventilation may be provided between the outer wall of the cavity 81 and the outer wall of the interposer 6. Further, a through hole and a through wiring 61 are formed in a portion corresponding to the outer wall of the cavity 81 in the interposer 6, and the through wiring 61 is rewired on the surface of the interposer 6. The through wiring 61 and the surface pad of the first element 1 are aligned and electrically connected via the solder bump 92. Thus, the function of the interposer 6 has not only the electrical connection in the vertical direction but also the function of accommodating the stacked elements.

  Similar to the first element 1, the third element 3 in which the through rewiring is formed is mounted on the upper surface of the interposer 6. With this structure, the first element 1 and the third element 3 are electrically connected via the interposer 6. The configuration of the third element 3 is the same as that of the first element 1.

  Fourth elements 4 a and 4 b are mounted on the upper surface of the third element 3. If the element is sufficiently small with respect to the dimension of the third element 3, a plurality of elements can be mounted on one element. In the embodiment shown in FIG. 1, two elements are mounted. However, as long as the dimensions allow, more elements can be mounted.

The interposer 7 is a second glass substrate mounted on the upper surface of the third element 3. However, like the interposer 6, it is not limited to glass.
A cavity 82 is formed in the interposer 7, and the fourth elements 4a and 4b are accommodated therein. The plane dimension of the cavity 82 must be equal to or greater than the plane dimension of the fourth elements 4a and 4b, and the height dimension must be equal to or greater than the height dimension of the fourth elements 4a and 4b. is there. The plane dimension of the interposer 7 itself is preferably equal to or less than the plane dimension of the third element 3, but even more than that is not related to the configuration of the present invention. Further, it is desirable that the height dimension of the interposer 7 itself be as thin as possible within the range of the height dimension of the cavity 82 described above.

  The interposer 7 together with the third element 3 forms a substantially sealed space that houses the fourth elements 4a and 4b. Moreover, you may fill with nitrogen as needed. However, the flow of gas molecules between the cavity 82 and the outside air is delayed due to hermeticity. In order to avoid this, a through hole for ventilation may be provided between the outer wall of the cavity 82 and the outer wall of the interposer 7. Further, a through hole and a through wiring 71 are formed in a portion corresponding to the outer wall of the cavity 82 in the interposer 7, and the through wiring 71 is rewired on the surface of the interposer 7. The through wiring 71 and the surface pad of the third element 3 are aligned and electrically connected via the solder bump 93. Thus, the function of the interposer 7 has not only the electrical connection in the vertical direction but also the function of accommodating the stacked elements.

As described above, the fourth elements 4 a and 4 b are accommodated in the cavity 82 formed inside the interposer 7, and the surface of the interposer 7 is formed on the third element 3 from above the third element 3 using the through wiring 71 formed in the interposer 7. A structure with rewiring formed is used.
Therefore, also in this embodiment of the present invention, the effects of facilitating the stacking of different dimensional elements, reducing the overall height dimension, and increasing the structural freedom are obtained as in the prior art.

On the upper surface of the interposer 7, the fifth element 5 as an image sensor is mounted. With this structure, the third element 3 and the fifth element 5 are electrically connected. The fifth element 5 includes a Si substrate 51, a dust-proof cap glass 52, a bonding layer 53, and a light emitting / receiving portion 54.
The bonding layer 53 for fixing the cap glass 52 is provided in a region other than the light emitting / receiving portion 54 on the fifth element 5. As the bonding layer 53, a resinous adhesive material such as epoxy, acrylic or imide is used for the cap glass of the image sensor. In the case where the upper limit of the heat resistance temperature of the element to be stacked is high, a metal or alloy having a low melting point, glass or the like can be used. In addition, when the material to be used has sufficient transparency with respect to the used wavelength of the fifth element 5, the bonding layer 53 can be formed on the entire surface of the fifth element 5.
The cap glass 52 is fixed on the fifth element 5 via the bonding layer 53. The material of the cap glass 52 needs to have excellent transparency with respect to the wavelength used, without impairing the optical characteristics of the fifth element 5. Therefore, it is selected according to the wavelength used for the fifth element 5 to be adopted.

Next, a method for manufacturing the stacked optical element package shown in FIG. 1 will be described.
First, a through rewiring is formed for the first element 1. The first element 1 may be an individual piece or a wafer. Next, the second element 2 is surface-mounted on the first element 1. Further, the interposer 6 in which the cavity 81 and the through wiring 61 have been formed is surface-mounted on the first element 1. Thereafter, the third element 3 on which the through rewiring is formed is mounted on the interposer 6. Subsequently, the fourth elements 4 a and 4 b are mounted on the surface of the third element 3. Thereafter, the interposer 7 having the cavity 82 formed and the through wiring 71 formed thereon is mounted on the third element 3. Finally, the fifth element 5 on which the cap glass 52 has been mounted and the through rewiring has been performed is mounted on the interposer 7. By following such an order, a build-up type laminated structure can be obtained.
However, the configuration of the stacked optical element package of the present invention is not limited by the above-described stacking order. For example, the manufacturing method may be such that after the second element 2 is surface-mounted on the first element 1, an upper layer laminated in advance is mounted on the second element 2.

FIG. 2 is a plan sectional view of an interposer having a vent hole.
In the figure, the interposer 6 is provided with a vent hole 62 for communicating the inside of the cavity 81 and the outside air. However, as long as there is no problem with the through-rewiring. By providing such a vent hole 62, it is possible to quickly release the heat generated with the operation of the second element 2 mounted inside the cavity 81 to the outside. Therefore, it is possible to improve the heat radiation failure of the element, which has been a problem with the element-embedded substrate.

  FIG. 3 is a cross-sectional view of another embodiment of the stacked optical element package of the present invention. In this embodiment, the fourth element 4 and the fifth element 5 are electrically connected via a through wiring 72 formed in the interposer 7. This point is different from the embodiment shown in FIG. 1, and the others are the same, so that the description thereof is omitted. According to such a configuration, not only electrical connection between two elements but also electrical connection between three or more elements becomes possible.

  FIG. 4 is a cross-sectional view of still another embodiment of the stacked optical element package of the present invention. In this embodiment, a cavity is provided for each fourth element. That is, the fourth element 4a is accommodated in the cavity 82a, and the fourth element 4b is accommodated in the cavity 82b. This point is different from the embodiment shown in FIG. 1, and the others are the same, so that the description thereof is omitted.

  FIG. 5 is a cross-sectional view of still another embodiment of the stacked optical element package of the present invention. In this embodiment, an interposer 6A is laid on the lowermost layer of the laminate, and the dimension of the interposer 6A is larger than the dimension of the element having the maximum dimension.

  By the way, when the number of stacked elements increases, the number of terminals routed to the surface of the lowermost element by the through wiring increases, and there is a possibility that rewiring cannot be performed for all terminals in the area of the lowermost element. Therefore, the through wiring from the element mounted on the upper layer in the structure is routed outside the element dimension of the interposer larger than the element dimension, and the terminal is formed (fanned out) outside the element dimension also in the lowermost layer interposer. By adopting such a structure, it becomes possible to cope with the multi-terminal of the laminate. Although the planar dimension of the stacked body is larger than the chip size, the mounting area can be saved as compared with the case where the stacked body is divided into two and each is mounted on the mounting substrate.

  In the realization of this structure, when the rewiring from the element is taken out of the element dimension, there is a possibility that a gap or a step is generated between the element and the interposer or between the element and the insulating layer. This is caused by a misalignment during the formation of the structure and a mismatch in the thermal expansion coefficients of the constituent materials after the formation of the structure. In such a situation, there is a risk that the wiring on the gap is disconnected. With respect to this problem, it is possible to minimize such danger by using a technique such as ink jet or dispensing as a wiring forming method. Copper (Cu) and silver (Ag) are generally preferred as wiring materials when using these methods, but are not limited to this, and other materials may be used.

  As described above, according to the embodiment of the present invention, it is possible to provide an optical element package in which semiconductor chips are stacked via an interposer and a large chip size optical element is installed on the uppermost stage.

  The laminated optical element package of the present invention can be applied to a light receiving device such as an image sensor or a light emitting device package such as a light emitting diode.

  DESCRIPTION OF SYMBOLS 1 1st element, 11 Silicon substrate, 12 1st insulating layer, 13 2nd insulating layer, 14 1st conductor layer, 15 2nd conductor layer, 16 3rd conductor layer, 2 2nd element, 3rd element, 4a 4b, 4th element, 5th element, 51 silicon substrate, 52 cap glass, 53 bonding layer, 54 light emitting / receiving part, 6 interposer, 62 vent hole, 7 interposer, 81-83 cavity, 91-93 solder bump.

Claims (4)

A first semiconductor element;
A substrate disposed on a main surface of the semiconductor element;
A second semiconductor element disposed in a gap defined by the main surface of the semiconductor element and the substrate;
Including at least a laminated structure,
A laminated optical element package, further comprising an optical element on the uppermost layer of the laminated structure.   The stacked optical element package according to claim 1, wherein the substrate is a glass substrate.   The stacked optical element package according to claim 1, wherein a through wiring is formed on the substrate.   4. The stacked optical element package according to claim 1, wherein the substrate has a vent hole that allows the air gap to communicate with outside air. 5.

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