JP2012042241A - Leakage current measurement circuit and leakage current measurement method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To measure a leakage current in a device to be measured with higher accuracy.SOLUTION: A leakage current measurement circuit comprises: a current mirror circuit (corresponding to MP1, MP2) for receiving the leakage current in a device 10 to be measured by one end and outputting a mirror current from an another end; a measuring terminal T1 for connecting a measurement system 20 which indirectly measures the leakage current; a switch element SW1 capable of connecting one end of the current mirror circuit with the measuring terminal T1; and a switch element SW2 capable of connecting the another end of the current mirror circuit with the measuring terminal T1 and to be opened/closed exclusively with the switch element SW1.

Description

  The present invention relates to a leakage current measuring circuit and a leakage current measuring method, and more particularly to a technique for measuring a leakage current of a semiconductor device.

  With the progress of the miniaturization structure of semiconductor devices, the influence of the current value of the leakage current of the device on the circuit operation combining the devices has become apparent. In addition, the leakage current is greatly influenced by variations in production of semiconductor devices. Therefore, it is required to measure the leak current of each device with high accuracy in order to confirm the circuit operation in the characteristic inspection of the semiconductor device.

  A technique for increasing the accuracy in measuring such a leakage current is disclosed in Patent Document 1. FIG. 8 is a circuit diagram of a leakage current measuring circuit disclosed in Patent Document 1. 8, n (n is a positive integer) PMOS transistors 1-1, 1-2,..., 1-n and n NMOS transistors 2-1, 2-2,. -N is arranged between the power supply voltage and the ground potential. The PMOS transistors 1-1, 1-2,..., 1-n have their sources commonly connected to the power supply (VDD), their gates commonly connected to the input terminal 51, and their drains commonly connected. The output terminal 53 is connected. The NMOS transistors 2-1, 2-2,..., 2-n have sources connected in common to the ground potential, gates connected in common and connected to the input terminal 52, and drains connected in common. And connected to the output terminal 53. Accordingly, the drains of all the MOS transistors are connected in common and connected to the output terminal 53.

  Now, when “L” level signals are input to the input terminals 51 and 52, the PMOS transistors 1-1, 1-2,..., 1-n are all turned on, and the NMOS transistors 2-1, 2- 2, ..., 2-n are all turned off. In this state, the current flowing from the PMOS transistor side to the source on the NMOS transistor side is measured. A current value obtained by dividing the measured current by n is an average leakage current IDDN flowing through the source of one NMOS transistor.

JP-A-5-41436

  The following analysis is given in the present invention.

  The prior art measures the leakage current as a total value by arranging MOS transistors as devices under measurement in parallel, and divides the current value as a measurement result by the number of devices arranged in parallel to obtain the leakage current value of each device under measurement. It is said. In this case, since the leakage current is very small, it is necessary to connect a large number of devices under measurement in parallel. Therefore, even if there are a few devices to be measured that exhibit abnormal leakage current, they are averaged, and it may be difficult to determine that there are devices to be measured that exhibit abnormal leakage current. That is, it is difficult to measure the leakage current with higher accuracy.

  A leak current measurement circuit according to one aspect of the present invention includes a current mirror circuit that receives a leak current in a system under test at one end and outputs a mirror current from the other end, and a measurement that indirectly measures the leak current. Exclusive of a measurement terminal for connecting the system, a first switch element that allows one end of the current mirror circuit to be connected to the measurement terminal, and a first switch element that allows the other end of the current mirror circuit to be connected to the measurement terminal A second switch element that is opened and closed automatically.

  According to another aspect of the present invention, a leakage current measuring method receives a leakage current in a system under test at one end of a current mirror circuit and measures and holds a potential at one end of the current mirror circuit. The mirror current at the other end is measured as the current that flows toward the held potential at one end.

  According to the present invention, it is possible to measure the leakage current in the system under measurement with higher accuracy.

1 is a circuit diagram of a leakage current measuring circuit according to a first embodiment of the present invention. It is a flowchart in the leakage current measurement which concerns on 1st Example of this invention. It is another circuit diagram of the leakage current measuring circuit according to the first embodiment of the present invention. FIG. 5 is a circuit diagram of a leakage current measuring circuit according to a second embodiment of the present invention. It is another circuit diagram of the leakage current measurement circuit based on the 2nd Example of this invention. FIG. 6 is a circuit diagram of a leakage current measurement circuit according to a third example of the present invention. It is another circuit diagram of the leakage current measuring circuit based on the 3rd Example of this invention. It is a circuit diagram of a conventional leakage current measurement circuit.

  The leakage current measuring circuit according to the embodiment of the present invention receives a leakage current in one system under measurement (corresponding to 10 in FIG. 1) at one end, and outputs a mirror current from the other end (MP1, MP2 in FIG. 1). 1), a measurement terminal (T1 in FIG. 1) for connecting a measurement system (20 in FIG. 1) for indirectly measuring the leakage current, and a first terminal that allows one end of the current mirror circuit to be connected to the measurement terminal. A switch element (SW1 in FIG. 1), and a second switch element (SW2 in FIG. 1) that is opened and closed exclusively with the first switch element, enabling the other end of the current mirror circuit to be connected to the measurement terminal; Is provided.

  The leakage current measuring circuit further includes a unity gain buffer (BUF in FIG. 4) between one end of the current mirror circuit and the first switch element, and the unity gain buffer is input to one end of the current mirror circuit. And connecting the output terminal to the first switch element so that the potential at one end of the current mirror circuit can be supplied to the measurement system via the measurement terminal when the first switch element is closed. Also good.

  According to such a leakage current measuring circuit, impedance conversion is performed by inserting a unity gain buffer, and the impedance of the device under measurement becomes invisible directly from the measurement system. Therefore, it is possible to measure the voltage of the device under measurement having an impedance higher than the internal impedance of the measurement system.

  The leak current measurement circuit further includes a leak correction circuit (30 in FIG. 6) connected to the input end of the unity gain buffer and supplying a current for correcting the inflow current from the input end to the inside of the unity gain buffer. You may make it prepare.

  In the leak current measurement circuit, the leak correction circuit receives an input current (40 in FIG. 6) that is a replica of the circuit that looks inside from the input end of the unity gain buffer, and receives an inflow current in the input circuit at one end. A correction current mirror circuit (corresponding to MP3 and MP4 in FIG. 6) for supplying a mirror current output from one end to one end of the current mirror circuit may be provided.

  In the leakage current measuring circuit, the current mirror circuit preferably has a mirror ratio larger than 1.

  According to such a leakage current measuring circuit, the current can be increased by the current mirror circuit, and the number of devices to be measured connected in parallel can be reduced. Therefore, the circuit scale of the device under measurement can be reduced.

  In the leakage current measuring method according to the embodiment of the present invention, the leakage current in the system under test is received at one end of the current mirror circuit, and the potential at one end of the current mirror circuit is measured and held at the other end of the current mirror circuit. The mirror current is measured as a current that flows toward the held potential at one end.

  According to the leak current measuring method as described above, the bias dependency of the current mirror can be corrected by measuring the potential at one end of the current mirror circuit and feeding back as a bias voltage at the time of current measurement. Therefore, it is possible to measure the leakage current with high accuracy.

  As described above, in the leakage current measurement, the leakage current can be measured with high accuracy. Therefore, even if the number of devices under measurement is reduced, the presence of an abnormal device can be determined when an abnormal leakage current occurs. That is, it is possible to make a pass / fail judgment with high accuracy when selecting a device.

  Hereinafter, it will be described in detail with reference to the drawings in accordance with embodiments.

  FIG. 1 is a circuit diagram of a leakage current measuring circuit according to the first embodiment of the present invention. In FIG. 1, the leakage current measurement circuit includes PMOS transistors MP1 and MP2, switch elements SW1 and SW2, and a measurement terminal T1. The PMOS transistor MP1 has a source connected to the power supply VDD, and a drain and a gate connected to the device under measurement 10. The PMOS transistor MP2 has a source connected to the power supply VDD, a drain connected to one end of the switch element SW2, and a gate connected to the gate of the PMOS transistor MP1. The PMOS transistors MP1 and MP2 constitute a current mirror circuit. Here, the size of the PMOS transistor MP2 is N (N> 1) times the size of the PMOS transistor MP1, and the mirror ratio is N.

  The switch element SW1 has one end connected to the drain of the PMOS transistor MP1 and the other end connected to the measurement terminal T1. The other end of the switch element SW2 is connected to the measurement terminal T1. A measurement system 20 that is a leakage current measuring device is connected to a measurement terminal T1.

  The leak current measuring circuit having the above configuration receives the leak current I1 of the device under test 10 at one end of the current mirror circuit, and outputs the mirror current I2 (I2 = N · I1) from the other end of the current mirror circuit.

  Next, the operation in the leakage current measurement will be described. FIG. 2 is a flowchart of the leakage current measurement according to the first embodiment of the present invention.

  The measurement system 20 turns on the switch element SW1 and turns off the switch element SW2, and measures the voltage at the measurement terminal T1, that is, the voltage value V1 applied to the device under measurement 10 (step S1).

  The measurement system 20 stores the measured voltage value V1 inside (step S2).

  The measurement system 20 turns off the switch SW1 and turns on the switch SW2, and applies the voltage value V1 obtained in step S2 from the measurement system 20 to the measurement terminal T1 (step S3).

  The measurement system 20 measures the mirror current I2 flowing through the measurement terminal T1 (Step S4). Here, the measurement function in steps S3 and S4 is called a voltage application ammeter.

  The measurement system 20 calculates the leakage current of the device under measurement 10 from the value obtained by dividing the current value (I2) measured in step S4 by the mirror ratio N (step S5).

  The measurement system 20 compares the leakage current value of the device under measurement 10 with a standard determined at the time of design, and determines pass / fail (step S6).

  According to the leak current measuring circuit as described above, the current I2 flowing through the PMOS transistor MP2 is proportional to the mirror ratio (= N times) of the current I1 flowing through the PMOS transistor MP1, and the mirror ratio is set to an appropriate value. Thus, the current I2 to be measured is sufficiently large with respect to the measurement accuracy of the measurement system 20, and measurement with high accuracy is possible.

  Further, when measuring the current I2 flowing through the PMOS transistor MP2, the voltage V1 of the drain of the PMOS transistor MP1 is applied to the drain of the PMOS transistor MP2. In general, a MOS transistor has a characteristic that even if a gate voltage is constant, a slight change in drain current occurs according to a change in drain voltage. Here, the mirror current can be measured more accurately by matching the drain voltages of the PMOS transistors MP1 and MP2 at the time of measurement (excluding the bias dependency of the current mirror) and combining the voltage-current characteristics of the two.

  FIG. 3 is another circuit diagram of the leakage current measuring circuit according to the first embodiment of the present invention. In the leakage current measuring circuit of FIG. 1, the power supply VDD and the ground are interchanged, and the current mirror circuit is configured by NMOS transistors MN1 and MN2. With such a configuration, the leakage current of the device under test 10a connected to a high potential (power supply VDD) can be measured in the same manner as described with reference to FIGS.

  FIG. 4 is a circuit diagram of a leakage current measuring circuit according to the second embodiment of the present invention. In FIG. 4, the same reference numerals as those in FIG. 4 further includes a unity gain buffer BUF between one end of the current mirror circuit (the drain of the PMOS transistor MP1) and the switch element SW1. The unity gain buffer BUF has an input end connected to one end of the current mirror circuit, an output end connected to the switch element SW1, and the potential V1 at one end of the current mirror circuit is gain 1 when the switch element SW1 is closed. Buffering is performed, and V2 can be supplied to the measurement system 20 via the measurement terminal T1. The operation at the time of measurement is the same as in the first embodiment.

  In the first embodiment, the voltage V1 applied to the device under test 10 is stored in the measurement system 20 as it is when the switch element SW1 is on and the switch element SW2 is off. On the other hand, in the second embodiment, when the voltage V1 applied to the device under test 10 is input to the unity gain buffer BUF, when the switch element SW1 is on and the switch element SW2 is off, V1 = V2 and measurement is performed. It is stored in the system 20.

  In the leakage current measurement circuit of the first embodiment, when the input impedance of the measurement system 20 is not so large as to be negligible as compared with the impedance of the device under measurement 10, this is obtained when the switch element SW1 is on and the switch element SW2 is off. The voltage differs from the voltage actually applied to the device under test 10 when the switch element SW1 is off and the switch element SW2 is on. This is because when the switch element SW1 is on and the switch element SW2 is off, the device under measurement 10 and the measurement system 20 appear as parallel impedances.

  On the other hand, according to the leakage current measurement circuit of the second embodiment, the input impedance of the measurement system 20 can be ignored through the unity gain buffer BUF. Therefore, the accurate value of the voltage applied to the device under test 10 is stored in the measurement system 20 when the switch element SW1 is on and the switch element SW2 is off.

  FIG. 5 is another circuit diagram of the leakage current measuring circuit according to the second embodiment of the present invention. In the leakage current measuring circuit of FIG. 4, the power supply VDD and the ground are interchanged, and the current mirror circuit is configured by NMOS transistors MN1 and MN2. In such a configuration, the leakage current of the device under test 10a connected to a high potential (power supply VDD) can be similarly measured.

  FIG. 6 is a circuit diagram of a leakage current measuring circuit according to the third embodiment of the present invention. 6, the same reference numerals as those in FIG. 4 represent the same items, and the description thereof is omitted. 6 includes a leakage correction circuit 30 connected to one end of the current mirror circuit (the drain of the PMOS transistor MP1) as compared to FIG.

  The leak correction circuit 30 includes a correction current mirror circuit composed of PMOS transistors MP3 and MP4, and an input circuit 40 connected to the current side of the correction current mirror circuit (drain of the PMOS transistor MP3). The input circuit 40 is a circuit (replica circuit) that generates a leak correction current having the same value as the input leak current of the unity gain buffer BUF and corresponds to the buffer input unit of the unity gain buffer BUF. The correction current mirror circuit supplies the generated leak correction current to the input terminal of the unity gain buffer BUF as the leak correction current I3.

  The leak correction circuit 30 corrects the leak current at the input end of the unity gain buffer BUF by supplying the leak correction current I3 to the input end of the unity gain buffer BUF, and flows to the device under test 10. It functions so that the current and the current I1 flowing through the PMOS transistor MP1 become equal. Therefore, the unity gain buffer BUF supplies the measurement system 20 with V2 equal to V1 that is more accurate, so that the measurement system 20 can perform measurement with higher accuracy.

  FIG. 7 is another circuit diagram of the leakage current measuring circuit according to the third embodiment of the present invention. In the leak current measuring circuit of FIG. 6, the power supply VDD and the ground are interchanged, and the current mirror circuit is configured by NMOS transistors MN1 and MN2. In such a configuration, the leakage current of the device under test 10a connected to a high potential (power supply VDD) can be similarly measured.

  It should be noted that the disclosures of the aforementioned patent documents and the like are incorporated herein by reference. Within the scope of the entire disclosure (including claims) of the present invention, the embodiments and examples can be changed and adjusted based on the basic technical concept. Various combinations and selections of various disclosed elements are possible within the scope of the claims of the present invention. That is, the present invention of course includes various variations and modifications that could be made by those skilled in the art according to the entire disclosure including the claims and the technical idea.

10 device under test 20 measurement system 30 leak correction circuit 40 input circuit BUF unity gain buffer MP1, MP2, MP3, MP4 PMOS transistor MN1, MN2 NMOS transistor SW1, SW2 switch element T1 measurement terminal

Claims (6)

A current mirror circuit that receives a leakage current in the measured system at one end and outputs a mirror current from the other end;
A measurement terminal for connecting a measurement system for indirectly measuring the leakage current;
A first switch element enabling one end of the current mirror circuit to be connected to the measurement terminal;
A second switch element that is opened and closed exclusively with the first switch element, the other end of the current mirror circuit being connectable to the measurement terminal;
A leakage current measuring circuit comprising: A unity gain buffer is further provided between one end of the current mirror circuit and the first switch element,
The unity gain buffer has an input terminal connected to one end of the current mirror circuit, an output terminal connected to the first switch element, and the current mirror circuit when the first switch element is closed. The leakage current measuring circuit according to claim 1, wherein a potential at one end can be supplied to the measuring system via the measuring terminal.   The leak correction circuit further comprising: a leak correction circuit that is connected to an input terminal of the unity gain buffer and supplies a current that corrects an inflow current from the input terminal to the inside of the unity gain buffer. Leakage current measurement circuit. The leak correction circuit is
An input circuit that is a replica of a circuit that looks inside from the input end of the unity gain buffer;
A correction current mirror circuit that receives an inflow current in the input circuit at one end and supplies a mirror current output from the other end to one end of the current mirror circuit;
The leakage current measuring circuit according to claim 3, further comprising:   2. The leakage current measuring circuit according to claim 1, wherein the current mirror circuit has a mirror ratio larger than 1. The leakage current in the system under test is received at one end of the current mirror circuit, and the potential at one end of the current mirror circuit is measured and held,
A leakage current measuring method, wherein a mirror current at the other end of the current mirror circuit is measured as a current flowing toward the held potential of the one end.

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