JP2012039046A - Semiconductor device, method of manufacturing the same and programming method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device in which energization of programming can be minimized, and drop in yield of logic circuit due to failure of fuse via cutting can be improved.SOLUTION: A via fuse cutting electric fuse 3 is formed at such a part where it is uncertain whether cutting of a fuse via is required or not. A via cut electric fuse 5 where the fuse via is omitted is formed at such a part where it is certain that cutting of a fuse via is required.

Description

  The present invention relates to a semiconductor device in which a logic circuit is formed by a via-cutting electric fuse, a manufacturing method thereof, and a programming method thereof.

  Due to the recent progress in miniaturization of semiconductor circuits, the size of SRAM (Static Random Access Memory) mounted on semiconductor devices has increased dramatically, and redundant circuits have been provided in SRAMs to improve yields so that redundant cells can be used when defects occur. The need to improve yield by replacing it is increasing.

  In addition, there is a growing need for mounting an embedded DRAM (Dynamic Random Access Memory) as a large-scale memory and mounting a chip ID (Identity) for ensuring traceability. There is a via-cutting type electric fuse as a logic element for switching a redundant circuit of such a memory or a chip ID (Patent Document 1).

  However, when a via-cutting type electric fuse is used, if a defective cutting or insufficient cutting occurs, the yield decreases. Therefore, it is necessary to minimize the fuse elements to be cut.

  Further, since the via-cutting type electric fuse cuts the fuse via by heat generation due to electric current, it necessarily takes time to cut, and it is necessary to minimize the fuse element to be cut.

  FIG. 6 shows a circuit diagram of a semiconductor device provided with a via-cutting electric fuse. FIG. 2 shows a cross-sectional view of an uncut via-cut type electric fuse 3, and FIG. 3 shows a cross-sectional view of a normally cut via-cut type electric fuse 4. FIG. 9 shows a flowchart of a fuse element programming method and a reading method.

  The logic determination circuit and the cutting circuit 1 are connected to a plurality of via-cutting electric fuses 3 of a device-specific logic circuit 6 and a chip individual logic circuit 7 by a selection circuit 2 so as to be freely connected and separated.

  The device-specific logic circuit 6 and the chip individual logic circuit 7 are programmed by cutting the fuse via of the via-cutting type electric fuse 3 selectively connected by the selection circuit 2 as necessary.

  The logic of the fuse element is inverted logic (0) when the via is cut and the current when the voltage is applied during reading is less than the threshold, and when the current when the voltage is applied during reading is not more than the threshold Is defined as positive logic (1).

JP 2007-305893 A

  When the programming method shown in the flowchart of FIG. 9 is used, the device-specific logic circuit 6 whose logic value is determined by a specific semiconductor device also needs to cut the via-cut type electric fuse 3 at the inverted logic (0) portion. .

  Therefore, when the via cutting failure remaining portion 17 as shown in FIG. 7 occurs, the upper layer wiring 11 and the lower layer wiring 12 remain connected, and the current flows above the threshold value at the time of reading, causing a determination failure, resulting in a decrease in yield. There is a problem.

  Further, when the via cutting insufficient portion 18 as shown in FIG. 8 occurs, the via cutting insufficient portion 18 is reattached to the lower layer wiring 12 due to reflow heat at the time of assembling the semiconductor device or attaching to the substrate. In the state shown in FIG. 7, similarly, there is a problem in that current flows at a threshold value or more during reading, causing a determination failure and yield reduction.

  A semiconductor device according to the present invention is a semiconductor device in which a logic circuit is programmed depending on whether or not a via-via type electric fuse is cut, and a via-cut type electric device having a fuse via in an undecided portion of whether or not to be cut is determined. A via-cutting type electric fuse in which a fuse via is omitted is formed in a portion where a fuse is formed and the necessity of cutting is determined.

  In the semiconductor device of the present invention, a via-cut type electric fuse is formed in a portion where it is not yet determined whether or not to cut the fuse via. For this reason, if necessary, the fuse via can be cut by electric heating and programmed. A via-cutting type electric fuse in which the fuse via is omitted is formed in a portion where the necessity of cutting is determined. For this reason, it is not necessary to energize to cut the fuse via when programming.

  The method for manufacturing a semiconductor device according to the present invention is a method for manufacturing a semiconductor device in which a logic circuit is programmed depending on whether or not a via via of a via-cut type electric fuse is cut. Forms a via-cutting type electric fuse having a fuse via, and forms a via-cutting type electric fuse in which the fuse via is omitted in a portion where the necessity of cutting is determined in the manufacturing stage.

  The programming method for a semiconductor device according to the present invention is a programming method for a semiconductor device in which a logic circuit is programmed depending on whether or not a via-via type electric fuse is blown. The via-cut type electric fuse cuts the fuse via by energization, and does not pass the via-cut type electric fuse that has been confirmed to be cut from the manufacturing stage.

  In the semiconductor device of the present invention, a via-cut type electric fuse is formed in a portion where it is not yet determined whether or not to cut the fuse via. For this reason, if necessary, the fuse via can be cut by electric heating and programmed. A via-cutting type electric fuse in which the fuse via is omitted is formed in a portion where the necessity of cutting is determined. For this reason, it is not necessary to energize to cut the fuse via when programming. Accordingly, it is possible to minimize the energization of programming, and it is possible to improve the decrease in the yield of the logic circuit due to defective cutting of the fuse via.

1 is a schematic circuit diagram showing a semiconductor device according to an embodiment of the present invention. It is a typical vertical side view which shows the internal structure of the via cutting | disconnection type electric fuse which has a fuse via common with the past. It is a typical vertical side view which shows the internal structure of the via cutting | disconnection type electric fuse of the state by which the fuse via was cut | disconnected. It is a typical vertical side view which shows the internal structure of the via-cutting type electric fuse which does not have a fuse via. 6 is a flowchart illustrating a programming method and a circuit reading method for a semiconductor device. It is a typical circuit diagram which shows the semiconductor device of one prior art example. It is a typical vertical side view showing an internal structure of a via-cutting type electric fuse in a state where a cutting failure has occurred in the fuse via. It is a typical vertical side view showing an internal structure of a via-cutting type electric fuse in a state where a cutting failure has occurred in the fuse via. It is a flowchart which shows the programming method and reading method of a fuse element.

  An embodiment of the present invention will be described below with reference to the drawings. However, the same parts as those of the conventional example described above with respect to the present embodiment are denoted by the same names and symbols, and detailed description thereof is omitted.

  FIG. 1 shows a circuit diagram of a semiconductor device provided with a via-cutting electric fuse of this embodiment. FIG. 2 is a cross-sectional view of a conventional via-cut type electric fuse 3 common to the prior art. FIG. 3 shows a cross-sectional view of a cut-through via-fused electric fuse 4 common to the prior art. FIG. 4 shows a cross-sectional view of the via-cutting electric fuse 5 (no fuse via) of the present embodiment.

  In the semiconductor device of the present embodiment, the logic circuits 6 and 7 are programmed depending on whether or not the fuse via 13 of the via-cutting electric fuse 3 is cut. However, as shown in FIG. 1, in the semiconductor device of the present embodiment, a via-cutting electric fuse 3 having a fuse via 13 is formed in a portion where the necessity of cutting is undecided, and the necessity for cutting is determined. A via-cutting type electric fuse 5 in which the fuse via 13 is omitted is formed in the portion where it is formed.

  As a manufacturing method of such a semiconductor device, a via-cutting type electric fuse 3 having a fuse via 13 is formed in a portion where the necessity of cutting is undecided at the manufacturing stage, and the necessity of cutting is determined at the manufacturing stage. A via-cut type electric fuse 5 in which the fuse via 13 is omitted is formed in the portion.

  As a programming method of the semiconductor device manufactured in this way, as shown in FIG. 5, the via-cutting electric fuse 3 that has been determined to be cut, which has not been determined at the manufacturing stage, cuts the fuse via 13 by energization, The via-cutting electric fuse 5 whose cutting has been confirmed from the manufacturing stage is not energized.

  By being manufactured and programmed in this manner, as shown in FIG. 1, a semiconductor device in which the logic circuits 6 and 7 are programmed by the via-cutting electric fuses 3 and 5 is formed.

  More specifically, in the semiconductor device of the present embodiment, the via-cutting electric fuse 3 includes an upper layer wiring 11 having a thickness of 0.22 μm and a lower layer wiring 12 having a thickness of 0.2 μm, as shown in FIG. The insulating film 14 is formed of copper wiring.

  A fuse via 13 having a diameter of 0.09 μm is provided to connect the upper and lower wirings 11 and 12. As shown in FIG. 3, the fuse via 13 is selectively cut by electric heating as required.

  On the other hand, as shown in FIG. 4, the via-cutting type electric fuse (without fuse via) 5 includes an upper layer wiring 11 having a thickness of 0.22 μm and a lower layer wiring 12 having a thickness of 0.2 μm formed of copper wiring in an insulating film 14. Is formed.

  However, as shown in the drawing, the fuse via 13 connecting the upper and lower wirings 11 and 12 is not formed from the beginning, and the upper and lower wirings 11 and 12 are physically separated by an insulating film thickness of 0.17 μm. .

  In the semiconductor device according to the present embodiment, as described above, a via-cutting electric fuse 3 is formed in a portion where the necessity of cutting is undecided at the manufacturing stage as described above, and a via is formed in a portion where the necessity of cutting is determined. A cutting-type electric fuse 5 is formed.

  In the present invention, after forming the insulating film 14, a groove constituting the lower layer wiring 12 is processed using the damascene method, the groove is buried by plating, and the lower layer wiring 12 is formed by the CMP method. Thereafter, after the insulating film 14 is grown again, the trench of the upper wiring 11 and the via-cutting electric fuses 3 and 4 are formed by using the dual damascene method.

  At that time, the via portion of the via-cut type electric fuse (no fuse via) 5 is changed in advance so that a via is not formed by a photomask pattern, and then grooves and vias are buried by plating, and CMP is performed. A via (fuse portion) 13 is formed in the via portion of the lower layer wiring 12 and the fuse 3.

  Compared with the cross-sectional view of the via-cutting electric fuse 4 shown in FIG. 3, the via is not formed in advance by a photomask at the time of manufacture, whereas the cutting via 15 and the cavity (fuse portion) 16 exist in the prior art. Therefore, the fuse vialess (fuse portion) 19 is formed of the insulating film 14 (see FIG. 4).

  By adopting this configuration, the inversion logic (0) of the device-specific logic circuit 6 is determined in advance without using the cutting circuit 1 as in the programming method shown in FIG. There is no need to do it.

  Therefore, the device-specific logic circuit 6 does not have a via cutting failure remaining portion 17 or a via cutting insufficient portion 18 due to the cutting operation as in the conventional example. As a result, erroneous determination of the inverted logic (0) of the device-specific logic circuit 6 does not occur, and the yield can be improved.

  In addition, since it is not necessary to program the inverted logic (0) portion of the device-specific logic circuit 6, it is possible to reduce the time required for programming.

  In the semiconductor device according to the present embodiment, the via-cutting electric fuses 3 and 5 in the inversion logic portion of the device-specific portion are different only in the presence or absence of the fuse via 13 and are determined by the resistance value of the via-cutting electric fuses 3 and 5. Since the logic determination circuit and the disconnection circuit 1 are determined by the current value, the same logic determination circuit and disconnection circuit 1 as the conventional element can be used.

  In addition, the presence or absence of the fuse via 13 can be easily changed because it can be performed only by changing the photomask in the via formation process. Further, since the determination can be performed by the same determination circuit, the need for another determination circuit is unnecessary, so that an increase in chip size due to the provision of another determination circuit can be prevented, and reading is easy.

  In the semiconductor device of the present embodiment, as described above, the via-cutting electric fuse 3 is formed in a portion where the necessity to cut the fuse via 13 is undecided. Therefore, if necessary, the fuse via 13 can be programmed by cutting with electric heat.

  A via-cutting type electric fuse 5 in which the fuse via 13 is omitted is formed in a portion where the necessity of cutting is determined. For this reason, it is not necessary to energize to cut the fuse via 13 when programming. Therefore, it is possible to minimize the energization of programming, and it is possible to improve the yield reduction of the logic circuits 6 and 7 due to the disconnection failure of the fuse via 13.

  The present invention is not limited to the present embodiment, and various modifications are allowed without departing from the scope of the present invention. In the above-described embodiment, the structure of each part has been specifically described. However, the structure and the like can be variously changed within a range that satisfies the present invention.

DESCRIPTION OF SYMBOLS 1 Logic judgment circuit and cutting circuit 2 Selection circuit 3 Via cutting type electric fuse 4 Via cutting type electric fuse 5 Via cutting type electric fuse (no fuse via)
6 Device-specific logic circuit 7 Chip individual logic circuit 11 Upper layer wiring 12 Lower layer wiring 13 Fuse via 14 Insulating film 15 Cutting via 16 Cavity (fuse portion)
17 Via cutting failure remaining part 18 Via cutting insufficient part 19 Fuse part (no fuse via)

Claims (3)

A semiconductor device in which a logic circuit is programmed by whether or not a fuse via of a via cut type electric fuse is cut,
The via-cutting electric fuse having the fuse via is formed in a portion where the necessity of cutting is undecided,
A semiconductor device in which the via-cutting type electric fuse in which the fuse via is omitted is formed in a portion where the necessity of cutting is determined. A method of manufacturing a semiconductor device in which a logic circuit is programmed based on whether or not a fuse via of a via cut type electric fuse is cut,
Forming the via-cutting electric fuse having the fuse via in a portion where the necessity of cutting is undecided in the manufacturing stage,
A method of manufacturing a semiconductor device, wherein the via-cut type electric fuse is formed by omitting the fuse via at a portion where the necessity of cutting is determined at a manufacturing stage. A method of programming a semiconductor device in which a logic circuit is programmed by whether or not a fuse via of a via cut type electric fuse is cut,
The via-cutting type electric fuse, which has been determined to be undecided at the manufacturing stage, cuts the fuse via by energization,
A method for programming a semiconductor device in which a current is not supplied to the via-cutting electric fuse that has been determined to be cut from the manufacturing stage.

Images