JP2012034266A - Edge correction circuit and edge correction method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve the problem of the conventional edge correction circuit in which an output video signal can deteriorate in image quality.SOLUTION: An edge correction circuit comprises: a first delay element group for delaying an input signal; an inclination detection circuit for determining continuity of the inclination of the input signal from the input signal and the delay signal of the input signal; first and second selection circuits which select signals delayed forward and backward from a sample point by the first delay element group according to the result of the determination; third and fourth selection circuits which select signals delayed forward and backward from the sample point by the first delay element group according to setting; and an intermediate value selection circuit which extracts the high frequency component of the input signal and selects the intermediate value between the value obtained by adding the extracted component to the sample point and the values of the signals selected by the first and second selection circuits.

Description

  The present invention relates to an edge correction circuit and an edge correction method.

  2. Description of the Related Art In recent years, image display devices such as liquid crystal displays and plasma displays have adopted a method for enhancing the sharpness of an image by enhancing the edge portion of the image as the image quality of the image signal is improved. As conventional edge correction circuits, there are techniques as described in Patent Documents 1 and 2.

  In Patent Document 1, the amount of inclination of an input video signal is detected, and a tap of the input video signal having a delay amount corresponding to the detection result is selected. Then, a predetermined gain is applied to the signal of the tap with the selected delay amount delayed before and after the sampling point to be processed, and added to the sampling point to be processed, thereby outputting a contour-corrected video signal. To do.

  With such a technique of Patent Literature 1, contour enhancement is performed by a shoot component generated in the vicinity of an edge of an image using the value of a signal of a pixel away from a sampling point according to the amount of inclination of an input video signal. . As a result, the contour of the video is enhanced and a sharper resolution can be obtained.

  In Patent Document 2, a high-frequency component of an input video signal at a sample point and an input video signal delayed before and after that (that is, an adjacent pixel signal at the sample point) is extracted and shaped, and added to the sample point. If the slope of the input video signal is steep among the value of the signal after the addition and the value of the input video signal delayed further back and forth, an intermediate value is selected as the output video signal.

  Such a technique of Patent Document 2 is LTI (Luminance Transient Improvement) that removes ringing of a video signal that has passed through a high-pass filter that is a FIR (Finite Impulse Response) filter. With this technique, it is possible to generate a video signal with a good contour sharpness while suppressing the occurrence of ringing and image quality deterioration.

JP 2005-236805 A International Publication No. 2005/084039

  In the technique of Patent Document 1, a shoot component (ringing) generated in the vicinity of an edge is generated by using a tap signal as far as possible from the sample point from the inclination of the video signal, and the solution is obtained by using the ringing. I can raise the image. However, in the technique of Patent Document 1, depending on the input video signal, a shoot may occur near the edge due to the ringing, and side effects such as overexposure, darkening, and pseudo contour may occur.

  FIG. 8 shows an example of the waveform of the output video signal with respect to the input video signal of the edge correction circuit according to Patent Document 1. As shown in part A in FIG. 8, in the technique of Patent Document 1, a large shoot component is generated, and this part becomes the above-described whiteout, blackout, pseudo contour, and the like. It should be pointed out that the technique disclosed in Patent Document 1 is not an LTI because ringing (shoot component) is intentionally generated near the edge of an image.

  Here, as a method for suppressing ringing, a technique as disclosed in Patent Document 2 is effective. In the technique of Patent Document 2, since an intermediate value of adjacent pixel signal values is selected by an intermediate value selection circuit, ringing can be removed. However, in the technique of Patent Document 2, it is difficult to generate an output video signal with a steep slope because the edge correction processing is performed by comparing pixels near the sample point. For this reason, the problem that the improvement of the inclination of an edge is not enough arises.

  FIG. 9 shows an example of the waveform of the output video signal with respect to the input video signal of the edge correction circuit according to Patent Document 2. As shown in portions B and C in FIG. 9, the waveform of the output video signal is disturbed at a sudden change point of the input video signal. This disturbance of the waveform may cause a problem that the picture of the output video changes with respect to the input video. In particular, in the portion C, in addition to the disturbance of the waveform of the output video signal, the transient is also deteriorated.

  Thus, in the conventional patent documents 1 and 2, there is a possibility that the output video signal as shown in FIGS. Therefore, in order to suppress such deterioration, it is conceivable to apply Patent Document 2 to Patent Document 1 which is a conventional technique. However, Patent Document 1 is a technique that dares to generate ringing (shoot component), and the application of Patent Document 2 that suppresses the shot component causes a contradictory problem. Therefore, there is a need for an edge correction technique that does not cause such a contradiction problem and prevents deterioration of the output video signal.

  One embodiment of the present invention sequentially delays an input signal by a unit delay amount, and includes a plurality of first delay signals having a delay before a correction target sample point of the input signal and a delay after the correction target sample point A first delay element group that generates a plurality of second delay signals, a plurality of first delay elements, a plurality of differential signals delayed by a unit delay amount from the input signal, An inclination detection circuit for determining the continuity of the inclination of the input signal from the delay difference signal, and a first selection delay signal having a delay amount according to a determination result of the inclination determination unit, the plurality of first delay signals A first selection circuit for selecting from the plurality of second delay signals, a second selection delay signal having a delay amount corresponding to the determination result of the inclination determination unit, and a setting A third selection delay signal having a delay amount corresponding to the signal. A third selection circuit that selects from the plurality of first delay signals, and a fourth selection that selects, from the plurality of second delay signals, a fourth selection delay signal having a delay amount corresponding to the setting signal. A high-pass filter that extracts a high-frequency component of the input signal based on a circuit, a signal of a correction target sample point of the input signal, and the third and fourth selection delay signals; An addition circuit that generates an addition signal that is added to the correction target sample points of the input signal and each value of the addition signal and the first and second selection delay signals are compared, and a signal having an intermediate value is output as an output signal And an intermediate value selection circuit.

  In another aspect of the present invention, the input signal is sequentially delayed by a unit delay amount, a plurality of first delay signals having a delay before the correction target sample point of the input signal, and the correction target sample point A plurality of second delay signals having a delay, the input signal, and a differential signal delayed by a unit delay amount from the input signal, and a plurality of delay differential signals sequentially delayed by a unit delay amount. A determination result of the continuity of the slope of the input signal is generated, a first selection delay signal having a delay amount according to the determination result is selected from the plurality of first delay signals, and a delay according to the determination result A second selection delay signal of an amount is selected from the plurality of second delay signals, a third selection delay signal of a delay amount according to a setting is selected from the plurality of first delay signals, A fourth selection delay signal having a delay amount according to the setting is Selected from a plurality of second delay signals, the high-frequency component of the input signal is extracted based on the signal of the correction target sample point of the input signal and the third and fourth alternative delay signals, and the extracted Generates an addition signal obtained by adding a high frequency component to the correction target sample point of the input signal, compares each value of the addition signal and the first and second selection delay signals, and outputs a signal having an intermediate value This is an edge correction program used as a signal.

  According to the present invention, the tap (delayed signal generated by the first delay element group) selected by the first and second selection circuits according to the determination result of the inclination detection circuit that determines the continuity of the inclination of the input signal. The width can be adjusted. In addition, the shoot component generated from the extracted component of the high-pass filter can be removed by the intermediate value selection circuit. As a result, the transient can be improved while preventing the output signal from deteriorating with respect to the input signal.

  The present invention makes it possible to obtain an output image signal with improved transients while suppressing the occurrence of image deterioration such as whitening and darkening of the input image signal.

1 is a block configuration of a television receiver according to a first embodiment. 3 is a configuration of an edge correction circuit according to the first exemplary embodiment. 3 is an example of a configuration of a high-pass filter according to the first embodiment. 3 is an example of operation waveforms of the edge correction circuit according to the first exemplary embodiment; 3 is a configuration of an edge correction circuit according to a second exemplary embodiment. It is a schematic diagram explaining a DE signal. This is a configuration of an edge correction circuit according to another embodiment. It is an example of the operation | movement waveform for demonstrating the problem of a prior art. It is an example of the operation | movement waveform for demonstrating the problem of a prior art.

  Embodiment 1 of the Invention

  Hereinafter, a specific first embodiment to which the present invention is applied will be described in detail with reference to the drawings. In the first embodiment, the present invention is applied to an edge correction circuit of a television receiver. FIG. 1 shows an example of a block configuration of a television receiver TV101 according to the present embodiment. As shown in FIG. 1, the television receiver TV 101 includes an antenna unit 102, a tuner unit 103, a decoder unit 104, an edge correction circuit 100, an encoder unit 105, and a display unit 106.

  The tuner unit 103 receives a digital broadcast signal from the antenna unit 102. The decoder unit 104 decodes the digital broadcast signal received by the tuner unit 103 and outputs it as a video signal.

  The edge correction circuit 100 receives the video signal output from the decoder unit 104, performs edge correction processing, and outputs the video signal.

  The encoder unit 105 encodes the video signal output from the edge correction circuit 100 into a signal that can be processed by the display unit 106. The display unit 106 displays an image according to the signal output from the encoder unit 105.

  Note that the decoder unit 104, the edge correction circuit 100, and the encoder unit 105 may be configured by one LSI.

  FIG. 2 shows a configuration of the edge correction circuit 100 which is a characteristic part of the present invention. As shown in FIG. 2, the edge correction circuit 100 includes delay elements 111 to 118, selection circuits 121 to 124, a high-pass filter 125, an adder 126, an intermediate value selection circuit 127, a slope detection circuit 130, It has a TAP register 150, a multiplier 160, a gain adjustment circuit 161, a gain register 162, an input terminal IN, and an output terminal OUT.

  The input terminal IN inputs a video signal (hereinafter referred to as an input video signal) output from the decoder unit 104 of FIG.

  The output terminal OUT outputs the output video signal edge-corrected by the edge correction circuit 100 to the encoder unit 105 in FIG.

  Delay elements 111 to 118 are connected in series between input terminal IN and node N118. The delay elements 111 to 118 delay the video signal input from the input terminal IN. In this example, the delay elements 111 to 118 are flip-flops that delay the input video signal by the sampling unit time T1. The delayed video signals delayed by the delay elements 111 to 118 are output to the nodes N111 to N118, respectively. The delayed video signals applied to the nodes N111 to N118 are denoted as S111 to S118, respectively. Moreover, each of these nodes is called a tap as needed.

  The inclination detection circuit 130 detects the continuity of the inclination of the input video signal. And the selection control signal SEL1 according to the detection result is output. The selection control signal SEL1 is a control signal that determines a signal to be selected by the selection circuits 121 and 122. The inclination detection circuit 130 includes a difference circuit 140, a difference determination circuit 131, delay elements 132 to 138, and a continuity determination circuit 139.

  The difference circuit 140 determines a difference value between a signal applied to the input terminal IN (input video signal) and a delayed video signal S111 (a signal obtained by delaying the input video signal by the sampling unit time T1) as a difference signal S140. Output to the circuit 131. The signal delayed by the sampling unit time T1 can be regarded as a video signal (for example, a luminance signal) of an adjacent pixel on the horizontal scanning line. From this, the difference determination circuit 131 can detect the inclination of the video signal between adjacent pixels. For this reason, when the value of the difference signal S140 is “0”, the video signals between adjacent pixels have the same value, and there is no inclination. When the value of the difference signal S140 has a positive or negative value, there is an inclination between adjacent pixels.

  The difference determination circuit 131 receives the difference signal S140 output from the difference circuit 140. If the value of the difference signal S140 is greater than a predetermined threshold (thr), a difference determination signal having a value “1” is output to the node N131. Alternatively, if the value of the difference signal S140 is smaller than a predetermined threshold (−thr), a difference determination signal having a value “−1” is output to the node N131. Alternatively, when the value of the difference signal S140 is within a predetermined threshold (−thr to thr), a difference determination signal having a value “0” is output to the node N131. Hereinafter, this difference determination signal is referred to as S131.

  When noise is added to the input video signal, even if the difference value is “0” (that is, there is no inclination of the video signal between adjacent pixels), the difference signal S140 also has a value other than “0” due to the noise. Has and fluctuates. Here, by setting the threshold value (−thr to thr), if the difference signal S140 is within the threshold value (−thr to thr), it can be regarded as noise and ignored. The difference circuit 140 and the difference determination circuit 131 may be a difference signal generation circuit having a single circuit configuration.

  Delay elements 132 to 138 are connected in series between nodes N132 and N138. The delay elements 132 to 138 delay the difference determination signal S131 at the node N131. In this example, the delay elements 132 to 138 are flip-flops that delay the input signal by the sampling unit time T1, as with the delay elements 111 to 118. The difference determination signals delayed by the delay elements 132 to 138 are output to the nodes N132 to N138, respectively. The signals output to these nodes N132 to N138 are referred to as difference determination signals S132 to S138, respectively.

  The continuity determination circuit 139 receives the difference determination signals S131 to S138 and determines how much the inclination of the video signal between adjacent pixels is continuous. Then, the determination result is output as a selection control signal SEL1.

  For example, when it is determined that the difference determination signals S131 to S138 have the same value (for example, all “1”), the value of the selection control signal SEL1 is output as “4”. Alternatively, when it is determined that the difference determination signals S132 to S136 have the same value, the value of the selection control signal SEL1 is output as “3”. Alternatively, when it is determined that the difference determination signals S133 to S136 have the same value, the value of the selection control signal SEL1 is output as “2”. Alternatively, when it is determined that the difference determination signals S134 and S135 have the same value, the value of the selection control signal SEL1 is output as “1”. Alternatively, when it is determined that the difference determination signals S134 and S135 are not the same value, the value of the selection control signal SEL1 is output as “0”.

  As described above, the difference determination signals S131 to S138 indicate the difference in the delayed video signal between adjacent taps. For this reason, for example, when the values of the difference determination signals S134 and S135 are both “1”, the delay video signals S113 to S115 monotonously increase. Further, for example, when the values of the difference determination signals S133 to S136 are all “1”, it means that the delay video signals S112 to S116 are monotonously increased. Further, for example, when the values of the difference determination signals S132 to S137 are all “1”, the delay video signals S111 to S117 are monotonously increased. Further, for example, when the values of the difference determination signals S131 to S138 are all “1”, it means that the input video signal monotonically increases from the delayed video signal S118.

  The selection circuit 123 receives the input video signal and the delayed video signals S111 to S113. Then, one of the input video signal and the delayed video signals S111 to S113 is selected according to the selection control signal SEL1, and is output as the selected video signal S123.

  For example, when the value of the selection control signal SEL1 is “1”, the delayed video signal S113 is selected and output. Alternatively, when the value of the selection control signal SEL1 is “2”, the delayed video signal S112 is selected and output. Alternatively, when the value of the selection control signal SEL1 is “3”, the delayed video signal S111 is selected and output. Alternatively, when the value of the selection control signal SEL1 is “4”, the input video signal is selected and output.

  The selection circuit 124 receives the delayed video signals S115 to S118. Then, one of the delayed video signals S115 to S118 is selected according to the selection control signal SEL1, and is output as the selected video signal S124.

  For example, when the value of the selection control signal SEL1 is “1”, the delayed video signal S115 is selected and output. Alternatively, when the value of the selection control signal SEL1 is “2”, the delayed video signal S116 is selected and output. Alternatively, when the value of the selection control signal SEL1 is “3”, the delayed video signal S117 is selected and output. Alternatively, when the value of the selection control signal SEL1 is “4”, the delayed video signal S118 is selected and output.

  As described above, the input video signal and the delayed video signals S111 to S118 can be regarded as being output from the corresponding taps, and the selection circuits 123 and 124 receive the selection control signal SEL1 from the inclination detection circuit 130, respectively. As the value increases, the interval between taps to be selected is increased.

  The selection circuit 121 receives the input video signal and the delayed video signals S111 to S113. Then, one of the input video signal and the delayed video signals S111 to S113 is selected according to the value held in the TAP register 150, and is output as the selected video signal S121.

  For example, when the value held in the TAP register 150 is “1”, the delayed video signal S113 is selected and output. Alternatively, when the value held in the TAP register 150 is “2”, the delayed video signal S112 is selected and output. Alternatively, when the value held in the TAP register 150 is “3”, the delayed video signal S111 is selected and output. Alternatively, when the value held in the TAP register 150 is “4”, the input video signal is selected and output.

  The selection circuit 122 receives the delayed video signals S115 to S118. Then, one of the delayed video signals S115 to S118 is selected according to the value held in the TAP register 150, and is output as the selected video signal S122.

  For example, when the value held in the TAP register 150 is “1”, the delayed video signal S115 is selected and output. Alternatively, when the value held in the TAP register 150 is “2”, the delayed video signal S116 is selected and output. Alternatively, when the value held in the TAP register 150 is “3”, the delayed video signal S117 is selected and output. Alternatively, when the value held in the TAP register 150 is “4”, the delayed video signal S118 is selected and output.

  The TAP register 150 controls the selection circuits 121 and 122 as described above according to the value held. The value of the TAP register 150 may be a fixed value or may be changed according to the control signal of the LSI controller. In the case of a fixed value, it is set by the control signal of the LSI controller when the LSI (see FIG. 1) including the edge correction circuit 100 is started.

  Alternatively, the value of the selection control signal SEL1 may be used as the value of the TAP register 150. For example, by setting the value of the TAP register 150 to (SEL1 + 1), the selection video signal output from the selection circuits 121 and 122 can be changed according to the inclination of the input video signal. However, when SEL1 = 4, the value of the TAP register 150 is not “5” but limited to “4”.

  The high pass filter 125 receives the selected video signals S121 and S122 and the delayed video signal S114 and extracts the high frequency components. An example of a specific configuration of the high-pass filter 125 is an FIR filter shown in FIG. This is an example, and the high-pass filter 125 may have a circuit configuration other than that shown in FIG.

  As illustrated in FIG. 3, the high pass filter 125 includes multipliers 141 to 143 and adders 144 and 145. The multiplication coefficients of the multipliers 141 to 143 are, for example, −1, +2, and −1, respectively. The multiplier 141 receives the selected video signal S121 and amplifies it with a predetermined multiplication coefficient. The multiplier 142 receives the delayed video signal S114 and amplifies it with a predetermined multiplication coefficient. The multiplier 143 receives the selected video signal S122 and amplifies it with a predetermined multiplication coefficient. Then, the outputs of the multipliers 141 to 143 are added by the adders 144 and 145, and the output signal S125 of the high pass filter 125 is output. The operation of the high-pass filter 125, which is an FIR filter shown in FIG.

  The multiplier 160 amplifies the high-pass filter output signal S125 output from the high-pass filter 125 by a gain value (for example, 1/2 or 1/4) set by the gain value generation circuit 161, and outputs the amplified signal to the adder 126. To do. The gain value set by the gain value generation circuit 161 can be changed according to the value held by the gain register 162.

  The adder 126 adds the high-pass filter output signal S125 amplified by the multiplier 160 to the delayed video signal S114, and outputs the result as an added video signal S126. That is, the edge correction circuit 100 uses the delayed video signal S114 as a correction target sample point. Hereinafter, the delayed video signal S114 is referred to as a correction target sample point signal as necessary.

  The intermediate value selection circuit 127 selects a signal having an intermediate value among the addition video signal S126 and the selection video signals S123 and S124. Then, the selected signal is output as an output video signal to the output terminal OUT. For example, when the selected video signal S121 is “1”, the added video signal S126 is “7”, and the selected video signal S122 is “5”, the intermediate value “5”, that is, the selected video signal S122 is selected. The output video signal is output to the output terminal OUT.

  An example of the operation waveform of the edge correction circuit 100 as described above is shown in FIG. FIG. 4 shows the waveform of the output video signal output by the edge correction circuit 100 with respect to the same input video signal as in FIGS. For comparison with the prior art, the waveform of the output video signal with respect to the input video signal of the edge correction circuit according to Patent Document 2 shown in FIG. 9 is also shown. As shown in FIG. 4, in the monotonously increasing portion and the simple decreasing portion of the input video signal waveform, the output video signal waveform has a steeper slope than the conventional technique, and the transient is improved. Furthermore, the occurrence of the waveform disturbance at the point of sudden fluctuation of the signal in FIG. 9 and the signal generated in FIG. 9 which has been a problem in the prior art is suppressed.

  As described above, in the edge correction circuit 100 according to the first embodiment, the inclination detection circuit 130 detects the continuity of the inclination of the input video signal, and the interval between taps selected by the selection circuits 123 and 124 according to the detection result. To spread. As a result, it is possible to remove the shoot component, suppress the waveform disturbance at the sudden fluctuation point of the input video signal, and improve the transient.

  Embodiment 2 of the Invention

  Hereinafter, a specific second embodiment to which the present invention is applied will be described in detail with reference to the drawings. In the second embodiment, as in the first embodiment, the present invention is applied to an edge correction circuit of a television receiver.

  FIG. 5 shows a configuration of the edge correction circuit 200 according to the second exemplary embodiment. As shown in FIG. 5, the edge correction circuit 200 includes delay elements 111 to 118, selection circuits 121 to 124, a high-pass filter 125, an adder 126, an intermediate value selection circuit 127, an inclination detection circuit 130, TAP register 150, multiplier 160, gain adjustment circuit 161, gain register 162, noise determination circuit 260, removal circuit 266, multiplier 267, input terminal IN, output terminal OUT, and DE input terminal It has DE_IN.

  In addition, the structure which attached | subjected the code | symbol same as FIG. 2 among the code | symbols shown in FIG. 5 has shown the structure same as or similar to FIG. The second embodiment is different from the first embodiment in that a noise determination circuit 260 and the like are newly added. In the second embodiment, the different parts will be described mainly, and the description of other parts similar to those in the first embodiment will be omitted.

  The DE input terminal DE_IN inputs a DE signal indicating whether or not the video input signal is a blanking portion signal. The DE signal is a signal in which DE = 0 in the blanking (black display) portion outside the display portion of the display as shown in the schematic diagram of FIG. Note that DE = 1 in the video display portion. The DE signal can be generated, for example, by using a horizontal synchronization signal.

  The noise determination circuit 260 includes an absolute value generation circuit 261, a limiter circuit 262, a threshold generation circuit 263, a coring value generation circuit 264, and a timing adjustment circuit 265.

  The noise determination circuit 260 detects a noise component riding on an input video signal in a section of DE = 0, that is, a blanking portion signal having no video signal. Then, the threshold value in the section of DE = 1 of the difference determination circuit 131 is changed according to the detected noise component. Further, it has a function of removing a value corresponding to the detected noise component from the output signal of the high-pass filter 125 in the section of DE = 1.

  The absolute value generation circuit 261 generates an absolute value of the difference signal S140 output from the difference circuit 140 and outputs the absolute value signal S261 to the limiter circuit 262.

  When the absolute value signal S261 becomes equal to or greater than a predetermined value (bthr), the limiter circuit 262 suppresses the absolute value signal S261 to a predetermined value (bthr) and outputs it to the threshold value generation circuit 263.

  For example, when the input video signal is suddenly large noise instead of constant noise, the difference signal S140 also has a large value. For this reason, the absolute value signal S261 output from the absolute value generation circuit 261 also has a large value. For this reason, the limiter circuit 262 has a function of removing the value when it is equal to or more than the predetermined value (bthr), assuming that it is the sudden noise component described above.

  The threshold value generation circuit 263 outputs an average value of the absolute value signal S261 input through the limiter circuit 262 as the threshold value signal STH. The threshold signal STH is input to the difference determination circuit 131. The threshold generation circuit 263 is configured by, for example, an IIR (Infinite Impulse Response) filter. By this IIR, it is possible to output the threshold signal STH that is suppressed so as not to react sensitively to a sudden change in input value.

  In the first embodiment, a fixed threshold value (−thr to thr) is preset in the difference determination circuit 131. However, in the second embodiment, the threshold value (−thr to thr) of the difference determination circuit 131 varies according to the threshold signal STH. Therefore, the threshold value (−thr to thr) of the difference determination circuit 131 is increased when large noise is on the input video signal, and the difference determination circuit 131 is set when only small noise is on the input video signal. The threshold value (-thr to thr) can be reduced.

  As described above, the noise determination circuit 260 detects a noise component on the blanking portion signal in the DE = 0 interval, and changes the threshold value in the DE = 1 interval of the difference determination circuit 131 according to the detection result. To do. For this reason, the operation in which the threshold value generation circuit 263 generates the threshold value signal STH is performed in a section where DE = 0. On the other hand, in the section of DE = 1, the value of the threshold signal STH generated in the section of DE = 0 is held, and the difference determination circuit 131 operates according to the threshold signal STH having the held value.

  Further, the operation of removing a value corresponding to the detected noise component from the output signal of the high-pass filter 125 performed by the removal circuit 266 described later is also performed based on the threshold signal STH generated in the section of DE = 0.

The coring value generation circuit 264 outputs a coring value signal SCOR corresponding to the threshold signal STH output from the threshold generation circuit 263. For example, the value of the coring value signal SCOR is calculated as shown in Expression (1) using the value of the threshold signal STH.
SCOR = COR_BASE + STH × COR_VAL (1)

  However, the values of COR_BASE and COR_VAL in equation (1) are parameters that can be arbitrarily adjusted by a register or the like.

  The removal circuit 266 inputs the coring value signal SCOR output from the coring value generation circuit 264 via the timing adjustment circuit 265. Then, the value of the coring value signal SCOR is divided from the value of the high-pass filter output signal S125 amplified by the multiplier 160. Then, the signal after the division is output as S266.

  The multiplier 267 multiplies the DE signal input via the timing adjustment circuit 265 and the output signal S266 of the removal circuit 266, and outputs the result.

  As described above, since the value of the blanking interval of the DE signal is “0”, the value output from the multiplier 267 is also fixed to “0”. Therefore, as the added video signal S126 output from the adder 126, the correction target sample point signal (delayed video signal S114) in the blanking interval is output as it is.

  On the other hand, since the value of the DE signal is “1” in the video display portion, the multiplier 267 becomes a through circuit and transmits the output signal S266 of the removal circuit 266 to the adder 126 at the subsequent stage. For this reason, the adder 126 adds the value of the output signal S266 of the removal circuit 266 and the correction target sample point signal (delayed video signal S114), and outputs the result as an added video signal S126.

  The timing adjustment circuit 265 includes a delay circuit and adjusts the output timing of the coring value signal SCOR and the DE signal. More specifically, the output timing of the coring value signal SCOR and the DE signal is adjusted according to the correction target sample point signal (delayed video signal S114) corresponding to the difference signal S131 input by the noise determination circuit 260.

  By including the noise determination circuit 260 configured as described above, the edge correction circuit 200 according to the second embodiment removes a value corresponding to the noise component when the noise component is on the input video signal. To generate an output video signal. In addition, by changing the threshold value of the difference determination circuit 131 according to the noise component, it is possible to increase the accuracy of detecting the continuity of the inclination of the input video signal by the inclination detection circuit 130. For this reason, compared with Embodiment 1, the noise tolerance with respect to an input video signal can be raised, and it becomes possible to improve the video quality of an output video signal more.

  Note that the present invention is not limited to the above-described embodiment, and can be changed as appropriate without departing from the spirit of the present invention.

  For example, a gain value generation circuit 370 may be added before the multiplier 267 as in the edge correction circuit 300 shown in FIG. The gain value generation circuit 370 adjusts the gain of the multiplier 267 when the value of the DE signal is “1”.

  For example, when the gain of the multiplier 267 is adjusted to 0.5 by the gain value generation circuit 370, the output signal S266 having a signal strength of 50% is added to the correction target sample point signal by the adder 126. The gain adjustment of the multiplier 267 by the gain value generation circuit 370 can be made variable according to the value held in the gain register 371. The gain register 371 may be included in the gain value generation circuit 370. The value of the gain register 371 is rewritten by a control signal from a controller or the like. Thus, the edge correction circuit 300 can adjust the strength of edge correction performed on the correction target sample point signal.

  The functions similar to those of the edge correction circuits 100 to 300 described above may be realized by a computer program such as a PC. That is, the data of the input video signal may be processed in software by the same operation as the edge correction circuits 100 to 300, and the processing result may be obtained as the data of the output video signal.

100, 200, 300 Edge correction circuit 101 Television receiver 102 Antenna unit 103 Tuner unit 104 Decoder unit 105 Encoder unit 106 Display unit 111 to 118 Delay elements 121 to 124 Selection circuit 125 High-pass filter 126 Adder 127 Intermediate value selection circuit 130 Inclination Detection circuit 150 TAP register IN Input terminal OUT Output terminal 131 Difference determination circuit 132 to 138 Delay element 139 Continuity determination circuit 140 Difference circuit 260 Noise determination circuit 266 Removal circuit 267 Multiplier DE_IN DE input terminal 261 Absolute value generation circuit 262 Limiter circuit 263 Threshold generation circuit 264 Coring value generation circuit 265 Timing adjustment circuit

Claims (10)

The input signal is sequentially delayed by a unit delay amount, a plurality of first delay signals having a delay before the correction target sample point of the input signal, and a plurality of second delay signals having a delay after the correction target sample point A first delay element group for generating a delay signal;
A slope detection circuit that determines the continuity of the slope of the input signal from a plurality of delay differential signals obtained by sequentially delaying the input signal and the differential signal delayed by the unit delay amount from the input signal;
A first selection circuit that selects, from the plurality of first delay signals, a first selection delay signal having a delay amount according to a determination result of the inclination determination unit;
A second selection circuit that selects, from the plurality of second delay signals, a second selection delay signal having a delay amount according to a determination result of the inclination determination unit;
A third selection circuit for selecting a third selection delay signal having a delay amount corresponding to the setting signal from the plurality of first delay signals;
A fourth selection circuit that selects, from the plurality of second delay signals, a fourth selection delay signal having a delay amount corresponding to the setting signal;
A high-pass filter that extracts a high-frequency component of the input signal based on the signal of the correction target sample point of the input signal and the third and fourth selection delay signals;
An addition circuit for generating an addition signal obtained by adding the extracted component of the high-pass filter to the correction target sample point of the input signal;
An edge correction circuit comprising: an intermediate value selection circuit that compares the values of the addition signal and the first and second selection delay signals and outputs a signal having an intermediate value as an output signal. The inclination detection circuit includes:
A difference signal generation circuit for generating a difference determination signal according to the input signal and a signal delayed by one unit delay amount with respect to the input signal generated by the first delay element group;
A second delay element group that sequentially delays the difference determination signal by a unit delay amount to generate a plurality of delay difference signals;
The edge correction circuit according to claim 1, further comprising: a continuity determination unit that determines continuity of the slope of the input signal from the plurality of delay difference signals. The difference signal generation circuit includes:
A difference circuit that generates a difference signal obtained by subtracting the input signal and a signal delayed by one unit delay amount with respect to the input signal generated by the first delay element group;
When the difference signal is within the range of the first threshold value to the second threshold value, the difference determination signal of the first value is generated, and when the difference signal is equal to or greater than the first threshold value, the second value of the difference signal is generated. The edge correction circuit according to claim 2, further comprising: a difference determination circuit that generates a difference determination signal and generates the difference determination signal having a third value when the difference determination signal is equal to or smaller than the second threshold value. The output signal is used for a video signal displayed by a display device,
It further has a noise determination circuit that generates a threshold signal for changing the first and second threshold values based on the difference signal generated in response to the input signal input when the video signal is a blank portion. The edge correction circuit according to claim 3. The noise determination circuit
A limiter circuit that outputs a signal suppressed to the predetermined value when the difference signal generated in response to the input signal input when the video signal is a blank portion is equal to or greater than a predetermined value;
The edge correction circuit according to claim 4, further comprising: a threshold value generation circuit that outputs a value obtained by averaging the value of the signal output from the limiter circuit a predetermined number of times as the threshold value signal. 6. A removal circuit connected between the high-pass filter and the adder and further removing a value corresponding to the threshold signal from the extracted component of the high-pass filter when the video signal is not a blank portion. The edge correction circuit described. A multiplier connected between the removal circuit and the adder;
The multiplier is
When the video signal is a blank portion, through the output signal of the removal circuit and output to the adder,
The edge correction circuit according to claim 6, wherein when the video signal is not a blank portion, an output signal of the removal circuit is multiplied by a predetermined multiplication coefficient and output to the adder. The edge correction circuit according to claim 1, wherein the setting signal is determined according to a value held in a setting register. The edge correction circuit according to claim 8, wherein a value of the setting register changes according to a determination result of the inclination detection circuit. The input signal is sequentially delayed by a unit delay amount, a plurality of first delay signals having a delay before the correction target sample point of the input signal, and a plurality of second delay signals having a delay after the correction target sample point A delay signal, and
A determination result of the continuity of the slope of the input signal is generated from the input signal and a plurality of delay differential signals obtained by sequentially delaying the differential signal delayed by the unit delay amount from the input signal,
Selecting a first selection delay signal having a delay amount according to the determination result from the plurality of first delay signals;
A second selection delay signal having a delay amount according to the determination result is selected from the plurality of second delay signals;
A third selection delay signal having a delay amount according to the setting is selected from the plurality of first delay signals;
A fourth selection delay signal having a delay amount according to the setting is selected from the plurality of second delay signals;
Extracting a high frequency component of the input signal based on the signal of the correction target sample point of the input signal and the third and fourth selection delay signals;
Generate an added signal obtained by adding the extracted high frequency component to the correction target sample point of the input signal,
An edge correction program for comparing each value of the addition signal and the first and second selection delay signals and using a signal having an intermediate value as an output signal.

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