JP2012028391A - Semiconductor light-emitting element and method of manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve such a problem that the yield is lowered due to lattice defect, or the like, when an LED element is enlarged, and although a method of making an LED element non-defective by blocking the LED elements, not forming bumps for flip-chip connection on a circuit board corresponding to a leaked block and then disabling this block is known, the manufacturing process is complicated because the block information of short-circuited LED elements is passed to the circuit board in this method.SOLUTION: In an LED element 10 where bumps 13 and 14 are formed on the electrode surface by plating and the electrode surface is blocked, the bump 14 is provided in a non-leaked block (p-type semiconductor layer (12)) and the bump 14 is not provided in a leaked block (p-type semiconductor layer (12x)). Since a plating bump is formed for a wafer, leakage information is not required to be passed to the circuit board side, and since processing can be performed in a state where the LED elements are arranged densely, manufacturing efficiency is good.

Description

  The present invention relates to a semiconductor light emitting device for flip chip mounting on a circuit board and a method for manufacturing the same.

  2. Description of the Related Art A semiconductor light emitting device (hereinafter referred to as an LED device unless otherwise specified) in which a semiconductor light emitting element (hereinafter referred to as an LED element unless otherwise specified) is mounted on a circuit board and packaged is known. This LED device often employs flip chip mounting that is excellent in heat dissipation characteristics, mounting area efficiency, and productivity. Flip chip mounting is a mounting method in which the electrode of an element and the electrode of a circuit board are opposed to each other and directly connected by a conductive member such as a bump.

  An LED element is obtained by creating a large number of elements on a substrate called a wafer by using a technique such as a photolithography method and cutting out the wafer into individual pieces. In this process, lattice defects are generated on the wafer at a certain rate. For this reason, when the area of the LED element becomes large, there has been a problem that the yield is lowered due to leakage due to lattice defects.

  As a countermeasure against this leak, there is a method in which the electrode surface of the LED element is blocked so that the block causing the leak is not used. For example, FIG. 6 of Patent Document 1 shows one of the plurality of p-side electrodes 105 (corresponding to blocks, the numbers are shown in FIG. 5 and the like) formed on a chip (LED element) (p electrode). 320 shows the submount 120 (circuit board), the bump 106, and the chip when it is determined that the current leakage point 320 has a current leak point. The p-electrode 320 is determined to have a current leak point by a current leak inspection of the chip, and the bump 106 is not formed in a corresponding part on the submount 120 on which the chip is mounted. As a result, the extraction electrode 304 and the p-electrode 320 are not connected to each other, so that the diode block including the p-electrode 320 becomes invalid, and a semiconductor light-emitting device free from leakage is obtained.

JP 2007-266427 A (FIG. 6)

  The semiconductor light emitting device disclosed in Patent Document 1 bumps into a circuit board (submount 120) region corresponding to a leaking block (p electrode 320) based on leak information of an LED element (chip) whose electrode surface is blocked. 106 is not formed, or the bump 106 in the region is crushed. The information of the shorted block of the LED element is taken and reflected in the bump formation on the circuit board {or deformation or removal of the bump (crushed in the third embodiment)} from the LED element side to the circuit board side Since it is necessary to transfer information to the manufacturing process, the manufacturing process becomes complicated and the production efficiency is lowered. Further, the process of crushing bumps after forming the bumps on the circuit board in a batch requires post-processing of the deformed or removed bumps, resulting in poor production efficiency.

  Accordingly, the present invention has been made in view of these problems, and in a semiconductor light emitting device having a blocked electrode surface, a semiconductor light emitting device in which a leaky block and an electrode of a circuit board are not connected can be efficiently manufactured. An object of the present invention is to provide a light emitting element and a manufacturing method thereof.

In order to solve the above-mentioned problems, the present invention provides a semiconductor light-emitting device having flip-chip mounting bumps on the electrode surface, and the electrode surface is blocked.
Blocks that do not leak include the bumps,
The leaking block does not include the bump.

Preferably, the bump is a gold bump, and a gold-tin eutectic layer, a tin layer, or a laminate of tin and gold is provided on the surface of the bump.

In order to solve the above-mentioned problem, the present invention provides a method for manufacturing a semiconductor light emitting device, wherein the electrode surface includes bumps for flip chip mounting, and the electrode surface is blocked.
A preparatory step of preparing a wafer in which the semiconductor light emitting elements before the bumps are formed and the leaking blocks are known,
Forming a resist film on the wafer with a resist film having an opening in a region in which the bump is grown; and
A sealing step of filling an opening of the resist film of the leaking block with a sealing member;
A bump growth step for growing the bumps by plating;
A resist film removing step for removing the resist film;
And singulating the semiconductor light emitting element into individual pieces.

  In the sealing step, a liquid sealing member may be applied to the opening portion of the resist film of the leaking block by a dispenser or an ink jet method to solidify the sealing member.

  Preferably, the bump is a gold bump, and includes a bonding layer forming step of forming a gold-tin eutectic layer, a tin layer, or a laminate of a tin layer and a gold layer after the bump growth step.

  The bump may be a gold bump grown by an electrolytic plating method, and the tin layer or the laminate of tin and gold may be formed by an electrolytic plating method in the bonding layer forming step.

  In the semiconductor light emitting device of the present invention, bumps are not formed on the leaking block based on the information of the leaking block. Therefore, when the semiconductor light emitting element is mounted on the circuit board, it is not necessary to transmit information related to the leak to the circuit board.

In the method for manufacturing a semiconductor light emitting device of the present invention, a corresponding opening of a resist film used for partial plating is sealed so as not to form a bump on a leaking block. Since this sealing process is to process the wafer, information on leaking blocks can be directly applied. That is, when the semiconductor light emitting element is mounted on the circuit board, it is not necessary to transmit information related to the leak, and the leaking block and the electrode of the circuit board are automatically insulated without special consideration for the circuit board. Further, since the sealing step is performed on a wafer in which semiconductor light emitting elements are densely packed, a large number of semiconductor light emitting elements can be processed at a time. Further, no bump is formed on the leaking block, so that no processing after the bump removal is necessary. As described above, the semiconductor light emitting device and the manufacturing method thereof of the present invention have high manufacturing efficiency.

The top view which looked at the LED element in 1st Embodiment of this invention from the electrode surface. Sectional drawing of the LED apparatus which mounted the LED element of FIG. FIG. 3 is a circuit diagram of the LED device of FIG. 2. The enlarged view of the area | region shown by B of FIG. Explanatory drawing for manufacturing the LED element of FIG. Explanatory drawing for manufacturing the LED element in 2nd Embodiment of this invention.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to FIGS. In the description of the drawings, the same or equivalent elements will be denoted by the same reference numerals, and redundant description will be omitted. For the sake of explanation, the scale of the members is changed as appropriate.
(First embodiment)

  The first embodiment of the present invention will be described in detail with reference to FIGS. The electrode surface of the LED element 10 of this embodiment will be described with reference to FIG. Sixteen blocked p-type semiconductor layers 12 are formed on the n-type semiconductor layer 11 serving as a common electrode. Four n-side bumps 13 exist in a region where the n-type semiconductor layer 11 is exposed from the p-type semiconductor layer 12. The p-type semiconductor layer 12 except for the p-type semiconductor layer 12x (showing that it leaks with a suffix x; the same applies hereinafter) includes a p-side bump 14.

  Each p-type semiconductor layer 12, 12 x is formed as a semi-independent diode by being stacked with the n-type semiconductor layer 11. That is, the p-type semiconductor layers 12 and 12x are independent anodes, while the n-type semiconductor layer 11 is a common cathode. Here, since the p-type semiconductor region 12x has a leak, there is no p-side bump 14. The n-side bump 13 and the p-side bump 14 are gold bumps formed by electrolytic plating. The protective film is not shown.

  The cross section of the LED device in which the LED element 10 is flip-chip mounted on the circuit board 20 will be described with reference to FIG. 2 is a cross-sectional view of the LED device including the AA line of FIG. First, the LED element 10 will be described. The n-type semiconductor layer 11 exists over the entire lower surface of the sapphire substrate 15. Four p-type semiconductor layers 12 and 12x are formed on the lower surface of the n-type semiconductor layer 11. The p-type semiconductor layers 12 and 12x and the gaps between the p-type semiconductor layers 12 and 12x are covered with a protective film 16, and the protective film 16 has an opening at the center of the p-type semiconductor layers 12 and 12x. The p-type semiconductor layer 12 has a p-side bump 14 in the opening of the protective film 16, and the p-type semiconductor layer 12 x has no p-side bump 14 in the opening of the protective film 16.

  Next, the circuit board 20 will be described. The circuit board 20 includes a + electrode 17 and a − electrode 19 (see FIG. 3) on the plate material 18. The + electrode 17 is connected to the p-side bump 14, and the − electrode 19 is connected to the n-side bump 13 (see FIG. 1). Although not shown, two output electrodes are formed on the lower surface of the circuit board 20 to be connected to the electrodes of the mother board. These output electrodes and the + electrode 17 and the − electrode 19 are connected through through holes. is doing. The circuit board 20 and the LED element 10 are covered with a phosphor layer.

  The sapphire substrate 15 has a thickness of 100 to 300 μm, and the n-type semiconductor layer 11 has a thickness of about 5 μm. The p-type semiconductor layer 12 has a total thickness of about 1 μm and includes a p-type GaN layer having a thickness of 100 to 200 nm. The protective film has a thickness of about 300 nm and is made of SiO2. The n-side bumps and the p-side bumps 13 and 14 have a thickness of 10 to 30 μm. The light emitting layer (not shown) is at the boundary between the n-type semiconductor layer 11 and the p-type semiconductor layer 12, and the planar shape is substantially equal to the p-type semiconductor layer 12. The plate material 18 of the circuit board 20 has a thickness of 300 μm and is made of alumina. The + electrode 17 is a copper foil having a thickness of 10 to 30 μm and a laminate of nickel and gold. The p-side bump 14 and the + electrode 17 are joined by gold tin eutectic.

FIG. 3 is a circuit diagram showing an equivalent circuit of the LED device of FIG. There are 16 diodes 30 corresponding to the stacked portion of the p-type semiconductor layers 12, 12 x and the n-type semiconductor layer 11. The cathode of each diode 30 corresponds to the common n-side semiconductor layer 11 and is connected to the negative electrode 19. The anode of each diode 30 corresponds to the p-type semiconductor layer 12, and the anode of the diode 30 having a short circuit is the p-type semiconductor layer 12x. The anode of the diode 30 without a short circuit is connected to the positive electrode 17, but the anode of the diode 30 with a short circuit is floating. This floating corresponds to the fact that no bump is attached to the p-type semiconductor layer 12x in FIG.

  The stacked structure from the circuit board 20 to the n-type semiconductor layer 11 will be described in detail with reference to FIG. 4 is an enlarged view of a region surrounded by B in FIG. On the plate material 18 of the circuit board 20, the + electrode 17, the bonding layer 14c, the gold bump portion 14b, the UBM (under bump metal) layer 14a, the metal layer 12b, the p-type GaN layer 12a, the light emitting layer 11a, and the n-type semiconductor layer. 11 are stacked. The p-side bump 14 is a laminate of the bonding layer 14c, the gold bump portion 14b, and the UBM layer 14a, and the p-type semiconductor layer 12 is a laminate of the metal layer 12b and the p-type GaN layer 12a.

  The + electrode 17 has a structure in which a copper foil having a thickness of 10 to 30 μm, a Ni layer having a thickness of about 2 μm, and an Au layer having a thickness of about 0.3 μm are stacked. The bonding layer 14 c is a laminate of a gold layer having a thickness of 1 μm and a tin layer having a thickness of 2 to 3 μm. The bonding layer 14 c becomes a gold-tin eutectic when bonded, and bonds the p-side bump 14 and the + electrode 17. Since the melting point of gold-tin eutectic bonding can be set to 300 ° C. to 420 ° C., the bonding can be maintained at a reflow temperature of about 250 ° C. even though bonding can be performed at a relatively low temperature. For this reason, it becomes an advantageous joining method when the LED device is mounted on the mother board. The gold bump portion 14b has a thickness of 10 to 30 μm. The UBM layer 24a is a metal layer formed when a part of a common electrode (also referred to as a plating electrode) for growing the gold bump portion 14b by electrolytic plating isolates the gold bump portion 14b electrically. 12b remains, has a thickness of 0.3 μm, and has a two-layer structure of TiW and Au.

  The metal layer 12b is formed by laminating a plurality of metal thin films such as an ITO layer, an Ag layer, and a gold layer in order to achieve various purposes such as improvement of current distribution, ohmic contact, reflection function, and prevention of atomic diffusion. The p-type semiconductor layer 12 composed of the metal layer 12b and the p-type GaN layer 12a has a thickness of about 1 μm. The light emitting layer 11a made of the GaN barrier layer and the InGaN well layer has a thickness of 60 nm, and the n-type semiconductor layer 11 made of n-type GaN has a thickness of about 5 μm.

  The manufacturing method of the LED element 10 of this embodiment is demonstrated with FIG. (A) is a wafer preparation process. The wafer 50 is obtained by arranging a plurality of LED elements 10 before the n-side bumps 13 (not shown) and the p-side bumps 14 are formed. FIG. 5 shows a cross section of the wafer 50 for only one element. In the wafer 50, an n-type semiconductor layer 11 and blocked p-type semiconductor layers 12 and 12x are stacked on a sapphire substrate 15 (the protective film 16 is not shown). In addition, the electrical characteristics of each LED element 10 have already been measured on the wafer 50, and the p-type semiconductor layer 12 (block) that has not leaked and the p-type semiconductor layer 12x (block) that has leaked have been found.

(B) is a plating electrode forming step. The UBM layer 14a is formed on the entire upper surface of the wafer 50 by sputtering. At this stage, since the UBM layer 14a is a plated electrode, it is not separated for each electrode. (C) is a resist film forming step. A resist film 51 having an opening in a region where the n-side bump 13 (not shown) and the p-side bump 14 are grown is formed. The resist film 51 forms an opening by photolithography. (D) is a sealing step. The opening of the resist film 51 of the leaking block (p-type semiconductor layer 12 x) is filled with a sealing member 52. At this time, the sealing member 52 is dropped with a dispenser (not shown) and heated to solidify the sealing member 52. The sealing member 52 may be applied to the opening by an ink jet method. (E) is a bump growth process. The wafer 50 is immersed in a plating solution (not shown) to grow the gold bump portion 14b. At the same time, a gold bump portion of the n-side bump 13 (not shown) is also grown.

  (F) and (g) are bonding layer forming steps, in which the bonding layer 14c is formed on the gold bump portion 14b of the p-side bump 14 by electrolytic plating (the same applies to the n-side bump 13). (F) is a step of forming a tin layer 53 and (g) is a step of forming a gold layer 54. The bonding layer 14 c is a stacked body in which a gold layer 54 is stacked on a tin layer 53. (H) is a resist film removing step. The UBM layer 14a (plating electrode) other than the region occupied by the p-side bump 14 (and the n-side bump 13) is exposed. At this time, the resist film 51 and the sealing member 52 are removed simultaneously. (I) is an etching process. The UBM layer 14a is etched using the n-side bump 13 and the p-side bump 14 as a mask. As a result, the UBM layer 14a remains under the p-side bump 14 (the same applies to the n-side bump 13). (J) is an individualization step. The wafer 50 is cut with a dicer (not shown) to obtain the LED element 10 that is divided into pieces.

In the present embodiment, the bonding layer 14 c has a two-layer structure of a tin layer 53 and a gold layer 54. Since both the tin layer 53 and the gold layer 54 can be formed by an electrolytic plating method, the manufacturing apparatus and the film thickness can be easily controlled, and the tin layer 53 and the gold layer 54 can be formed only at a necessary place. This is particularly advantageous when a thick expensive gold layer is applied. When the p-side bump 14 and the + electrode 17 are joined, the tin layer 53 is first melted, gold is melted from the gold bump portion 14b and the gold layer 54, and the tin layer 53 becomes a gold-tin eutectic. Since the gold layer 53 is mainly intended to prevent the oxidation of the tin layer 53, the gold layer 54 is omitted and only the tin layer is left, and gold is melted from the gold bump portion 14b at the time of bonding to make the tin layer a gold-tin eutectic. May be.
(Second Embodiment)

  A second embodiment of the present invention will be described in detail with reference to FIG. In contrast to the first embodiment, the LED element 66 of this embodiment has the same electrode surface, state mounted on the circuit board 20, and equivalent circuit as shown in FIGS. 1, 2, and 3, and an n-side bump (not shown). The p-side bump 64 has a different laminated structure and formation method.

  The manufacturing method of the LED element 66 of this embodiment is demonstrated with FIG. (A) is a wafer preparation process. The wafer 60 is the same as that shown in FIG. (B) is a resist film forming step. A resist film 61 having an opening in a region where an n-side bump (not shown) and a p-side bump 64 are grown is formed. The resist film 61 forms an opening by photolithography. (C) is a sealing step. The opening of the resist film 61 of the leaking block (p-type semiconductor layer 12 x) is filled with a sealing member 62. At this time, the sealing member 62 is dropped with a dispenser (not shown) and heated to solidify the sealing member 62. (D) is a bump growth process. The wafer 60 is immersed in a plating solution (not shown) to grow a gold bump portion 64b (the same applies to the n-side bump). The n-type semiconductor layer 11 is used as a common electrode for plating.

  (E) is a bonding layer forming step. A bonding layer 64c made of gold-tin eutectic is formed by a sputtering method. The bonding layer 64 c is formed on the entire surface of the wafer 60. (F) is a resist film removing step. The sealing member 62, the resist film 51, and the bonding layer 64c formed on the sealing member 62 together with the resist film 61 are removed. (G) is an individualization step. The wafer 60 is cut with a dicer (not shown), and the LED element 66 separated into pieces is obtained.

  The manufacturing method of the present embodiment is different from the manufacturing method of the first embodiment (FIG. 5) in that there is no UBM layer forming step / etching step and the bonding layer 64c made of gold-tin eutectic is formed by a sputtering method. And the process is shortened.

In the first and second embodiments, the n-side and p-side bumps 13, 14, and 64 are gold bumps formed by electrolytic plating. However, the member that becomes the core of the bump is not limited to gold, and may be another alloy or metal material such as solder, copper, or aluminum. Moreover, it is not limited to the joining method by a gold tin eutectic, You may join by other alloys and metals, such as solder. If a bonding method using gold-tin eutectic is employed, the bonding stability during reflow is guaranteed as described above. The plating method is not limited to the electrolytic plating method, and may be a sputtering method, a CVD method or a vapor deposition method. However, as described above, the electrolytic plating method is simple in manufacturing equipment and manufacturing conditions and has high material efficiency.

  In the first and second embodiments, the bonding layers 14c and 64c are formed on the n-side and p-side bumps 13, 14, and 64. The bonding layer may be formed on the + electrode 17 and the − electrode 19 of the circuit board 20. However, it is easier to handle the bonding layers 14c and 64c formed on the wafers 50 and 60 in which the LED elements 10 are densely packed. Becomes higher.

10, 66 ... LED element (semiconductor light emitting device),
11 ... n-type semiconductor layer,
11a ... light emitting layer,
12, 12x ... p-type semiconductor layer,
12a ... p-type GaN layer,
12b ... metal layer,
13 ... n-side bump,
14,64 ... p side bump,
14a ... UBM layer,
14b, 64b ... gold bump part,
14c, 64c ... bonding layer,
15 ... sapphire substrate,
16 ... Protective film,
17 ... + electrode,
18 ... board material,
19 ...- electrodes,
20 ... circuit board,
30 ... a diode,
50, 60 ... wafer,
51, 61 ... resist film,
52, 62 ... sealing member,
53 ... tin layer,
54 ... Gold layer.

Claims (6)

In a semiconductor light-emitting device comprising bumps for flip chip mounting on the electrode surface, and the electrode surface is blocked,
Blocks that do not leak include the bumps,
The leaking block does not include the bump, and the semiconductor light emitting device.   2. The semiconductor light emitting element according to claim 1, wherein the bump is a gold bump, and a gold tin eutectic layer, a tin layer, or a laminate of tin and gold is provided on the surface of the bump. In the method for manufacturing a semiconductor light emitting device comprising flip-chip mounting bumps on the electrode surface, the electrode surface being blocked,
A preparatory step of preparing a wafer in which the semiconductor light emitting elements before the bumps are formed and the leaking blocks are known,
Forming a resist film on the wafer with a resist film having an opening in a region in which the bump is grown; and
A sealing step of filling an opening of the resist film of the leaking block with a sealing member;
A bump growth step for growing the bumps by plating;
A resist film removing step for removing the resist film;
A method of manufacturing a semiconductor light emitting device, comprising: a step of cutting the wafer and separating the semiconductor light emitting device into pieces.   The liquid sealing member is applied to the opening of the resist film of the leaking block by a dispenser or an ink jet method in the sealing step, and the sealing member is solidified. A method for manufacturing a semiconductor light emitting device.   The bump is a gold bump, and includes a bonding layer forming step of forming a gold-tin eutectic layer, a tin layer, or a laminate of a tin layer and a gold layer after the bump growth step. Or 4. A method for producing a semiconductor light-emitting device according to 4. 6. The bump according to claim 5, wherein the bump is a gold bump grown by an electrolytic plating method, and the tin layer or the laminate of tin and gold is formed by an electrolytic plating method in the bonding layer forming step. A method for manufacturing a semiconductor light emitting device.

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